FUJITSU SEMICONDUCTOR
DATA SHEET
Copyright©2008-2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2010.7
For the information for microcontroller supports, see the following web site.
http://edevice.fujitsu.com/micom/en-support/
8-bit Microcontroller
CMOS
F2MC-8FX MB95200H/210H Series
MB95F204H/F204K/F203H/F203K/F202H/F202K
MB95F214H/F214K/F213H/F213K/F212H/F212K
■DESCRIPTION
MB95200H/210H is a series of general-purpose, single-chip microcontrollers. In addition to a compact instruction
set, the microcontrollers of this series contain a variety of peripheral resources.
Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■FEATURES
•F
2MC-8FX CPU core
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instructions
• Bit manipulation instructions, etc.
• Clock (main OSC clock and sub-OSC clock are only available in MB95F204H/F204K/F203H/F203K/F202H/
F202K)
• Selectable main clock source
Main OSC clock (up to 16.25 MHz, maximum machine clock frequency: 8.125 MHz)
External clock (up to 32.5 MHz, maximum machine clock frequency: 16.25 MHz)
Main internal CR clock (1/8/10 MHz ± 3%, maximum machine clock frequency: 10 MHz)
• Selectable subclock source
Sub-OSC clock (32.768 kHz)
External clock (32.768 kHz)
Sub-internal CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 200 kHz)
•Timer
• 8/16-bit composite timer
• Timebase timer
• Watch prescaler
•LIN-UART (MB95F204H/F204K/F203H/F203K/F202H/F202K)
• Full duplex double buffer
Capable of clock-synchronized serial data transfer and clock-asynchronized serial data transfer
(Continued)
DS07-12623-5E
MB95200H/210H Series
2DS07-12623-5E
(Continued)
• External interrupt
• Interrupt by edge detection (rising edge, falling edge, and both edges can be selected)
• Can be used to wake up the device from different low-power consumption (standby) modes
• 8/10-bit A/D converter
• 8-bit or 10-bit resolution can be selected.
• Low power consumption (standby) mode
• Stop mode
• Sleep mode
• Watch mode
• Timebase timer mode
• I/O port (Max: 17) (MB95F204K/F203K/F202K)
• General-purpose I/O ports (Max):
CMOS I/O: 15, N-ch open drain: 2
• I/O port (Max: 16) (MB95F204H/F203H/F202H)
• General-purpose I/O ports (Max):
CMOS I/O: 15, N-ch open drain: 1
• I/O port (Max: 5) (MB95F214K/F213K/F212K)
• General-purpose I/O ports (Max):
CMOS I/O: 3, N-ch open drain: 2
• I/O port (Max: 4) (MB95F214H/F213H/F212H)
• General-purpose I/O ports (Max):
CMOS I/O: 3, N-ch open drain: 1
• On-chip debug
• 1-wire serial control
• Serial writing supported (asynchronous mode)
• Hardware/software watchdog timer
• Built-in hardware watchdog timer
• Low-voltage detection reset circuit
• Built-in low-voltage detector
• Clock supervisor counter
• Built-in clock supervisor counter function
• Programmable port input voltage level
• CMOS input level / hysteresis input level
• Flash memory security function
• Protects the contents of flash memory
MB95200H/210H Series
DS07-12623-5E 3
■PRODUCT LINE-UP
(Continued)
Part number
Parameter
MB95
F204H
MB95
F203H
MB95
F202H
MB95
F204K
MB95
F203K
MB95
F202K
MB95
F214H
MB95
F213H
MB95
F212H
MB95
F214K
MB95
F213K
MB95
F212K
Type Flash memory product
Clock
supervisor
counter
It supervises the main clock oscillation.
ROM capacity 16 KB 8 KB 4 KB 16 KB 8 KB 4 KB 16 KB 8 KB 4 KB 16 KB 8 KB 4 KB
RAM capacity 496 B 496 B 240 B 496 B 496 B 240 B 496 B 496 B 240 B 496 B 496 B 240 B
Low-voltage
detection reset No Yes No Yes
Reset input Dedicated Software select Dedicated Software select
CPU functions
Number of basic instructions : 136
Instruction bit length : 8 bits
Instruction length : 1 to 3 bytes
Data bit length : 1, 8, and 16 bits
Minimum instruction execution time : 61.5 ns (with machine clock = 16.25 MHz)
Interrupt processing time : 0.6 µs (with machine clock = 16.25 MHz)
General-
purpose I/O
I/O ports (Max): 16
CMOS: 15, N-ch: 1
I/O ports (Max): 17
CMOS: 15, N-ch: 2
I/O ports (Max): 4
CMOS: 3, N-ch: 1
I/O ports (Max): 5
CMOS: 3, N-ch: 2
Timebase timer Interrupt cycle : 0.256 ms - 8.3 s (when external clock = 4 MHz)
Hardware/
software
watchdog timer
Reset generation cycle
Main oscillation clock at 10 MHz : 105 ms (Min)
The sub-CR clock can be used as the source clock of the hardware watchdog.
Wild register It can be used to replace three bytes of data.
LIN-UART
A wide range of communication speed can be
selected by a dedicated reload timer.
It has a full duplex double buffer.
Clock-synchronized serial data transfer and
clock-asynchronized serial data transfer is
enabled.
The LIN function can be used as a LIN master or
a LIN slave.
No LIN-UART
8/10-bit A/D
converter
6 ch. 2 ch.
8-bit or 10-bit resolution can be selected.
8/16-bit
composite
timer
2 ch. 1 ch.
The timer can be configured as an "8-bit timer x 2 channels" or a "16-bit timer x 1 channel".
It has built-in timer function, PWC function, PWM function and input capture function.
Count clock: it can be selected from internal clocks (seven types) and external clocks.
It can output square wave.
External
interrupt
6 ch. 2 ch.
Interrupt by edge detection (rising edge, falling edge, or both edges can be selected.)
It can be used to wake up the device from standby modes.
On-chip debug 1-wire serial control
It supports serial writing. (asynchronous mode)
MB95200H/210H Series
4DS07-12623-5E
(Continued)
Part number
Parameter
MB95
F204H
MB95
F203H
MB95
F202H
MB95
F204K
MB95
F203K
MB95
F202K
MB95
F214H
MB95
F213H
MB95
F212H
MB95
F214K
MB95
F213K
MB95
F212K
Watch
prescaler Eight different time intervals can be selected.
Flash memory
It supports automatic programming, Embedded Algorithm,
write/erase/erase-suspend/erase-resume commands.
It has a flag indicating the completion of the operation of Embedded Algorithm.
Number of write/erase cycles: 100000
Data retention time: 20 years
For write/erase, external Vpp(+10 V) input is required.
Flash Security Feature for protecting the contents of the flash
Standby mode Sleep mode, stop mode, watch mode, timebase timer mode
Package SDIP-24
SOP-20
DIP-8
SOP-8
MB95200H/210H Series
DS07-12623-5E 5
■PACKAGES AND CORRESPONDING PRODUCTS
O: Available
X: Unavailable
Part number
Package
MB95
F204H
MB95
F203H
MB95
F202H
MB95
F204K
MB95
F203K
MB95
F202K
MB95
F214H
MB95
F213H
MB95
F212H
MB95
F214K
MB95
F213K
MB95
F212K
24-pin plastic
SDIP OOOOOOXXXXXX
20-pin plastic
SOP OOOOOOXXXXXX
8-pin plastic DIPXXXXXXOOOOOO
8-pin plastic SOPXXXXXXOOOOOO
MB95200H/210H Series
6DS07-12623-5E
■ DIFFERENCES AMONG PRODUCTS AND NOTES ON PRODUCT SELECTION
• Current consumption
When using the on-chip debug function, take account of the current consumption of flash erase/program.
For details of current consumption, see “■ ELECTRICAL CHARACTERISTICS”.
• Package
For details of information on each package, see “■ PACKAGES AND CORRESPONDING PRODUCTS” and
“■PACKAGE DIMENSIONS”.
• Operating voltage
The operating voltage varies, depending on whether the on-chip debug function is used or not.
For details of the operating voltage, see “■ ELECTRICAL CHARACTERISTICS”.
• On-chip debug function
The on-chip debug function requires that VCC, VSS and 1 serial-wire be connected to an evaluation tool. In addition,
if the flash memory data has to be updated, the RSTX/PF2 pin must also be connected to the same evaluation tool.
MB95200H/210H Series
DS07-12623-5E 7
■PIN ASSIGNMENT
P12/EC0/DBG
N.C.
P07/INT07
P06/INT06/TO01
P05/INT05/AN05/TO00/HCLK2
P04/INT04/AN04/SIN/HCLK1/EC0
P03/INT03/AN03/SOT
P02/INT02/AN02/SCK
P01/AN01
P00/AN00
N.C.
P64/EC1
X0/PF0
N.C.
X1/PF1
Vss
X1A/PG2
X0A/PG1
Vcc
C
RSTX/PF2
TO10/P62
N.C.
TO11/P63
(TOP VIEW)
24 pins
(SDIP24)
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
P12/EC0/DBG
P06/INT06/TO01
P05/AN05/TO00/HCLK2
P04/INT04/AN04/HCLK1/EC0
Vss
Vcc
C
RSTX/PF2
(TOP VIEW)
8 pins
8
7
6
5
1
2
3
4
* The number of usable pins is 20.
P12/EC0/DBG
P07/INT07
P06/INT06/TO01
P05/INT05/AN05/TO00/HCLK2
P04/INT04/AN04/SIN/HCLK1/EC0
P03/INT03/AN03/SOT
P02/INT02/AN02/SCK
P01/AN01
P00/AN00
P64/EC1
X0/PF0
X1/PF1
Vss
X1A/PG2
X0A/PG1
Vcc
C
RSTX/PF2
TO10/P62
TO11/P63
(TOP VIEW)
20 pins
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
MB95200H/210H Series
8DS07-12623-5E
■PIN DESCRIPTION (MB95200H Series 24 pins)
(Continued)
Pin no. Pin name
I/O
circuit
type*
Function
1PF0 BGeneral-purpose I/O port
X0 Main clock input oscillation pin
2 N.C. — It is an internally unconnected pin. Always leave it unconnected.
3PF1 BGeneral-purpose I/O port
X1 Main clock I/O oscillation pin
4V
SS — Power supply pin (GND)
5PG2 CGeneral-purpose I/O port
X1A Subclock I/O oscillation pin
6PG1 CGeneral-purpose I/O port
X0A Subclock input oscillation pin
7V
CC — Power supply pin
8 C — Capacitor connection pin
9
PF2
A
General-purpose I/O port
RSTX Reset pin
This is a dedicated reset pin in MB95F202H/F203H/F204H.
10 P62 D
General-purpose I/O port
High-current port
TO10 8/16-bit composite timer ch. 1 output pin
11 N.C. −It is an internally unconnected pin. Always leave it unconnected.
12 P63 D
General-purpose I/O port
High-current port
TO11 8/16-bit composite timer ch. 1 output pin
13 P64 DGeneral-purpose I/O port
EC1 8/16-bit composite timer ch. 1 clock input pin
14 N.C. — It is an internally unconnected pin. Always leave it unconnected.
15 P00 EGeneral-purpose I/O port
AN00 A/D converter analog input pin
16 P01 EGeneral-purpose I/O port
AN01 A/D converter analog input pin
17
P02
E
General-purpose I/O port
INT02 External interrupt input pin
AN02 A/D converter analog input pin
SCK LIN-UART clock I/O pin
MB95200H/210H Series
DS07-12623-5E 9
(Continued)
*: For the I/O circuit types, see "■ I/O CIRCUIT TYPE".
Pin no. Pin name
I/O
circuit
type*
Function
18
P03
E
General-purpose I/O port
INT03 External interrupt input pin
AN03 A/D converter analog input pin
SOT LIN-UART data output pin
19
P04
F
General-purpose I/O port
INT04 External interrupt input pin
AN04 A/D converter analog input pin
SIN LIN-UART data input pin
HCLK1 External clock input pin
EC0 8/16-bit composite timer ch. 0 clock input pin
20
P05
E
General-purpose I/O port
High-current port
INT05 External interrupt input pin
AN05 A/D converter analog input pin
TO00 8/16-bit composite timer ch. 0 output pin
HCLK2 External clock input pin
21
P06
G
General-purpose I/O port
High-current port
INT06 External interrupt input pin
TO01 8/16-bit composite timer ch. 0 output pin
22 P07 GGeneral-purpose I/O port
INT07 External interrupt input pin
23 N.C. — It is an internally unconnected pin. Always leave it unconnected.
24
P12
H
General-purpose I/O port
EC0 8/16-bit composite timer ch. 0 clock input pin
DBG DBG input pin
MB95200H/210H Series
10 DS07-12623-5E
■PIN DESCRIPTION (MB95200H Series 20 pins)
(Continued)
Pin no. Pin name
I/O
circuit
type*
Function
1PF0/X0B
General-purpose I/O port
This pin is also used as the main clock input oscillation pin.
2PF1/X1B
General-purpose I/O port
This pin is also used as the main clock input/output oscillation pin.
3V
SS — Power supply pin (GND)
4PG2/X1AC
General-purpose I/O port
This pin is also used as the subclock input/output oscillation pin.
5PG1/X0AC
General-purpose I/O port
This pin is also used as the subclock input oscillation pin.
6V
CC — Power supply pin
7 C — Capacitor connection pin
8PF2/RSTXA
General-purpose I/O port
This pin is also used as a reset pin.
This pin is a dedicated reset pin in MB95F204H/F203H/F202H.
9 P62/TO10 D
General-purpose I/O port
High-current port
This pin is also used as the 8/16-bit composite timer ch. 1 output.
10 P63/TO11 D
General-purpose I/O port
High-current port
This pin is also used as the 8/16-bit composite timer ch. 1 output.
11 P64/EC1 D General-purpose I/O port
This pin is also used as the 8/16-bit composite timer ch. 1 clock input.
12 P00/AN00 E General-purpose I/O port
This pin is also used as the A/D converter analog input.
13 P01/AN01 E General-purpose I/O port
This pin is also used as the A/D converter analog input.
14 P02/INT02/AN02/
SCK E
General-purpose I/O port
This pin is also used as the external interrupt input.
This pin is also used as the A/D converter analog input.
This pin is also used as the LIN-UART clock I/O.
15 P03/INT03/AN03/
SOT E
General-purpose I/O port
This pin is also used as the external interrupt input.
This pin is also used as the A/D converter analog input.
This pin is also used as the LIN-UART data output.
16 P04/INT04/AN04/
SIN/HCLK1/EC0 F
General-purpose I/O port
This pin is also used as the external interrupt input.
This pin is also used as the A/D converter analog input.
This pin is also used as the LIN-UART data input.
This pin is also used as the external clock input.
This pin is also used as the 8/16-bit composite timer ch. 0 clock input.
MB95200H/210H Series
DS07-12623-5E 11
(Continued)
*: For the I/O circuit types, see "■ I/O CIRCUIT TYPE".
Pin no. Pin name
I/O
circuit
type*
Function
17 P05/INT05/AN05/
TO00/HCLK2 E
General-purpose I/O port
High-current port
This pin is also used as the external interrupt input.
This pin is also used as the A/D converter analog input.
This pin is also used as the 8/16-bit composite timer ch. 0 output.
This pin is also used as the external clock input.
18 P06/INT06/TO01 G
General-purpose I/O port
High-current port
This pin is also used as the external interrupt input.
This pin is also used as the 8/16-bit composite timer ch. 0 output.
19 P07/INT07 G General-purpose I/O port
This pin is also used as the external interrupt input.
20 P12/EC0/DBG H
General-purpose I/O port
This pin is also used as the DBG input pin.
This pin is also used as the 8/16-bit composite timer ch. 0 clock input.
MB95200H/210H Series
12 DS07-12623-5E
■PIN DESCRIPTION (MB95210H Series)
*: For the I/O circuit types, see "■ I/O CIRCUIT TYPE".
Pin no. Pin name
I/O
circuit
type*
Function
1V
SS — Power supply pin (GND)
2V
CC — Power supply pin
3 C — Capacitor connection pin
4 RSTX/PF2 A
General-purpose I/O port
This pin is also used as a reset pin.
This pin is a dedicated reset pin in MB95F214H/F213H/F212H.
5P04/INT04/AN04/
HCLK1/EC0 E
General-purpose I/O port
This pin is also used as the external interrupt input.
This pin is also used as the A/D converter analog input.
This pin is also used as the external clock input.
This pin is also used as the 8/16-bit composite timer ch. 0 clock input.
6P05/AN05/TO00/
HCLK2 E
General-purpose I/O port
High-current port
This pin is also used as the A/D converter analog input.
This pin is also used as the 8/16-bit composite timer ch. 0 output.
This pin is also used as the external clock input.
7 P06/INT06/TO01 G
General-purpose I/O port
High-current port
This pin is also used as the external interrupt input.
This pin is also used as the 8/16-bit composite timer ch. 0 output.
8 P12/EC0/DBG H
General-purpose I/O port
This pin is also used as the DBG input pin.
This pin is also used as the 8/16-bit composite timer ch. 0 clock input.
MB95200H/210H Series
DS07-12623-5E 13
■I/O CIRCUIT TYPE
(Continued)
Type Circuit Remarks
A• N-ch open drain output
• Hysteresis input
• Reset output
B
• Oscillation circuit
• High-speed side
Feedback resistance: approx. 1 MΩ
•CMOS output
• Hysteresis input
C
• Oscillation circuit
• Low-speed side
Feedback resistance: approx. 10 MΩ
•CMOS output
• Hysteresis input
• Pull-up control available
N-ch
Reset output / Digital output
Reset input / Hysteresis output
Standby control / Port select
Clock input
Port select
Digital output
Digital output
Standby control
Hysteresis input
Digital output
Digital output
Standby control
Hysteresis input
Port select
X1
X0
N-ch
P-ch
N-ch
P-ch
Clock input
X1A
X0A
Standby control / Port select
N-ch
P-ch
Port select
Digital output
Digital output
Standby control
Hysteresis input
N-ch
Digital output
Digital output
Digital output
Standby control
Hysteresis input
P-ch
RPull-up control
Port select
P-ch
RPull-up control
MB95200H/210H Series
14 DS07-12623-5E
(Continued)
Type Circuit Remarks
D
•CMOS output
• Hysteresis input
E
•CMOS output
• Hysteresis input
• Pull-up control available
F
•CMOS output
• Hysteresis input
• CMOS input
• Pull-up control available
G
• Hysteresis input
•CMOS output
• Pull-up control available
H
• N-ch open drain output
• Hysteresis input
N-ch
P-ch
Digital output
Digital output
Standby control
Hysteresis input
N-ch
P-ch
P-ch
RPull-up control
Digital output
Digital output
Analog input
A/D control
Standby control
Hysteresis input
N-ch
P-ch
P-ch
RPull-up control
Digital output
Digital output
Analog input
A/D control
Standby control
Hysteresis input
CMOS input
N-ch
P-ch
P-ch
RPull-up control
Digital output
Digital output
Standby control
Hysteresis input
N-ch
Standby control
Hysteresis input
Digital output
MB95200H/210H Series
DS07-12623-5E 15
■NOTES ON DEVICE HANDLING
• Preventing latch-ups
When using the device, ensure that the voltage applied does not exceed the maximum voltage rating.
In a CMOS IC, if a voltage higher than VCC or a voltage lower than VSS is applied to an input/output pin that is
neither a medium-withstand voltage pin nor a high-withstand voltage pin, or if a voltage out of the rating range
of power supply voltage mentioned in “1. Absolute Maximum Ratings” of ■ ELECTRICAL CHARACTERISTICS”
is applied to the VCC pin or the VSS pin, a latch-up may occur.
When a latch-up occurs, power supply current increases significantly, which may cause a component to be
thermally destroyed.
• Stabilizing supply voltage
Supply voltage must be stabilized.
A malfunction may occur when power supply voltage fluctuates rapidly even though the fluctuation is within the
guaranteed operating range of the VCC power supply voltage.
As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (p-p value) at
the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient
fluctuation rate does not exceed 0.1 V/ms at a momentary fluctuation such as switching the power supply.
• Notes on using the external clock
When an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from
subclock mode or stop mode.
■PIN CONNECTION
• Treatment of unused pins
If an unused input pin is left unconnected, a component may be permanently damaged due to malfunctions or
latch-ups. Always pull up or pull down an unused input pin through a resistor of at least 2 kΩ. Set an unused
input/output pin to the output state and leave it unconnected, or set it to the input state and treat it the same as
an unused input pin. If there is an unused output pin, leave it unconnected.
• Power supply pins
To reduce unnecessary electro-magnetic emission, prevent malfunctions of strobe signals due to an increase
in the ground level, and conform to the total output current standard, always connect the VCC pin and the VSS pin
to the power supply and ground outside the device. In addition, connect the current supply source to the VCC pin
and the VSS pin with low impedance.
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between the VCC pin and the
VSS pin at a location close to this device.
• DBG pin
Connect the DBG pin directly to an external pull-up resistor.
To prevent the device from unintentionally entering the debug mode due to noise, minimize the distance between
the DBG pin and the VCC or VSS pin when designing the layout of the printed circuit board.
The DBG pin should not stay at “L” level after power-on until the reset output is released.
• RSTX pin
Connect the RSTX pin directly to an external pull-up resistor.
To prevent the device from unintentionally entering the reset mode due to noise, minimize the distance between
the RSTX pin and the VCC or VSS pin when designing the layout of the printed circuit board.
The RSTX/PF2 pin functions as the reset input/output pin after power-on. In addition, the reset output can be
enabled by the RSTOE bit of the SYSC register, and the reset input function or the general purpose I/O function
can be selected by the RSTEN bit of the SYSC register.
MB95200H/210H Series
16 DS07-12623-5E
• C pin
Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The bypass capacitor for the
VCC pin must have a capacitance larger than CS. For the connection to a smoothing capacitor CS, see the diagram
below. To prevent the device from unintentionally entering an unknown mode due to noise, minimize the distance
between the C pin and CS and the distance between CS and the VSS pin when designing the layout of a printed
circuit board.
C
Cs
DBG
RSTX
• DBG/RSTX/C pin connection diagram
MB95200H/210H Series
DS07-12623-5E 17
■BLOCK DIAGRAM (MB95200H Series)
MB95200H/210H Series
18 DS07-12623-5E
■BLOCK DIAGRAM (MB95210H Series)
Flash with security function
(16/8/4 KB)
RAM (496/240 B)
Interrupt controller
8/10-bit A/D converter
8/16-bit composite timer (0)
Reset with LVD
CR oscillator
Clock control
On-chip debug
Wild register
External interrupt
Port Port
F
2
MC-8FX CPU
Internal Bus
(P05
*3
/TO00)
(P06
*3
/TO01)
P12
*1
/EC0, (P04/EC0)
P05
*3
/AN05, (P04/AN04)
(P04/HCLK1)
(P05
*3
/HCLK2)
(P12/DBG)
P04/INT04, P06
*3
/INT06
C
V
CC
V
SS
*1: PF2 and P12 are Nch open drain pins.
*2: Software option
*3: P05 and P06 are high-current ports.
PF2
*1
/RSTX
*2
MB95200H/210H Series
DS07-12623-5E 19
■CPU CORE
• Memory Space
The memory space of the MB95200H/210H Series is 64 KB in size, and consists of an I/O area, a data area,
and a program area. The memory space includes areas intended for specific purposes such as general-purpose
registers and a vector table. The memory maps of the MB95200H/210H Series are shown below.
• Memory Maps
I/O
0000
H
0080
H
-
0090
H
RAM 496 B
0280
H
Register
0100
H
0200
H
-
Extension I/O
0F80
H
1000
H
-
C000
H
Flash 16 KB
FFFF
H
I/O
0000
H
0080
H
-
0090
H
RAM 496 B
0280
H
Register
0100
H
0200
H
-
Extension I/O
0F80
H
1000
H
-
E000
H
Flash 8 KB
I/O
-
RAM 240 B
Register
-
Extension I/O
-
Flash 4 KB
FFFF
H
0000
H
0080
H
0090
H
0100
H
0180
H
0F80
H
1000
H
F000
H
FFFF
H
MB95F204H/F204K
/F214H/F214K
MB95F203H/F203K/
F213H/F213K
MB95F202H/F202K/
F212H/F212K
MB95200H/210H Series
20 DS07-12623-5E
■I/O MAP (MB95200H Series)
(Continued)
Address Register
abbreviation Register name R/W Initial value
0000HPDR0 Port 0 data register R/W 00000000B
0001HDDR0 Port 0 direction register R/W 00000000B
0002HPDR1 Port 1 data register R/W 00000000B
0003HDDR1 Port 1 direction register R/W 00000000B
0004H— (Disabled) — —
0005HWATR Oscillation stabilization wait time setting register R/W 11111111B
0006H— (Disabled) — —
0007HSYCC System clock control register R/W XXXXXX11B
0008HSTBC Standby control register R/W 00000XXXB
0009HRSRR Reset source register R XXXXXXXXB
000AHTBTC Timebase timer control register R/W 00000000B
000BHWPCR Watch prescaler control register R/W 00000000B
000CHWDTC Watchdog timer control register R/W 00000000B
000DHSYCC2 System clock control register 2 R/W XX100011B
000EH
to
0015H
— (Disabled) — —
0016HPDR6 Port 6 data register R/W 00000000B
0017HDDR6 Port 6 direction register R/W 00000000B
0018H
to
0027H
— (Disabled) — —
0028HPDRF Port F data register R/W 00000000B
0029HDDRF Port F direction register R/W 00000000B
002AHPDRG Port G data register R/W 00000000B
002BHDDRG Port G direction register R/W 00000000B
002CHPUL0 Port 0 pull-up register R/W 00000000B
002DH
to
0034H
— (Disabled) — —
0035HPULG Port G pull-up register R/W 00000000B
0036HT01CR1 8/16-bit composite timer 01 status control register 1 ch. 0 R/W 00000000B
0037HT00CR1 8/16-bit composite timer 00 status control register 1 ch. 0 R/W 00000000B
0038HT11CR1 8/16-bit composite timer 11 status control register 1 ch. 1 R/W 00000000B
0039HT10CR1 8/16-bit composite timer 10 status control register 1 ch. 1 R/W 00000000B
003AH
to
0048H
— (Disabled) — —
0049HEIC10 External interrupt circuit control register ch. 2/ch. 3 R/W 00000000B
MB95200H/210H Series
DS07-12623-5E 21
(Continued)
Address Register
abbreviation Register name R/W Initial value
004AHEIC20 External interrupt circuit control register ch. 4/ch. 5 R/W 00000000B
004BHEIC30 External interrupt circuit control register ch. 6/ch. 7 R/W 00000000B
004CH
to
004FH
— (Disabled) — —
0050HSCR LIN-UART serial control register R/W 00000000B
0051HSMR LIN-UART serial mode register R/W 00000000B
0052HSSR LIN-UART serial status register R/W 00001000B
0053HRDR/TDR LIN-UART receive/transmit data register R/W 00000000B
0054HESCR LIN-UART extended status control register R/W 00000100B
0055HECCR LIN-UART extended communication control register R/W 000000XXB
0056H
to
006BH
— (Disabled) — —
006CHADC1 8/10-bit A/D converter control register 1 R/W 00000000B
006DHADC2 8/10-bit A/D converter control register 2 R/W 00000000B
006EHADDH 8/10-bit A/D converter data register (Upper) R/W 00000000B
006FHADDL 8/10-bit A/D converter data register (Lower) R/W 00000000B
0070H
to
0071H
— (Disabled) — —
0072HFSR Flash memory status register R/W 000X0000B
0073H
to
0075H
— (Disabled) — —
0076HWREN Wild register address compare enable register R/W 00000000B
0077HWROR Wild register data test setting register R/W 00000000B
0078H—Mirror of register bank pointer (RP) and direct bank pointer
(DP) ——
0079HILR0 Interrupt level setting register 0 R/W 11111111B
007AHILR1 Interrupt level setting register 1 R/W 11111111B
007BHILR2 Interrupt level setting register 2 R/W 11111111B
007CHILR3 Interrupt level setting register 3 R/W 11111111B
007DHILR4 Interrupt level setting register 4 R/W 11111111B
007EHILR5 Interrupt level setting register 5 R/W 11111111B
007FH— (Disabled) — —
0F80HWRARH0 Wild register address setting register (Upper) ch. 0 R/W 00000000B
MB95200H/210H Series
22 DS07-12623-5E
p
(Continued)
Address Register
abbreviation Register name R/W Initial value
0F81HWRARL0 Wild register address setting register (Lower) ch. 0 R/W 00000000B
0F82HWRDR0 Wild register data setting register ch. 0 R/W 00000000B
0F83HWRARH1 Wild register address setting register (Upper) ch. 1 R/W 00000000B
0F84HWRARL1 Wild register address setting register (Lower) ch. 1 R/W 00000000B
0F85HWRDR1 Wild register data setting register ch. 1 R/W 00000000B
0F86HWRARH2 Wild register address setting register (Upper) ch. 2 R/W 00000000B
0F87HWRARL2 Wild register address setting register (Lower) ch. 2 R/W 00000000B
0F88HWRDR2 Wild register data setting register ch. 2 R/W 00000000B
0F89H
to
0F91H
— (Disabled) — —
0F92HT01CR0 8/16-bit composite timer 01 status control register 0 ch. 0 R/W 00000000B
0F93HT00CR0 8/16-bit composite timer 00 status control register 0 ch. 0 R/W 00000000B
0F94HT01DR 8/16-bit composite timer 01 data register ch. 0 R/W 00000000B
0F95HT00DR 8/16-bit composite timer 00 data register ch. 0 R/W 00000000B
0F96HTMCR0 8/16-bit composite timer 00/01 timer mode control register
ch. 0 R/W 00000000B
0F97HT11CR0 8/16-bit composite timer 11 status control register 0 ch. 1 R/W 00000000B
0F98HT10CR0 8/16-bit composite timer 10 status control register 0 ch. 1 R/W 00000000B
0F99HT11DR 8/16-bit composite timer 11 data register ch. 1 R/W 00000000B
0F9AHT10DR 8/16-bit composite timer 10 data register ch. 1 R/W 00000000B
0F9BHTMCR1 8/16-bit composite timer 10/11 timer mode control register
ch. 1 R/W 00000000B
0F9CH
to
0FBBH
— (Disabled) — —
0FBCHBGR1 LIN-UART baud rate generator register 1 R/W 00000000B
0FBDHBGR0 LIN-UART baud rate generator register 0 R/W 00000000B
0FBEH
to
0FC2H
— (Disabled) — —
0FC3HAIDRL A/D input disable register (Lower) R/W 00000000B
0FC4H
to
0FE3H
— (Disabled) — —
0FE4HCRTH Main CR clock trimming register (Upper) R/W 1XXXXXXXB
0FE5HCRTL Main CR clock trimming register (Lower) R/W 000XXXXXB
MB95200H/210H Series
DS07-12623-5E 23
(Continued)
• R/W access symbols
• Initial value symbols
Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an undefined value is returned.
Address Register
abbreviation Register name R/W Initial value
0FE6H
to
0FE7H
— (Disabled) — —
0FE8HSYSC System configuration register R/W 11000011B
0FE9HCMCR Clock monitoring control register R/W XX000000B
0FEAHCMDR Clock monitoring data register R/W 00000000B
0FEBHWDTH Watchdog timer selection ID register (Upper) R/W XXXXXXXXB
0FECHWDTL Watchdog timer selection ID register (Lower) R/W XXXXXXXXB
0FEDH— (Disabled) — —
0FEEHILSR Input level select register R/W 00000000B
0FEFH
to
0FFFH
— (Disabled) — —
R/W : Readable / Writable
R : Read only
W : Write only
0 : The initial value of this bit is “0”.
1 : The initial value of this bit is “1”.
X : The initial value of this bit is undefined.
MB95200H/210H Series
24 DS07-12623-5E
■I/O MAP (MB95210H Series)
(Continued)
Address Register
abbreviation Register name R/W Initial value
0000HPDR0 Port 0 data register R/W 00000000B
0001HDDR0 Port 0 direction register R/W 00000000B
0002HPDR1 Port 1 data register R/W 00000000B
0003HDDR1 Port 1 direction register R/W 00000000B
0004H— (Disabled) — —
0005HWATR Oscillation stabilization wait time setting register R/W 11111111B
0006H— (Disabled) — —
0007HSYCC System clock control register R/W XXXXXX11B
0008HSTBC Standby control register R/W 00000XXXB
0009HRSRR Reset source register R XXXXXXXXB
000AHTBTC Timebase timer control register R/W 00000000B
000BHWPCR Watch prescaler control register R/W 00000000B
000CHWDTC Watchdog timer control register R/W 00000000B
000DHSYCC2 System clock control register 2 R/W XX100011B
000EH
to
0015H
— (Disabled) — —
0016H— (Disabled) — —
0017H— (Disabled) — —
0018H
to
0027H
— (Disabled) — —
0028HPDRF Port F data register R/W 00000000B
0029HDDRF Port F direction register R/W 00000000B
002AH— (Disabled) — —
002BH— (Disabled) — —
002CHPUL0 Port 0 pull-up register R/W 00000000B
002DH
to
0034H
— (Disabled) — —
0035H— (Disabled) — —
0036HT01CR1 8/16-bit composite timer 01 status control register 1 ch. 0 R/W 00000000B
0037HT00CR1 8/16-bit composite timer 00 status control register 1 ch. 0 R/W 00000000B
0038H— (Disabled) — —
0039H— (Disabled) — —
003AH
to
0048H
— (Disabled) — —
0049H— (Disabled) — —
MB95200H/210H Series
DS07-12623-5E 25
(Continued)
Address Register
abbreviation Register name R/W Initial value
004AHEIC20 External interrupt circuit control register ch. 4 R/W 00000000B
004BHEIC30 External interrupt circuit control register ch. 6 R/W 00000000B
004CH
to
004FH
— (Disabled) — —
0050H— (Disabled) — —
0051H— (Disabled) — —
0052H— (Disabled) — —
0053H— (Disabled) — —
0054H— (Disabled) — —
0055H— (Disabled) — —
0056H
to
006BH
— (Disabled) — —
006CHADC1 8/10-bit A/D converter control register 1 R/W 00000000B
006DHADC2 8/10-bit A/D converter control register 2 R/W 00000000B
006EHADDH 8/10-bit A/D converter data register (Upper) R/W 00000000B
006FHADDL 8/10-bit A/D converter data register (Lower) R/W 00000000B
0070H
to
0071H
— (Disabled) — —
0072HFSR Flash memory status register R/W 000X0000B
0073H
to
0075H
— (Disabled) — —
0076HWREN Wild register address compare enable register R/W 00000000B
0077HWROR Wild register data test setting register R/W 00000000B
0078H—Mirror of register bank pointer (RP) and direct bank pointer
(DP) ——
0079HILR0 Interrupt level setting register 0 R/W 11111111B
007AHILR1 Interrupt level setting register 1 R/W 11111111B
007BH— (Disabled) — —
007CH— (Disabled) — —
007DHILR4 Interrupt level setting register 4 R/W 11111111B
007EHILR5 Interrupt level setting register 5 R/W 11111111B
007FH— (Disabled) — —
0F80HWRARH0 Wild register address setting register (Upper) ch. 0 R/W 00000000B
0F81HWRARL0 Wild register address setting register (Lower) ch. 0 R/W 00000000B
0F82HWRDR0 Wild register data setting register ch. 0 R/W 00000000B
MB95200H/210H Series
26 DS07-12623-5E
(Continued)
Address Register
abbreviation Register name R/W Initial value
0F83HWRARH1 Wild register address setting register (Upper) ch. 1 R/W 00000000B
0F84HWRARL1 Wild register address setting register (Lower) ch. 1 R/W 00000000B
0F85HWRDR1 Wild register data setting register ch. 1 R/W 00000000B
0F86HWRARH2 Wild register address setting register (Upper) ch. 2 R/W 00000000B
0F87HWRARL2 Wild register address setting register (Lower) ch. 2 R/W 00000000B
0F88HWRDR2 Wild register data setting register ch. 2 R/W 00000000B
0F89H
to
0F91H
— (Disabled) — —
0F92HT01CR0 8/16-bit composite timer 01 status control register 0 ch. 0 R/W 00000000B
0F93HT00CR0 8/16-bit composite timer 00 status control register 0 ch. 0 R/W 00000000B
0F94HT01DR 8/16-bit composite timer 01 data register ch. 0 R/W 00000000B
0F95HT00DR 8/16-bit composite timer 00 data register ch. 0 R/W 00000000B
0F96HTMCR0 8/16-bit composite timer 00/01 timer mode control register
ch. 0 R/W 00000000B
0F97H— (Disabled) — —
0F98H— (Disabled) — —
0F99H— (Disabled) — —
0F9AH— (Disabled) — —
0F9BH— (Disabled) — —
0F9CH
to
0FBBH
— (Disabled) — —
0FBCH— (Disabled) — —
0FBDH— (Disabled) — —
0FBEH
to
0FC2H
— (Disabled) — —
0FC3HAIDRL A/D input disable register (Lower) R/W 00000000B
0FC4H
to
0FE3H
— (Disabled) — —
0FE4HCRTH Main CR clock trimming register (Upper) R/W 1XXXXXXXB
0FE5HCRTL Main CR clock trimming register (Lower) R/W 000XXXXXB
0FE6H
to
0FE7H
— (Disabled) — —
0FE8HSYSC System configuration register R/W 11000011B
MB95200H/210H Series
DS07-12623-5E 27
(Continued)
• R/W access symbols
• Initial value symbols
Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an undefined value is returned.
Address Register
abbreviation Register name R/W Initial value
0FE9HCMCR Clock monitoring control register R/W XX000000B
0FEAHCMDR Clock monitoring data register R/W 00000000B
0FEBHWDTH Watchdog timer selection ID register (Upper) R/W XXXXXXXXB
0FECHWDTL Watchdog timer selection ID register (Lower) R/W XXXXXXXXB
0FEDH— (Disabled) — —
0FEEHILSR Input level select register R/W 00000000B
0FEFH
to
0FFFH
— (Disabled) — —
R/W : Readable / Writable
R : Read only
W : Write only
0 : The initial value of this bit is “0”.
1 : The initial value of this bit is “1”.
X : The initial value of this bit is undefined.
MB95200H/210H Series
28 DS07-12623-5E
■INTERRUPT SOURCE TABLE (MB95200H Series)
Interrupt source
Interrupt
request
number
Vector table address
Bit name of
interrupt level
setting register
Priority order of
interrupt sourc-
es of the same
level (occurring
simultaneously)
Upper Lower
External interrupt ch. 4 IRQ0 FFFAHFFFBHL00 [1:0] High
External interrupt ch. 5 IRQ1 FFF8HFFF9HL01 [1:0]
External interrupt ch. 2 IRQ2 FFF6HFFF7HL02 [1:0]
External interrupt ch. 6
External interrupt ch. 3 IRQ3 FFF4HFFF5HL03 [1:0]
External interrupt ch. 7
—IRQ4FFF2
HFFF3HL04 [1:0]
8/16-bit composite timer ch. 0
(Lower) IRQ5 FFF0HFFF1HL05 [1:0]
8/16-bit composite timer ch. 0
(Upper) IRQ6 FFEEHFFEFHL06 [1:0]
LIN-UART (reception) IRQ7 FFECHFFEDHL07 [1:0]
LIN-UART (transmission) IRQ8 FFEAHFFEBHL08 [1:0]
—IRQ9FFE8
HFFE9HL09 [1:0]
—IRQ10FFE6HFFE7HL10 [1:0]
—IRQ11FFE4
HFFE5HL11 [1:0]
—IRQ12FFE2
HFFE3HL12 [1:0]
—IRQ13FFE0
HFFE1HL13 [1:0]
8/16-bit composite timer ch. 1
(Upper) IRQ14 FFDEHFFDFHL14 [1:0]
— IRQ15 FFDCHFFDDHL15 [1:0]
— IRQ16 FFDAHFFDBHL16 [1:0]
—IRQ17FFD8HFFD9HL17 [1:0]
8/10-bit A/D converter IRQ18 FFD6HFFD7HL18 [1:0]
Timebase timer IRQ19 FFD4HFFD5HL19 [1:0]
Watch prescaler IRQ20 FFD2HFFD3HL20 [1:0]
—IRQ21FFD0
HFFD1HL21 [1:0]
8/16-bit composite timer ch. 1
(Lower) IRQ22 FFCEHFFCFHL22 [1:0]
Flash memory IRQ23 FFCCHFFCDHL23 [1:0] Low
MB95200H/210H Series
DS07-12623-5E 29
■INTERRUPT SOURCE TABLE (MB95210H Series)
Interrupt source
Interrupt
request
number
Vector table address
Bit name of
interrupt level
setting register
Priority order of
interrupt sourc-
es of the same
level (occurring
simultaneously)
Upper Lower
External interrupt ch. 4 IRQ0 FFFAHFFFBHL00 [1:0] High
—IRQ1 FFF8HFFF9HL01 [1:0]
—IRQ2 FFF6HFFF7HL02 [1:0]
External interrupt ch. 6
—IRQ3 FFF4HFFF5HL03 [1:0]
—
—IRQ4FFF2
HFFF3HL04 [1:0]
8/16-bit composite timer ch. 0
(Lower) IRQ5 FFF0HFFF1HL05 [1:0]
8/16-bit composite timer ch. 0
(Upper) IRQ6 FFEEHFFEFHL06 [1:0]
—IRQ7FFECHFFEDHL07 [1:0]
—IRQ8FFEA
HFFEBHL08 [1:0]
—IRQ9FFE8
HFFE9HL09 [1:0]
—IRQ10FFE6HFFE7HL10 [1:0]
—IRQ11FFE4
HFFE5HL11 [1:0]
—IRQ12FFE2
HFFE3HL12 [1:0]
—IRQ13FFE0
HFFE1HL13 [1:0]
— IRQ14 FFDEHFFDFHL14 [1:0]
— IRQ15 FFDCHFFDDHL15 [1:0]
— IRQ16 FFDAHFFDBHL16 [1:0]
—IRQ17FFD8HFFD9HL17 [1:0]
8/10-bit A/D converter IRQ18 FFD6HFFD7HL18 [1:0]
Timebase timer IRQ19 FFD4HFFD5HL19 [1:0]
Watch prescaler IRQ20 FFD2HFFD3HL20 [1:0]
—IRQ21FFD0
HFFD1HL21 [1:0]
— IRQ22 FFCEHFFCFHL22 [1:0]
Flash memory IRQ23 FFCCHFFCDHL23 [1:0] Low
MB95200H/210H Series
30 DS07-12623-5E
■ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Symbol Rating Unit Remarks
Min Max
Power supply voltage*1VCC VSS−0.3 VSS+6V
Input voltage*1VI1 VSS−0.3 VCC+0.3 V Other than PF2*2
VI2 VSS−0.3 10.5 V PF2
Output voltage*1VOVSS−0.3 VSS+6V*2
Maximum clamp current ICLAMP -2 +2 mA Applicable to pins listed in *3
Total maximum clamp
current Σ|ICLAMP| — 20 mA Applicable to pins listed in *3
“L” level maximum
output current
IOL1 —15 mA Other than P05, P06, P62 and P63*4
IOL2 15 P05, P06, P62 and P63*4
“L” level average current
IOLAV1
—
4
mA
Other than P05, P06, P62 and P63*4
Average output current =
operating current × operating ratio
(1 pin)
IOLAV2 12
P05, P06, P62 and P63*4
Average output current =
operating current × operating ratio
(1 pin)
“L” level total maximum
output current ΣIOL — 100 mA
“L” level total average
output current ΣIOLAV —50mA
Total average output current =
operating current × operating ratio
(Total number of pins)
“H” level maximum
output current
IOH1 —-15 mA Other than P05, P06, P62 and P63*4
IOH2 -15 P05, P06, P62 and P63*4
“H” level average
current
IOHAV1
—
-4
mA
Other than P05, P06, P62 and P63*4
Average output current =
operating current × operating ratio
(1 pin)
IOHAV2 -8
P05, P06, P62 and P63*4
Average output current =
operating current × operating ratio
(1 pin)
“H” level total maximum
output current ΣIOH —-100mA
“H” level total average
output current ΣIOHAV —-50mA
Total average output current =
operating current × operating ratio
(Total number of pins)
Power consumption Pd — 320 mW
Operating temperature TA-40 +85 °C
Storage temperature Tstg -55 +150 °C
MB95200H/210H Series
DS07-12623-5E 31
*1: The parameter is based on VSS = 0.0 V.
*2: VI and VO must not exceed VCC+0.3 V. VI must not exceed the rated voltage. However, if the maximum current
to/from an input is limited by means of an external component, the ICLAMP rating is used instead of the VI rating.
*3: Applicable to the following pins: P00 to P07, P62 to P64, PG1, PG2, PF0, PF1 (P00 to P03, P07, P62 to P64,
PG1, PG2, PF0 and PF1 are available in MB95F204H/F203H/F202H/F204K/F203K/F202K.)
• Use under recommended operating conditions.
• Use with DC voltage (current).
• The HV (High Voltage) signal is an input signal exceeding the VCC voltage. Always connect a limiting resistor
between the HV (High Voltage) signal and the microcontroller before applying the HV (High Voltage) signal.
• The value of the limiting resistor should be set to a value at which the current to be input to the microcontroller
pin when the HV (High Voltage) signal is input is below the standard value, irrespective of whether the current
is transient current of stationary current.
• When the microcontroller drive current is low, such as in low power consumption modes, the HV (High Voltage)
input potential may pass through the protective diode to increase the potential of the VCC pin, affecting other
devices.
• If the HV (High Voltage) signal is input when the microcontroller power supply is off (not fixed at 0 V), since
power is supplied from the pins, incomplete operations may be executed.
• If the HV (High Voltage) input is input after power-on, since power is supplied from the pins, the voltage of
power supply may not be sufficient to enable a power-on reset.
• Do not leave the HV (High Voltage) input pin unconnected.
• Example of a recommended circuit:
*4: P62 and P63 are available in MB95F204H/F203H/F202H/F204K/F203K/F202K.
WARNING: A semiconductor device may be damaged by applying stress (voltage, current, temperature, etc.) in
excess of the absolute maximum rating. Therefore, ensure that not a single parameter exceeds its
absolute maximum rating.
HV(High Voltage) input (0 V to 16 V)
Protective diode
VCC
N-ch
P-ch
R
Limiting
resistor
• Input/Output Equivalent Circuit
MB95200H/210H Series
32 DS07-12623-5E
2. Recommended Operating Conditions
(VSS=0.0 V)
*1: The value varies depending on the operating frequency, the machine clock and the analog guaranteed range.
*2: The value is 2.88 V when the low-voltage detection reset is used.
*3: Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The bypass capacitor for the
VCC pin must have a capacitance larger than CS. For the connection to a smoothing capacitor CS, see the diagram
below. To prevent the device from unintentionally entering an unknown mode due to noise, minimize the distance
between the C pin and CS and the distance between CS and the VSS pin when designing the layout of a printed
circuit board.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the electrical characteristics of the device are warranted when the device
is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact sales
representatives beforehand.
Parameter Symbol Value Unit Remarks
Min Max
Power supply
voltage VCC
2.4*1*25.5*1
V
In normal operation Other than on-chip debug
mode
2.3 5.5 Hold condition in stop mode
2.9 5.5 In normal operation On-chip debug mode
2.3 5.5 Hold condition in stop mode
Smoothing
capacitor CS0.022 1 µF *3
Operating
temperature TA
-40 +85 °COther than on-chip debug function
+5 +35 On-chip debug function
DBG / RSTX / C pin connection diagram
C
Cs
RSTX
DBG
*
Since the DBG pin becomes a communication pin in on-chip debug mode,
set a pull-up resistor value suiting the input/output specifications of P12/DBG.
*:
MB95200H/210H Series
DS07-12623-5E 33
3. DC Characteristics
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to +85°C)
(Continued)
Parameter Symbol Pin name Condition Value Unit Remarks
Min Typ Max
“H” level
input voltage
VIHI P04 *10.7 VCC —VCC+0.3 V
When CMOS input
level (hysteresis
input) is selected
VIHS
P00 to P07,
P12,
P62 to P64,
PF0 to PF1,
PG1 to PG2
*10.8 VCC —VCC+0.3 V Hysteresis input
VIHM PF2 — 0.7 VCC — 10.5 V Hysteresis input*5
“L” level
input voltage
VIL P04 *1VSS−0.3 — 0.3 VCC V
When CMOS input
level (hysteresis
input) is selected
VILS
P00 to P07,
P12,
P62 to P64,
PF0 to PF1,
PG1 to PG2
*1VSS−0.3 — 0.2 VCC V Hysteresis input
VILM PF2 — VSS−0.3 — 0.3 VCC V Hysteresis input
Open-drain
output
application
voltage
VDPF2, P12 — VSS−0.3 — VSS+5.5 V
“H” level
output
voltage
VOH1
Output pins
other than P05,
P06, P62, P63,
PF2 and P12*2
IOH = -4 mA VCC−0.5 — — V
VOH2 P05, P06, P62,
P63*2 IOH = -8 mA VCC−0.5 — — V
“L” level
output
voltage
VOL1
Output pins
other than P05,
P06, P62 and
P63*2
IOL = 4 mA — — 0.4 V
VOL2 P05, P06, P62,
P63*2 IOL = 2 mA — — 0.4 V
Input leak
current (Hi-Z
output leak
current)
ILI All input pins 0.0 V < VI < VCC -5 — +5 µA
When pull-up
resistance is
disabled
Pull-up
resistance RPULL P00 to P07,
PG1, PG2*3 VI = 0 V 25 50 100 kΩ
When pull-up
resistance is
enabled
MB95200H/210H Series
34 DS07-12623-5E
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to +85°C)
(Continued)
Parameter Symbol Pin name Condition Value Unit Remarks
Min Typ Max
Input
capacitance CIN Other than VCC
and VSS f = 1 MHz — 5 15 pF
Power
supply
current*4
ICC
VCC
(External clock
operation)
VCC = 5.5 V
FCH = 32 MHz
FMP = 16 MHz
Main clock mode
(divided by 2)
—13 17 mA
Flash memory
product (except
writing and
erasing)
—33.539.5 mA
Flash memory
product (at writing
and erasing)
— 15 21 mA At A/D conversion
ICCS
VCC = 5.5 V
FCH = 32 MHz
FMP = 16 MHz
Main sleep mode
(divided by 2)
—5.5 9 mA
ICCL
VCC = 5.5 V
FCL = 32 kHz
FMPL = 16 kHz
Subclock mode
(divided by 2)
TA = +25 °C
— 65 153 µA
ICCLS
VCC = 5.5 V
FCL = 32 kHz
FMPL = 16 kHz
Subsleep mode
(divided by 2)
TA = +25 °C
—10 84 µA
ICCT
VCC = 5.5 V
FCL = 32 kHz
Watch mode
Main stop mode
TA = +25°C
— 5 30 µA
MB95200H/210H Series
DS07-12623-5E 35
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to +85°C)
*1: The input level of P04 can be switched between “CMOS input level” and “hysteresis input level”. The input level
selection register (ILSR) is used to switch between the two input levels.
*2: P62 and P63 are available in MB95F204H/F203H/F202H/F204K/F203K/F202K.
*3: P00 to P03, P07, PG1 and PG2 are available in MB95F204H/F203H/F202H/F204K/F203K/F202K.
(Continued)
Parameter Symbol Pin name Condition Value Unit Remarks
Min Typ Max
Power
supply
current*4
ICCMCR
VCC
VCC = 5.5 V
FCRH = 10 MHz
FMP = 10 MHz
Main CR clock
mode
—8.6—mA
ICCSCR
VCC = 5.5 V
Sub-CR clock
mode
(divided by 2)
TA = +25 °C
— 110 410 µA
ICCTS VCC
(External clock
operation)
VCC = 5.5 V
FCH = 32 MHz
Timebase timer
mode
TA = +25 °C
—1.1 3mA
ICCH
VCC = 5.5 V
Substop mode
TA = +25 °C
— 3.5 22.5 µA
Main stop mode
for single clock
selection
ILVD
VCC
Current
consumption for
low-voltage
detection circuit
only
—3754µA
ICRH
Current
consumption for
the internal main
CR oscillator
—0.50.6mA
ICRL
Current
consumption for
the internal sub-CR
oscillator
oscillating at
100 kHz
—2072µA
MB95200H/210H Series
36 DS07-12623-5E
(Continued)
*4: • The power supply current is determined by the external clock. When the low-voltage detection option is
selected, the power-supply current will be the sum of adding the current consumption of the low-voltage
detection circuit (ILVD) to a specified value. In addition, when both the low-voltage detection option and the CR
oscillator are selected, the power supply current will be the sum of adding up the current consumption of the
low-voltage detection circuit, the current consumption of the CR oscillators (ICRH, ICRL) and a specified value.
In on-chip debug mode, the CR oscillator (ICRH) and the low-voltage detection circuit are always enabled, and
current consumption therefore increases accordingly.
• See "4. AC Characteristics: (1) Clock Timing" for FCH and FCL.
• See "4. AC Characteristics: (2) Source Clock/Machine Clock" for FMP and FMPL.
*5 : PF2 act as high voltage supply for the flash memory during program and erase. It can tolerate high voltage
input. For details, see section “6. Flash Memory Program/Erase Characteristics”.
MB95200H/210H Series
DS07-12623-5E 37
4. AC Characteristics
(1) Clock Timing
(VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = -40°C to +85°C)
(Continued)
Parameter Symbol Pin name Condition Value Unit Remarks
Min Typ Max
Clock frequency
FCH
X0, X1 — 1 — 16.25 MHz When the main oscillation
circuit is used
X0 X1 open 1 — 12 MHz
When the main external
clock is used
X0, X1 *
1 — 32.5 MHz
HCLK1,
HCLK2 —
FCRH ——
9.7 10 10.3 MHz When the main CR clock is
used
3.3 V ≤ Vcc ≤ 5.5 V(-40 °C ≤ TA ≤ 40 °C)
2.4 V ≤ Vcc < 3.3 V(0 °C ≤ TA ≤ 40 °C)
7.76 8 8.24 MHz
0.97 1 1.03 MHz
9.55 10 10.45 MHz When the main CR clock is
used
3.3 V ≤ Vcc ≤ 5.5 V (40 °C < TA ≤ 85 °C)
7.64 8 8.36 MHz
0.955 1 1.045 MHz
9.5 10 10.5 MHz When the main CR clock is
used
2.4 V ≤ Vcc < 3.3 V
(-40 °C ≤ TA < 0 °C, 40 °C < TA ≤ 85 °C)
7.6 8 8.4 MHz
0.95 1 1.05 MHz
FCL X0A, X1A —
−32.768 — kHz When the sub oscillation
circuit is used
−32.768 — kHz When the sub-external
clock is used
FCRL — — 50 100 200 kHz When the sub-CR clock is
used
Clock cycle time tHCYL
X0, X1 — 61.5 — 1000 ns When the main oscillation
circuit is used
X0 X1 open 83.4 — 1000 ns
When the external clock is
used
X0, X1 *
30.8 — 1000 ns
HCLK1,
HCLK2 —
tLCYL X0A, X1A — — 30.5 — µs When the subclock is used
Input clock pulse
width
tWH1
tWL1
X0 X1 open 33.4 — — ns
When the external clock is
used, the duty ratio should
range between 40% and
60%.
X0, X1 *
12.4 — — ns
HCLK1,
HCLK2 —
tWH2
tWL2 X0A — — 15.2 — µs
MB95200H/210H Series
38 DS07-12623-5E
(Continued)
(VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = -40°C to +85°C)
* : The external clock signal is input to X0 and the inverted external clock signal to X1.
Parameter Symbol Pin name Condition Value Unit Remarks
Min Typ Max
Input clock rise
time and fall time
tCR
tCF
X0 X1 open — — 5 ns
When the external clock is
used
X0, X1 *
—— 5ns
HCLK1,
HCLK2 —
CR oscillation
start time
tCRHWK ————80µs
When the main CR clock is
used
tCRLWK ————10µs
When the sub-CR clock is
used
MB95200H/210H Series
DS07-12623-5E 39
X0, X1, HCLK1, HCLK2 0.8 V
CC
0.2 V
CC
0.2 V
CC
0.8 V
CC
t
WH1
t
WL1
0.2 V
CC
t
HCYL
t
CR
t
CF
Figure of main clock input port external connection
When a crystal oscillator or
a ceramic oscillator is used
X0 X1
F
CH
When the external clock is
used
X0 X1
F
CH
When the external clock is
used
HCLK1/HCLK2
F
CH
When the external clock is used
(X1 is open)
X0 X1
Open
F
CH
X0A 0.8 V
CC
0.2 V
CC
0.2 V
CC
0.8 V
CC
t
WH2
t
WL2
0.2 V
CC
t
LCYL
t
CR
t
CF
Figure of subclock input port external connection
When a crystal oscillator or
a ceramic oscillator is used
When the external clock is used
X0A X1A X0A X1A
Open
F
CL
F
CL
MB95200H/210H Series
40 DS07-12623-5E
(2) Source Clock/Machine Clock
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to +85°C)
*1: This is the clock before it is divided according to the division ratio set by the machine clock division ratio selection
bits (SYCC : DIV1 and DIV0) . This source clock is divided to become a machine clock according to the division
ratio set by the machine clock division ratio selection bits (SYCC : DIV1 and DIV0) . In addition, a source clock
can be selected from the following.
• Main clock divided by 2
• Main CR clock
• Subclock divided by 2
• Sub-CR clock divided by 2
(Continued)
Parameter Symbol Pin
name
Value Unit Remarks
Min Typ Max
Source clock
cycle time*1tSCLK —
61.5 — 2000 ns
When the main external clock is used
Min: FCH = 32.5 MHz, divided by 2
Max: FCH = 1 MHz, divided by 2
100 — 1000 ns
When the main CR clock is used
Min: FCRH = 10 MHz
Max: FCRH = 1 MHz
—61—µs
When the sub-CR clock is used
FCL = 32.768 kHz, divided by 2
—20—µs
When the sub-oscillation clock is used
FCRL = 100 kHz, divided by 2
Source clock
frequency
FSP
—
0.5 — 16.25 MHz When the main oscillation clock is used
1 — 10 MHz When the main CR clock is used
FSPL
— 16.384 — kHz When the sub-oscillation clock is used
—50—kHz
When the sub-CR clock is used
FCRL = 100 kHz, divided by 2
Machine clock
cycle time*2
(minimum
instruction
execution time)
tMCLK —
61.5 — 32000 ns
When the main oscillation clock is used
Min: FSP = 16.25 MHz, no division
Max: FSP = 0.5 MHz, divided by 16
100 — 16000 ns
When the main CR clock is used
Min: FSP = 10 MHz
Max: FSP = 1 MHz, divided by 16
61 — 976.5 µs
When the sub-oscillation clock is used
Min: FSPL = 16.384 kHz, no division
Max: FSPL = 16.384 kHz, divided by 16
20 — 320 µs
When the sub-CR clock is used
Min: FSPL = 50 kHz, no division
Max: FSPL = 50 kHz, divided by 16
Machine clock
frequency
FMP
—
0.031 — 16.25 MHz When the main oscillation clock is used
0.0625 — 10 MHz When the main CR clock is used
FMPL
1.024 — 16.384 kHz When the sub-oscillation clock is used
3.125 — 50 kHz When the sub-CR clock is used
FCRL = 100 kHz
MB95200H/210H Series
DS07-12623-5E 41
(Continued)
*2: This is the operating clock of the microcontroller. A machine clock can be selected from the following.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
MB95200H/210H Series
42 DS07-12623-5E
Schematic diagram of the clock generation block
F
CH
(main oscillation)
F
CRH
(Internal main
CR clock)
F
CL
(sub-oscillation) F
CRL
(Internal sub-
CR clock)
SCLK
(source clock)
MCLK
(machine clock)
Clock mode select bits
(SYCC2: RCS1, RCS0)
Machine clock division
ratio select bits
(SYCC : DIV1, DIV0)
Division
circuit
x
x
x
x
1
1/4
1/8
1/16
Divided
by 2
Divided
by 2
Divided
by 2
Operating voltage (V)
A/D converter operation range
5.5
5.0
4.0
3.5
3.0
2.4
16 kHz 3 MHz 10 MHz 16.25 MHz
Source clock frequency (F
SP
/F
SPL
)
Operating voltage (V)
A/D converter operation range
5.5
5.0
4.0
3.5
3.0
2.9
16 kHz 3 MHz 12.5 MHz 16.25 MHz
Source clock frequency (F
SP
)
Operating voltage - Operating frequency (When TA = -40 oC to +85 oC)
MB95200H/210H (without the on-chip debug function)
Operating voltage - Operating frequency (When TA = +5 oC to +35 oC)
MB95200H/210H (with the on-chip debug function)
MB95200H/210H Series
DS07-12623-5E 43
(3) External Reset
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to +85°C)
*1: See “(2) Source Clock/Machine Clock” for tMCLK.
*2: The oscillation time of an oscillator is the time that the amplitude reaches 90%. The crystal oscillator has an
oscillation time of between several ms and tens of ms. The ceramic oscillator has an oscillation time of between
hundreds of µs and several ms. The external clock has an oscillation time of 0 ms. The CR oscillator clock has
an oscillation time of between several µs and several ms.
Parameter Symbol Value Unit Remarks
Min Max
RSTX “L” level
pulse width tRSTL
2 tMCLK*1— ns In normal operation
Oscillation time of the
oscillator*2+100 —µs
In stop mode, subclock mode,
sub-sleep mode, watch mode,
and power on
100 — µs In timebase timer mode
0.2 VCC
RSTX
0.2 VCC
tRSTL
0.2 VCC 0.2 VCC
100 μs
RSTX
X0
Internal
operating
clock
90% of
amplitude
Oscillation
time of
oscillator Oscillation stabilization wait time
Execute instructionInternal reset
In normal operation
In stop mode, sub-clock mode, sub-sleep mode, watch mode, and power-on
tRSTL
MB95200H/210H Series
44 DS07-12623-5E
(4) Power-on Reset
(VSS = 0.0 V, TA = -40°C to +85°C)
Parameter Symbol Condition Value Unit Remarks
Min Max
Power supply rising time tR——50ms
Power supply cutoff time tOFF — 1 — ms Wait time until power-on
0.2 V0.2 V
tOFFtR
2.5 V
0.2 V
VCC
VCC
2.3 V
VSS
Hold condition in stop mode
Limiting the slope of rising within
30 mV/ms is recommended.
A sudden change of power supply voltage may activate the power-on
reset function. When changing the power supply voltage during the
operation, set the slope of rising to within 30 mV/ms as shown below.
Note:
MB95200H/210H Series
DS07-12623-5E 45
(5) Peripheral Input Timing
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to +85°C)
*1: See “(2) Source Clock/Machine Clock” for tMCLK.
*2: INT02, INT03, INT05, INT07 and EC1 are available in MB95F204H/F203H/F202H/F204K/F203K/F202K.
Parameter Symbol Pin name Value Unit
Min Max
Peripheral input “H” pulse width tILIH INT02 to INT07, EC0, EC1*2 2 tMCLK*1 —ns
Peripheral input “L” pulse width tIHIL 2 tMCLK*1 —ns
INT02 to INT07,
EC0, EC1*2
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
tILIH tIHIL
MB95200H/210H Series
46 DS07-12623-5E
(6) LIN-UART Timing (Available in MB95F204H/F203H/F202H/F204K/F203K/F202K only)
Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is disabled*2.
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0)
(VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = -40°C to +85°C)
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a
falling edge of the serial clock.
*2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.
*3: See “(2) Source Clock/Machine Clock” for tMCLK.
Parameter Symbol Pin name Condition Value Unit
Min Max
Serial clock cycle time tSCYC SCK
Internal clock
operation output pin:
CL = 80 pF+1 TTL
5 tMCLK*3—ns
SCK ↓→ SOT delay time tSLOVI SCK, SOT -95 +95 ns
Valid SIN → SCK ↑tIVSHI SCK, SIN tMCLK*3+190 — ns
SCK ↑→ valid SIN hold time tSHIXI SCK, SIN 0 — ns
Serial clock “L” pulse width tSLSH SCK
External clock
operation output pin:
CL = 80 pF+1 TTL
3 tMCLK*3−tR—ns
Serial clock “H” pulse width tSHSL SCK tMCLK*3+95 — ns
SCK ↓→ SOT delay time tSLOVE SCK, SOT — 2 tMCLK*3+95 ns
Valid SIN → SCK ↑tIVSHE SCK, SIN 190 — ns
SCK ↑→ valid SIN hold time tSHIXE SCK, SIN tMCLK*3+95 — ns
SCK fall time tFSCK — 10 ns
SCK rise time tRSCK — 10 ns
MB95200H/210H Series
DS07-12623-5E 47
0.8 V 0.8 V
2.4 V
t
SLOVI
t
IVSHI
t
SHIXI
2.4 V
0.8 V
SCK
SOT
SIN
0.8 V
CC
0.2 V
CC
0.8 V
CC
0.2 V
CC
t
SCYC
Internal shift clock mode
SCK
SOT
SIN
t
SLOVE
t
IVSHE
t
SHIXE
2.4 V
0.8 V
t
F
t
R
t
SLSH
t
SHSL
0.8 V
CC
0.2 V
CC
0.8 V
CC
0.2 V
CC
0.8 V
CC
0.8 V
CC
0.8 V
CC
0.2 V
CC
0.2 V
CC
External shift clock mode
MB95200H/210H Series
48 DS07-12623-5E
Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is disabled*2.
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0)
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to +85°C)
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a
falling edge of the serial clock.
*2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.
*3: See “(2) Source Clock/Machine Clock” for tMCLK.
Parameter Symbol Pin name Condition Value Unit
Min Max
Serial clock cycle time tSCYC SCK
Internal clock
operation output pin:
CL = 80 pF+1 TTL
5 tMCLK*3—ns
SCK ↑→ SOT delay time tSHOVI SCK, SOT -95 +95 ns
Valid SIN → SCK ↓tIVSLI SCK, SIN tMCLK*3+190 — ns
SCK ↓→ valid SIN hold time tSLIXI SCK, SIN 0 — ns
Serial clock “H” pulse width tSHSL SCK
External clock
operation output pin:
CL = 80 pF+1 TTL
3 tMCLK*3−tR—ns
Serial clock “L” pulse width tSLSH SCK tMCLK*3+95 −—ns
SCK ↑→ SOT delay time tSHOVE SCK, SOT — 2 tMCLK*3+95 ns
Valid SIN → SCK ↓tIVSLE SCK, SIN 190 — ns
SCK ↓→ valid SIN hold time tSLIXE SCK, SIN tMCLK*3+95 — ns
SCK fall time tFSCK — 10 ns
SCK rise time tRSCK — 10 ns
MB95200H/210H Series
DS07-12623-5E 49
2.4 V 2.4 V
0.8 V
tSHOVI
tIVSLI tSLIXI
2.4 V
0.8 V
SCK
SOT
SIN
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
tSCYC
Internal shift clock mode
SCK
SOT
SIN
tSHOVE
tIVSLE tSLIXE
2.4 V
0.8 V
tF
tR
tSHSL tSLSH
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
0.2 VCC0.2 VCC 0.2 VCC
0.8 VCC
0.8 VCC
External shift clock mode
MB95200H/210H Series
50 DS07-12623-5E
Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is enabled*2.
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1)
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to +85°C)
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a
falling edge of the serial clock.
*2: The serial clock delay function is a function that delays the output signal of the serial clock for half clock.
*3: See “(2) Source Clock/Machine Clock” for tMCLK.
Parameter Symbol Pin name Condition Value Unit
Min Max
Serial clock cycle time tSCYC SCK
Internal clock
operation output pin:
CL = 80 pF+1 TTL
5 tMCLK*3—ns
SCK ↑→ SOT delay time tSHOVI SCK, SOT -95 +95 ns
Valid SIN → SCK ↓tIVSLI SCK, SIN tMCLK*3+190 — ns
SCK ↓→ valid SIN hold time tSLIXI SCK, SIN 0 — ns
SOT → SCK ↓ delay time tSOVLI SCK, SOT — 4 tMCLK*3ns
2.4 V
0.8 V 0.8 V
tSHOVI
tSOVLI
tIVSLI tSLIXI
2.4 V
0.8 V
2.4 V
0.8 V
SCK
SOT
SIN 0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
tSCYC
MB95200H/210H Series
DS07-12623-5E 51
Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is enabled*2.
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1)
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to +85°C)
*1:There is a function used to choose whether the sampling of reception data is performed at a rising edge or a
falling edge of the serial clock.
*2: The serial clock delay function is a function that delays the output signal of the serial clock for half clock.
*3: See “ (2) Source Clock/Machine Clock” for tMCLK.
Parameter Symbol Pin name Condition Value Unit
Min Max
Serial clock cycle time tSCYC SCK
Internal clock opera-
tion output pin:
CL = 80 pF+1 TTL
5 tMCLK*3—ns
SCK ↓→ SOT delay time tSLOVI SCK, SOT -95 +95 ns
Valid SIN → SCK ↑tIVSHI SCK, SIN tMCLK*3+190 — ns
SCK ↑→ valid SIN hold time tSHIXI SCK, SIN 0 — ns
SOT → SCK ↑ delay time tSOVHI SCK, SOT — 4 tMCLK*3ns
0.8 V
2.4 V 2.4 V
tSLOVI
tSOVHI
tIVSHI tSHIXI
2.4 V
0.8 V
2.4 V
0.8 V
SCK
SOT
SIN 0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
tSCYC
MB95200H/210H Series
52 DS07-12623-5E
(7) Low-voltage Detection
(VSS = 0.0 V, TA = -40°C to +85°C)
Parameter Symbol Value Unit Remarks
Min Typ Max
Release voltage VDL+2.52 2.7 2.88 V At power supply rise
Detection voltage VDL−2.42 2.6 2.78 V At power supply fall
Hysteresis width VHYS 70 100 — mV
Power supply start voltage Voff ——2.3V
Power supply end voltage Von 4.9 — — V
Power supply voltage
change time
(at power supply rise)
tr
1——µs
Slope of power supply that the reset
release signal generates
— 3000 — µs
Slope of power supply that the reset
release signal generates within the
rating (VDL+)
Power supply voltage
change time
(at power supply fall)
tf
300 — — µs Slope of power supply that the reset
detection signal generates
— 300 — µs
Slope of power supply that the reset
detection signal generates within the
rating (VDL-)
Reset release delay time td1 ——300µs
Reset detection delay time td2 ——20µs
MB95200H/210H Series
DS07-12623-5E 53
VHYS
td2 td1
tr
tf
VCC
Internal reset signal
Von
Voff
VDL+
VDL-
time
time
MB95200H/210H Series
54 DS07-12623-5E
5. A/D Converter
(1) A/D Converter Electrical Characteristics
(VCC = 4.0 V to 5.5 V, VSS = 0.0 V, TA = -40°C to +85°C)
Parameter Symbol Value Unit Remarks
Min Typ Max
Resolution
—
— — 10 bit
Total error -3—+3LSB
Linearity error -2.5 — +2.5 LSB
Differential linear
error -1.9 — +1.9 LSB
Zero transition
voltage VOT VSS−1.5 LSB VSS+0.5 LSB VSS+2.5 LSB V
Full-scale transition
voltage VFST VCC−4.5 LSB VCC−2 LSB VCC+0.5 LSB V
Compare time — 0.9 — 16500 µs 4.5 V ≤ VCC ≤ 5.5 V
1.8 — 16500 µs 4.0 V ≤ VCC < 4.5 V
Sampling time —
0.6 — ∞µs
4.5 V ≤ VCC ≤ 5.5 V,
with external
impedance < 5.4 kΩ
1.2 — ∞µs
4.0 V ≤ VCC ≤ 4.5 V,
with external
impedance < 2.4 kΩ
Analog input current IAIN -0.3 — +0.3 µA
Analog input voltage VAIN VSS —VCC V
MB95200H/210H Series
DS07-12623-5E 55
(2) Notes on Using the A/D Converter
• External impedance of analog input and its sampling time
• The A/D converter has a sample and hold circuit. If the external impedance is too high to keep sufficient
sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely
affecting A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, considering
the relationship between the external impedance and minimum sampling time, either adjust the register value
and operating frequency or decrease the external impedance so that the sampling time is longer than the
minimum value. In addition, if sufficient sampling time cannot be secured, connect a capacitor of about 0.1 µF
to the analog input pin.
• A/D conversion error
As |VCC−VSS| decreases, the A/D conversion error increases proportionately.
ComparatorAnalog input
During sampling: ON
Note: The values are reference values.
~
~~
~
4.5 VV
CC 5.5 V: R 1.95 kΩ (Max), C 17 pF (Max)
~
~~
~
<4.0 VV
CC 4.5 V:R 8.98 kΩ (Max), C 17 pF (Max)
RC
<
<<
• Analog input equivalent circuit
[External impedance = 0 kΩ to 100 kΩ]
External impedance [kΩ]
External impedance [kΩ]
Minimum sampling time [μs] Minimum sampling time [μs]
[External impedance = 0 kΩ to 20 kΩ]
100
90
80
70
60
50
40
30
20
10
0
20
18
16
14
12
10
8
6
4
2
0
0 2 4 6 8 101214 10 234
(VCC >
=4.5 V)
(VCC >
=4.0 V)
(VCC >
=4.5 V)
(VCC >
=4.0 V)
• Relationship between external impedance and minimum sampling time
MB95200H/210H Series
56 DS07-12623-5E
(3) Definitions of A/D Converter Terms
• Resolution
It indicates the level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit: LSB)
It indicates how much an actual conversion value deviates from the straight line connecting
the zero transition point (“00 0000 0000” ← → “00 0000 0001”) of a device to
the full-scale transition point (“11 1111 1111“ ← → “11 1111 1110”) of the same device.
• Differential linear error (unit: LSB)
It indicates how much the input voltage required to change the output code by 1 LSB deviates from an ideal
value.
• Total error (unit: LSB)
It indicates the difference between an actual value and a theoretical value. The error can be caused by a zero
transition error, a full-scale transition errors, a linearity error, a quantum error, or noise.
(Continued)
VSS
VFST
Ideal I/O characteristics
VCC
001
002
003
004
3FD
3FE
3FF
Digital output
Digital output
2.0 LSB
VOT
1 LSB
0.5 LSB
Total error
Analog inputAnalog input
001
002
003
004
3FD
3FE
3FF
Actual conversion
characteristic
Ideal characteristic
Actual conversion
characteristic
N
VNT
: A/D converter digital output value
: Voltage at which the digital output transits from (N - 1) to N
{1 LSB x (N-1) + 0.5 LSB}
VNT
VSS VCC
Total error of
digital output N
VNT - {1 LSB x (N - 1) + 0.5 LSB}
1 LSB [LSB]=
VCC - VSS
1024 (V)1 LSB =
MB95200H/210H Series
DS07-12623-5E 57
(Continued)
Zero transition error
Linearity error
Full-scale transition error
001
002
003
004
3FD
3FE
3FF
Digital output
Differential linear error
of digital output N
V(N+1)T - VNT
1 LSB - 1=
Linearity error
of digital output N
VNT - {1 LSB x N + VOT}
1 LSB
=
Digital output
Analog input
001
002
3FC
3FD
003
3FE
3FF
004
Actual conversion
characteristic
Ideal
characteristic
Actual conversion
characteristic
VOT (measurement value)
Actual conversion
characteristic
Actual conversion
characteristic
VFST
(measurement
value)
VSS VCC
Analog input
VSS VCC
Digital output
Analog input
VSS VCC
Ideal characteristic
{1 LSB x N + V
OT
}
Actual conversion
characteristic
Ideal
characteristic
Actual conversion
characteristic
VOT (measurement value)
VFST
(measurement
value)
VNT
Differential linearity error
N-2
N-1
N
N+1
Digital output
Analog input
VSS VCC
Actual conversion
characteristic
Ideal characteristic
VNT
Actual conversion
characteristic V(N+1)T
N
VNT
: A/D converter digital output value
: Voltage at which the digital output transits from (N - 1) to N
VOT (ideal value) = VSS + 0.5 LSB [V]
VFST (ideal value) = VCC - 2.0 LSB [V]
MB95200H/210H Series
58 DS07-12623-5E
6. Flash Memory Program/Erase Characteristics
*1: TA = +25°C, VCC = 5.0 V, 100000 cycles
*2: TA = +85°C, VCC = 4.5 V, 100000 cycles
*3: This value is converted from the result of a technology reliability assessment. (The value is converted from the
result of a high temperature accelerated test by using the Arrhenius equation with the average temperature being
+85°C) .
Parameter Value Unit Remarks
Min Typ Max
Chip erase time — 1*115*2s00H programming time prior to erasure is
excluded.
Byte programming time — 32 3600 µs System-level overhead is excluded.
Erase/program voltage 9.5 10 10.5 V The erase/program voltage must be
applied to the PF2 pin in erase/program.
Current drawn on PF2 — — 5.0 mA Current consumption of PF2 pin during
flash memory program/erase
Erase/program cycle — 100000 — cycle
Power supply voltage at erase/
program 3.0 — 5.5 V
Flash memory data retention
time 20*3— — year Average TA = +85°C
MB95200H/210H Series
DS07-12623-5E 59
■SAMPLE ELECTRICAL CHARACTERISTICS
• Power supply current•temperature
(Continued)
I
CC
- V
CC
T
A
=+25°C, F
MP
=2, 4, 8, 10, 16 MHz (divided by 2)
Main clock mode with the external clock operating
V
CC
[V]
I
CC
[mA]
F
MP
=16 MHz
F
MP
=10 MHz
F
MP
=8 MHz
F
MP
=4 MHz
F
MP
=2 MHz
234567
20
15
10
5
0
I
CC
- T
A
V
CC
=5.5 V, F
MP
=10, 16 MHz (divided by 2)
Main clock mode with the external clock operating
T
A
[°C]
I
CC
[mA]
-50 0 +50 +100 +150
20
15
10
5
0
F
MP
=16 MHz
F
MP
=10 MHz
I
CCS
- V
CC
T
A
=+25°C, F
MP
=2, 4, 8, 10, 16 MHz (divided by 2)
Main sleep mode with the external clock operating
V
CC
[V]
I
CCS
[mA]
F
MP
=8 MHz
F
MP
=10 MHz
F
MP
=16 MHz
F
MP
=4 MHz
F
MP
=2 MHz
234567
20
15
10
5
0
I
CCS
- T
A
V
CC
=5.5 V, F
MP
=10, 16 MHz (divided by 2)
Main sleep mode with the external clock operating
T
A
[°C]
I
CCS
[mA]
-50 0 +50 +100 +150
20
15
10
5
0
F
MP
=16 MHz
F
MP
=10 MHz
I
CCL
- V
CC
T
A
=+25°C, F
MPL
=16 kHz (divided by 2)
Subclock mode with the external clock operating
V
CC
[V]
I
CCL
[µA]
234567
100
75
50
25
0
ICCL - TA
VCC=5.5 V, FMPL=16 kHz (divided by 2)
Subclock mode with the external clock operating
TA[°C]
ICCL[µA]
-50 0 +50 +100 +150
100
75
50
25
0
MB95200H/210H Series
60 DS07-12623-5E
(Continued)
(Continued)
I
CCLS
- V
CC
T
A
=+25°C, F
MPL
=16 kHz (divided by 2)
Subsleep mode with the external clock operating
V
CC
[V]
I
CCLS
[µA]
234567
100
75
50
25
0
I
CCLS
- T
A
V
CC
=5.5 V, F
MPL
=16 kHz (divided by 2)
Subsleep mode with the external clock operating
T
A
[°C]
I
CCLS
[µA]
-50 0 +50 +100 +150
100
75
50
25
0
I
CCT
- V
CC
T
A
=+25°C, F
MPL
=16 kHz (divided by 2)
Clock mode with the external clock operating
V
CC
[V]
I
CCT
[µA]
2345 67
100
75
50
25
0
I
CCT
- T
A
V=5.5 V, F
MPL
=16 kHz (divided by 2)
Clock mode with the external clock operating
T
A
[°C]
I
CCT
[µA]
-50 0 +50 +100 +150
100
75
50
25
0
ICTS - VCC
TA=+25°C, FMP=2, 4, 8, 10, 16 MHz (divided by 2)
Timebase timer mode with the external clock operating
VCC[V]
ICTS[mA]
234567
2.0
1.5
1.0
0.5
0.0
FMP=2 MHz
FMP=4 MHz
FMP=8 MHz
FMP=16 MHz
FMP=10 MHz
I
CTS
- T
A
V=5.5 V, F
MP
=10, 16 MHz (divided by 2)
Timebase timer mode with the external clock operating
T
A
[°C]
I
CTS
[mA]
-50 0 +50 +100 +150
2.0
1.5
1.0
0.5
0.0
F
MP
=10 MHz
F
MP
=16 MHz
MB95200H/210H Series
DS07-12623-5E 61
(Continued)
ICCH - VCC
TA=+25°C, FMPL=(stop)
Substop mode wtih the external clock stopping
VCC[V]
ICCH[µA]
234567
20
15
10
5
0
ICCH - TA
V=5.5 V, FMPL=(stop)
Substop mode with the external clock stopping
TA[°C]
ICCH[µA]
-50 0 +50 +100 +150
20
15
10
5
0
ICCMCR - VCC
TA=+25°C, FMP=1, 8, 10 MHz (no division)
Main clock mode with the internal main CR clock operating
VCC[V]
ICCMCR[mA]
2345 67
20
15
10
5
0
FMP=8 MHz
FMP=1 MHz
FMP=10 MHz
I
CCMCR
- T
A
V=5.5 V, F
MPL
=1, 8, 10 MHz (no division)
Main clock mode with the internal main CR clock operating
T
A
[°C]
I
CCMCR
[mA]
-50 0 +50 +100 +150
20
15
10
5
0
F
MP
=1 MHz
F
MP
=8 MHz
F
MP
=10 MHz
I
CCSCR
- V
CC
T
A
=+25°C, F
MPL
=50 kHz (divided by 2)
Subclock mode with the internal sub-CR clock operating
V
CC
[V]
I
CCSCR
[µA]
234567
200
150
100
50
0
F
MPL
=50 kHz
I
CCSCR
- T
A
V
CC
=5.5 V, F
MPL
=50 kHz (divided by 2)
Subclock mode with the internal sub-CR clock operating
T
A
[°C]
I
CCSCR
[µA]
-50 0 +50 +100 +150
200
150
100
50
0
F
MPL
=50 kHz
MB95200H/210H Series
62 DS07-12623-5E
• Input voltage
VIHI - VCC and VILI - VCC
TA=+25°C
VCC[V]
VIHI/VILI[V]
234567
5
4
3
2
1
0
VIHI
VILI
VIHS - VCC and VILS - VCC
TA=+25°C
VCC[V]
VIHS/VILS[V]
234567
5
4
3
2
1
0
VILS
VIHS
VIHM - VCC and VILM - VCC
TA=+25°C
VCC[V]
VIHM/VILM[V]
234567
5
4
3
2
1
0
VILM
VIHM
MB95200H/210H Series
DS07-12623-5E 63
• Output voltage
(VCC-VOH1) - IOH
TA=+25°C
IOH[mA]
VCC-VOH1[V]
VCC=2.4 V
VCC=2.7 V
VCC=3.5 V
VCC=4.5 V
VCC=5.0 V
VCC=5.5 V
0 -2 -4 -6 -8 -10
1.0
0.8
0.6
0.4
0.2
0.0
(VCC-VOH2) - IOH
TA=+25°C
IOH[mA]
VCC-VOH2[V]
0 -2 -4 -6 -8 -10
1.0
0.8
0.6
0.4
0.2
0.0
VCC=2.4 V
VCC=2.7 V
VCC=3.5 V
VCC=4.5 V
VCC=5.0 V
VCC=5.5 V
VOL1 - IOL
TA=+25°C
IOL[mA]
VOL1[V]
0246810
1.0
0.8
0.6
0.4
0.2
0.0
VCC=2.4 V
VCC=2.7 V
VCC=3.5 V
VCC=4.5 V
VCC=5.0 V
VCC=5.5 V
VOL2 - IOL
TA=+25°C
IOL[mA]
VOL2[V]
02 4681012
1.0
0.8
0.6
0.4
0.2
0.0
VCC=2.4 V
VCC=2.7 V
VCC=3.5 V
VCC=4.5 V
VCC=5.0 V
VCC=5.5 V
MB95200H/210H Series
64 DS07-12623-5E
• Pull-up
RPULL - VCC
TA=+25°C
VCC[V]
RPULL[kΩ]
23456
250
200
150
100
50
0
MB95200H/210H Series
DS07-12623-5E 65
■MASK OPTIONS
No. Part Number
MB95F204H
MB95F203H
MB95F202H
MB95F214H
MB95F213H
MB95F212H
MB95F204K
MB95F203K
MB95F202K
MB95F214K
MB95F213K
MB95F212K
Selection Method Setting disabled Setting disabled
1
Low-voltage detection reset
• With low-voltage detection
reset
• Without low-voltage detec-
tion reset
Without low-voltage detection
reset
With low-voltage detection
reset
2
Reset
• With dedicated reset input
• Without dedicated reset in-
put
With dedicated reset input Without dedicated reset input
MB95200H/210H Series
66 DS07-12623-5E
■ORDERING INFORMATION
Part Number Package
MB95F204HP-G-SH-SNE2
MB95F204KP-G-SH-SNE2
MB95F203HP-G-SH-SNE2
MB95F203KP-G-SH-SNE2
MB95F202HP-G-SH-SNE2
MB95F202KP-G-SH-SNE2
24-pin plastic SDIP
(DIP-24P-M07)
MB95F204HPF-G-SNE2
MB95F204KPF-G-SNE2
MB95F203HPF-G-SNE2
MB95F203KPF-G-SNE2
MB95F202HPF-G-SNE2
MB95F202KPF-G-SNE2
20-pin plastic SOP
(FPT-20P-M09)
MB95F214HPH-G-SNE2
MB95F214KPH-G-SNE2
MB95F213HPH-G-SNE2
MB95F213KPH-G-SNE2
MB95F212HPH-G-SNE2
MB95F212KPH-G-SNE2
8-pin plastic DIP
(DIP-8P-M03)
MB95F214HPF-G-SNE2
MB95F214KPF-G-SNE2
MB95F213HPF-G-SNE2
MB95F213KPF-G-SNE2
MB95F212HPF-G-SNE2
MB95F212KPF-G-SNE2
8-pin plastic SOP
(FPT-8P-M08)
MB95200H/210H Series
DS07-12623-5E 67
■PACKAGE DIMENSIONS
Please check the latest package dimensions at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
24-pin plastic SDIP Lead pitch 1.778 mm
Package width
×
package length
6.40 mm × 22.86 mm
Sealing method Plastic mold
Mounting height 4.80 mm Max
24-pin plastic SDIP
(DIP-24P-M07)
(DIP-24P-M07)
C
2008-2010 FUJITSU SEMICONDUCTOR LIMITED D24066S-c-1-2
#22.86±0.10(.900±.004)
INDEX
TYP.
7.62(.300)
6.40±0.10
(.252±.004)
BTM E-MARK
–0.04
+.004
–.002.010
0.25 +0.10
112
24 13
4.80(.189)MAX
+0.20
–0.30
+.008
–.012
3.00 .118
1.778(.070)
(.039±.004)
1.00±0.10 +0.09
–0.04
+.004
–.002
.017
0.43
MIN
0.50(.020)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Note 1) Pins width and pins thickness include plating thickness.
Note 2) Pins width do not include tie bar cutting remainder.
Note 3) # : These dimensions do not include resin protrusion.
MB95200H/210H Series
68 DS07-12623-5E
Please check the latest package dimensions at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
20-pin plastic SOP Lead pitch 1.27 mm
Package width
×
package length
7.50 mm × 12.70 mm
Lead shape Gullwing
Lead bend
direction Normal bend
Sealing method Plastic mold
Mounting height 2.65 mm Max
20-pin plastic SOP
(FPT-20P-M09)
(FPT-20P-M09)
C
2008-2010 FUJITSU SEMICONDUCTOR LIMITED F20030S-c-1-2
Details of "A" part
INDEX
0.10(.004)
(.008±.004)
0.20±0.10
–.007
+.005
.099
–0.17
+0.13
2.52 (Mounting height)
0~8°
(Stand off)
0.80+0.47
–0.30
.031+.019
–.012
"A"
–.001
+.003
.010
0.25 +0.07
–0.02
#12.70±0.10(.500±.004)
1120
1.27(.050)
1 10
0.25(.010) M
–0.05
+0.09
0.40
.016 +.004
–.002
#7.50±0.10
(.295±.004)
–0.20
+0.40
10.2
.402 +.016
–.008
BTM E-MARK
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Note 1) Pins width and pins thickness include plating thickness.
Note 2) Pins width do not include tie bar cutting remainder.
Note 3) # : These dimensions do not include resin protrusion.
MB95200H/210H Series
DS07-12623-5E 69
Please check the latest package dimensions at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
8-pin plastic DIP Lead pitch 2.54 mm
Sealing method
Plastic mold
8-pin plastic DIP
(DIP-8P-M03)
(DIP-8P-M03)
C
2006-2010 FUJITSU SEMICONDUCTOR LIMITED D08008S-c-1-4
0.25±0.05
(.010±.002)
15° MAX
.370 –.012
+.016
–0.30
+0.40
9.40
(.250±.010)
6.35±0.25
INDEX
14
85
0.50(.020)
MIN
TYP.
2.54(.100)
(.018±.003)
0.46±0.08
3.00(.118)MIN
4.36(.172)MAX
1.52
.060 –0
+.012
–0
+0.30
–0
–00.99 +0.30
+.012
.039
.035
0.89
+.014
+0.35
–.012
–0.30
TYP.
7.62(.300)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
MB95200H/210H Series
70 DS07-12623-5E
(Continued)
Please check the latest package dimensions at the following URL.
http://edevice.fujitsu.com/package/en-search/
8-pin plastic SOP Lead pitch 1.27 mm
Package width
×
package length
5.30 mm × 5.24 mm
Lead shape Gullwing
Lead bend
direction Normal bend
Sealing method Plastic mold
Mounting height 2.10 mm Max
8-pin plastic SOP
(FPT-8P-M08)
(FPT-8P-M08)
C
2008-2010 FUJITSU SEMICONDUCTOR LIMITED F08016S-c-1-2
Details of "A" part
#5.30±0.10
(.209±.004)
INDEX
1.27(.050)
14
58
0.43±0.05
(.017±.002)
"A"
(Stand off)
0~8°
(Mounting height)
2.10(.083)
MAX
0.10 +0.15
–0.05
–.002
+.006
.004
7.80+0.45
–0.10
+.018
–.004.307
#5.24±0.10
(.206±.004)
BTM E-MARK
0.20±0.05
(.008±.002)
+0.10
–0.200.75
.030 +.004
–.008
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Note 1) Pins width and pins thickness include plating thickness.
Note 2) Pins width do not include tie bar cutting remainder.
Note 3) # : These dimensions do not include resin protrusion.
MB95200H/210H Series
DS07-12623-5E 71
■MAIN CHANGES IN THIS EDITION
The vertical lines marked in the left side of the page show the changes.
Page Section Change results
30 ■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Changed the characteristics of Input voltage.
33
3. DC Characteristics Corrected the maximum value of “H” level input voltage for PF2
pin.
VCC + 0.3 → 10.5
Corrected the maximum value of Open-drain output application
voltage.
0.2Vcc → Vss + 5.5
36 Added the footnote *5.
39 4. AC Characteristics
(1) Clock Timing
Added a figure of HCLK1/HCLK2.
42
(2) Source Clock/Machine Clock Corrected the graph of Operating voltage - Operating frequency
(with the on-chip debug function).
(Corrected the pitch)
43 (3) External Reset Added “and power on” to the remarks column.
58
6. Flash Memory Program/Erase
Characteristics
Added the row of “Current drawn on PF2”.
Corrected the minimum value of Power supply voltage at erase/
program.
4.5 → 3.0
MB95200H/210H Series
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
FUJITSU SEMICONDUCTOR AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://us.fujitsu.com/micro/
Europe
FUJITSU SEMICONDUCTOR EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/semiconductor/
Korea
FUJITSU SEMICONDUCTOR KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
Asia Pacific
FUJITSU SEMICONDUCTOR ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fujitsu.com/sg/services/micro/semiconductor/
FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.
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The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not
warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device
based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or
any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other
right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property
rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear
facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in
connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department