1
2
3
4
8
7
6
5
GND
TRIG
OUT
RESET
VCC
DISCH
THRES
CONT
3 2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
NC
DISCH
NC
THRES
NC
NC
TRIG
NC
OUT
NC
NC
GND
NC
CONT
NC VCC
NC
NC
RESET
NC
NC – No internal connection
NA555...D OR P PACKAGE
NE555...D, P, PS, OR PW PACKAGE
SA555...D OR P PACKAGE
SE555...D, JG, OR P PACKAGE
(TOP VIEW)
SE555...FK PACKAGE
(TOP VIEW)
NA555, NE555, SA555, SE555
www.ti.com
SLFS022H –SEPTEMBER 1973–REVISED JUNE 2010
PRECISION TIMERS
Check for Samples: NA555,NE555,SA555,SE555
1FEATURES
• Timing From Microseconds to Hours • Adjustable Duty Cycle
• Astable or Monostable Operation • TTL-Compatible Output Can Sink or Source up
to 200 mA
DESCRIPTION/ORDERING INFORMATION
These devices are precision timing circuits capable of producing accurate time delays or oscillation. In the
time-delay or monostable mode of operation, the timed interval is controlled by a single external resistor and
capacitor network. In the astable mode of operation, the frequency and duty cycle can be controlled
independently with two external resistors and a single external capacitor.
The threshold and trigger levels normally are two-thirds and one-third, respectively, of VCC. These levels can be
altered by use of the control-voltage terminal. When the trigger input falls below the trigger level, the flip-flop is
set, and the output goes high. If the trigger input is above the trigger level and the threshold input is above the
threshold level, the flip-flop is reset and the output is low. The reset (RESET) input can override all other inputs
and can be used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset, and the output goes
low. When the output is low, a low-impedance path is provided between discharge (DISCH) and ground.
The output circuit is capable of sinking or sourcing current up to 200 mA. Operation is specified for supplies of
5 V to 15 V. With a 5-V supply, output levels are compatible with TTL inputs.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 1973–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas On products compliant to MIL-PRF-38535, all parameters are
Instruments standard warranty. Production processing does not tested unless otherwise noted. On all other products, production
necessarily include testing of all parameters. processing does not necessarily include testing of all parameters.
NA555, NE555, SA555, SE555
SLFS022H –SEPTEMBER 1973–REVISED JUNE 2010
www.ti.com
ORDERING INFORMATION(1)
VTHRES MAX
TAPACKAGE(2) ORDERABLE PART NUMBER TOP-SIDE MARKING
VCC = 15 V
PDIP – P Tube of 50 NE555P NE555P
Tube of 75 NE555D
SOIC – D NE555
Reel of 2500 NE555DR
0°C to 70°C 11.2 V SOP – PS Reel of 2000 NE555PSR N555
Tube of 150 NE555PW
TSSOP – PW N555
Reel of 2000 NE555PWR
PDIP – P Tube of 50 SA555P SA555P
–40°C to 85°C 11.2 V Tube of 75 SA555D
SOIC – D SA555
Reel of 2000 SA555DR
PDIP – P Tube of 50 NA555P NA555P
–40°C to 105°C 11.2 V Tube of 75 NA555D
SOIC – D NA555
Reel of 2000 NA555DR
PDIP – P Tube of 50 SE555P SE555P
Tube of 75 SE555D
SOIC – D SE555D
–55°C to 125°C 10.6 Reel of 2500 SE555DR
CDIP – JG Tube of 50 SE555JG SE555JG
LCCC – FK Tube of 55 SE555FK SE555FK
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Table 1. FUNCTION TABLE
TRIGGER THRESHOLD DISCHARGE
RESET OUTPUT
VOLTAGE(1) VOLTAGE(1) SWITCH
Low Irrelevant Irrelevant Low On
High <1/3 VCC Irrelevant High Off
High >1/3 VCC >2/3 VCC Low On
High >1/3 VCC <2/3 VCC As previously established
(1) Voltage levels shown are nominal.
2Submit Documentation Feedback Copyright © 1973–2010, Texas Instruments Incorporated
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1
S
R
R1
TRIG
THRES
VCC
CONT
RESET
OUT
DISCH
GND
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
4
8
5
6
2
1
7
3
NA555, NE555, SA555, SE555
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SLFS022H –SEPTEMBER 1973–REVISED JUNE 2010
FUNCTIONAL BLOCK DIAGRAM
A. Pin numbers shown are for the D, JG, P, PS, and PW packages.
B. RESET can override TRIG, which can override THRES.
Copyright © 1973–2010, Texas Instruments Incorporated Submit Documentation Feedback 3
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NA555, NE555, SA555, SE555
SLFS022H –SEPTEMBER 1973–REVISED JUNE 2010
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Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VCC Supply voltage(2) 18 V
VIInput voltage CONT, RESET, THRES, TRIG VCC V
IOOutput current ±225 mA
D package 97
P package 85
qJA Package thermal impedance(3) (4) °C/W
PS package 95
PW package 149
FK package 5.61
qJC Package thermal impedance(5) (6) °C/W
JG package 14.5
TJOperating virtual junction temperature 150 °C
Case temperature for 60 s FK package 260 °C
Lead temperature 1, 6 mm (1/16 in) from case for 60 s JG package 300 °C
Tstg Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND.
(3) Maximum power dissipation is a function of TJ(max), qJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD= (TJ(max) - TA)/qJA. Operating at the absolute maximum TJof 150°C can affect reliability.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
(5) Maximum power dissipation is a function of TJ(max), qJC, and TC. The maximum allowable power dissipation at any allowable case
temperature is PD= (TJ(max) - TC)/qJC. Operating at the absolute maximum TJof 150°C can affect reliability.
(6) The package thermal impedance is calculated in accordance with MIL-STD-883.
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
NA555, NE555, SA555 4.5 16
VCC Supply voltage V
SE555 4.5 18
VIInput voltage CONT, RESET, THRES, and TRIG VCC V
IOOutput current ±200 mA
NA555 –40 105
NE555 0 70
TAOperating free-air temperature °C
SA555 –40 85
SE555 –55 125
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SLFS022H –SEPTEMBER 1973–REVISED JUNE 2010
Electrical Characteristics
VCC = 5 V to 15 V, TA= 25°C (unless otherwise noted) NA555
SE555 NE555
PARAMETER TEST CONDITIONS UNIT
SA555
MIN TYP MAX MIN TYP MAX
VCC = 15 V 9.4 10 10.6 8.8 10 11.2
THRES voltage level V
VCC = 5 V 2.7 3.3 4 2.4 3.3 4.2
THRES current(1) 30 250 30 250 nA
4.8 5 5.2 4.5 5 5.6
VCC = 15 V TA= –55°C to 125°C 3 6
TRIG voltage level V
1.45 1.67 1.9 1.1 1.67 2.2
VCC = 5 V TA= –55°C to 125°C 1.9
TRIG current TRIG at 0 V 0.5 0.9 0.5 2 mA
0.3 0.7 1 0.3 0.7 1
RESET voltage level V
TA= –55°C to 125°C 1.1
RESET at VCC 0.1 0.4 0.1 0.4
RESET current mA
RESET at 0 V –0.4 –1 –0.4 –1.5
DISCH switch off-state 20 100 20 100 nA
current 9.6 10 10.4 9 10 11
VCC = 15 V TA= –55°C to 125°C 9.6 10.4
CONT voltage V
(open circuit) 2.9 3.3 3.8 2.6 3.3 4
VCC = 5 V TA= –55°C to 125°C 2.9 3.8
0.1 0.15 0.1 0.25
VCC = 15 V, IOL = 10 mA TA= –55°C to 125°C 0.2
0.4 0.5 0.4 0.75
VCC = 15 V, IOL = 50 mA TA= –55°C to 125°C 1
2 2.2 2 2.5
VCC = 15 V, IOL = 100 mA
Low-level output voltage TA= –55°C to 125°C 2.7 V
VCC = 15 V, IOL = 200 mA 2.5 2.5
VCC = 5 V, IOL = 3.5 mA TA= –55°C to 125°C 0.35
0.1 0.2 0.1 0.35
VCC = 5 V, IOL = 5 mA TA= –55°C to 125°C 0.8
VCC = 5 V, IOL = 8 mA 0.15 0.25 0.15 0.4
13 13.3 12.75 13.3
VCC = 15 V, IOL = –100 mA TA= –55°C to 125°C 12
High-level output voltage VCC = 15 V, IOH = –200 mA 12.5 12.5 V
3 3.3 2.75 3.3
VCC = 5 V, IOL = –100 mA TA= –55°C to 125°C 2
VCC = 15 V 10 12 10 15
Output low, No load VCC = 5 V 3 5 3 6
Supply current mA
VCC = 15 V 9 10 9 13
Output high, No load VCC = 5 V 2 4 2 5
(1) This parameter influences the maximum value of the timing resistors RAand RBin the circuit of Figure 12. For example,
when VCC = 5 V, the maximum value is R = RA+ RB≉3.4 MΩ, and for VCC = 15 V, the maximum value is 10 MΩ.
Copyright © 1973–2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): NA555 NE555 SA555 SE555
NA555, NE555, SA555, SE555
SLFS022H –SEPTEMBER 1973–REVISED JUNE 2010
www.ti.com
Operating Characteristics
VCC = 5 V to 15 V, TA= 25°C (unless otherwise noted) NA555
SE555 NE555
TEST
PARAMETER UNIT
SA555
CONDITIONS(1)
MIN TYP MAX MIN TYP MAX
Each timer, monostable(3) TA= 25°C 0.5 1.5(4) 1 3
Initial error of timing %
interval(2) Each timer, astable(5) 1.5 2.25
Each timer, monostable(3) TA= MIN to MAX 30 100(4) 50
Temperature coefficient of ppm/
timing interval °C
Each timer, astable(5) 90 150
Each timer, monostable(3) TA= 25°C 0.05 0.2(4) 0.1 0.5
Supply-voltage sensitivity of %/V
timing interval Each timer, astable(5) 0.15 0.3
CL= 15 pF,
Output-pulse rise time 100 200(4) 100 300 ns
TA= 25°C
CL= 15 pF,
Output-pulse fall time 100 200(4) 100 300 ns
TA= 25°C
(1) For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
(2) Timing interval error is defined as the difference between the measured value and the average value of a random sample from each
process run.
(3) Values specified are for a device in a monostable circuit similar to Figure 9, with the following component values: RA= 2 kΩto 100 kΩ,
C = 0.1 mF.
(4) On products compliant to MIL-PRF-38535, this parameter is not production tested.
(5) Values specified are for a device in an astable circuit similar to Figure 12, with the following component values: RA= 1 kΩto 100 kΩ,
C = 0.1 mF.
6Submit Documentation Feedback Copyright © 1973–2010, Texas Instruments Incorporated
Product Folder Link(s): NA555 NE555 SA555 SE555
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
TA = 125°C
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
TA = 25°C
IOL − Low-Level Output Current − mA
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
VCC = 5 V
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
TA = −55°C
0.1
0.04
0.01 1 2 4 7 10 20 40 70 100
0.07
1
0.4
0.7
10
4
7
0.02
0.2
2
− Low-Level Output Voltage − VVOL
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
VCC = 10 V
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
− Low-Level Output Voltage − VVOL
IOL − Low-Level Output Current − mA
0.1
0.04
0.01 1 2 4 7 10 20 40 70 100
0.07
1
0.4
0.7
10
4
7
0.02
0.2
2
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
TA = 125°C
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
TA = 25°C
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
TA= −55°C
TA = 125°C
TA = 25°C
TA = −55°C
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
VCC = 15 V
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
− Low-Level Output Voltage − VVOL
IOL − Low-Level Output Current − mA
0.1
0.04
0.01 1 2 4 7 10 20 40 70 100
0.07
1
0.4
0.7
10
4
7
0.02
0.2
2
1
0.6
0.2
0
1.4
1.8
2.0
0.4
1.6
0.8
1.2
−
IOH − High-Level Output Current − mA
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
TA = 125°C
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
TA = 25°C
100704020107421
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
VCC = 5 V to 15 V
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
TA = −55°C
VCC VOH − V oltage Drop − V
)
(
DROP BETWEEN SUPPLY VOLTAGE AND OUTPUT
vs
HIGH-LEVEL OUTPUT CURRENT
NA555, NE555, SA555, SE555
www.ti.com
SLFS022H –SEPTEMBER 1973–REVISED JUNE 2010
TYPICAL CHARACTERISTICS
Data for temperatures below 0°C and above 70°C are applicable for SE555 circuits only.
Figure 1. Figure 2.
Figure 3. Figure 4.
Copyright © 1973–2010, Texas Instruments Incorporated Submit Documentation Feedback 7
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5
4
2
1
0
9
3
5 6 7 8 9 10 11
− Supply Current − mA
7
6
8
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
10
12 13 14 15
TA = 25°C
TA = 125°C
TA = −55°C
Output Low,
No Load
CC
I
VCC − Supply Voltage − V
1
0.995
0.990
0.9850 5 10
1.005
1.010
NORMALIZED OUTPUT PULSE DURATION
(MONOSTABLE OPERATION)
vs
SUPPLY VOLTAGE
1.015
15 20
CC
VPulse Duration Relative to Value at = 10 V
VCC − Supply Voltage − V
1
0.995
0.990
0.985
−75 −25 25
1.005
1.010
NORMALIZED OUTPUT PULSE DURATION
(MONOSTABLE OPERATION)
vs
FREE-AIR TEMPERATURE
1.015
75 125
TA − Free-Air Temperature − °C
−50 0 50 100
VCC = 10 V
Pulse Duration Relative to Value at TA = 255C
0
100
200
300
400
500
600
700
800
900
1000
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
Lowest Level of Trigger Pulse – ×VCC
tPD – Propagation Delay Time – ns
TA= 125°C
TA= 70°C
TA= 25°C
TA= 0°C
TA= –55°C
PROPAGATION DELAY TIME
vs
LOWEST VOLTAGE LEVEL
OF TRIGGER PULSE
NA555, NE555, SA555, SE555
SLFS022H –SEPTEMBER 1973–REVISED JUNE 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Data for temperatures below 0°C and above 70°C are applicable for SE555 circuits only.
Figure 5. Figure 6.
Figure 7. Figure 8.
8Submit Documentation Feedback Copyright © 1973–2010, Texas Instruments Incorporated
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VCC
(5 V to 15 V)
RARL
Output
GND
OUT
VCC
CONT
RESET
DISCH
THRES
TRIGInput
Î
Î
Î
58
4
7
6
2
3
1
Pin numbers shown are for the D, JG, P, PS, and PW packages.
NA555, NE555, SA555, SE555
www.ti.com
SLFS022H –SEPTEMBER 1973–REVISED JUNE 2010
APPLICATION INFORMATION
Monostable Operation
For monostable operation, any of these timers can be connected as shown in Figure 9. If the output is low,
application of a negative-going pulse to the trigger (TRIG) sets the flip-flop (Q goes low), drives the output high,
and turns off Q1. Capacitor C then is charged through RAuntil the voltage across the capacitor reaches the
threshold voltage of the threshold (THRES) input. If TRIG has returned to a high level, the output of the threshold
comparator resets the flip-flop (Q goes high), drives the output low, and discharges C through Q1.
Figure 9. Circuit for Monostable Operation
Monostable operation is initiated when TRIG voltage falls below the trigger threshold. Once initiated, the
sequence ends only if TRIG is high for at least 10 µs before the end of the timing interval. When the trigger is
grounded, the comparator storage time can be as long as 10 µs, which limits the minimum monostable pulse
width to 10 µs. Because of the threshold level and saturation voltage of Q1, the output pulse duration is
approximately tw= 1.1RAC. Figure 11 is a plot of the time constant for various values of RAand C. The threshold
levels and charge rates both are directly proportional to the supply voltage, VCC. The timing interval is, therefore,
independent of the supply voltage, so long as the supply voltage is constant during the time interval.
Applying a negative-going trigger pulse simultaneously to RESET and TRIG during the timing interval discharges
C and reinitiates the cycle, commencing on the positive edge of the reset pulse. The output is held low as long
as the reset pulse is low. To prevent false triggering, when RESET is not used, it should be connected to VCC.
Copyright © 1973–2010, Texas Instruments Incorporated Submit Documentation Feedback 9
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− Output Pulse Duration − s
C − Capacitance − µF
10
1
10−1
10−2
10−3
10−4
1001010.10.01
10−5
0.001
tw
RA = 10 MΩ
RA = 10 kΩ
RA = 1 kΩ
RA = 100 kΩ
RA = 1 MΩ
Voltage − 2 V/div
Time − 0.1 ms/div
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
Capacitor Voltage
Output Voltage
Input Voltage
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
RA = 9.1 kΩ
CL = 0.01 µF
RL = 1 kΩ
See Figure 9
Voltage − 1 V/div
Time − 0.5 ms/div
tH
Capacitor Voltage
Output Voltage
tL
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
RA = 5 kW RL = 1 kW
RB = 3 kW See Figure 12
C = 0.15 µF
GND
OUT
VCC
CONT
RESET
DISCH
THRES
TRIG
C
RB
RA
Output
RL
0.01 µF
VCC
(5 V to 15 V)
(see Note A)
Î
Î
Î
NOTE A: Decoupling CONT voltage to ground with a capacitor can
improve operation. This should be evaluated for individual
applications.
Open
5 8
4
7
6
2
3
1
Pin numbers shown are for the D, JG, P, PS, and PW packages.
NA555, NE555, SA555, SE555
SLFS022H –SEPTEMBER 1973–REVISED JUNE 2010
www.ti.com
Figure 10. Typical Monostable Waveforms Figure 11. Output Pulse Duration vs Capacitance
Astable Operation
As shown in Figure 12, adding a second resistor, RB, to the circuit of Figure 9 and connecting the trigger input to
the threshold input causes the timer to self-trigger and run as a multivibrator. The capacitor C charges through
RAand RBand then discharges through RBonly. Therefore, the duty cycle is controlled by the values of RAand
RB.
This astable connection results in capacitor C charging and discharging between the threshold-voltage level
(≉0.67 × VCC) and the trigger-voltage level (≉0.33 × VCC). As in the monostable circuit, charge and discharge
times (and, therefore, the frequency and duty cycle) are independent of the supply voltage.
Figure 12. Circuit for Astable Operation Figure 13. Typical Astable Waveforms
10 Submit Documentation Feedback Copyright © 1973–2010, Texas Instruments Incorporated
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tH+0.693 (RA)RB) C
tL+0.693 (RB) C
Other useful relationships are shown below.
period +tH)tL+0.693 (RA)2RB) C
frequency [1.44
(RA)2RB) C
Output driver duty cycle +tL
tH)tL+RB
RA)2RB
Output waveform duty cycle
+tL
tH+RB
RA)RB
Low-to-high ratio
+tH
tH)tL+1– RB
RA)2RB
f − Free-Running Frequency − Hz
C − Capacitance − µF
100 k
10 k
1 k
100
10
1
1001010.10.01
0.1
0.001
RA + 2 RB = 10 MΩ
RA + 2 RB = 1 MΩ
RA + 2 RB = 100 kΩ
RA + 2 RB = 10 kΩ
RA + 2 RB = 1 kΩ
Time − 0.1 ms/div
Voltage − 2 V/div
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
VCC = 5 V
RA = 1 kΩ
C = 0.1 µF
See Figure 15
Capacitor Voltage
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Output Voltage
Input Voltage
VCC (5 V to 15 V)
DISCH
OUT
VCC
RESET
RLRA
A5T3644
C
THRES
GND
CONT
TRIG
Input
0.01 µF
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Output
4 8
3
7
6
2
5
1
Pin numbers shown are shown for the D, JG, P, PS, and PW packages.
NA555, NE555, SA555, SE555
www.ti.com
SLFS022H –SEPTEMBER 1973–REVISED JUNE 2010
Figure 12 shows typical waveforms generated during astable operation. The output high-level duration tHand
low-level duration tLcan be calculated as follows:
Figure . Figure 14. Free-Running Frequency
Missing-Pulse Detector
The circuit shown in Figure 15 can be used to detect a missing pulse or abnormally long spacing between
consecutive pulses in a train of pulses. The timing interval of the monostable circuit is retriggered continuously by
the input pulse train as long as the pulse spacing is less than the timing interval. A longer pulse spacing, missing
pulse, or terminated pulse train permits the timing interval to be completed, thereby generating an output pulse
as shown in Figure 16.
Figure 15. Circuit for Missing-Pulse Detector Figure 16. Completed Timing Waveforms for
Missing-Pulse Detector
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Voltage − 2 V/div
Time − 0.1 ms/div
Capacitor Voltage
Output Voltage
Input Voltage
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
VCC = 5 V
RA = 1250 Ω
C = 0.02 µF
See Figure 9
NA555, NE555, SA555, SE555
SLFS022H –SEPTEMBER 1973–REVISED JUNE 2010
www.ti.com
Frequency Divider
By adjusting the length of the timing cycle, the basic circuit of Figure 9 can be made to operate as a frequency
divider. Figure 17 shows a divide-by-three circuit that makes use of the fact that retriggering cannot occur during
the timing cycle.
Figure 17. Divide-by-Three Circuit Waveforms
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THRES
GND C
RA
RL
VCC (5 V to 15 V)
Output
DISCH
OUT
VCC
RESET
TRIG
CONT
Modulation
Input
(see Note A)
Clock
Input
NOTE A: The modulating signal can be direct or capacitively coupled
to CONT. For direct coupling, the effects of modulation source
voltage and impedance on the bias of the timer should be
considered.
4 8
3
7
6
2
5
Pin numbers shown are for the D, JG, P, PS, and PW packages.
1
Voltage − 2 V/div
Time − 0.5 ms/div
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
Capacitor Voltage
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
Output Voltage
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
Clock Input Voltage
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
RA = 3 kΩ
C = 0.02 µF
RL = 1 kΩ
See Figure 18
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
Modulation Input Voltage
NA555, NE555, SA555, SE555
www.ti.com
SLFS022H –SEPTEMBER 1973–REVISED JUNE 2010
Pulse-Width Modulation
The operation of the timer can be modified by modulating the internal threshold and trigger voltages, which is
accomplished by applying an external voltage (or current) to CONT. Figure 18 shows a circuit for pulse-width
modulation. A continuous input pulse train triggers the monostable circuit, and a control signal modulates the
threshold voltage. Figure 19 shows the resulting output pulse-width modulation. While a sine-wave modulation
signal is shown, any wave shape could be used.
Figure 18. Circuit for Pulse-Width Modulation Figure 19. Pulse-Width-Modulation Waveforms
Copyright © 1973–2010, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): NA555 NE555 SA555 SE555
Voltage − 2 V/div
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
RA = 3 kΩ
RB = 500 Ω
RL = 1 kΩ
See Figure 20
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
Capacitor Voltage
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Output Voltage
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
Modulation Input Voltage
Time − 0.1 ms/div
RB
Modulation
Input
(see Note A) CONT
TRIG
RESET VCC
OUT
DISCH
VCC (5 V to 15 V)
RLRA
C
GND
THRES
NOTE A: The modulating signal can be direct or capacitively coupled
to CONT. For direct coupling, the effects of modulation
source voltage and impedance on the bias of the timer
should be considered.
Pin numbers shown are for the D, JG, P, PS, and PW packages.
4 8
3
7
6
2
5
Output
NA555, NE555, SA555, SE555
SLFS022H –SEPTEMBER 1973–REVISED JUNE 2010
www.ti.com
Pulse-Position Modulation
As shown in Figure 20, any of these timers can be used as a pulse-position modulator. This application
modulates the threshold voltage and, thereby, the time delay, of a free-running oscillator. Figure 21 shows a
triangular-wave modulation signal for such a circuit; however, any wave shape could be used.
Figure 20. Circuit for Pulse-Position Modulation Figure 21. Pulse-Position-Modulation Waveforms
14 Submit Documentation Feedback Copyright © 1973–2010, Texas Instruments Incorporated
Product Folder Link(s): NA555 NE555 SA555 SE555
S
VCC
RESET VCC
OUT
DISCH
GND
CONT
TRIG
4 8
3
7
6
1
5
2
THRES
RC
CC
0.01
CC = 14.7 µF
RC = 100 kΩOutput C
RESET VCC
OUT
DISCH
GND
CONT
TRIG
4 8
3
7
6
1
5
2
THRES
RB33 kΩ
0.001
0.01
µF
CB = 4.7 µF
RB = 100 kΩ
Output BOutput A
RA = 100 kΩ
CA = 10 µF
µF
0.01
µF
0.001
33 kΩ
RA
THRES
2
5
1
6
7
3
84
TRIG
CONT
GND
DISCH
OUT
VCC
RESET
µF
µF
CB
CA
Pin numbers shown are for the D, JG, P, PS, and PW packages.
NOTE A: S closes momentarily at t = 0.
Voltage − 5 V/div
t − Time − 1 s/div
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
See Figure 22
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
Output A
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
Output B
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
Output C
ÏÏÏ
ÏÏÏ
ÏÏÏ
ÏÏÏ
t = 0
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
twC = 1.1 RCCC
ÏÏ
ÏÏ
ÏÏ
twC
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
twB = 1.1 RBCB
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
twA = 1.1 RACA
ÏÏÏ
ÏÏÏ
ÏÏÏ
ÏÏÏ
twA
ÏÏÏ
ÏÏÏ
ÏÏÏ
ÏÏÏ
twB
NA555, NE555, SA555, SE555
www.ti.com
SLFS022H –SEPTEMBER 1973–REVISED JUNE 2010
Sequential Timer
Many applications, such as computers, require signals for initializing conditions during start-up. Other
applications, such as test equipment, require activation of test signals in sequence. These timing circuits can be
connected to provide such sequential control. The timers can be used in various combinations of astable or
monostable circuit connections, with or without modulation, for extremely flexible waveform control. Figure 22
shows a sequencer circuit with possible applications in many systems, and Figure 23 shows the output
waveforms.
Figure 22. Sequential Timer Circuit
Figure 23. Sequential Timer Waveforms
Copyright © 1973–2010, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): NA555 NE555 SA555 SE555
PACKAGE OPTION ADDENDUM
www.ti.com 18-Oct-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
JM38510/10901BPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510
/10901BPA
M38510/10901BPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510
/10901BPA
NA555D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 105 NA555
NA555DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 105 NA555
NA555DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 105 NA555
NA555DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 105 NA555
NA555P ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -40 to 105 NA555P
NA555PE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -40 to 105 NA555P
NE555D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 NE555
NE555DE4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 NE555
NE555DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 NE555
NE555DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 NE555
NE555DRE4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 NE555
NE555DRG3 PREVIEW SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 NE555
NE555DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 NE555
NE555P ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU | CU SN N / A for Pkg Type 0 to 70 NE555P
NE555PE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 NE555P
PACKAGE OPTION ADDENDUM
www.ti.com 18-Oct-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
NE555PSLE OBSOLETE SO PS 8 TBD Call TI Call TI 0 to 70
NE555PSR ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555
NE555PSRE4 ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555
NE555PSRG4 ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555
NE555PW ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555
NE555PWE4 ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555
NE555PWG4 ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555
NE555PWR ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555
NE555PWRE4 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555
NE555PWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555
NE555Y OBSOLETE 0 TBD Call TI Call TI 0 to 70
SA555D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA555
SA555DE4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA555
SA555DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA555
SA555DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 SA555
SA555DRE4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA555
SA555DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA555
SA555P ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SA555P
SA555PE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SA555P
PACKAGE OPTION ADDENDUM
www.ti.com 18-Oct-2013
Addendum-Page 3
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SE555D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 SE555
SE555DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 SE555
SE555DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 SE555
SE555DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 SE555
SE555FKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 SE555FKB
SE555JG ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 SE555JG
SE555JGB ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 SE555JGB
SE555N OBSOLETE PDIP N 8 TBD Call TI Call TI -55 to 125
SE555P ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 SE555P
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Oct-2013
Addendum-Page 4
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SE555, SE555M :
•Catalog: SE555
•Military: SE555M
•Space: SE555-SP, SE555-SP
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
•Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
NA555DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
NA555DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
NE555DR SOIC D 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1
NE555DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
NE555DRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
NE555DRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
NE555PSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
NE555PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
SA555DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SA555DR SOIC D 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1
SA555DRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SE555DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SE555DRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Oct-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
NA555DR SOIC D 8 2500 340.5 338.1 20.6
NA555DR SOIC D 8 2500 367.0 367.0 35.0
NE555DR SOIC D 8 2500 364.0 364.0 27.0
NE555DR SOIC D 8 2500 340.5 338.1 20.6
NE555DRG4 SOIC D 8 2500 340.5 338.1 20.6
NE555DRG4 SOIC D 8 2500 367.0 367.0 35.0
NE555PSR SO PS 8 2000 367.0 367.0 38.0
NE555PWR TSSOP PW 8 2000 367.0 367.0 35.0
SA555DR SOIC D 8 2500 340.5 338.1 20.6
SA555DR SOIC D 8 2500 364.0 364.0 27.0
SA555DRG4 SOIC D 8 2500 340.5 338.1 20.6
SE555DR SOIC D 8 2500 367.0 367.0 35.0
SE555DRG4 SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Oct-2013
Pack Materials-Page 2
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUAR Y 1997
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE
0.310 (7,87)
0.290 (7,37)
0.014 (0,36)
0.008 (0,20)
Seating Plane
4040107/C 08/96
5
4
0.065 (1,65)
0.045 (1,14)
8
1
0.020 (0,51) MIN
0.400 (10,16)
0.355 (9,00)
0.015 (0,38)
0.023 (0,58)
0.063 (1,60)
0.015 (0,38)
0.200 (5,08) MAX
0.130 (3,30) MIN
0.245 (6,22)
0.280 (7,11)
0.100 (2,54)
0°–15°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
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