1
FEATURES APPLICATIONS
DESCRIPTION/
TPS65530A
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............................................................................................................................................................ SLVS835C – APRIL 2008 – REVISED APRIL 2009
FULLY INTEGRATED 8-CHANNEL DC/DC CONVERTER FOR DIGITAL STILL CAMERAS
•Digital Still Cameras (DSCs)2
•8-Channel DC/DC Converter andLow Dropout (LDO)
•Portable Electronics Equipment•Integrated Power MOSFET Switch Except CH8– Boost (CH5/7)
ORDERING INFORMATION– Buck (CH1/3)
The TPS65530A is a fully integrated 8-channel– Buck-Boost (CH2/4)
switching dc/dc converter, and seven channels have– Invert (CH6)
integrated power FET.•Low-Power Suspend Mode (Sleep Mode)
CH2/4 are configured for H bridge for buck-boost•Power ON/OFF Sequence (CH1/2/3 and CH5/6)
topology and single inductor supports. These•LED-Back Light Brightness Control (CH7)
channels achieve higher efficiency in spite ofinput/output voltage conditions.•Fixed Switching Frequency (CH1 – 4: 1.5 MHz,CH5 – 8: 750 kHz)
CH7 has a brightness control and drives white LEDby constant current. Also, CH7 supports overvoltage•Fixed Max Duty Cycle Internally
protection (OVP) for open load.•Soft Start
CH1/2/3 have a power ON/OFF sequence suitable for•Undervoltage Lockout (UVLO)
a digital still camera (DSC) system. CH5/6 have a•Protection
power ON/OFF sequence, depending on the CCD.– Thermal Shutdown (TSD)
Power ON/OFF for CCD block (CH5/6) is selectableby the input voltage level at the SEQ56 pin. CH4 and– Overvoltage Protection (OVP)
CH7 have individual ON/OFF sequences.– Overcurrent Protection (OCP) Except CH8
The TPS65530A high switching frequency is•Supply Voltage Range: 1.5 V to 5.5 V
achieved by an integrated power MOSFET switch. It•Operating Temperature Range: – 25 ° C to 85 ° C
reduces external parts dynamically. Shutdown current•6 × 6 mm, 0.4-mm Pitch, 48-Pin QFN Package
consumption is less than 1 µA as a typical value.
ORDERING INFORMATION
T
A
PACKAGE
(1) (2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
Reel of 250 TPS65530ARSLT– 25 ° C to 85 ° C QFN TPS65530AReel of 2500 TPS65530ARSLR
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008 – 2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
CHANNEL CONFIGURATION
14
16
17
18
19
20
21
22
23
24
13
15
5
4
3
2
1
8
7
6
9
12
11
10
32
33
34
35
36
29
30
31
28
25
26
27
48
47
46
45
44
43
42
41
40
39
38
37
SW4S
PGND4
SW4I
VOUT4
FB4
ENAFE
XSLEEP
EN7
S/S
AGND
REF
VCC2
SW2S
PGND2
SW2I
VOUT2
FB2
VCC1
SW1
PGND1
FB1
FB3
VCC3
SW3
PGND3
SW8LD
LL8
SW8HD
FB8
FBG7/8
B-ADJ
FBC
CIN
FBV
SW7
PS
PGND5/7
SW5
SWOUT
VCC5
FB5
VCC6
SW6
FB6
S/S56
EN56
SEQ56
VCC4
QFNPACKAGE
(TOP VIEW)
PowerPAD™
TPS65530A
SLVS835C – APRIL 2008 – REVISED APRIL 2009 ............................................................................................................................................................
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
MAXIMUMOUTPUTOPERATION RECTIFY CONTROL SUPPLYCHANNEL VOLTAGE APPLICATIONMODE MODE METHOD CURRENT(V)
(mA)
CH1 Buck SW Synchronous Voltage 0.9 to 2.5 Engine core 600Engine I/OCH2 Buck-boost SW Synchronous Average current 2.5 to 3.6 600(DSP I/F)CH3 Buck SW Synchronous Voltage 0.9 to 2.5 External memory 300CH4 Buck-boost SW Synchronous Average current 2.2 to 3.6 AFE 300CH5 Boost SW Nonsynchronous Peak current Up to 18 CCD+ 50CH6 Invert SW Nonsynchronous Voltage – 10 to – 5 CCD – 100CH7 Boost SW Nonsynchronous Voltage 3 to 20 Backlight LED 25Motor controllerCH8 Boost SW Synchronous Voltage 3.3 to 5.5 –and IC drive supplyLow dropout Internal supply forREF – – 2.8 15voltage logic
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............................................................................................................................................................ SLVS835C – APRIL 2008 – REVISED APRIL 2009
TERMINAL FUNCTIONS
TERMINAL
I/O
(1)
DESCRIPTIONNO. NAME
1 SW4S O Buck-side terminal of coil for CH42 PGND4 G GND for CH4 low-side FET3 SW4I I Boost-side terminal of coil for CH44 V
OUT4
O Output of CH4Output voltage feedback for CH4. The external resistors should be connected as close as possible5 FB4 I
to the terminal.6 ENAFE I Enable for CH4 (L: Disable, H: Enable)7 XSLEEP I Control for sleep mode/normal operation (L: Sleep mode, H: Normal operation)8 EN7 I Enable for CH7 (L: Disable, H: Enable)Soft-start time adjustment. The time is programmable by an external capacitor (see the Soft Start9 S/S I/O
description).10 AGND G Analog ground11 REF O Output of LDO. From 2.2 µF to 4.7 µF, capacitor should be connected to AGND.12 V
CC2
P Power supply at CH2 buck-side FET from battery13 SW2S O Buck-side terminal of coil for CH214 PGND2 G GND for CH2 low-side FET15 SW2I I Boost-side terminal of coil for CH216 V
OUT2
O Output of CH2Output voltage feedback for CH2. The external resistors should be connected as close as possible17 FB2 O
to the terminal.18 V
CC1
P Power supply at CH1 high-side FET from battery19 SW1 O Output of CH1. The terminal should be connected to the external inductor.20 PGND1 G GND for CH1 low-side FETOutput voltage feedback for CH1. The external resistors should be connected as close as possible21 FB1 I
to the terminal.
Output voltage feedback for CH3. The external resistors should be connected as close as possible22 FB3 I
to the terminal.23 V
CC3
P Power supply at CH3 high-side FET from battery24 SW3 O Output of CH3. The terminal should be connected to the external inductor.25 PGND3 G GND for CH3 low-side FETOutput for CH8 external low-side FET drive. The terminal is connected to the gate of the low-side26 SW8LD O
external FET.Switching output for CH8 at wake mode. The terminal is switched when the output voltage of CH827 LL8 O
is less than 2.5 V.Output for CH8 external high-side FET drive. The terminal is connected to the gate of the28 SW8HD O
high-side external FET.29 PS I Power input for IC inside. The terminal should be connected to CH8 output voltage.Output voltage feedback for CH8. The external resistors should be connected as close as possible30 FB8 I
to the terminal.31 FBG7/8 I GND for CH7/8 feedback resistors32 B-ADJ I Brightness adjustment for W-LED33 FBC I Output current feedback for CH734 CIN I Input current at CH7 load switchOutput voltage feedback for CH7. The external resistors should be connected as close as possible35 FBV I
to the terminal.36 SW7 O Output of CH7. The terminal should be connected to the external inductor.Power GND for CH5/7. The terminal should be connected by power ground layer at PCB via a37 PGND5/7 G
through hole.38 SW5 O Low-side terminal of coil for CH5
(1) I = input, O = output, I/O = input/output, P = power supply, G = GND
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TERMINAL FUNCTIONS (continued)
TERMINAL
I/O
(1)
DESCRIPTIONNO. NAME
39 SWOUT O High-side terminal of coil for CH540 V
CC5
P Power supply at CH5 high-side FET from batteryOutput voltage feedback for CH5. The external resistors should be connected as close as possible41 FB5 I
to the terminal.42 V
CC6
P Power supply at CH6 load switch from battery43 SW6 O Output of CH6. The terminal should be connected to the external inductor.Output voltage feedback for CH6. The external resistors should be connected as close as possible44 FB6 I
to the terminal.
Soft-start time adjustment for CH5/6. The time is programmable by external capacitor (see the Soft45 S/S56 I/O
Start description).46 EN56 I Enable for CH5/6 (L: Disable, H: Enable)47 SEQ56 I Sequence select for CH5/6 (see the Power ON/OFF Sequence description)48 V
CC4
P Power supply at CH4 high-side FET from batteryMust be soldered to achieve appropriate power dissipation. Should be connected to PGND to useBack side PowerPAD™ G
aΦ0.3-mm through hole.
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ABSOLUTE MAXIMUM RATINGS
(1)
DISSIPATION RATINGS
RECOMMENDED OPERATING CONDITIONS
TPS65530A
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............................................................................................................................................................ SLVS835C – APRIL 2008 – REVISED APRIL 2009
over operating free-air temperature range (unless otherwise noted)
UNIT
V
CC1
, V
CC2
, V
CC3
, V
CC4
, V
CC5
, V
CC6
, SWOUT, FB2, FB4,FB5, FB8, FBC, FBV. PS, XSLEEP, ENAFE, SEQ56,EN56, EN7, SW4S, SW4I, V
OUT4
, V
OUT2
, SW1, SW3, – 0.3 to 6SW8LD, SW8HD, FBG78(based on PGND or AGND)SW2S, SW2I – 0.3 to 7BADJ, SS, FB1, FB3, FB6, SS56 – 0.3 to 3Input voltage range VLL8 – 0.3 to 7REF – 0.3 to 3.6SW5 – 0.3 to 22SW7, CIN – 0.3 to 27SW6 (based on V
CC6
) – 20PGND1, PGND2, PGND3, PGND4, PGND57, AGND – 0.3 to 0.3CIN 0.05SW2S, SW2I 3.3SW4S, SW4I 1.65SW1 1.9SW3 1Switching current ASW5 1.6SW6 – 1.35SW7 1.2LL8 1SW8LD, SW8HD 0.6T
J
Maximum junction temperature range – 30 to 150 ° CT
stg
Storage temperature range – 40 to 150 ° CESD rating, Human-Body Model (HBM) JEDEC JESD22A-A114 2 kVESD rating, Charged-Device Model (CDM) JEDEC JESD22A-C101 500 V
(1) Stresses beyond those listed under " absolute maximum ratings " may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under " recommended operatingconditions " is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
POWER RATINGS POWER RATINGS RATEPACKAGE R
θJA
(1)
T
A
< 25 ° C T
A
> 25 ° C
48-pin QFN 27 ° C/W 2.9 W 0.029 ° C/W
(1) The thermal resistance, R
θJA
, is based on a soldered PowerPAD package on a 2S2P JEDEC board (3-in × 3-in, four layers) usingthermal vias (0.3-mm diameter × 12 vias)
MIN MAX UNIT
V
CC1
, V
CC2
, V
CC4
, V
CC5
1.5 5.5Supply voltage VV
CC3
, V
CC6
2.5 5.5XSLEEP, ENAFE, EN56, EN7 1.4High-level input voltage VSEQ56 1.4 REFLow-level input voltage XSLEEP, ENAFE, EN56, EN7, SEQ56 0.4 VOperating temperature – 25 85 ° C
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ELECTRICAL CHARACTERISTICS
TPS65530A
SLVS835C – APRIL 2008 – REVISED APRIL 2009 ............................................................................................................................................................
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0 ° C ≤T
J
≤125 ° C, 1.8 V ≤V
CC2
≤5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
For All Circuits
I
CC_Iq
V
CC2
= VPS = 3.6 V, XSLEEP = AGND 1 10
µAI
CC_sleep
V
CC2
= 3.6 V, VPS = 5 V, XSLEEP = AGND,
40 70Consumption current at PS (pin 29) ENAFE = V
CC2
I
CC_PWM
V
CC2
= 3.6 V , VPS = 5 V, XSLEEP = V
CC2
,
20 30 mAENAFE = V
CC2
, EN56 = V
CC2
, EN7 = V
CC2
I
CC_Iq2
V
CC2
= VPS = 3.6 V, XSLEEP = AGND 1 10
µAI
CC_sleep2
V
CC2
= 3.6 V, VPS = 5 V, XSLEEP = AGND,
12 30Consumption current at V
CC2
(pin 12) ENAFE = V
CC2
I
CC_PWM2
V
CC2
= 3.6 V , VPS = 5 V, XSLEEP = V
CC2
,
0.3 1 mAENAFE = V
CC2
, EN56 = V
CC2
, EN7 = V
CC2
TSD Thermal shutdown temperature
(2)
150 ° CV
(UV_ON)
UVLO detect level V
CC2
from 0 V to 5.5 V, XSLEEP = V
CC2
1.25 1.4 1.55 VV
(UV_OFF)
UVLO hysteresis V
CC2
from 5.5 V to 0 V 50 100 150 mVOSC Internal OSC frequency V
CC2
= 3.6 V 1.35 1.5 1.65 MHzO
SC_SUB
CH5 – 8 switching frequency OSC = 1.5 MHz, VPS = 5 V 750 KHzREF output voltage XSLEEP = V
CC2
2.72 2.8 3.03 VI
ss
SS source current S/S = AGND 6 10 14 µAPulldown resistance at XSLEEP,
XSLEEP = ENAFE = EN56 = EN7 = SEQ56 = 3 V 200 k ΩENAFE, EN56, EN7, SEQ56
CH1
V
CC1
Supply voltage 1.5 5.5 VV
OUT1
Output voltage
(2)
0.9 2.5 VV
CC1
> 2.4 V, V
OUT1
= 1.2 V,I
OUT1
Output current
(2)
Feedback resistance: R1 = 330 k Ω, 600 mAR2 = 330 k Ω
V
FB1
FB1 reference voltage No load 0.59 0.6 0.61 VOvercurrent protection threshold 0.9 1.9 AOvervoltage protection threshold
0.67 0.75 0.83 V(sensing at FB1 pin)High-side Nch FET ON resistance
(3)
VPS = 5 V 320 500 m Ω
Low-side Nch FET ON resistance
(3)
VPS = 5 V 200 250 m Ω
Trigger voltage to start CH3 0.48 VTrigger voltage to power off LDO 0.25 V
CH2
V
CC2
Supply voltage 1.5 5.5 VV
OUT2
Output voltage
(2)
2.5 3.6 VV
CC2
> 2.4 V, V
OUT2
= 3.3 V,I
OUT2
Output current
(2)
Feedback resistance: R1 = 180 k Ω, 600 mAR2 = 820 k Ω
V
FB2
FB2 reference voltage No load 0.595 0.605 0.615 VOvercurrent protection threshold 2.6 3.3 AOvervoltage protection threshold
0.67 0.75 0.83 V(sensing at FB2 pin)High-side FET
VPS = 5 V 100 210ON resistanceBuck
mΩside
(3)
Low-side FET
VPS = 5 V 450 600ON resistance
(1) T
A
= 25 ° C(2) Specified by design(3) The value of FET ON resistance includes the resistance of bonding wire.
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............................................................................................................................................................ SLVS835C – APRIL 2008 – REVISED APRIL 2009
ELECTRICAL CHARACTERISTICS (continued)0 ° C ≤T
J
≤125 ° C, 1.8 V ≤V
CC2
≤5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
High-side FET
VPS = 5 V 130 240ON resistanceBoost
mΩside
(3)
Low-side FET
VPS = 5 V 80 140ON resistanceTrigger voltage to power off CH3 V
OUT2
= 0.5 V 0.5 VV
OUT2
leakage current V
OUT2
= 0.5 V 1 µANch FET ON resistance for discharge XSLEEP = AGND, ENAFE = AGND 1 2 k Ω
CH3
V
CC3
Supply voltage 2.5 5.5 VV
OUT3
Output voltage
(2)
0.9 2.5 VV
CC3
> 2.5 V, V
OUT3
= 1.8 V,I
OUT3
Output current
(2)
Feedback resistance: R1 = 220 k Ω, 300 mAR2 = 470 k Ω
V
FB3
FB3 reference voltage No load 0.59 0.6 0.61 VOvercurrent protection threshold 0.6 1 AOvervoltage protection threshold
0.67 0.75 0.83 V(sensing at FB3 pin)High-side Nch FET ON resistance
(4)
VPS = 5 V 370 750 m Ω
Low-side Nch FET ON resistance
(4)
VPS = 5 V 300 600 m Ω
Nch FET ON resistance for discharge XSLEEP = AGND, ENAFE = AGND 1 2 k Ω
Trigger voltage to start CH2 0.48 VTrigger voltage to power off CH1 0.2 V
CH4
V
CC4
Supply voltage 1.5 5.5 VV
OUT4
Output voltage
(5)
2.2 3.6 VV
CC4
> 2.4 V, V
OUT4
= 3.3 V,I
OUT4
Output current
(5)
Feedback resistance: R1 = 82 k Ω, 100 300 mAR2 = 330 k Ω
V
FB4
FB4 reference voltage No load 0.595 0.605 0.615 VOvercurrent protection threshold 1.4 1.65 AOvervoltage protection threshold
0.67 0.75 0.83 V(sensing at FB4 pin)High-side FET
VPS = 5 V 130 310ON resistanceBuck
mΩside
(4)
Low-side FET
VPS = 5 V 600 730ON resistance
High-side FET
VPS = 5 V 170 270ON resistanceBoost
mΩside
(4)
Low-side FET
VPS = 5 V 130 250ON resistanceV
OUT4
leakage current V
OUT4
= 0.5 V 1 µANch FET ON resistance for discharge XSLEEP = AGND, ENAFE = AGND 1 2 k Ω
CH5
V
CC5
Supply voltage 1.5 5.5 VV
OUT5
Output voltage
(5)
V
CC5
18 VV
FB5
FB5 reference voltage No load 0.98 1 1.02 VV
CC5
> 2.4 V, V
OUT5
= 15 V,I
OUT5
Output current
(5)
Feedback resistance: R1 = 40 k Ω, 50 mAR2 = 560 k Ω
(4) The value of FET ON resistance includes the resistance of bonding wire.(5) Specified by design
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SLVS835C – APRIL 2008 – REVISED APRIL 2009 ............................................................................................................................................................
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ELECTRICAL CHARACTERISTICS (continued)0 ° C ≤T
J
≤125 ° C, 1.8 V ≤V
CC2
≤5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
Overcurrent protection threshold 1.3 1.6 AOvervoltage protection threshold
1.09 1.25 1.38 V(sensing at FB5 pin)Nch FET ON resistance
(4)
VPS = 5 V 610 900 m Ω
Load switch ON resistance
1.5 V < V
CC5
< 5.5 V 100 470 m Ω(between V
CC5
and SW5)Load switch ramp-up time 1.5 V < V
CC5
< 5.5 V,
200 µS(between V
CC5
and SW5)
(5)
SWOUT capacitance = 4.7 µFLoad switch leakage current
1µA(between V
CC5
and SW5)Max duty cycle 96 98 %Trigger voltage to start up CH6 SEQ56 = AGND 0.8 V
CH6
V
CC6
Supply voltage 2.5 5.5 VV
OUT6
Output voltage
(5)
– 10 – 5 VV
CC6
> 2.8 V, V
OUT6
= – 7.5 V,I
OUT6
Output current
(5)
Feedback resistance: R1 = 136 k Ω, 100 mAR2 = 820 k Ω
V
FB6
FB6 reference voltage No load – 0.02 0 0.02 VOvercurrent protection threshold V
CC6
> 2.8 V 1.1 1.35 AOvervoltage protection threshold
– 0.3 – 0.2 – 0.1 V(sensing at FB6 pin)Pch FET ON resistance
(6)
V
CC6
= 3.6 V 640 1100 m Ω
Max duty cycle 84 91 98 %Trigger voltage to power off CH6 SEQ56 = AGND 0.5 0.53 0.56 VV
S/S56
S/S56 pin voltage 1.22 1.25 1.28 VI
S/S56
S/S56 pin source current S/S56 = AGND 170 200 230 µA
CH7
V
CC7
Supply voltage
(7)
1.5 5.5 VV
OUT7
Output voltage
(8)
V
CC7
< V
OUT7
3 20 VV
CC7
> 2.4 V, V
OUT7
= 15 V,Feedback resistance: R1 = 47 k Ω,I
OUT7_L
Lower output current
(7)
3.7 5 6.3 mAR2 = 680 k Ω, Rsense = 10 Ω,B_ADJ pin voltage = 0 VV
CC7
> 2.4 V, V
OUT7
= 15 V,Feedback resistance: R1 = 47 k Ω,I
OUT7_H
Higher output current
(7)
23.7 25 26.3 mAR2 = 680 k Ω, Rsense = 10 Ω,B_ADJ pin voltage = 1 VV
FBV
FBV reference voltage No load 0.97 1 1.03 VOvervoltage protection threshold
1.15 1.25 1.35 V(sensing at FBV pin)Overcurrent protection threshold 0.8 1.2 ANch FET ON resistance
(6)
700 1200 m Ω
Max duty cycle 86 91 99 %Load switch ON resistance 2 4 Ω
Load switch leakage current
1µA(between C-IN and FBC)R
B-ADJ
B-ADJ pin input impedance 1 M Ω
(6) The value of FET ON resistance includes the resistance of bonding wire.(7) Specified by design(8) Due to constant current control for CH7, the operating condition is that Input voltage is less than LED supply voltage (output voltage).
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............................................................................................................................................................ SLVS835C – APRIL 2008 – REVISED APRIL 2009
ELECTRICAL CHARACTERISTICS (continued)0 ° C ≤T
J
≤125 ° C, 1.8 V ≤V
CC2
≤5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
CH8
T
A
= 25 ° C,
1.8 5.5Start up (XSLEEP from AGND to V
CC2
)Supply voltage
(7)
VXSLEEP = V
CC2
1.5 5.5VPS Output voltage
(7)
3.3 5.5 VXSLEEP = H, ENAFE = AGND, No load 1.23 1.25 1.27V
FB8
FB8 reference voltage VCH8 operation mode: PFM mode, No load 1.2 1.25 1.35Fixed ON time at PFM mode V
CC2
= 3.6 V 250 nsMax duty cycle 76 85 92 %Source impedance VPS = 5 V, ISW = 100 mA 5 7.5SW8LD
Ωdriver
Sink impedance VPS = 5 V, ISW = – 100 mA 1 1.5Source impedance VPS = 5 V, ISW = 100 mA 10 15SW8HD
Ωdriver
Sink impedance VPS = 5 V, ISW = – 100 mA 5 7.5Overvoltage protection threshold
1.3 1.56 1.8 V(sensing at FB8 pin)FBG7/8 FET ON resistance VPS = 5 V, XSLEEP = V
CC2
0.6 k Ω
FBG7/8 leakage current XSLEEP = AGND, ENAFE = AGND 1 µA
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S/S
PGND5/7
CIN
To
CH7
TSD
SEQUENCE
CONTROL
CH1/2/3
W/
Discharge
SEQUENCE
CONTROL
(CH5/6)
EEPROM
OCP+UV
X64
CH1-6,8
1/2
1.5MHz
OSC
FromEN7
VCC6
S/ 56S
S 6W CH6
INV
FB6
F 5B
CH3
Buck
CP/BST
INT
POR
S/S,
REF
LDO
U-SD
Power
CH2
Buck
Boost
CP/BST
CP/BST
CH4
Buck
Boost
CP/BST
CP/BST
CH1
Buck
CP/BST
SW5
SWOUT CH5
Boost
CP
VCC5
SW7
FBC
CH7
Boost
FBV
B- ADJ
FB8
PS
SW8LD
LL8
SW8HD
FBG7/8
CH8
Boost
Start
Up
PFM
F 3B
VCC3
SW4I
FB4
VCC2
VOUT4
SW2I
AGND
REF
EN7
XSLEEP
VOUT2
FB2
SW2S
GND2
VCC1
SW4S
PGND4
ENAFE
VCC4
PGND3
S 3W
PGND1
SW1
FB1
48
SEQ56
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
45
46 47
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
EN56
TPS65530A
SLVS835C – APRIL 2008 – REVISED APRIL 2009 ............................................................................................................................................................
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BLOCK DIAGRAM
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APPLICATION INFORMATION
TPS65530A
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............................................................................................................................................................ SLVS835C – APRIL 2008 – REVISED APRIL 2009
A. When output voltage is higher than input voltage at 2AA battery models, V
CC1
and V
CC3
should be connected to theCH8 output. When the 2AA battery is connected, V
CC6
should be connected to the CH8 output.B. The external FET for CH8 is dependent on the load. When the motor is connected to CH8, the external FET is large.C. It is acceptable to connect directly to PS without resistor.
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FUNCTIONAL DESCRIPTION
Logic True Table
Power ON/OFF Sequence
TPS65530A
SLVS835C – APRIL 2008 – REVISED APRIL 2009 ............................................................................................................................................................
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The enable/disable of each channel is controlled by logic input signals level at XSLEEP (pin 7 for all channels),ENAFE (pin 6 for CH4), EN56 (pin 46 for CH5/6) and EN7 (pin 8 for CH7). Table 1 is the summary of theenable/disable mode.
Table 1. Control Pin vs Enable/Disable
NO. OF
XSLEEP ENAFE EN56 EN7 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8
(1)
LDOSTATE
1 L L – – OFF OFF OFF OFF OFF OFF OFF OFF OFF2 H L L L ON ON ON OFF OFF OFF OFF PWM ON3 H L L H ON ON ON OFF OFF OFF ON PWM ON4 H L H L ON ON ON OFF ON ON OFF PWM ON5 H L H H ON ON ON OFF ON ON ON PWM ON6 H H L L ON ON ON ON OFF OFF OFF PWM ON7 H H L H ON ON ON ON OFF OFF ON PWM ON8 H H H L ON ON ON ON ON ON OFF PWM ON9 H H H H ON ON ON ON ON ON ON PWM ON10
(2)
L H – – OFF OFF OFF OFF OFF OFF OFF PFM OFF
(1) PWM = pulse width modulation, PFM = pulse frequency modulation(2) State 10 (CH8: PFM mode) must go through State 2.
This device has the power ON/OFF sequence of CH1/2/3/8/REF and CH5/6 for DSC application. TheCH1/2/3/8/REF sequence is shown in Figure 1 . The CH5/6 sequence is shown in Figure 2 . CH4 and CH7 haveindividual sequences but CH4 – 6 have the subordinate relationship with CH1 – 3 because the slope of soft start isthe same and puts high priority of CH1 – 3 to avoid the functional conflict (see the Soft Start description). Due tothis, CH4 – 6 should not be ON before CH1 – 3 are ON. When XSLEEP is forced low, all channels turn OFF withthe power OFF sequence.
Figure 1. CH1/CH2/CH3/CH8/REF Power ON/OFF Sequence
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Soft Start
Undervoltage Lockout (UVLO)
Protection
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............................................................................................................................................................ SLVS835C – APRIL 2008 – REVISED APRIL 2009
Figure 2. CH5/6 Power ON/OFF Sequence
This function reduces the rush current from the battery at start-up. This device has two slopes defined by S/S(pin 9) and S/S56 (pin 45). The slopes of CH1 – 4 are defined by S/S; the slopes of CH5/6 depend on SEQ56 (pin47) signal level. When SEQ56 is low, the slope of CH5 is defined by S/S; the slope of CH6 is defined by S/S56.When SEQ56 is high, the slopes of CH5/6 are defined by S/S56. The soft-start time is calculated by Equation 1and Equation 2 .
T
S/S
= C
S/S
× 60 (1)
T
S/S56
= C
S/S56
× 6.25 (2)
Where:
C
S/S
= Capacitance at S/S [ µF]
T
S/S
= Soft-start duration defined by S/S [ms]
C
S/S56
= Capacitance at S/S56 [ µF]
T
S/S56
= Soft-start duration defined by S/S56 [ms]
The recommended capacitances are C
S/S
= 0.1 [ µF] or T
S/S
= 6.0 [ms], C
S/S56
= 1.0 [ µF] or T
S/S56
= 6.25 [ms].
This device monitors the battery voltage level at V
CC2
(pin 12) When XSLEEP is high and V
CC2
is less than thethreshold (defined in Electrical Characteristics as UVLO detect level), the operation shuts down immediatelywithout the power OFF sequence. UVLO has a hysteresis as shown in Figure 3 . This factor is defined inElectrical Characteristics as UVLO hysteresis.
Figure 3. UVLO Hysteresis
The TPS65530A has three protection conditions: overcurrent protection (OCP), overvoltage protection (OVP),and thermal shutdown (TSD) (see Table 2 ).
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CHANNEL DESCRIPTIONS
CH1/3 Description
TPS65530A
SLVS835C – APRIL 2008 – REVISED APRIL 2009 ............................................................................................................................................................
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Table 2. Protection Conditions
PROTECTION CH1 – CH6 CH7 CH8 REF (LDO)
All CH shutdown All CH shutdown (latch-off)Change All CH shutdown (latch-off)
Forced OFF at MOSFET (latch-off) (without power (without power OFFmode (without power OFF sequence)
OFF sequence) sequence)Current over the threshold, V
OUTDetect less than 80% to compare the Current over the V
OUT
less than 70% to V
OUT
less than 80% tocondition target, and threshold compare the target compare the targetcount 64 cycle × 1.5 MHzXSLEEP: Change level from LowOCP
to High XSLEEP: Change level XSLEEP: Change level fromCurrent less than theENAFE: Change level from Low from Low to High Low to Highthreshold (automaticto High (for CH4) ENAFE: Change level ENAFE: Change level fromrestoration)Comeback EN56: Change level from Low to from Low to High Low to Highorcondition High (for CH5/6) or orV
CC2
: Apply more thanor V
CC2
: Apply more than V
CC2
: Apply more than UVLOUVLO threshold (1.4 V)V
CC2
: Apply more than UVLO UVLO threshold (1.4 V) threshold (1.4 V) afterafter removing V
CC2threshold (1.4 V) after removing after removing V
CC2
removing V
CC2V
CC2
Forced OFF atChange Forced OFF at applicable CH
MOSFET, load switch Forced OFF at MOSFETmode MOSFET
turns ONDetect Voltage over the threshold at Voltage over the Voltage over theOVP No OVP functioncondition feedback threshold at feedback threshold at feedbackVoltage less than theComeback Voltage less than the threshold at EN7: Change level from
threshold at feedbackcondition feedback (auto-recovery) Low to High
(auto-recovery)Change
All CH shutdown (without power OFF sequence)mode
DetectTSD The junction temperature is more than the threshold.condition
Comeback XSLEEP: Change level from Low to High, ENAFE: Change level from Low to High (for CH4), EN56: Change level fromcondition Low to High (for CH5/6), or V
CC2
: More than 1.4 V
Both CH1 and CH3 are the same topology. CH1/3 are the voltage-mode-controlled synchronous buck convertersfor engine core (CH1) or external memory (CH3). Both high-side and low-side switches are integrated into thedevice and consist of NMOS-FET only. The gate of the high-side switch is driven by bootstrap circuit. Thecapacitance of the bootstrap is included in the device. These channels are able to operate up to 100% dutycycle.
This device has a discharge path to use the switch (Q_Discharge1/3) for the CH1/3 output capacitor via theinductor. The switch is activated after the power OFF sequence has started. Typical resistance at the dischargecircuit is 1 k Ω. When the device detects the threshold at FB1/3 after the power OFF sequence has started, theMOSFET turns OFF and the output is fixed with high impedance.
It is acceptable to connect the battery to V
CC1
/V
CC3
(pins 18/23) directly when the battery voltage is more than2.5 V. When the battery voltage is less than 2.5 V, the CH8 output should be connected to V
CC1
/V
CC3
.
The output voltage is programmed from 0.9 V to 2.5 V (both CH1 and CH3) to use the feedback loop sensed bythe external resistances. The output voltage is calculated by Equation 3 . The block diagram is shown in Figure 4 .
V
OUT
= (1 + R2/R1) × 0.6 [V] (3)
Where:
V
OUT
= Output voltage [V]
R1, R2 = Feedback resistance (see Figure 4 )
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CH1/3 Recommended Parts
CH2/4 Description
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............................................................................................................................................................ SLVS835C – APRIL 2008 – REVISED APRIL 2009
Figure 4. CH1/3 Block Diagram
Table 3. Recommended Parts for Inductor (CH1/3)
VENDOR TYPE NO. INDUCTANCE ( µH) DCR (m Ω) SIZE (mm)
TOKO DE2812C-1098AS-4R7M 4.7 130 2.8 × 3.0 × 1.2
Table 4. Recommended Parts for Capacitor (Input, CH1/3)
VENDOR TYPE NO. CAPACITANCE ( µF) TOLERANCE (%) SIZE (mm)
Murata GRM21BB30J226ME38 22.0 20 2.0 × 1.25 × 1.25 (EIA code: 0805)
Table 5. Recommended Parts for Capacitor (Output, CH1/3)
VENDOR TYPE NO. CAPACITANCE ( µF) TOLERANCE (%) SIZE (mm)
TDK C2012X5R0J106M 10.0 20 2.0 × 1.25 × 1.25 (EIA code: 0805)
Both CH2 and CH4 are the same topology. CH2/4 are the average current-mode-controlled synchronousback-boost converters for engine I/O (CH2) or AFE (CH4). This converter is an adapted H-bridge circuit to usefour switches. These switches are integrated into the device and consist of NMOS-FET only. The gate of thehigh-side switch is controlled by the bootstrap circuit. The capacitance of the bootstrap is included in the device.
The device automatically switches from buck operation to boost operation or from boost operation to buckoperation as required by the configuration. It always uses one active switch, one rectifying switch, one switchpermanently on, and one switch permanently off. Therefore, it operates as a buck converter when the inputvoltage is higher than the output voltage, and as a boost converter when the input voltage is lower than theoutput voltage. There is no mode of operation in which all four switches are permanently switching.
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This device has a discharge switch (Q_Discharge2/4) for the CH2/4 output capacitor. The typical ON resistanceat the discharge switch is 1 k Ω. The discharge switch is activated when XSLEEP turns low. For CH4 only, theswitch is also activated when ENAFE turns low. After output voltage reaches approximately 0.5 V, the dischargeswitch turns OFF and V
OUT2
/V
OUT4
is changed into high impedance. The output voltage is programmable from 2.5V to 3.6 V (for CH2) or from 2.2 V to 3.6 V (for CH4) to use the feedback loop sensed by the externalresistances. The output voltage is calculated by Equation 4 . The block diagram is shown in Figure 5 .
V
OUT
= (1 + R2/R1) × 0.6 [V] (4)
Where:
V
OUT
= Output voltage [V]
R1, R2 = Feedback resistance (see Figure 5 )
Figure 5. CH2/4 Block Diagram
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CH2/4 Recommended Parts
CH5 Description
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Table 6. Recommended Parts for Inductor (CH2)
VENDOR TYPE NO. INDUCTANCE ( µH) DCR (m Ω) SIZE (mm)
TOKO DE2812C-1098AS-2R7M 2.7 72 2.8 × 3.0 × 1.2
Table 7. Recommended Parts for Inductor (CH4)
VENDOR TYPE NO. INDUCTANCE ( µH) DCR (m Ω) SIZE (mm)
TOKO DE2812C-1098AS-4R7M 4.7 130 2.8 × 3.0 × 1.2
Table 8. Recommended Parts for Capacitor (Input, CH2/4)
VENDOR TYPE NO. CAPACITANCE ( µF) TOLERANCE (%) SIZE (mm)
Murata GRM21BB30J226ME38 22.0 20 2.0 × 1.25 × 1.25 (EIA code: 0805)
Table 9. Recommended Parts for Capacitor (Output, CH2/4)
VENDOR TYPE NO. CAPACITANCE ( µF) TOLERANCE (%) SIZE (mm)
Taiyo Yuden JMK212BJ476MG-T 47.0 20 2.0 × 1.25 × 1.25 (EIA code: 0805)
CH5 is the peak current-mode-controlled nonsynchronous boost converter for CCD+. The switch betweeninductor and power GND is integrated into the device and consists of NMOS-FET. Also, this device has a loadswitch between the battery and inductor and consists of NMOS-FET. The gate of the switch is controlled by acharge-pump circuit. The output voltage is programmable up to 18 V to use the feedback loop sensed by theexternal resistances. The output voltage is calculated by Equation 5 . The block diagram is shown in Figure 6 .
V
OUT5
= (1 + R2/R1) × 1.0 [V] (5)
Where:
V
OUT5
= Output voltage of CH5 [V]
R1, R2 = Feedback resistance (see Figure 6 )
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CH5 Recommended Parts
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SLVS835C – APRIL 2008 – REVISED APRIL 2009 ............................................................................................................................................................
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Figure 6. CH5 Block Diagram
Table 10. Recommended Parts for Inductor (CH5)
VENDOR TYPE NO. INDUCTANCE ( µH) DCR (m Ω) SIZE (mm)
TOKO DE2812C-1098AS-120M 12.0 340 2.8 × 3.0 × 1.2
Table 11. Recommended Parts for Capacitor (Output, CH5)
VENDOR TYPE NO. CAPACITANCE ( µF) TOLERANCE (%) SIZE (mm)
Murata GRM31CB31E106KA75 10.0 10 3.2 × 1.6 × 1.6 (EIA code: 1206)
Table 12. Recommended Parts for Capacitor (SWOUT, CH5)
VENDOR TYPE NO. CAPACITANCE ( µF) TOLERANCE (%) SIZE (mm)
TDK C2012X5R1A335M 3.3 20 2.0 × 1.25 × 1.25 (EIA code: 0805)
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CH6 Description
CH6 Recommended Parts
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Table 13. Recommended Parts for Diode (CH5)
VENDOR TYPE NO. VR (V) IF (mA) VF (V)/IF (A) CAPACITANCE (pF) SIZE (mm)
Sanyo SB0503EJ 30 500 0.55/0.5 16.5 1.6 × 0.8 × 0.6
CH6 is the voltage-mode-controlled nonsynchronous inverting converter for CCD – . The switch between the inputvoltage and inductor is integrated into the device and consists of PMOS-FET. It is acceptable to connect thebattery to V
CC6
(pin 42) directly when the battery voltage is more than 2.5 V. When the battery voltage is lessthan 2.5 V, the CH8 output should be connected to V
CC6
. The output voltage is programmable from – 10 V to– 5 V to use the feedback loop sensed by the external resistances. The output voltage is calculated byEquation 6 . The block diagram is shown in Figure 7 .
V
OUT6
= 1.25 – (1 + R2/R1) × 1.25 [V] (6)
Where:
V
OUT
= Output voltage of CH6 [V]
R1, R2 = Feedback resistance (see Figure 7 )
Figure 7. CH6 Block Diagram
Table 14. Recommended Parts for Inductor (CH6)
VENDOR TYPE NO. INDUCTANCE ( µH) DCR (m Ω) SIZE (mm)
TOKO DE2815C-1071AS-120M 12.0 240 2.8 × 3.0 × 1.2
Table 15. Recommended Parts for Capacitor (Input, CH6)
VENDOR TYPE NO. CAPACITANCE ( µF) TOLERANCE (%) SIZE (mm)
Murata GRM21BB31A106KE18 10.0 10 2.0 × 1.25 × 1.25 (EIA code: 0805)
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CH7 Description
LED BADJ
SENSE SENSE
0.2 0.05
I = • V +
R R
(7)
TPS65530A
SLVS835C – APRIL 2008 – REVISED APRIL 2009 ............................................................................................................................................................
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Table 16. Recommended Parts for Capacitor (Output, CH6)
VENDOR TYPE NO. CAPACITANCE ( µF) TOLERANCE (%) SIZE (mm)
Murata GRM31CB31E106KA75 10.0 10 3.2 × 1.6 × 1.6 (EIA code: 1206)
Table 17. Recommended Parts for Diode (CH6)
VENDOR TYPE NO. VR (V) IF (mA) VF (V)/IF (A) CAPACITANCE (pF) SIZE (mm)
Sanyo SB0503EJ 30 500 0.55/0.5 16.5 1.6 × 0.8 × 0.6
CH7 is the voltage-mode-controlled nonsynchronous boost converter for the backlight LED. The switch betweenthe inductor and power GND is integrated into the device and consists of NMOS-FET. Also, this device has aload switch to control the output current and consists of NMOS-FET. The output current is constant and iscalculated by Equation 7 . It is controlled by the B_ADJ (pin 32) input voltage as shown in Figure 8 . The B_ADJinput voltage is required as an analog input. When it is required to input PWM signal for B_ADJ, the RC filter isneeded.
Where:
I
LED
= Output current of CH7 [A]
R
SENSE
= Sense resistor between FBC and PGND5/7 [ Ω]
V
BADJ
= B_ADJ input voltage (0 < V
BADJ
< 1) [V]
Figure 8. Output Current vs B_ADJ Input Voltage (RSENSE = 10 Ω)
The principle of the operation is to adjust the duty cycle of the MOSFET. When the B_ADJ input voltage ischanged, the level of “ A ” point shown in Figure 9 is changed to get the desired duty cycle compared to the sensecurrent.
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Figure 9. LED Brightness Control Block Diagram
At first, CH7 operates as pulse frequency modulation (PFM) mode at start-up. After reaching the target outputvoltage, CH7 operation is changed from PFM mode to pulse width modulation (PWM) mode automatically. Theoutput voltage is programmable up to 20 V to use the feedback loop sensed by the external resistances. Themaximum output voltage is calculated by Equation 8 . The block diagram is shown in Figure 10 .
V
OUT7 MAX
= 1 + (R2/R1) × 1.25 [V] (8)
Where:
V
OUT7 MAX
= Maximum output voltage of CH7 [V]
R1, R2 = Feedback resistance (see Figure 10 )
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CH7 Recommended Parts
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Figure 10. CH7 Block Diagram
Table 18. Recommended Parts for Inductor (CH7)
VENDOR TYPE NO. INDUCTANCE ( µH) DCR (m Ω) SIZE (mm)
TOKO DE2815C-1071AS-120M 12.0 240 2.8 × 3.0 × 1.2
Table 19. Recommended Parts for Capacitor (Input, CH7)
VENDOR TYPE NO. CAPACITANCE ( µF) TOLERANCE (%) SIZE (mm)
Murata GRM21BB31A106KE18 10.0 10 2.0 × 1.25 × 1.25 (EIA code: 0805)
Table 20. Recommended Parts for Diode (CH7)
VENDOR TYPE NO. VR (V) IF (mA) VF (V)/IF (A) CAPACITANCE ( µF) SIZE (mm)
Sanyo SB0503EJ 30 500 0.55/0.5 16.5 1.6 × 0.8 × 0.6
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CH8 Description
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............................................................................................................................................................ SLVS835C – APRIL 2008 – REVISED APRIL 2009
Table 21. Recommended Parts for Capacitor (Output, CH7)
VENDOR TYPE NO. CAPACITANCE ( µF) TOLERANCE (%) SIZE (mm)
Murata GRM31CB31E106KA75 10.0 10 3.2 × 1.6 × 1.6 (EIA code: 1206)
CH8 uses an external FET. It is based on voltage-mode-controlled synchronous boost converter topology usedfor motor control and an IC inside driver. CH8 output should connect to PS (pin 29) because PS is the path tosupply the power for the driver of each channel. This channel has two operation modes – PWM and PFM. Theoperation depends on the XSLEEP (pin 7) and ENAFE (pin 6) signal level.
When XSLEEP turns high, CH8 operates as PWM mode. The ENAFE signal level does not matter. For start-up(less than 2.5 V at CH8 output), CH8 operates as WAKE mode to use the internal MOSFET switch connected toLL8 (pin 27). The duty cycle of WAKE mode is fixed. After PS voltage reaches 2.5 V, CH8 operation is changedfrom WAKE mode to PFM mode automatically. PFM mode is driven by the external MOSFET switch. When PSvoltage reaches 90% of the target voltage, the operation mode is changed from PFM mode to PWM modeautomatically. To operate CH8 in PFM mode only, XSLEEP must be high at first. After that, XSLEEP goes lowand ENAFE is high for PFM mode. PFM operation is recommended for the IC drive only from an efficiency pointof view.
CH8 has reversed current protection to monitor the different voltage between LL8 and PS. The protectionmonitors the difference between both PFM mode and PWM mode. When LL8 voltage is larger than PS voltage,the function is activated. When the function is activated, SW8HD (pin 28) level is changed from high to low;SW8LD (pin 26) level stays low. This means that LL8 voltage converges the battery voltage naturally.
The recovery condition is dependent on the operation mode. When CH8 operates as PFM mode, the condition isthat FB8 (pin 30) voltage is less than 1.25 V. When CH8 operates as PWM mode, the condition is that LL8voltage is smaller than PS voltage at the rising edge of the internal clock.
The output voltage is programmable from 3.3 V to 5.5 V to use the feedback loop sensed by the externalresistances. The output voltage is calculated by Equation 9 . The block diagram is shown in Figure 11 .
V
OUT8
= (1 + R1/R2) × 1.25 [V] (9)
Where:
V
OUT8
= Output voltage of CH8 [V]
R1, R2 = Feedback resistance (see Figure 11 )
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CH8 Recommended Parts
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Figure 11. CH8 Block Diagram
For Motor Control and IC Inside Driver
Table 22. Recommended Parts for Inductor (CH8)
VENDOR TYPE NO. INDUCTANCE ( µH) DCR (m Ω) SIZE (mm)
TOKO DE4518-1124-4R3M 4.3 54 4.5 × 4.7 × 1.8
Table 23. Recommended Parts for Capacitor (Input, CH8)
VENDOR TYPE NO. CAPACITANCE ( µF) TOLERANCE (%) SIZE (mm)
TDK C3216X5R0J226M 22.0 × 2 pcs 20 3.2 × 1.6 × 0.85 (EIA code: 1206)
Table 24. Recommended Parts for Capacitor (Output, CH8)
VENDOR TYPE NO. CAPACITANCE ( µF) TOLERANCE (%) SIZE (mm)
Murata GRM31MB31A106KE18 10.0 × 2 pcs 10 3.2 × 1.6 × 1.15 (EIA code: 1206)
Table 25. Recommended Parts for FET (CH8)
ID (DC) ID (DC) Rds(on) Rds(on)VENDOR TYPE NO. QG (N-ch) (nQ) QG (P-ch) (nQ)(N-ch) (A) (P-ch) (A) (N-ch) ( Ω) (P-ch) ( Ω)
VEC2607 4.5 – 4.0 0.032/4 V 0.037/ – 4.5 V 7.6 11.0Sanyo
VEC2611 3.0 – 2.6 0.053/4 V 0.080/ – 4.5 V 8.8 6.5
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Layout Consideration
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............................................................................................................................................................ SLVS835C – APRIL 2008 – REVISED APRIL 2009
For IC Inside Driver Only
Table 26. Recommended Parts for Inductor (CH8)
VENDOR TYPE NO. INDUCTANCE ( µH) DCR (m Ω) SIZE (mm)
Taiyo Yuden LB2518T330 33 700 1.8 × 2.5 × 1.8
Table 27. Recommended Parts for Capacitor (Input, CH8)
VENDOR TYPE NO. CAPACITANCE ( µF) TOLERANCE (%) SIZE (mm)
TDK C3216X5R0J226M 22 20 3.2 × 1.6 × 0.85 (EIA code: 1206)
Table 28. Recommended Parts for Capacitor (Output, CH8)
VENDOR TYPE NO. CAPACITANCE ( µF) TOLERANCE (%) SIZE (mm)
TDK C1608X5R0J475M 4.7 20 1.6 × 0.8 × 0.8 (EIA code: 0603)
Table 29. Recommended Parts for FET (CH8)
ID (DC) ID (DC) Rds(on) Rds(on)VENDOR TYPE NO. QG (N-ch) (nQ) QG (P-ch) (nQ)(N-ch) (A) (P-ch) (A) (N-ch) ( Ω) (P-ch) ( Ω)
ON
NTZD3155C 0.54 – 0.43 0.4/4.5 V 0.5 / – 4.5 V 1.5 1.7Semiconductor
Sanyo SCH2615 1.2 – 0.9 0.28/4 V 0.47/ – 4.5 V 1.15 1.43
To avoid ground shift problems due to the high currents in the switches, separate AGND (pin 10) from PGND1(pin 20), PGND2 (pin 14), PGND3 (pin 25), PGND4 (pin 2), and PGND5/7 (pin 37). The reference GND for allcontrol signals, such as XSLEEP, is AGND. The power switches inside the IC are connected to PGND1, PGND2,PGND3, PGND4, and PGND5/7. Both grounds must be connected on the printed circuit board (PCB) (ideally atonly one point).
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS65530ARSLR ACTIVE VQFN RSL 48 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS65530ARSLRG4 ACTIVE VQFN RSL 48 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS65530ARSLT ACTIVE VQFN RSL 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS65530ARSLTG4 ACTIVE VQFN RSL 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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PACKAGE OPTION ADDENDUM
www.ti.com 5-Apr-2010
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS65530ARSLR VQFN RSL 48 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2
TPS65530ARSLR VQFN RSL 48 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2
TPS65530ARSLT VQFN RSL 48 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2
TPS65530ARSLT VQFN RSL 48 250 180.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS65530ARSLR VQFN RSL 48 2500 367.0 367.0 38.0
TPS65530ARSLR VQFN RSL 48 2500 367.0 367.0 38.0
TPS65530ARSLT VQFN RSL 48 250 210.0 185.0 35.0
TPS65530ARSLT VQFN RSL 48 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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