INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT4040 12-stage binary ripple counter Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification 12-stage binary ripple counter 74HC/HCT4040 (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. FEATURES * Output capability: standard A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. * ICC category: MSI Each counter stage is a static toggle flip-flop. GENERAL DESCRIPTION The 74HC/HCT4040 are high-speed Si-gate CMOS devices and are pin compatible with "4040" of the "4000B" series. They are specified in compliance with JEDEC standard no. 7A. APPLICATIONS * Frequency dividing circuits * Time delay circuits The 74HC/HCT4040 are 12-stage binary ripple counters with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve parallel outputs * Control counters QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC tPHL/ tPLH propagation delay HCT CL = 15 pF; VCC = 5 V CP to Q0 14 16 ns Qn to Qn+1 8 8 ns fmax maximum clock frequency 90 79 MHz CI input capacitance 3.5 3.5 pF CPD power dissipation capacitance per package 20 20 pF notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". December 1990 2 Philips Semiconductors Product specification 12-stage binary ripple counter 74HC/HCT4040 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 8 GND ground (0 V) 9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1 Q0 to Q11 parallel outputs 10 CP clock input (HIGH-to-LOW, edge-triggered) 11 MR master reset input (active HIGH) 16 VCC positive supply voltage Fig.1 Pin configuration. December 1990 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification 12-stage binary ripple counter 74HC/HCT4040 FUNCTION TABLE INPUTS OUTPUTS CP MR Qn X L L H no change count L Notes 1. H = HIGH voltage level L = LOW voltage level X = don't care = LOW-to-HIGH clock transition = HIGH-to-LOW clock transition Fig.4 Functional diagram. Fig.5 Logic diagram. Fig.6 Timing diagram. December 1990 4 Philips Semiconductors Product specification 12-stage binary ripple counter 74HC/HCT4040 DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 min. -40 to +85 typ. max. min. max. -40 to +125 min. UNIT VCC WAVEFORMS (V) max. tPHL/ tPLH propagation delay CP to Q0 47 17 14 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 Fig.7 tPHL/ tPLH propagation delay Qn to Qn+1 28 10 8 100 20 17 125 25 21 150 30 26 ns 2.0 4.5 6.0 Fig.7 tPHL propagation delay MR to Qn 61 22 18 185 37 31 230 46 39 280 56 48 ns 2.0 4.5 6.0 Fig.7 tTHL/ tTLH output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 Fig.7 tW clock pulse width HIGH or LOW 80 16 14 14 5 4 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.7 tW master reset pulse width; HIGH 80 16 14 22 8 6 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.7 trem removal time MR to CP 50 10 9 8 3 2 65 13 11 75 15 13 ns 2.0 4.5 6.0 Fig.7 fmax maximum clock pulse frequency 6.0 30 35 27 82 98 4.8 24 28 4.0 20 24 MHz 2.0 4.5 6.0 Fig.7 December 1990 5 Philips Semiconductors Product specification 12-stage binary ripple counter 74HC/HCT4040 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI Note to HCT types The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT CP MR 0.85 1.10 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 min. -40 to +85 typ. max. min. max. -40 to +125 min. UNIT VCC (V) WAVEFORMS max. tPHL/ tPLH propagation delay CP to Q0 19 40 50 60 ns 4.5 Fig.7 tPHL/ tPLH propagation delay Qn to Qn+1 10 20 25 30 ns 4.5 Fig.7 tPHL propagation delay MR to Qn 23 45 56 68 ns 4.5 Fig.7 tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.7 tW clock pulse width HIGH or LOW 16 7 20 24 ns 4.5 Fig.7 tW master reset pulse width; HIGH 16 6 20 24 ns 4.5 Fig.7 trem removal time MR to CP 10 2 13 15 ns 4.5 Fig.7 fmax maximum clock pulse frequency 30 72 24 20 MHz 4.5 Fig.7 December 1990 6 Philips Semiconductors Product specification 12-stage binary ripple counter 74HC/HCT4040 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output transition times and the maximum clock pulse frequency. Also showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset to clock (CP) removal time. PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". December 1990 7