Rev 0.7 / Nov. 2005 1
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Document Title
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash Memory
Revision History
Revision
No. History Draft Date Remark
0.0 Initial Draft. Nov. 19. 2004 Preliminary
0.1 Jan. 20. 2005 Preliminary
0.2 Mar. 03. 2005 Preliminary
1) Add Errata
tCLS tCLH tWP tALS tALH tDS tWC tR
Specification 010 25 0 10 20 50 25us
Relaxed value 515 45 5 15 25 70 27us
Case tRC tRP tREH tREA
Specification Read(all) 50 20 20 30
Relaxed value Except for
ID Read 50 20 20 30
ID Read 60 25 30 30
2) Add note.4(table14)
3) Add application note(Power on/off Sequence & Auto sleep mode)
- Texts & figures are added.
4) Change AC parameters
Case tDH
Before x8, x16 10
After x8 10
x16 15
1) Change AC parameters
case tDH
Before x8 10
x16 15
Afer x8, x16 15
2) Add tADL(=100ns) parameters
3) Add Muliti Die Concurrent Operations and Extended Read Status
- Texts and table are added.
4) Edit Table.8
5) Change FBGA Package Dimension
Rev 0.7 / Nov. 2005 2
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Revision History
-Continued-
Revision
No. History Draft Date Remark
0.3 Apr. 01. 2005 Preliminary
0.4
1) Correct AC Timing Characristics Table
- Errata value is eddited.
- tADL(max) is changed to tADL(min )
2) Chage Errata
- tREA is deleted from the Errata
3) Correct Operating Current( Typ.)
- before : 10mA -> after : 15mA(3.3V)
- before : 8mA -> after : 10mA(1.8V)
Apr. 06. 2005 Preliminary
0.5
1) Correct the test Conditions (DC Characteristics table)
2) Change AC Conditions table
3) Add tWW parameter ( tWW = 100ns, min)
- Texts & Figures are added.
- tWW is added in AC timing characteristics table.
4) Edit System Interface Using CE don’t care Figures.
5) Correct Address Cycle Map.
Aug. 05. 2005 Preliminary
1) Change Errata
- Errata values (tWP & tWC) are changed
tCLS tCLH tWP tALS tALH tDS tWC tR
Before 515 45 5 15 25 70 25us
After 515 40 5 15 25 60 27us
Case tRC tRP tREH
before Except fo r
ID Read 50 20 20
ID Read 60 25 30
after Read (all) 60 25 30
Test Conditions (ICC1) Test Conditions (ILI, ILO)
Before tRC=50ns, CE#=VIL,
IOUT=0mA VIN=VOUT=0 to 3.6V
After tRC(1.8V=60ns,3.3V=50ns)
CE#=VIL, IOUT=0mA VIN=VOUT=0 to Vcc (max)
Rev 0.7 / Nov. 2005 3
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Revision History
-Continued-
Revision
No. History Draft Date Remark
0.6
1) Change 2Gb Package Type.
- FBGA package is deleted.
- WSOP package is changed to USOP package.
- Figure & dimension are changed.
2) Correct PKG dimension (TSOP, USOP PKG)
3) Add tRBSY (Table 12)
- tRBSY (Dummy Busy Time for Cache Read)
- tRBSY is 5us (typ.)
4) Delete Errata
5) Change AC Characteristics
Oct. 19. 2005
0.7
1) Change Ac Characteristics
Nov. 04. 2005
CP
Before 0.050
After 0.100
tRC tRP tREH
Before 60 25 30
After 60 40 30
50 25 20
tRC tRP tREH
Before R e ad ID 60 40 30
Data Read 50 25 20
After Read ID 60 25 30
Data Read 50 25 20
Rev 0.7 / Nov. 2005 4
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
FEATURES SUMMARY
HIGH DENSITY NAND FLASH MEMORIES
- Cost effective solutions for mass storage applications
NAND INTERFACE
- x8 or x16 bus width.
- Multiplexed Address/ Data
- Pinout compatibility for all densities
SUPPLY VOLTAGE
- 3.3V device: VCC = 2.7 to 3.6V : HY27UGXX2G2M
- 1.8V device: VCC = 1.7 to 1.95V : HY27SGXX2G2M
Memory Cell Array
= (2K+ 64) Bytes x 64 Pages x 2,048 Blocks
= (1K+32) Words x 64 pages x 2,048 Blocks
PAGE SIZE
- x8 device : (2K + 64 spare) Bytes
: HY27(U/S)G082G2M
- x16 device: (1K + 32 spare) Words
: HY27(U/S)G162G2M
BLOCK SIZE
- x8 device: (128K + 4K spare) Bytes
- x16 device: (64K + 2K spare) Words
PAGE READ / PROGRAM
- Random access: 27us (max.)
- Sequential access: 60ns (min.)
- Page program time: 300us (typ.)
COPY BACK PROGRAM MODE
- Fast page copy without external buffering
CACHE PROGRAM MODE
- Internal Cache Register to improve the program
throughput
FAST BLOCK ERASE
- Block erase time: 2ms (Typ.)
STATUS REGISTER
ELECTRONIC SIGNATURE
- Manufacturer Code
- Device Code
CHIP ENABLE DON'T CARE OPTION
- Simple interface with microcontroller
AUTOMATIC PAGE 0 READ AT POWER-UP OPTION
- Boot from NAND support
- Automatic Memory Download
SERIAL NUMBER OPTION
HARDWARE DATA PROTECTION
- Program/Erase locked during Power transitions
DATA INTEGRITY
- 100,000 Program/Erase cycles
- 10 years Data Retention
PACKAGE
- HY27(U/S)G(08/16)2G2M-T(P)
: 48-Pin TSOP1 (12 x 20 x 1.2 mm)
- HY27(U/S)G(08/16)2G2M-T (Lead)
- HY27(U/S)G(08/16)2G2M-TP (Lead Free)
- HY27(U/S)G(08/16)2G2M-S(P)
: 48-Pin USOP1 (12 x 17 x 0.65 mm)
- HY27(U/S)G(08/16)2G2M-S (Lead)
- HY27(U/S)G(08/16)2G2M-SP (Lead Free)
Rev 0.7 / Nov. 2005 5
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
1. SUMMARY DESCRIPTION
The HYNIX HY27(U/S)G(08/16)2G2M series is a 256Mx8bit with spare 8Mx8 bit capacit y. The device is offe r ed in 1.8V
Vcc Power Supply and in 3.3V Vcc Power Supply.
Its NAND cell provides the most cost-effective solution for the solid state mass storage market.
The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old
data is erased.
The device contains 2048 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected
Flash cells.
A program oper ation allows to write the 21 12-byte page in typical 300 us and an er ase operation can be performed in
typical 2ms on a 128K-byte(X8 device) block.
Data in the page mode can be read out at 60ns cycle time per byte. The I/O pins serve as the ports for address and
data input/output as well as command input. This interface allows a reduced pin count and easy migr ation to wards dif-
ferent densities, without any rearrangement of footprint.
Commands, Data and Addresses are synchronously introduced using CE#, WE#, ALE and CLE input pin.
The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where
required, and internal verification and margining of data.
The modifying can be locked using the WP# input pin.
The output pin RB# (open drain buffer) signals the status of the device during each operation. In a system with mul-
tiple memories the RB# pins can be connected all together to provide a global status signal.
Even the write-intensive system s can take adv antag e of the HY27(U/S)G(08/1 6)2G2M e xtended re liability of 100K pro-
gram/erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm.
Optionally the chip could be offered with the CE# don’t care function. This option allows the direct download of the
code from the NAND Flash memory device by a microcontroller, since the CE# transitions do not stop the read opera-
tion.
The copy back function allows the optimization of defective blocks management : when a page progr am oper ation fails
the data can be directly prog ra mmed in another page inside the same arr ay section without the time consuming serial
data insertion phase.
The cache program feature allows the data insertion in the cache register while the data register is copied into the
flash array. This pipelined program operation improves the program throughput when long files are written inside the
memory.
A cache read feature is also implemented . This feature allows to dramatically improve the read throughput when con-
secutive pages have to be streamed out.
This device includes also extra features like OTP/Unique ID area, Automatic Read at Power Up, Read ID2 extension.
The HYNIX HY27(U/S)G(08/16)2G2M series is available in 48 - TSOP1 12 x 20 mm , 48 - USOP1 12 x 17 mm.
1.1 Product List
PART NUMBER ORIZATION VCC RANGE PACKAGE
HY27SG082G2M x8 1.70 - 1.95 Volt
48TSOP1 / 48USOP1
HY27SG162G2M x16
HY27UG082G2M x8 2.7V - 3.6 Volt
HY27UG162G2M x16
Rev 0.7 / Nov. 2005 6
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Figure1: Logic Diagram
9&&
966
35(
:3
&/(
$/(
5(
:(
&( ,2a,2
,2a,2[2QO\
5%
IO15 - IO8 Data Input / Outputs (x16 only)
IO7 - IO0 Data Input / Outputs
CLE Command latch enable
ALE Address latch enable
CE# Chip Enable
RE# Read Enable
WE# Write Enable
WP# Write Protect
RB# Ready / Busy
Vcc Power Supply
Vss Ground
NC No Connection
PRE Power-On Read Enable
Table 1: Signal Names
Rev 0.7 / Nov. 2005 7
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
1&
1&
1&
1&
1&
1&
5%
5(
&(
1&
1&
9FF
9VV
1&
1&
&/(
$/(
:(
:3
1&
1&
1&
1&
1&
9VV
,2
,2
,2
,2
,2
,2
,2
,2
1&
35(
9FF
1&
1&
1&
,2
,2
,2
,2
,2
,2
,2
,2
9VV
1$1')ODVK
7623
[
1&
1&
1&
1&
1&
1&
5%
5(
&(
1&
1&
9FF
9VV
1&
1&
&/(
$/(
:(
:3
1&
1&
1&
1&
1&
1&
1&
1&
1&
,2
,2
,2
,2
1&
1&
35(
9FF
9VV
1&
1&
1&
,2
,2
,2
,2
1&
1&
1&
1&
1$1')ODVK
7623
[
1&
1&
1&
1&
1&
1&
5%
5(
&(
1&
1&
9FF
9VV
1&
1&
&/(
$/(
:(
:3
1&
1&
1&
1&
1&
1&
1&
1&
1&
,2
,2
,2
,2
1&
1&
35(
9FF
9VV
1&
1&
1&
,2
,2
,2
,2
1&
1&
1&
1&
1$1')ODVK
8623
[
1&
1&
1&
1&
1&
1&
5%
5(
&(
1&
1&
9FF
9VV
1&
1&
&/(
$/(
:(
:3
1&
1&
1&
1&
1&
9VV
,2
,2
,2
,2
,2
,2
,2
,2
1&
35(
9FF
1&
1&
1&
,2
,2
,2
,2
,2
,2
,2
,2
9VV
1$1')ODVK
8623
[
Figure 2. 48TSOP1 Contactions, x8 and x16 Device
Figure 3. 48USOP1 Contactions, x8 and x16 Device
Rev 0.7 / Nov. 2005 8
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
1.2 PIN DESCRIPTION
Pin Name Description
IO0-IO7
IO8-IO15(1)
DATA INPUTS/OUTPUTS
The IO pins allow to input command, address and data and to output data during read / program
operations. The inputs are latched on the rising edge of Write Enable (WE#). The I/O buffer float to
High-Z when the device is deselected or the outputs are disabled.
CLE COMMAND LATCH ENABLE
This input activates the latching of the IO inputs inside the Command Register on the Rising edge of
Write Enable (WE#).
ALE ADDRESS LATCH ENABLE
This input activates the latching of the IO inputs inside the Address Register on the Rising edge of
Write Enable (WE#).
CE# CHIP ENABLE
This input controls the selection of the device. When the device is busy CE# low does not deselect the
memory.
WE# WRITE EN AB LE
This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise
edge of WE#.
RE#
READ ENABLE
The RE# input is the serial data-out control, and when active drives the data onto the I/O bus. Data is
valid tREA after the falling edge of RE# which also increments the internal column address counter by
one.
WP# WRITE PROTECT
The WP# pin, when Low , provides an Har dware pr otection against undesired modify (program / erase)
operations.
RB# READY BUSY
The Ready/Busy output is an Open Drain pin that signals the state of the memory.
VCC SUPPLY VOLTAGE
The VCC supplies the power for all the operations (Read, Write, Erase).
VSS GROUND
NC NO CONNECTION
PRE
To Enable and disable the Power On Auto Read. When PRE is a logic high, Power-On Auto-Read mode
are enabled, and when PRE is a logic low, Power-On Auto-Read mode are disabled. Power-On Auto-
Read mode is available only on 3.3V device.
Not using POWER-ON AUTO-READ, connect it Vss or leave it N.C
Table 2: Pin Description
NOTE:
1. For x16 version only
2. A 0.1uF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple
the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required
during program and erase operations.
Rev 0.7 / Nov. 2005 9
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7
1st Cycle A0 A1 A2 A3 A4 A5 A6 A7
2nd Cycle A8 A9 A10 A11 L(1) L(1) L(1) L(1)
3rd Cycle A12 A13 A14 A15 A16 A17 A18 A19
4th Cycle A20 A21 A22 A23 A24 A25 A26 A27
5th Cycle A28 L(1) L(1) L(1) L(1) L(1) L(1) L(1)
Table 3: Address Cycle Map(x8)
NOTE:
1. L must be set to Low.
IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8-IO15
1st Cycle A0 A1 A2 A3 A4 A5 A6 A7 L(1)
2nd Cycle A8 A9 A10 L(1) L(1) L(1) L(1) L(1) L(1)
3rd Cycle A11 A12 A13 A14 A15 A16 A17 A18 L(1)
4th Cycle A19 A20 A21 A22 A23 A24 A25 A26 L(1)
5th Cycle A27 L(1) L(1) L(1) L(1) L(1) L(1) L(1) L(1)
Table 4: Address Cycle Map(x16)
NOTE:
1. L must be set to Low.
FUNCTION 1st CYCLE 2nd CYCLE 3rd CYCLE Acceptable command
during busy
READ 1 00h 30h -
READ FOR COPY-BACK 00h 35h -
READ ID 90h - -
RESET FFh - - Yes
PAGE PROGRAM (start) 80h 10h -
COPY BACK PGM (start) 85h 10h -
CACHE PROGRAM 80h 15h -
BLOCK ERASE 60h D0h -
READ STATUS REGISTER 70h - - Yes
RANDOM DATA INPUT 85h - -
RANDOM DATA OUTPUT 05h E0h -
CACHE READ START 00h 31h -
CACHE READ EXIT 34h - -
EXTENDED READ STATUS 72h/73h/74h/75h - - Yes
Table 5: Command Set
Rev 0.7 / Nov. 2005 10
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
CLE ALE CE# WE# RE# WP# MODE
H L L Rising H X Read Mode Command Input
L H L Rising H X Address Input(5 cycles)
H L L Rising H H Wri te Mode Command Input
L H L Rising H H Address Input(5 cycles)
LLLRisingHHData Input
LL
L(1) H Falling X Sequential Read and Data Output
L L L H H X During Read (Busy)
XXXXXHDuring Program (Busy)
XXXXXHDuring Erase (Busy)
XXXXXLWrite Protect
XXHXX0V/VccStand By
Table 6: Mode Selection
NOTE:
1. With the CE# don’t care option CE# high during latency time does not stop the read operation
Rev 0.7 / Nov. 2005 11
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
2. BUS OPERATION
There are six standard bus operations that control the device. These are Command Input, Address Input, Da ta Input,
Data Output, Write Protect, and Standby.
Typically glitches less than 5 ns on Chip Enable, Write Enable and R ead Enable are ignor ed by the memory and do not
affect bus operations.
2.1 Command Input.
Command Input bus operation is used to give a command to the memory device. Command are accepted with Chip
Enable low, Command Latch Enable High, Address Latch Enable low and Read Enable High and latched on the rising
edge of Write Enable. Moreover for commands that starts a modifying operation (write/erase) the Write Protect pin
must be high. See figure 5 and table 13 for details of the timings requirements. Command codes are alw ays applied on
IO7:0, disregarding the bus configuration (X8/X16).
2.2 Address Input.
Address Input bus operation allows the insertion of the memory address. To insert the 28 (x8 device) addresses
needed to access the 2Gbit 5 cycles are needed. Addresses are accepted with Chip Enable low, Address Latch Enable
High, Command Latch Enable low and Read Enable high and latched on the rising edge of Write Enable. Moreover f or
commands that starts a modify operation (write/erase) the Write Protect pin must be high. See figure 6 and table 13
for details of the timings requirements. Addresses are always applied on IO7:0, disregarding the bus configuration
(X8/X16).
2.3 Data Input.
Data Input bus operation allows to feed to the device the data to be programmed. The data insertion is serially and
timed by the Write Enable cycles. Data are accepted only with Chip Enable low, Address Latch Enable low, Command
Latch Enable low , Rea d Enable High, and Write Pr otect High and latched on the rising edge of W rite Enable. See figure
7 and table 13 for details of the timings requirements.
2.4 Data Output.
Data Output bus operation allows to read data from the memory array and to check the status register content, the
lock status and the ID data. Data can be serially shifted out toggling the Read Enable pin with Chip Enable low, Write
Enable High, Address Latch Enable low, and Command Latch Enable low. See figures 8,10,11 and table 13 for details
of the timings requirements.
2.5 Write Protect.
Hardware Write Protection is activated when the Write Protect pin is low. In this condit ion modify operation do not
start and the content of the memory is not altered. Write Protect pin is not latched by Write Enable to ensure the pro-
tection even during the power up.
2.6 Standby.
In Standby mode the device is deselected, outputs are disabled and Power Consumption is reduced.
Rev 0.7 / Nov. 2005 12
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
3. DEVICE OPERATION
3.1 Page Read.
Upon initial device power up , the device def aults to Rea d mode. This operation is also initiated by writing 00h and 30h
to the command register along with five address cycles. In two consecutive read operations, the second one doesn’t’
need 00h command, which fiv e address cy cles and 30h comman d initiates that operation. Two types of operations are
available : random read, serial page read. The random read mode is enabled when the page address is changed. The
2112 bytes (X8 device) or 1056 words (X16 device) of data within the selected page are transferred to the data regis-
ters in less than 27us(tR). The sy stem contr oller ma y detect the completion of this data transfer (tR) by analyzing the
output of R/B pin. Once the data in a page is loaded into the data registers, they may be read out in 60ns cycle time
by sequentially pulsing RE#. The repetitive high to low transitions of the RE# clock make the device output the data
starting from the selected column address up to the last column address.
The device may output random data in a page instead of the consecutive sequential data by writing random data out-
put command.
The column address of next data , which is going to be out, may be changed to the addr ess which follows r andom data
output command.
Random data output can be operated multiple times regardless of how many times it is done in a page.
3.2 Page Program.
The device is progr ammed bas ically by page, but it does allow multiple partial page pr ogr amming of a word or co nsec-
utive bytes up to 2112 (X8 device) or words up to 1056 (X16 device), in a single page program cycle. The number of
consecutive partial page programming operation within the same page without an intervening erase operation must
not exceed 4 times for main array (X8 device:1time/512byte, X16 device:1time/256word) and 4 times for spare array
(X8 device:1time/16byte ,X16 device:1time/8word).
The addressing should be done in sequential order in a block. A page program cycle consists of a serial data
loading period in which up to 2112bytes (X8 device) or 1056words (X16 device) of data may be loaded into the data
register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate
cell.
The serial data loading period begins by inputting the Serial Data Input command (80h), followed by the five cycle
address inputs and then serial data. The words other than those to be programmed do not need to be loaded. The
device supports random data input in a page. The column address of next data, which will be entered, may be
changed to the address which follows r andom data input command (85h). Random data input may be operated multi-
ple times regardless of how many times it is done in a page.
The Page Program confirm command (10h) initiates the programming process. Writing 10h alone without previously
entering the serial data will not initiate the programming process. The internal write state controller automatica lly exe -
cutes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other
tasks. Once the program pr ocess starts, the Read Status Regi ster command may be entered to read the status register.
The system controller can detect the completion of a program cycle by monitoring the RB# output, or the Status bit (I/
O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in
progress. When the Page Program is complete, the Write Status Bit (I/O 0) may be checked. The internal write verify
detects only errors for "1"s tha t ar e not successfully progr a mmed to "0"s. The command register remains in Read Sta -
tus command mode until another valid command is written to the command register. Figure 13 details the sequence.
Rev 0.7 / Nov. 2005 13
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
3.3 Block Erase.
The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an
Erase Setu p command (60h). Only addr ess A18 to A28 (X8) or A17 to A27 (X16) is v alid while A1 2 to A17 (X8 ) or A11
to A16 (X16) is ignored. The Erase Confirm command (D0h) following the block address loading initiates the internal
erasing proces s. This two-s tep seque nce of setup f ollowed by execution command ensures that memory contents are
not accidentally erased due to external noise conditions.
At the rising edge of WE# after the erase confirm command input, the internal write controller handles erase and
erase-verify.
Once the erase pr ocess starts, the Rea d Status R egister command ma y be entered to r ead the status register. The sys-
tem controller can detect the completion of an erase by monitoring the RB# output, or the Status bit (I/O 6) of the
Status Register. Only the Read Status command and Reset command are valid while erasing is in progress. When the
erase operation is completed, the Write Status Bit (I/O 0) may be checked.
Figure 17 details the sequence.
3.4 Copy-Back Program.
The copy-back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an
external memory. Since the time-consuming cycles of serial access and re-loading cycles are remov ed, the system pe r-
formance is improv ed. The benefit is especially obvious when a portion of a block is upda ted and the rest of the block
also nee d to be copied to the newly assigned free block. The operation for performing a copy-back program is a
sequential execution of page-read without serial access and copying-program with the address of destination page. A
read operation with "35h" command and the address of the source page moves the whole 2112byte (X8 device) or
1056word (X16 device) data into the internal data buffer. As soon as the device returns to Ready state, Copy Back
command (85h) with the address cycles of destination page may be written. The Program Confirm command (10h) is
required to actually begin the prog r amming ope r at ion. Data input cy cle for modifying a portion o r mu lt i pl e distant por-
tions of the source page is allowed as shown in Figure 13.
"When there is a program-failure at Copy-Back operation, error is reported by pass/fail status. But, if
Copy-Back operations are accumulated over time, bit e rror due to charge loss is not checked by external
error detection/correction scheme. For this reason, two bit error correction is recommended for the use
of Copy-Back operation."
Figure 15 shows the command sequence for the copy-back operation.
3.5 Read Status Reg is ter.
The device contains a Status R egister which may be r ead to find out whether read, program or er ase oper ation is com -
pleted, and whether the program or er ase oper ation is completed successf ully. After writing 70h command to the com-
mand register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE# or
RE#, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple
memory connections even when RB# pins are common-wired. RE# or CE# does not need to be toggled for updated
status. Refer to table 15 for specific Status Register definitions. The command register remains in Status Read mode
until further commands are issued to it. Therefore, if the status register is read during a random read cycle, the read
command (00h) should be given before starting read cycles. See figure 9 for details of the Read Status operation.
Rev 0.7 / Nov. 2005 14
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
3.6 Read ID.
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an
address input of 00h. F our read cy cles sequentially output the manufactur er code (ADh), and the device code and 00h,
4th cycle ID, respectively. The command register remains in Read ID mode until further commands are issued to it.
Figure 1 8 shows the operation sequence, while tables 15 to 17 explain the byte meaning.
3.7 Reset.
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state
during random rea d, progr am or erase mode, the reset oper ation will abort these oper ations. The contents of memory
cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is
cleared to wait for the next command, and the Status R egister is clear ed to v alue E0h when WP# is high. If the device
is already in reset state a new reset command will not be accepted by the command register. The RB# pin transitions
to low for tRST after the Reset command is written. Refer to figure 24.
3.8 Cache Program.
Cache Program is an extension of Page Program, which is executed with 2112byte (X8 device) or 1056word (X16
device) data registers, and is available only within a block. Since the device has 1 page of cache memory, serial data
input may be executed while data stored in data register are programmed into memory cell. After writing the first set
of data up to 2112byte (X8 device) or 1056word (X16 device) into the selected cache registers, Cache Program com-
mand (15h) instead of actual Page Program (10h) is input to make cache registers free and to start internal program
operation. To transfer data from cache registers to data registers, the device remains in Busy state for a short period
of time (tRBSY) and has its cache registers ready for the next data-input while the internal programming gets started
with the data loaded into data registers. Read Status command (70h) may be issued to find out when cache registers
become ready by polling the Cache-Busy status bit (I/O 6). Pass/fail status of only the previous page is available upon
the return to Ready state. When the next set of data is input with the Cache Program command, tCBSY is affected by
the progress of pending internal programming. The programming of the cache registers is initiated only when the
pending program cy cle is finished and the data registers are av ailable for the tr ansfer of data fr om cache registers. The
status bit (I/O5) for internal Ready/Busy may be polled to identify the completion of internal programming.
If the system monitors the progress of progr amming only with RB#, the last page of the target progr amming sequence
must be programmed with actual Page Program command (10h). If the Cache Program command (15h) is used
instead, status bit (I/O5) must be polled to find out when the last programming is actually finished before starting
other operations such as read. Pass/fail status is available in two steps. I/O 1 returns with the status of the previous
page upon Ready or I/O6 status bit changing to "1", and later I/O 0 with the status of current page upon true Ready
(returning from internal programming) or I/O 5 status bit changing to "1". I/O 1 may be read together when I/O 0 is
checked. See figure 16 for more details.
NOTE : Since pr ogra mming the last page does not employ caching, the pr ogram time has to be that of P age Progr am.
However, if the previous program cycle with the cache data has not finished, the actual program cycle of the
last page is initiated only after completion of the previous cycle, which can be expressed as the following
formula.
tPROG= Program time for the last page+ Program time for the ( last -1 )th page -
(Program command cycle time + Last page data loading time)
Rev 0.7 / Nov. 2005 15
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
3.9 Cache Read
Cache read operation allows automatic download of consecutive pages, up to the whole device. Immediately after 1st
latency end, while user can start reading out data, device internally starts reading following page.
Start address of 1st page is at page start (A<10:0>=00h), after 1st latency time (tr) , automatic data download will
be uninterrupted. In fact latency time is 27us, while download of a page require at least 100us for x8 device (50us for
x16 device).
Cache read operation command is like standard read, except for confirm code (30h for standard read, 31h for cache
read) user can check operation status using :
- RB# ( ‘0’ means latency ongoing, download not possible, ‘1’ means download of n page possible, even if device
internally is active on n+1 page
- Status register (SR<6> behave like RB#, SR<5> is ‘0’ when device is internally reading and ‘1’ when device is idle)
To exit cache read operation a cache read exit command (34h) must be issued. this command can be given any time
(both device idle and reading).
If device is active (SR<5>=0) it will go idle within 5us, while if it is not active, device itself will go busy for a time
shorter then tRBSY before becoming again idle and ready to accept any further commands.
If user arrives reading last byte/word of the memory array, then has to stop by giving a cache read exit command.
Random data output is not available in cache read.
Cache read operation must be done only block by block if system needs to avoid reading also from invalid blocks.
Rev 0.7 / Nov. 2005 16
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
4. OTHER FEATURES
4.1 Data Protection & Power On/Off Sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal
voltage detector disables all functions whenever Vcc is below about 1.1V(1.8V device), 2.0V(3.3V device). WP# pin
provides hardware protection and is recommended to be kept at VIL during power-up and power-down. A recovery
time of minimum 10us is required befor e internal circuit gets ready f or any command sequences as shown in Figure25.
The two-step command sequence for program/erase provides additional software protection.
4.2 Ready/Busy.
The device has a Ready/Busy output that provides method of indicating the completion of a page program, erase,
copy-back, cache program and random read completion. The RB# pin is normally high and goes to low when the
device is busy (after a reset, read, program, erase operation). It returns to high when the internal controller has fin-
ished the operation. The pin is an open-drain driver thereby allowing two or more RB# outputs to be Or-tied. Because
pull-up resistor value is related to tr(RB#) and current dr ain during busy (Ibusy), an appropriate va lue can be obtained
with the following reference chart (Fig 26). Its value can be determined by the following guidance.
4.3 Power-On Auto-Read
The device is designed to off er automatic reading of the first page without command and addres s input sequence dur-
ing power-on.
An interna l voltage detector enables auto-page read functions when Vcc reaches about 1.8V. PRE pin controls activa-
tion of auto- page read function. Auto-page read function is enabled only when PRE pin is logic high state. Serial
access may be done after power-on without latency. Power-On Auto Read mode is available only on 3.3V device.
Rev 0.7 / Nov. 2005 17
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Symbol Parameter Value Unit
1.8V 3.3V
TA
Ambient Operating Temperature (Commercial Temperature Range) 0 to 70 0 to 70 ℃
Ambient Operating Temperature (Extended Temperature Range) -25 to 85 -25 to 85 ℃
Ambient Operating Temperature (Industrial Temperature Range) -40 to 85 -40 to 85 ℃
TBIAS Temperature Under Bias -50 to 125 -50 to 125 ℃
TSTG Storage Temperature -65 to 150 -65 to 150 ℃
VIO(2) Input or Output Voltage -0.6 to 2.7 -0.6 to 4.6 V
Vcc Supply Voltage -0.6 to 2.7 -0.6 to 4.6 V
Table 8: Absolute maximum ratings
NOTE:
1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute
Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of
the device at these or a ny other conditions ab ove those indicated in the Ope rating sectio ns of this specification is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
2. Minimum Voltage may undershoot to -2V during transition and for less than 20ns during transitions.
Parameter Symbol Min Typ Max Unit
Valid Block Number NVB 2008 2048 Blocks
Table 7: Valid Blocks Number
Rev 0.7 / Nov. 2005 18
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
$''5(66
5(*,67(5
&2817(5
352*5$0
(5$6(
&21752//(5
+9*(1(5$7,21
&200$1'
,17(5)$&(
/2*,&
&200$1'
5(*,67(5
'$7$
5(*,67(5
,2
5(
%8))(56
<'(&2'(5
3$*(%8))(5
;
'
(
&
2
'
(
5
0ELW0ELW
1$1')ODVK
0(025<$55$<
:3
&(
:(
&/(
$/(
35(
$a$
Figure 4: Block Diagram
Rev 0.7 / Nov. 2005 19
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Parameter Symbol Test Conditions 1.8Volt 3.3Volt Unit
Min Typ Max Min Typ Max
Operating
Current
Sequential
Read ICC1 tRC(1.8V=60ns,
3.3V=50ns)
CE#=VIL, IOUT=0mA -1020-1530mA
Program ICC2 - - 10 20 - 15 30 mA
Erase ICC3 - - 10 20 - 15 30 mA
Stand-by Current (TTL) ICC4 CE#=VIH,
PRE=WP#=0V/Vcc --1- 1mA
Stand-by Current
(CMOS) ICC5 CE#=Vcc-0.2,
PRE=WP#=0V/Vcc - 20 100 - 20 100 uA
Input Leakage Current ILI VIN=0 to Vcc (max) - - ±20 --
±20 uA
Output Leakage Current ILO VOUT =0 to Vcc (max) - - ±20 --
±20 uA
Input High Voltage VIH - Vcc-0.4 - Vcc+0.
32-
Vcc+0
.3 V
Input Low Voltage VIL --0.3-
0.2xVc
c-0.3 - 0.2xVc
cV
Output High Voltage
Level VOH IOH=-100uA Vcc-0.1 - - - - - V
IOH=-400uA - - - 2.4 - - V
Output Low Voltage
Level VOL IOL=100uA - - 0.1 - - - V
IOL=2.1mA - - - - - 0.4 V
Output Low Current
(RB#) IOL
(RB#) VOL=0.2V 3 4 - - - - mA
VOL=0.4V - - - 8 10 - mA
Table 9: DC and Operating Characteristics
Parameter Value
1.8Volt 3.3Volt
Input Pulse Levels 0V to Vcc 0.4V to 2.4V
Input Rise and Fall Times 5ns 5ns
Input and Output Timing Levels Vcc / 2 1.5V
Output Load (1.7V - 1.95Volt & 2.7V - 3.3V) 1 TTL GATE and CL=30pF 1 TTL GATE and CL=50pF
Output Load (3.0V - 3.6V) 1 TTL GATE and CL=100pF
Table 10: AC Conditions
Rev 0.7 / Nov. 2005 20
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Item Symbol Test Condition Min Max Unit
Input / Output Capacitance CI/O VIL=0V - 20 pF
Input Capacitance CIN VIN=0V - 20 pF
Table 11: Pin Capacitance (TA=25C, F=1.0MHz)
Parameter Symbol Min Typ Max Unit
Program Time tPROG - 300 700 us
Dummy Busy Time for Cache Program tCBSY - 3 700 us
Dummy Busy Time for Cache Read tRBSY -5-us
Dummy Busy Time for the Lock or Lock-tight Block tLBSY -510us
Number of partial Program Cycles in the same page Main Array NOP - - 4 Cycles
Spare Array NOP - - 4 Cycles
Block Erase Time tBERS -23ms
Table 12: Program / Erase Characteristics
Rev 0.7 / Nov. 2005 21
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Parameter Symbol 1.8Volt 3.3Volt Unit
Min Max Min Max
CLE Setup ti m e tCLS 55ns
CLE Hold time tCLH 15 15 ns
CE# setup time tCS 00ns
CE# hold time tCH 10 10 ns
WE# pulse width tWP 40 40 ns
ALE setup time tALS 55ns
ALE hold time tALH 15 15 ns
Data setup time tDS 25 25 ns
Data hold ti m e tDH 15 15 ns
Write Cycle time tWC 60 60 ns
WE# High hold time tWH 20 20 ns
ALE to Data Loading time tADL(2) 100 100 ns
Data Transfer from Cell to register tR27 27 us
ALE to RE# Delay tAR 10 10 ns
CLE to RE# Delay tCLR 10 10 ns
Ready to RE# Low tRR 20 20 ns
RE# Pulse Width (ID Re ad) tRP 25 25 ns
RE# Pulse Width (Data Read) tRP 25 25 ns
WE# High to Busy tWB 100 100 ns
Read Cycle Time (ID Read) tRC 60 60 ns
Read Cycle Time (Data Read) tRC 50 50 ns
RE# Access Time tREA 30 30 ns
RE# High to Output High Z tRHZ 30 30 ns
CE# High to Output High Z tCHZ 20 20 ns
RE or CE High to Outp ut hold tOH 15 1 5 ns
RE# High Hold Time (ID Read) tREH 30 30 ns
RE# High Hold Time (Data Read) tREH 20 20 ns
Output High Z to RE# low tIR 00ns
CE# Access Time tCEA 45 45 ns
WE# High to RE# low tWHR 60 60 ns
Device Resetting Time (Read / Program / Erase) tRST 5/10/500(1) 5/10/500(1) us
Write Protection time tWW(3) 100 100 ns
Table 13: AC Timing Characteristics
NOTE:
1. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us
2. tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle
3. Program / Erase Enable Operation : tWP# high to tWE# High.
Program / Erase Disable Operation : tWP# Low to tWE# High.
Rev 0.7 / Nov. 2005 22
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
IO Pagae
Program Block
Erase Cache
Program Read Cache
Read CODING
0 Pass / Fail Pass / Fail Pass / Fa il (N) NA Pass: ‘0’ Fail: ‘1’
1NA NAPass / Fail (N-1)NA Pass: ‘0’ Fail: ‘1’
(Only for Cache Program,
else Don’t care)
2NA NA NA NA -
3NA NA NA NA -
4NA NA NA NA -
5 Ready/Busy Ready/Busy P/E/R
Controller Bit Ready/Busy P/E/R
Controller Bit Active: ‘0’ Idle: ‘1’
6 Ready/Busy Ready/Busy Cac he Register
Free Ready/Busy Ready/Busy Busy: ‘0’ Ready’: ‘1’
7 Write Protect Write Protect Write Protect Write Protect Protected: ‘0’ Not
Protected: ‘1’
Table 14: Status Register Coding
DEVICE IDENTIFIER BYTE DESCRIPTION
1st Manufacturer Code
2nd Device Identifier
3rd Don't care
4th Page Size, Block Size, Spare Size, Organizati on
Table 15: Device Identifier Coding
Part Number Voltage Bus Width Manufacture Code Device Code 3rd Code 4th Code
HY27UH084G2M 3.3V x8 ADh DAh don’t care 15h
HY27SH084G2M 3.3Vx16 ADh CAh don’t care 55h
HY27UH164G2M 1.8V x8 ADh AAh don’t care 15h
HY27SH164G2M 1.8V x16 ADh BAh don’t care 55h
Table 16: Read ID Data Table
Rev 0.7 / Nov. 2005 23
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Description IO7 IO6 IO5-4 IO3 IO2 IO1-0
Page Si ze
(Without Spare Area)
1K
2K
Reserved
Reserved
0 0
0 1
1 0
1 1
Spare Area Size
(Byte / 512Byte) 8
16 0
1
Serial Access Time Standard (50ns)
Fast (30ns) 0
1
Block Size
(Without Spare Area)
64K
128K
256K
Reserved
0 0
0 1
1 0
1 1
Organization X8
X16 0
1
Not Used Reserved
Table 17: 4th Byte of Device Identifier Description
Rev 0.7 / Nov. 2005 24
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Figure 5: Command Latch Cycle
W&/
6
W&6
W:3
&RPPDQG
&/(
&(
:(
$/(
,2[
W'+W'6
W$/6 W$/+
W&/+
W&+
W&/6
W&6
W:3
W:& W:& W:&
W:3 W:3 W:3
W$/6
W:+W:+W:+W:+
W$/+ W$/6W$/6W$/6W$/6
&RO$GG
W$/+ W$/+ W$/+ W$/+
W'+
&RO$GG 5RZ$GG 5RZ$GG 5RZ$GG
W:&
W'+ W'+ W'+ W'+
W'6 W'6 W'6 W'6
W'6
&/(
&(
:(
$/(
,2[
Figure 6: Address Latch Cycle
Rev 0.7 / Nov. 2005 25
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
W
&($
W
5($
W
53
W
5($
W
5+=
W
5+=
'RXW 'RXW 'RXW
W
&+=
W
2+
W
2+
W
5($
W
5(+
W
5&
W
55
127(67UDQVLWLRQLVPHDVXUHGP9IURPVWHDG\VWDWHYROWDJHZLWKORDG
7KLVSDUDPHWHULVVDPSOHGDQGQRWWHVWHG
&(
5(
5%
,2[
W:&W$/6
W&/+
W&+
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W:+
',1 ',1 ',1ILQDO
W:+
W'+ W'+ W'+
W'6 W'6 W'6
W:3 W:3
&/(
$/(
&(
,2[
:(
Figure 8: Sequential Out Cycle after Read (CLE=L, WE#=H, ALE=L)
Figure 7. Input Data Latch Cycle
Rev 0.7 / Nov. 2005 26
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Figure 9: Status Read Cycle
W&/6
W&/5
W&/+
W&6
W&+
W:3
W:+5
W&($
W'6 W5($
W&+=
W5+=
K 6WDWXV2XWSXW
W'+ W,5
&(
:(
,2
[
&/(
5(
&/(
$/(
&(
,2[
:(
5(
5%
W
:&
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&/5
W
55
K K&RO$GG
&ROXPQ$GGUHVV 5RZ$GGUHVV
&RO$GG 5RZ$GG 5RZ$GG
%XV\
'RXW1 'RXW1 'RXW0
W
:%
W
$5
W
5
W
5&
W
5+=
5RZ$GG
Figure 10: Read1 Operation (Read One Page)
Rev 0.7 / Nov. 2005 27
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
W:%
W$5
W&+=
W2+
W5&
W5
W55
%XV\
K K 'RXW
1'RXW
1 'RXW
1
&RO
$GG &RO
$GG 5RZ
$GG 5RZ
$GG 5RZ
$GG
&ROXPQ$GGUHVV 5RZ$GGUHVV
&(
:(
$/(
5(
,2[
5%
Figure 11: Read1 Operation inter cepted by CE#
Rev 0.7 / Nov. 2005 28
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
&/(
$/(
&(
5(
5%
,2[
:(
W&/5
K
&ROXPQ$GGUHVV 5RZ$GGUHVV
%XV\
K K (K
'RXW1 'RXW0
'RXW1 'RXW0
&RO$GG 5RZ$GG 5RZ$GG 5RZ$GG
&RO$GG
&ROXPQ$GGUHVV
&RO$GG &RO$GG
W5 W5&
W:%
W$5
W55
W:+5
W5($
Figure 12 : Random Data output
Rev 0.7 / Nov. 2005 29
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Figure 13: Page Program Operation
&/(
$/(
&(
5(
5%
,2[
:(
W:&
K &RO
$GG
6HULDO'DWD
,QSXW&RPPDQG &ROXPQ$GGUHVV 5RZ$GGUHVV 5HDG6WDWXV
&RPPDQG
3URJUDP
&RPPDQG
,2R 6XFFHVVIXO3URJUDP
,2R (UURULQ3URJUDP
;GHYLFHP E\WH
;GHYLFHP ZRUG
XSWRP%\WH
6HULDO,QSXW
&RO
$GG 5RZ
$GG 5RZ
$GG 5RZ
$GG 'LQ
1'LQ
0K K ,2R
W:&
W:% W352*
W:&
W$'/
Rev 0.7 / Nov. 2005 30
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
&/(
$/(
&(
5(
5%
,2[
:(
W:&
K 'LQ
1'LQ
0'LQ
-'LQ
.
K K K
,2
&RO$GG &RO$GG &RO$GG &RO$GG5ZR$GG 5ZR$GG 5ZR$GG
W:&
W$'/ W$'/
W:%
W352*
6HULDO'DWD
,QSXW&RPPDQG 5DQGRP'DWD
,QSXW&RPPDQG
&ROXPQ$GGUHVV &ROXPQ$GGUHVV5RZ$GGUHVV 6HULDO,QSXW 6HULDO,QSXW 3URJUDP
&RPPDQG
5HDG6WDWXV
&RPPDQG
W:&
Figure 14 : Random Data In
Rev 0.7 / Nov. 2005 31
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
&/(
$/(
&(
5(
5%
1RWHVW$'/LVWKHWLPHIURPWKH:(ULVLQJHGJHRIILQDODGGUHVVF\FOHWRWKH:(ULVLQJHGJHRIILUVWGDWDF\FOH
,2[
:(
W:%
W:%
W352*
W5
K
&ROXPQ$GGUHVV 5RZ$GGUHVV &ROXPQ$GGUHVV
%XV\ %XV\
&RS\%DFN'DWD
,QSXW&RPPDQG ,2 6XFFHVVIXO3URJUDP
,2 (UURULQ3URJUDP
5RZ$GGUHVV
K K K
K
,2
'DWD1'DWD
&RO
$GG
&RO
$GG
5RZ
$GG
5RZ
$GG
5RZ
$GG &RO
$GG
&RO
$GG
5RZ
$GG
5RZ
$GG
5RZ
$GG
W:&
W$'/
5HDG6WDWXV
&RPPDQG
Figure 15 : Copy Back Program
Rev 0.7 / Nov. 2005 32
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
&/(
$/(
&(
5(
5%
,2[
:(
5%
,2[
([&DFKH3URJUDP
W:&
K
K K ,2
3URJUDP&RQILUP
&RPPDQG7UXH
/DVW3DJH,QSXW3URJUDP
0D[WLPHVUHSHDWDEOH
W&%6<PD[XV
W&%6<
&RO$GG5RZ$GG'DWD
W&%6< W&%6< W352*
6HULDO'DWD
,QSXW&RPPDQG &ROXPQ
$GGUHVV 5RZ
$GGUHVV 6HULDO,QSXW 3URJUDP
&RPPDQG
'XPP\
K K
$GGUHVV
'DWD,QSXW $GGUHVV
'DWD,QSXW $GGUHVV
'DWD,QSXW $GGUHVV
'DWD,QSXW
K K K KK K K
K K
'LQ
1'LQ
0'LQ
1'LQ
0
&RO
$GG 5RZ
$GG 5RZ
$GG 5RZ
$GG
&RO
$GG
W:% W352*
W:% W&%6<
&RO
$GG 5RZ
$GG 5RZ
$GG 5RZ
$GG
&RO
$GG
Figure 16 : Cache Program
Rev 0.7 / Nov. 2005 33
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
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Figure 17: Block Erase Operation (Erase One Block)
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Figure 18: Read ID Operation
Rev 0.7 / Nov. 2005 34
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
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Figure 20: exit from cache read in 5us when device internally is reading
Rev 0.7 / Nov. 2005 35
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
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Figure 21:start address at page start :after 1st latency uninterrupted data flow
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System Interface Using CE don’t care
To simplify system int erface, CE may be deasserted during data loading or sequential data-reading as shown below. So, it is possible
to connect NAND Flash to a microprocessor. The only function that was removed from standard NAND Flash to make CE don't care
read operation was disabling of the automatic sequential read function.
Rev 0.7 / Nov. 2005 36
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
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Figure 23: Automatic Read at Power On
Rev 0.7 / Nov. 2005 37
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
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Figure 25: Power On/Off Timing
* See the application Note 1.
Rev 0.7 / Nov. 2005 38
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
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Figure 26: Ready/Busy Pin electrical specifications
Rev 0.7 / Nov. 2005 39
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Figure 27: page programming within a block
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Rev 0.7 / Nov. 2005 40
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Bad Block Management
Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the
blocks are v alid. A Bad Block does not aff ect the performance of v alid blocks because it is isolated from the bit line and
common source line by a select transistor. The devices are supplied with all the locations inside valid blocks
erased(FFh). The Bad Block Inf ormation is written prior to shipping. Any block where the 1st Byte in the sp are a rea of
the 1st or 2nd page(if the 1st page is Bad) does not contain FFh is a Bad Block. The Bad Block Information must be
read before any erase is attempted as the Bad Block Information may be erased. For the system to be able to recog-
nize the Bad Blocks based on the original information it is recommended to create a Bad Block table following the flow-
chart shown in Figure 28. The 1st block, which is placed on 00h block address is guaranteed to be a valid block.
Bad Replacement
Over the lifetime of the device additional Bad Blocks may dev elop. In this case the b lock has to be replaced by copying
the data to a valid block. These additional Bad Blocks can be identified as attempts to progr am or er ase them will give
errors in the Status Register.
As the failure of a page program operation does not affect the data in other pages in the same block, the block can be
replaced by re-programming the current data and copying the rest of the replaced block to an available valid block.
The Copy Back Program command can be used to copy the data to a valid block.
See the “Copy Back Program” section for more details.
Refer to Table 18 for the recommended procedure to follow if an error occurs during an operation.
Operation Recommended Procedure
Erase Block Replacement
Program Block R e placement or ECC
Read ECC
Table 18: Block Failure
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Figure 28: Bad Block Management Flowchart
Rev 0.7 / Nov. 2005 41
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Write Protect Operation
The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations
are enabled and disabled as follows (Figure 29~32)
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Figure 29: Enable Programming
Figure 30: Disable Programming
Rev 0.7 / Nov. 2005 42
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
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Figure 31: Enable Erasing
Figure 32: Disable Erasing
Rev 0.7 / Nov. 2005 43
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
5. APPENDIX : Extra Features
5.1 Automatic Page0 Read after Power Up
The timing diagram related to this operation is shown in Fig. 23
Due to this functionality the CPU can directly download the boot loader from the first page of the NAND flash, storing
it inside the internal cache and starting the execution after the download completed.
5.2 Stacked Devices Access
A small logic insi de the device s allow s the pos sibilit y to stac k up to 2 devices in a single package without changing the
pinout of the memory. To do this the internal address register can store up to 29 addresses (512 Mbyte addressing
field) and basing on the 2 MSB p attern ea ch device inside the package can decide if remain active (1 over 4) or “hang-
up” the connection entering the Stand-By.
5.3 Addressing for program operation
Within a block, the pages must be progr ammed consecutively from LSB (le ast significant bit) page of the block to MSB
(most significant bit) page of the block. Random address programming is prohibited. See Fig. 27.
5.4 Multiple Die Concurrent Operations and Extended Read Status
When the 1Gbit is stacked to form a 2Gbit DDP some concurrent oper atio ns (lik e Er as e while Read, Read while write,
etc. ) are a vailable. Moreo ver an extended R ead Status R egister F eature is included to check the status of each stacked
device. In more details it is possible to run a first operation selecting the first 1Gbit, then activate a concurrent opera-
tion on the second (or third or fourth) device, checking the p rogression of these oper ations by the use of the extended
Read Status Re gister feature.
The command sequence to be used is shown in Table 19. The result is the typical Read Status Pattern.
FUNCTION COMMAND
Read Status 1st device (AX<= 0x07FFFFFF) 72h
Read Status 2nd device (0x07FFFFFF <AX<= 0x0FFFFFFF) 73h
Read Status 3rd device (0x0FFFFFFF <AX<= 0x17FFFFFF) 74h
Read Status 4th device (0x17FFFFFF <AX<= 0x1FFFFFFF) 75h
Table 19: Extended Read Status Register Commands
Rev 0.7 / Nov. 2005 44
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Table 20: 48-pin TSOP1, 12 x 20mm, Package Mechanical Data
Symbol millimeters
Min Typ Max
A1.200
A1 0.050 0.150
A2 0.980 1.030
B 0.170 0.250
C 0.100 0.200
CP 0.100
D 11.910 12.000 12.120
E 19.900 20.000 20.100
E1 18.300 18.400 18.500
e 0.500
L 0.500 0.680
alpha 0 5
Figure 33. 48-pin TSOP1, 12 x 20mm, Package Outline
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Rev 0.7 / Nov. 2005 45
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Symbol millimeters
Min Typ Max
A0.650
A1 0 0.050 0.080
A2 0.470 0.520 0.570
B 0.130 0.160 0.230
C 0.065 0.100 0.175
C10.450 0.650 0.750
CP 0.100
D 16.900 17.000 17.100
D1 11.910 12.000 12.120
E 15.300 15.400 15.500
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Table 20: 48pin-USOP1, 12 x 17mm, Package Mechanical Data
Figure 34. 48pin-USOP1, 12 x 17mm, Package Outline
Rev 0.7 / Nov. 2005 46
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
MARKING INFORMATION- TSOP1 / USOP
Packag M arking Exam ple
TSOP1
/
USOP
K O R
H Y 2 7 x G x x 2 G 2 M
x x x x Y W W x x
- hynix
- K O R
- H Y27xGxx2G2M xxxx
HY : HYNIX
2 7 : NAND Flash
x : Pow er Supply
G: Classification
x x : B it O r ga n iza tion
2G: Density
2: Mode
M: Version
x : Package Type
x : Package M aterial
x : Operating Tem perature
x : Bad Block
- Y : Year (ex: 5= year 2005, 06= year 2006)
- w w: Work Week (ex: 12= work week 12)
- xx : Process C ode
Note
- C ap ita l Lette r
- S m a ll Le tter
: H ynix S ymb ol
: Or ig in C o u n try
: U(2.7V ~3.6V), L(2.7V), S(1.8V)
: S in g le L e v e l C e ll+Do uble Die +L a r g e B lo c k
: 08(x8), 16(x16)
: 2G b it
: 1n CE & 1R/nB; S equential Row Read D isable
: 1 st G e ne ration
: T(48-TSOP1), S(48-U SOP)
: B lan k(N orm al), P(Lead Free )
: C (0℃~70℃), E(-2 5℃~85℃)
M(-30℃~85℃), I(-40 ℃~85℃)
: B(Included Bad Block), S(1~ 5 Bad Block),
P(All G ood Block)
: Fixed Item
: N on -fixed Ite m
: Pa rt N u m b e r
Rev 0.7 / Nov. 2005 47
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Application Note
1. Power-on/off Sequence
After power is on, the device starts an internal ci rcuit initialization when the power supply voltage reaches a specific
level. The device shows its internal initialization status with the Ready/Busy signal if initializati on i s on pro gr ess. Whil e
the device is initializing, the device sets internal registeries to default value and generates internal biases to operate
circuits. Typical ly the initializing time of 20us is required.
Power-off or power fail ure before write/erase operation is complete will cause a loss of data. The WP# signal helps
user to protect not only the data integrity but also device circuitry from being damaged at power-on/off by keeping
WP# at VIL during power-on/off.
For the device to operate stably, it is highly recommended to operate the device as shown Fig.35.
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Figure 35: Power-on/off sequence
Rev 0.7 / Nov. 2005 48
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
2. Automatic sleep mode for low power consumption
The device provides the automatic sleep function for low power consu mption.
The device enters the automatic sleep mode by keeping CE# at VIH level for 10us without any additional command
input, and exits simply by lowering CE# to VIL level.
Typically, consecutive operation is executable right after deactiv ating the automatic sleep mode, while tCS of 100ns is
required prior to following operation as shown in Fig.36.
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Figure 36: tCS setting when deactivating the auto sleep mode
