S-5725 Series www.ablic.com www.ablicinc.com HIGH-SPEED BIPOLAR HALL EFFECT LATCH Rev.2.5_02 (c) ABLIC Inc., 2011-2015 The S-5725 Series, developed by CMOS technology, is a high-accuracy Hall IC that operates with a high-sensitivity, a highspeed detection and low current consumption. The output voltage changes when the S-5725 Series detects the intensity level of magnetic flux density and a polarity change. Using the S-5725 Series with a magnet makes it possible to detect the rotation status in various devices. High-density mounting is possible by using the small SOT-23-3 or the super-small SNT-4A packages. Due to its high-accuracy magnetic characteristics, the S-5725 Series can make operation's dispersion in the system combined with magnet smaller. Caution This product is intended to use in general electronic devices such as consumer electronics, office equipment, and communications devices. Before using the product in medical equipment or automobile equipment including car audio, keyless entry and engine control unit, contact to ABLIC Inc. is indispensable. Features Pole detection: Detection logic for magnetism*1: *1 Output form : Magnetic sensitivity*1: *1 Operating cycle (current consumption) : Power supply voltage range: Operation temperature range: Built-in power-down circuit: Lead-free (Sn 100%), halogen-free Bipolar latch VOUT = "L" at S pole detection VOUT = "H" at S pole detection Nch open-drain output, CMOS output BOP = 0.8 mT typ. BOP = 1.8 mT typ. BOP = 3.0 mT typ. BOP = 7.0 mT typ. tCYCLE = 50 s (IDD = 1400.0 A) typ. tCYCLE = 1.25 ms (IDD = 60.0 A) typ. tCYCLE = 6.05 ms (IDD = 13.0 A) typ. VDD = 2.7 V to 5.5 V Ta = 40C to 85C Extends battery life (only SNT-4A) *1. The option can be selected. Applications Plaything, portable game Home appliance Housing equipment Industrial equipment Packages SOT-23-3 SNT-4A 1 HIGH-SPEED BIPOLAR HALL EFFECT LATCH S-5725 Series Rev.2.5_02 Block Diagrams 1. Nch open-drain output product 1. 1 Product without power-down function VDD OUT Sleep / Awake logic *1 *1 Chopping stabilized amplifier VSS *1. Parasitic diode Figure 1 1. 2 Product with power-down function (SNT-4A) VDD *1 Power-down circuit Sleep / Awake logic OUT CE *1 *1 *1 Chopping stabilized amplifier VSS *1. Parasitic diode Figure 2 2 HIGH-SPEED BIPOLAR HALL EFFECT LATCH S-5725 Series Rev.2.5_02 2. CMOS output product 2. 1 Product without power-down function VDD Sleep / Awake logic *1 *1 OUT Chopping stabilized amplifier *1 VSS *1. Parasitic diode Figure 3 2. 2 Product with power-down function (SNT-4A) VDD *1 Power-down circuit Sleep / Awake logic *1 CE OUT *1 *1 *1 Chopping stabilized amplifier VSS *1. Parasitic diode Figure 4 3 HIGH-SPEED BIPOLAR HALL EFFECT LATCH S-5725 Series Rev.2.5_02 Product Name Structure 1. Product name S-5725 x x B x x - xxxx U Environmental code U: Lead-free (Sn 100%), halogen-free Package name (abbreviation) and packing specifications*1 M3T1: SOT-23-3, Tape I4T1: SNT-4A, Tape Magnetic sensitivity 9: BOP = 0.8 mT typ. 0: BOP = 1.8 mT typ. 1: BOP = 3.0 mT typ. 3: BOP = 7.0 mT typ. Detection logic for magnetism L: VOUT = "L" at S pole detection H: VOUT = "H" at S pole detection Pole detection B: Bipolar latch Output form N: Nch open-drain output C: CMOS output Operating cycle C: tCYCLE = 6.05 ms typ. D: tCYCLE = 1.25 ms typ. E: tCYCLE = 50 s typ. H: tCYCLE = 6.05 ms typ. I: tCYCLE = 1.25 ms typ. J: tCYCLE = 50 s typ. (Without power-down function) (Without power-down function) (Without power-down function) (With power-down function, SNT-4A) (With power-down function, SNT-4A) (With power-down function, SNT-4A) *1. Refer to the tape drawing. 2. Packages Table 1 Package Name SOT-23-3 SNT-4A 4 Package Drawing Codes Dimension Tape Reel Land MP003-C-P-SD PF004-A-P-SD MP003-C-C-SD PF004-A-C-SD MP003-Z-R-SD PF004-A-R-SD PF004-A-L-SD HIGH-SPEED BIPOLAR HALL EFFECT LATCH S-5725 Series Rev.2.5_02 3. Product name list 3. 1 SOT-23-3 3. 1. 1 Nch open-drain output product Table 2 Product Name Operating Cycle (tCYCLE) Power-down Function Output Form Nch open-drain output Nch open-drain 6.05 ms typ. Unavailable S-5725CNBL0-M3T1U output Nch open-drain S-5725CNBL1-M3T1U 6.05 ms typ. Unavailable output Nch open-drain S-5725DNBL1-M3T1U 1.25 ms typ. Unavailable output Nch open-drain S-5725ENBL9-M3T1U Unavailable 50 s typ. output Nch open-drain S-5725ENBL0-M3T1U Unavailable 50 s typ. output Nch open-drain S-5725ENBL1-M3T1U Unavailable 50 s typ. output Nch open-drain S-5725ENBH1-M3T1U Unavailable 50 s typ. output Remark Please contact our sales office for products other than the above. S-5725CNBL9-M3T1U 3. 1. 2 6.05 ms typ. Unavailable Pole Detection Bipolar latch Bipolar latch Bipolar latch Bipolar latch Bipolar latch Bipolar latch Bipolar latch Bipolar latch Detection Logic for Magnetism VOUT = "L" at S pole detection VOUT = "L" at S pole detection VOUT = "L" at S pole detection VOUT = "L" at S pole detection VOUT = "L" at S pole detection VOUT = "L" at S pole detection VOUT = "L" at S pole detection VOUT = "H" at S pole detection Magnetic Sensitivity (BOP) 0.8 mT typ. 1.8 mT typ. 3.0 mT typ. 3.0 mT typ. 0.8 mT typ. 1.8 mT typ. 3.0 mT typ. 3.0 mT typ. CMOS output product Table 3 Product Name Operating Cycle (tCYCLE) S-5725CCBL9-M3T1U 6.05 ms typ. Unavailable CMOS output S-5725CCBL0-M3T1U 6.05 ms typ. Unavailable CMOS output S-5725CCBL1-M3T1U 6.05 ms typ. Unavailable CMOS output S-5725DCBL1-M3T1U 1.25 ms typ. Unavailable CMOS output S-5725ECBL9-M3T1U 50 s typ. Unavailable CMOS output S-5725ECBL0-M3T1U 50 s typ. Unavailable CMOS output S-5725ECBL1-M3T1U 50 s typ. Unavailable CMOS output S-5725ECBH0-M3T1U 50 s typ. Unavailable CMOS output S-5725ECBH1-M3T1U 50 s typ. Unavailable CMOS output Power-down Function Output Form Pole Detection Bipolar latch Bipolar latch Bipolar latch Bipolar latch Bipolar latch Bipolar latch Bipolar latch Bipolar latch Bipolar latch Detection Logic for Magnetism VOUT = "L" at S detection VOUT = "L" at S detection VOUT = "L" at S detection VOUT = "L" at S detection VOUT = "L" at S detection VOUT = "L" at S detection VOUT = "L" at S detection VOUT = "H" at S detection VOUT = "H" at S detection pole pole pole pole pole pole pole pole pole Magnetic Sensitivity (BOP) 0.8 mT typ. 1.8 mT typ. 3.0 mT typ. 3.0 mT typ. 0.8 mT typ. 1.8 mT typ. 3.0 mT typ. 1.8 mT typ. 3.0 mT typ. Remark Please contact our sales office for products other than the above. 5 HIGH-SPEED BIPOLAR HALL EFFECT LATCH S-5725 Series 3. 2 Rev.2.5_02 SNT-4A 3. 2. 1 Nch open-drain output product Table 4 Product Name Operating Cycle (tCYCLE) Power-down Function Output Form Nch open-drain output Nch open-drain S-5725HNBH0-I4T1U 6.05 ms typ. Available output Nch open-drain S-5725INBH0-I4T1U 1.25 ms typ. Available output Nch open-drain S-5725JNBH0-I4T1U Available 50 s typ. output Remark Please contact our sales office for products other than the above. S-5725ENBH3-I4T1U 3. 2. 2 50 s typ. Unavailable Pole Detection Bipolar latch Bipolar latch Bipolar latch Bipolar latch Detection Logic for Magnetism VOUT = "H" detection VOUT = "H" detection VOUT = "H" detection VOUT = "H" detection at S pole at S pole at S pole at S pole Magnetic Sensitivity (BOP) 7.0 mT typ. 1.8 mT typ. 1.8 mT typ. 1.8 mT typ. CMOS output product Table 5 Product Name Operating Cycle (tCYCLE) Power-down Function Output Form S-5725ECBL9-I4T1U 50 s typ. Unavailable CMOS output S-5725ECBL0-I4T1U 50 s typ. Unavailable CMOS output S-5725ECBH0-I4T1U 50 s typ. Unavailable CMOS output S-5725HCBH0-I4T1U 6.05 ms typ. Available CMOS output S-5725HCBH1-I4T1U 6.05 ms typ. Available CMOS output S-5725ICBH0-I4T1U 1.25 ms typ. Available CMOS output S-5725ICBH1-I4T1U 1.25 ms typ. Available CMOS output S-5725JCBH0-I4T1U 50 s typ. Available CMOS output S-5725JCBH1-I4T1U 50 s typ. Available CMOS output Remark Please contact our sales office for products other than the above. 6 Pole Detection Bipolar latch Bipolar latch Bipolar latch Bipolar latch Bipolar latch Bipolar latch Bipolar latch Bipolar latch Bipolar latch Detection Logic for Magnetism VOUT = "L" at S detection VOUT = "L" at S detection VOUT = "H" at S detection VOUT = "H" at S detection VOUT = "H" at S detection VOUT = "H" at S detection VOUT = "H" at S detection VOUT = "H" at S detection VOUT = "H" at S detection pole pole pole pole pole pole pole pole pole Magnetic Sensitivity (BOP) 0.8 mT typ. 1.8 mT typ. 1.8 mT typ. 1.8 mT typ. 3.0 mT typ. 1.8 mT typ. 3.0 mT typ. 1.8 mT typ. 3.0 mT typ. HIGH-SPEED BIPOLAR HALL EFFECT LATCH S-5725 Series Rev.2.5_02 Pin Configurations 1. SOT-23-3 Top view 1 2 Table 6 Pin No. 3 Symbol Pin Description 1 VSS GND pin 2 VDD Power supply pin 3 OUT Output pin Figure 5 2. SNT-4A Table 7 Top view 1 2 4 3 Figure 6 Pin No. Symbol Description 1 VDD Power supply pin 2 VSS 3 CE 4 OUT GND pin Enabling pin "H": Enables operation "L": Power-down Output pin 7 HIGH-SPEED BIPOLAR HALL EFFECT LATCH S-5725 Series Rev.2.5_02 Absolute Maximum Ratings Table 8 Item Symbol (Ta = 25C unless otherwise specified) Absolute Maximum Rating Unit Power supply voltage VDD VSS 0.3 to VSS 7.0 Input voltage VCE VSS 0.3 to VDD 0.3 V Output current IOUT 2.0 mA Output voltage Power dissipation Nch open-drain output product CMOS output product SOT-23-3 SNT-4A VOUT PD V VSS 0.3 to VSS 7.0 V VSS 0.3 to VDD 0.3 430*1 300*1 V mW mW Operation ambient temperature Topr 40 to 85 C Storage temperature Tstg 40 to 125 C *1. When mounted on board [Mounted board] (1) Board size: (2) Name: 114.3 mm 76.2 mm t1.6 mm JEDEC STANDARD51-7 Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Power Dissipation (PD) [mW] 600 SNT-4A 200 0 Figure 7 8 SOT-23-3 400 0 150 100 50 Ambient Temperature (Ta) [C] Power Dissipation of Package (When Mounted on Board) HIGH-SPEED BIPOLAR HALL EFFECT LATCH S-5725 Series Rev.2.5_02 Electrical Characteristics 1. Product without power-down function 1. 1 S-5725CxBxx Table 9 Item Power supply voltage Current consumption (Ta = 25C, VDD = 5.0 V, VSS = 0 V unless otherwise specified) Test Condition Min. Typ. Max. Unit Circuit Symbol VDD IDD Average value Nch open-drain output product Output voltage VOUT Output transistor Nch, IOUT = 2 mA Output transistor Nch, IOUT = 2 mA CMOS output product Output transistor Pch, IOUT = 2 mA Nch open-drain output product Output transistor Nch, VOUT = 5.5 V 2.7 5.0 13.0 5.5 20.0 V A 1 0.4 V 2 0.4 V 2 VDD 0.4 V 3 1 A 4 Leakage current ILEAK Awake mode time tAW 0.05 ms Sleep mode time tSL 6.00 ms Operating cycle tCYCLE 6.05 12.00 ms 1. 2 tAW tSL S-5725DxBxx Table 10 Item Power supply voltage Current consumption Output voltage (Ta = 25C, VDD = 5.0 V, VSS = 0 V unless otherwise specified) Test Condition Min. Typ. Max. Unit Circuit Symbol VDD IDD VOUT Average value Nch open-drain output product Output transistor Nch, IOUT = 2 mA Output transistor Nch, IOUT = 2 mA CMOS output product Output transistor Pch, IOUT = 2 mA Nch open-drain output product Output transistor Nch, VOUT = 5.5 V 2.7 5.0 60.0 5.5 90.0 V A 1 0.4 V 2 0.4 V 2 VDD 0.4 V 3 1 A 4 Leakage current ILEAK Awake mode time tAW 0.05 ms Sleep mode time tSL 1.20 ms Operating cycle tCYCLE 1.25 2.50 ms tAW tSL 9 HIGH-SPEED BIPOLAR HALL EFFECT LATCH S-5725 Series 1. 3 Rev.2.5_02 S-5725ExBxx Table 11 Item Power supply voltage Current consumption Output voltage (Ta = 25C, VDD = 5.0 V, VSS = 0 V unless otherwise specified) Test Condition Min. Typ. Max. Unit Circuit Symbol VDD IDD VOUT Average value Nch open-drain output product Output transistor Nch, IOUT = 2 mA Output transistor Nch, IOUT = 2 mA CMOS output product Output transistor Pch, IOUT = 2 mA Nch open-drain output product Output transistor Nch, VOUT = 5.5 V 2.7 5.0 5.5 1400.0 2000.0 V A 1 0.4 V 2 0.4 V 2 VDD 0.4 V 3 1 A 4 Leakage current ILEAK Awake mode time tAW 50 s Sleep mode time tSL 0 s Operating cycle tCYCLE 50 100 s 10 tAW tSL HIGH-SPEED BIPOLAR HALL EFFECT LATCH S-5725 Series Rev.2.5_02 2. Product with power-down function (SNT-4A) 2. 1 S-5725HxBxx Table 12 Item Power supply voltage Current consumption Current consumption during power-down Output voltage (Ta = 25C, VDD = 5.0 V, VSS = 0 V unless otherwise specified) Test Condition Min. Typ. Max. Unit Circuit Symbol 2.7 5.0 13.0 5.5 20.0 V A 1 VCE = VSS 1 A 6 Nch open-drain output product 0.4 V 2 0.4 V 2 VDD 0.4 V 3 1 A 4 VDD IDD Average value IDD2 VOUT Output transistor Nch, IOUT = 2 mA Output transistor Nch, IOUT = 2 mA CMOS output product Output transistor Pch, IOUT = 2 mA Nch open-drain output product Output transistor Nch, VOUT = 5.5 V Leakage current ILEAK Awake mode time tAW 0.05 ms Sleep mode time tSL 6.00 ms Operating cycle tCYCLE 6.05 12.00 ms Enabling pin input voltage "L" VCEL VDD 0.3 V Enabling pin input voltage "H" VCEH VDD 0.7 V Enabling pin input current "L" ICEL VDD = 5.0 V, VCE = 0 V 1 1 A 7 Enabling pin input current "H" ICEH VDD = 5.0 V, VCE = 5.0 V 1 1 A 8 Power-down transition time tOFF 100 s Enable transition time tON 100 s Output logic update time after inputting "H" to enabling pin tOE 200 s tAW tSL 11 HIGH-SPEED BIPOLAR HALL EFFECT LATCH S-5725 Series 2. 2 Rev.2.5_02 S-5725IxBxx Table 13 Item Power supply voltage Current consumption Current consumption during power-down Output voltage (Ta = 25C, VDD = 5.0 V, VSS = 0 V unless otherwise specified) Test Condition Min. Typ. Max. Unit Circuit Symbol 2.7 5.0 60.0 5.5 90.0 V A 1 VCE = VSS 1 A 6 Nch open-drain output product 0.4 V 2 0.4 V 2 VDD 0.4 V 3 1 A 4 VDD IDD Average value IDD2 VOUT Output transistor Nch, IOUT = 2 mA Output transistor Nch, IOUT = 2 mA CMOS output product Output transistor Pch, IOUT = 2 mA Nch open-drain output product Output transistor Nch, VOUT = 5.5 V Leakage current ILEAK Awake mode time tAW 0.05 ms Sleep mode time tSL 1.20 ms Operating cycle tCYCLE 1.25 2.50 ms tAW tSL Enabling pin input voltage "L" VCEL VDD 0.3 V Enabling pin input voltage "H" VCEH VDD 0.7 V Enabling pin input current "L" ICEL VDD = 5.0 V, VCE = 0 V 1 1 A 7 Enabling pin input current "H" ICEH VDD = 5.0 V, VCE = 5.0 V 1 1 A 8 Power-down transition time tOFF 100 s Enable transition time tON 100 s Output logic update time after tOE inputting "H" to enabling pin 200 s 12 HIGH-SPEED BIPOLAR HALL EFFECT LATCH S-5725 Series Rev.2.5_02 2. 3 S-5725JxBxx Table 14 Item Power supply voltage Current consumption Current consumption during power-down Output voltage (Ta = 25C, VDD = 5.0 V, VSS = 0 V unless otherwise specified) Test Condition Min. Typ. Max. Unit Circuit Symbol V A 1 1 A 6 0.4 V 2 0.4 V 2 VDD 0.4 V 3 1 A 4 VDD IDD Average value IDD2 VCE = VSS Nch open-drain output product VOUT Output transistor Nch, IOUT = 2 mA Output transistor Nch, IOUT = 2 mA CMOS output product Output transistor Pch, IOUT = 2 mA Nch open-drain output product Output transistor Nch, VOUT = 5.5 V 2.7 5.0 5.5 1400.0 2000.0 Leakage current ILEAK Awake mode time tAW 50 s Sleep mode time tSL 0 s Operating cycle tCYCLE 50 100 s Enabling pin input voltage "L" VCEL VDD 0.3 V Enabling pin input voltage "H" VCEH VDD 0.7 V Enabling pin input current "L" ICEL VDD = 5.0 V, VCE = 0 V 1 1 A 7 Enabling pin input current "H" ICEH VDD = 5.0 V, VCE = 5.0 V 1 1 A 8 Power-down transition time tOFF 100 s Enable transition time tON 100 s Output logic update time after inputting "H" to enabling pin tOE 200 s tAW tSL 13 HIGH-SPEED BIPOLAR HALL EFFECT LATCH S-5725 Series Rev.2.5_02 Magnetic Characteristics 1. Product with BOP = 0.8 mT typ. Table 15 Item Operation point*1 S pole Release point*2 N pole Hysteresis width*3 2. Symbol BOP BRP BHYS (Ta = 25C, VDD = 5.0 V, VSS = 0 V unless otherwise specified) Condition Min. Typ. Max. Unit Test Circuit 0.1 0.8 1.5 mT 5 1.5 0.8 0.1 mT 5 BHYS = BOP BRP 1.6 mT 5 Product with BOP = 1.8 mT typ. Table 16 Item Operation point*1 S pole Release point*2 N pole Hysteresis width*3 3. Symbol BOP BRP BHYS (Ta = 25C, VDD = 5.0 V, VSS = 0 V unless otherwise specified) Condition Min. Typ. Max. Unit Test Circuit 0.9 1.8 2.7 mT 5 2.7 1.8 0.9 mT 5 BHYS = BOP BRP 3.6 mT 5 Product with BOP = 3.0 mT typ. Table 17 (Ta = 25C, VDD = 5.0 V, VSS = 0 V unless otherwise specified) Item Operation point*1 S pole Release point*2 N pole Hysteresis width*3 4. Symbol BOP BRP BHYS Condition BHYS = BOP BRP Min. 1.4 4.0 Typ. 3.0 3.0 6.0 Max. 4.0 1.4 Unit mT mT mT Test Circuit 5 5 5 Product with BOP = 7.0 mT typ. Table 18 (Ta = 25C, VDD = 5.0 V, VSS = 0 V unless otherwise specified) Item *1 Operation point S pole *2 Release point N pole Hysteresis width*3 Symbol BOP BRP BHYS Condition BHYS = BOP BRP Min. 5.0 8.5 Typ. 7.0 7.0 14.0 Max. 8.5 5.0 Unit mT mT mT Test Circuit 5 5 5 *1. BOP: Operation point BOP is the value of magnetic flux density when the output voltage (VOUT) changes after the magnetic flux density applied to the S-5725 Series by the magnet (S pole) is increased (by moving the magnet closer). VOUT retains the status until a magnetic flux density of the N pole higher than BRP is applied. *2. BRP: Release point BRP is the value of magnetic flux density when the output voltage (VOUT) changes after the magnetic flux density applied to the S-5725 Series by the magnet (N pole) is increased (by moving the magnet closer). VOUT retains the status until a magnetic flux density of the S pole higher than BOP is applied. *3. BHYS: Hysteresis width BHYS is the difference between BOP and BRP. Remark The unit of magnetic density mT can be converted by using the formula 1 mT = 10 Gauss. 14 HIGH-SPEED BIPOLAR HALL EFFECT LATCH S-5725 Series Rev.2.5_02 Test Circuits 1. Product without power-down function A *1 R 100 k VDD VDD S-5725 Series OUT S-5725 Series OUT VSS VSS *1. A V Resistor (R) is unnecessary for the CMOS output product. Figure 8 Test Circuit 1 Figure 9 Test Circuit 2 VDD VDD S-5725 Series OUT S-5725 Series OUT VSS A VSS V Figure 10 Test Circuit 3 A V Figure 11 Test Circuit 4 R*1 100 k VDD S-5725 Series OUT VSS *1. V Resistor (R) is unnecessary for the CMOS output product. Figure 12 Test Circuit 5 15 HIGH-SPEED BIPOLAR HALL EFFECT LATCH S-5725 Series 2. Rev.2.5_02 Product with power-down function (SNT-4A) A CE VDD R*1 100 k CE S-5725 Series OUT VDD S-5725 Series OUT VSS VSS *1. CE Figure 14 Test Circuit 2 VDD CE S-5725 Series OUT VSS A VDD S-5725 Series OUT CE V Resistor (R) is unnecessary for the CMOS output product. Figure 17 Test Circuit 5 A V A *1 VSS S-5725 Series OUT Figure 16 Test Circuit 4 R 100 k CE VDD VSS V Figure 15 Test Circuit 3 16 V Resistor (R) is unnecessary for the CMOS output product. Figure 13 Test Circuit 1 *1. A VDD R*1 100 k S-5725 Series OUT VSS *1. Resistor (R) is unnecessary for the CMOS output product. Figure 18 Test Circuit 6 HIGH-SPEED BIPOLAR HALL EFFECT LATCH S-5725 Series Rev.2.5_02 A CE VDD S-5725 Series OUT VSS Figure 19 Test Circuit 7 A CE VDD S-5725 Series OUT VSS Figure 20 Test Circuit 8 17 HIGH-SPEED BIPOLAR HALL EFFECT LATCH S-5725 Series Rev.2.5_02 Standard Circuits 1. Product without power-down function *1 R 100 k VDD S-5725 Series OUT VSS CIN 0.1 F *1. Resistor (R) is unnecessary for the CMOS output product. Figure 21 2. Product with power-down function (SNT-4A) *1 R 100 k VDD VDD or VSS CE S-5725 Series OUT VSS CIN 0.1 F *1. Resistor (R) is unnecessary for the CMOS output product. Figure 22 Caution The above connection diagram and constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. 18 HIGH-SPEED BIPOLAR HALL EFFECT LATCH S-5725 Series Rev.2.5_02 Operation 1. Direction of applied magnetic flux The S-5725 Series detects the magnetic flux density which is vertical to the marking surface. Figure 23 and Figure 24 show the direction in which magnetic flux is being applied. 1. 1 SOT-23-3 1. 2 SNT-4A N S N S Marking surface Marking surface Figure 23 2. Figure 24 Position of Hall sensor Figure 25 and Figure 26 show the position of Hall sensor. The center of this Hall sensor is located in the area indicated by a circle, which is in the center of a package as described below. The following also shows the distance (typ. value) between the marking surface and the chip surface of a package. 2. 1 SOT-23-3 2. 2 SNT-4A Top view Top view 1 2 1 The center of Hall sensor; in this 0.3 mm 4 2 3 The center of Hall sensor; in this 0.3 mm 3 0.16 mm (typ.) 0.7 mm (typ.) Figure 25 Figure 26 19 HIGH-SPEED BIPOLAR HALL EFFECT LATCH S-5725 Series 3. Rev.2.5_02 Basic operation The S-5725 Series changes the output voltage (VOUT) according to the level of the magnetic flux density and a polarity change (N pole or S pole) applied by a magnet. Definition of the magnetic field is performed every operating cycle indicated in " Electrical Characteristics". 3. 1 Product with VOUT = "L" at S pole detection When the magnetic flux density of the S pole perpendicular to the marking surface exceeds the operation point (BOP) after the S pole of a magnet is moved closer to the marking surface of the S-5725 Series, VOUT changes from "H" to "L". When the N pole of a magnet is moved closer to the marking surface of the S-5725 Series and the magnetic flux density of the N pole is higher than the release point (BRP), VOUT changes from "L" to "H". In case of BRP B BOP, VOUT retains the status. Figure 27 shows the relationship between the magnetic flux density and VOUT. VOUT BHYS H L N pole 0 BRP BOP S pole Magnetic flux density (B) Figure 27 3. 2 Product with VOUT = "H" at S pole detection When the magnetic flux density of the S pole perpendicular to the marking surface exceeds BOP after the S pole of a magnet is moved closer to the marking surface of the S-5725 Series, VOUT changes from "L" to "H". When the N pole of a magnet is moved closer to the marking surface of the S-5725 Series and the magnetic flux density of the N pole is higher than BRP, VOUT changes from "H" to "L". In case of BRP B BOP, VOUT retains the status. Figure 28 shows the relationship between the magnetic flux density and VOUT. VOUT BHYS H L N pole BRP 0 Magnetic flux density (B) Figure 28 20 BOP S pole Rev.2.5_02 HIGH-SPEED BIPOLAR HALL EFFECT LATCH S-5725 Series Precautions If the impedance of the power supply is high, the IC may malfunction due to a supply voltage drop caused by feedthrough current. Take care with the pattern wiring to ensure that the impedance of the power supply is low. Note that the IC may malfunction if the power supply voltage rapidly changes. Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit. Large stress on this IC may affect on the magnetic characteristics. Avoid large stress which is caused by bend and distortion during mounting the IC on a board or handle after mounting. ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by products including this IC of patents owned by a third party. 21 HIGH-SPEED BIPOLAR HALL EFFECT LATCH S-5725 Series Rev.2.5_02 Marking Specifications 1. SOT-23-3 Top view (1) to (3): (4): 1 (1) (2) (3) (4) 2 3 Product name vs. Product code 1. 1 Nch open-drain output product Product Code Product Name (1) (2) (3) S-5725CNBL9-M3T1U X 9 R S-5725CNBL0-M3T1U X 9 S S-5725CNBL1-M3T1U X 9 J S-5725DNBL1-M3T1U X 9 K S-5725ENBL9-M3T1U X 9 V S-5725ENBL0-M3T1U X 9 A S-5725ENBL1-M3T1U X 9 B S-5725ENBH1-M3T1U X 9 L 1. 2 CMOS output product Product Name S-5725CCBL9-M3T1U S-5725CCBL0-M3T1U S-5725CCBL1-M3T1U S-5725DCBL1-M3T1U S-5725ECBL9-M3T1U S-5725ECBL0-M3T1U S-5725ECBL1-M3T1U S-5725ECBH0-M3T1U S-5725ECBH1-M3T1U 22 Product Code (1) (2) (3) X 9 P X 9 Q X 9 T X 9 U X 9 W X 9 X X 9 C X 9 Z X 9 Y Product code (Refer to Product name vs. Product code.) Lot number HIGH-SPEED BIPOLAR HALL EFFECT LATCH S-5725 Series Rev.2.5_02 2. SNT-4A Top view (1) to (3): 1 Product code (Refer to Product name vs. Product code.) 4 (1) (2) (3) 2 3 Product name vs. Product code 2. 1 Nch open-drain output product Product Code Product Name (1) (2) (3) S-5725ENBH3-I4T1U X 8 A S-5725HNBH0-I4T1U X 9 D S-5725INBH0-I4T1U X 9 F S-5725JNBH0-I4T1U X 9 H 2. 2 CMOS output product Product Name S-5725ECBL9-I4T1U S-5725ECBL0-I4T1U S-5725ECBH0-I4T1U S-5725HCBH0-I4T1U S-5725HCBH1-I4T1U S-5725ICBH0-I4T1U S-5725ICBH1-I4T1U S-5725JCBH0-I4T1U S-5725JCBH1-I4T1U Product Code (1) (2) (3) X 9 W X 9 X X 9 Z X 9 E X 9 M X 9 G X 9 N X 9 I X 9 O 23 2.90.2 1 2 3 +0.1 0.16 -0.06 0.950.1 1.90.2 0.40.1 No. MP003-C-P-SD-1.1 TITLE SOT233-C-PKG Dimensions No. MP003-C-P-SD-1.1 ANGLE UNIT mm ABLIC Inc. +0.1 o1.5 -0 4.00.1 2.00.1 +0.25 o1.0 -0 0.230.1 4.00.1 1.40.2 3.20.2 1 2 3 Feed direction No. MP003-C-C-SD-2.0 TITLE SOT233-C-Carrier Tape No. MP003-C-C-SD-2.0 ANGLE UNIT mm ABLIC Inc. 12.5max. 9.20.5 Enlarged drawing in the central part o130.2 No. MP003-Z-R-SD-1.0 SOT233-C-Reel TITLE MP003-Z-R-SD-1.0 No. QTY. ANGLE UNIT mm ABLIC Inc. 3,000 1.20.04 3 4 +0.05 0.08 -0.02 2 1 0.65 0.480.02 0.20.05 No. PF004-A-P-SD-6.0 TITLE SNT-4A-A-PKG Dimensions No. PF004-A-P-SD-6.0 ANGLE UNIT mm ABLIC Inc. +0.1 o1.5 -0 4.00.1 2.00.05 0.250.05 +0.1 1.450.1 2 1 3 4 o0.5 -0 4.00.1 0.650.05 Feed direction No. PF004-A-C-SD-2.0 TITLE SNT-4A-A-Carrier Tape No. PF004-A-C-SD-2.0 ANGLE UNIT mm ABLIC Inc. 12.5max. 9.00.3 Enlarged drawing in the central part o130.2 (60) (60) No. PF004-A-R-SD-1.0 TITLE SNT-4A-A-Reel No. PF004-A-R-SD-1.0 QTY. ANGLE UNIT mm ABLIC Inc. 5,000 0.52 1.16 2 0.52 0.35 1. 2. 0.3 1 (0.25 mm min. / 0.30 mm typ.) (1.10 mm ~ 1.20 mm) 0.03 mm 1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.). 2. Do not widen the land pattern to the center of the package (1.10 mm to 1.20 mm). Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package. 2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm or less from the land pattern surface. 3. Match the mask aperture size and aperture position with the land pattern. 4. Refer to "SNT Package User's Guide" for details. 1. 2. (0.25 mm min. / 0.30 mm typ.) (1.10 mm ~ 1.20 mm) TITLE SNT-4A-A -Land Recommendation PF004-A-L-SD-4.1 No. No. PF004-A-L-SD-4.1 ANGLE UNIT mm ABLIC Inc. Disclaimers (Handling Precautions) 1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and application circuit examples, etc.) is current as of publishing date of this document and is subject to change without notice. 2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of any specific mass-production design. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other right due to the use of the information described herein. 3. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described herein. 4. Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute maximum ratings, operation voltage range and electrical characteristics, etc. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to the use of the products outside their specified ranges. 5. Before using the products, confirm their applications, and the laws and regulations of the region or country where they are used and verify suitability, safety and other factors for the intended use. 6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related laws, and follow the required procedures. 7. The products are strictly prohibited from using, providing or exporting for the purposes of the development of weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear, biological or chemical weapons or missiles, or use any other military purposes. 8. The products are not designed to be used as part of any device or equipment that may affect the human body, human life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment, aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by ABLIC, Inc. Do not apply the products to the above listed devices and equipments. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of the products. 9. In general, semiconductor products may fail or malfunction with some probability. The user of the products should therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social damage, etc. that may ensue from the products' failure or malfunction. The entire system in which the products are used must be sufficiently evaluated and judged whether the products are allowed to apply for the system on customer's own responsibility. 10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the product design by the customer depending on the intended use. 11. The products do not affect human health under normal use. However, they contain chemical substances and heavy metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be careful when handling these with the bare hands to prevent injuries, etc. 12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used. 13. The information described herein contains copyright information and know-how of ABLIC Inc. The information described herein does not convey any license under any intellectual property rights or any other rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express permission of ABLIC Inc. 14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales representative. 15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into the English language and the Chinese language, shall be controlling. 2.4-2019.07 www.ablic.com