IS24C01B IS24C02B IS24C01B/02B 2-WIRE (I C) 2 1K-bit/2K-bit SERIAL EEPROM Integrated Silicon Solution, Inc. -- www.issi.com Rev. F 09/11/09 1 IS24C01B IS24C02B Table of Contents Features ................................................................................................3 Description ............................................................................................3 Functional Block Diagram .......................................................................4 Pin Configuration & Description ...............................................................5 Device Operations ..................................................................................6 Absolute Maximum Ratings .....................................................................14 DC Characteristics ..................................................................................14 AC Characteristics ..................................................................................15 Ordering Information ...............................................................................16 Packaging Information .............................................................................17 2 Integrated Silicon Solution, Inc. -- www.issi.com Rev. F 9/11/09 IS24C01B IS24C02B 1K-bit/2K-bit 2-WIRE SERIAL CMOS EEPROM FEATURES Description * Two-Wire Serial Interface, I2CTM compatible - Bi-directional data transfer protocol * Wide Voltage Operation - Vcc = 1.8V to 5.5V * 400 KHz (2.5V) and 1 MHz (5.0V) compatibility * Low Power - Standby Current: 1 A or less (1.8V) - Read Current: 2 mA or less (5.0V) - Write Current: 3 mA or less (5.0V) * Hardware Data Protection - Write Protect Pin * Sequential Read Feature * Filtered Inputs for Noise Suppression * Self time write cycle with auto clear 5 ms max. @ 2.5V * Memory Organization: - IS24C01B: 128x8 (1K bits) - IS24C02B: 256x8 (2K bits) * 8-Byte Page Write Buffer * High Reliability - Endurance: 1,000,000 Cycles - Data Retention: 100 Years * Industrial temperature grade * Packages: SOIC/SOP, TSSOP, DFN, and UDFN. The IS24C01B and IS24C02B are EEPROM devices that use the industrial standard 2-wire, I2C, interface for communications. The IS24C01B and IS24C02B contain a memory array of 1K-bits (128 x 8) and 2K-bits (256 x 8), respectively. Each device is organized into 8 byte pages for page write mode. This EEPROM operates in a wide voltage range of 1.8V to 5.5V to be compatible with most application voltages. ISSI designed this device family to be a practical, low-power 2-wire EEPROM solution. The devices are offered in lead-free, RoHS, halogen free or Green. The available package types are 8-pin SOIC, TSSOP, DFN, and UDFN. The IS24C01B/02B maintains compatibility with the popular 2-wire bus protocol, so it is easy to use in applications implementing this bus type. The simple bus consists of the Serial Clock wire (SCL) and the Serial Data wire (SDA). Using the bus, a Master device such as a microcontroller is usually connected to one or more Slave devices such as this device. The bit stream over the SDA line includes a series of bytes, which identifies a particular Slave device, an instruction, an address within that Slave device, and a series of data, if appropriate. The IS24C01B/02B has a Write Protect pin (WP) to allow blocking of any write instruction transmitted over the bus. Copyright (c) 2008 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for critical medical or surgical equipment, aerospace systems, or for other applications planned to support or sustain life. It is the customer's obligation to optimize the design in their own products for the best performance and optimization on the functionality and etc. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and prior placing orders for products. Integrated Silicon Solution, Inc. -- www.issi.com Rev. F 09/11/09 3 IS24C01B IS24C02B FUNCTIONAL BLOCK DIAGRAM HIGH VOLTAGE GENERATOR, TIMING & CONTROL 8 SDA 5 SCL 6 WP 7 CONTROL LOGIC SLAVE ADDRESS REGISTER & COMPARATOR A0 1 A1 2 A2 3 GND 4 EEPROM ARRAY WORD ADDRESS COUNTER ACK nMOS 4 X DECODER Vcc Y DECODER Clock DI/O > DATA REGISTER Integrated Silicon Solution, Inc. -- www.issi.com Rev. F 9/11/09 IS24C01B IS24C02B PIN CONFIGURATION 8-pad UDFN, DFN 8-Pin SOIC, TSSOP A0 1 8 VCC A0 1 8 VCC A1 2 7 WP A1 2 7 WP A2 3 6 SCL A2 3 6 SCL GND 4 5 SDA GND 4 5 SDA (Top View) PIN DESCRIPTIONS A0-A2 SDA SCL WP Vcc GND Address Inputs Serial Address/Data I/O Serial Clock Input Write Protect Input Power Supply Ground SCL This input clock pin is used to synchronize the data transfer to and from the device. SDA The SDA is a Bi-directional pin used to transfer addresses and data into and out of the device. The SDA pin is an open drain output and can be wire-Or'ed with other open drain or open collector outputs. The SDA bus requires a pullup resistor to Vcc. Integrated Silicon Solution, Inc. -- www.issi.com Rev. F 9/11/09 A0, A1, A2 The A0, A1 and A2 are the device address inputs. The IS24C01B/02B uses the A0, A1, and A2 for hardware addressing and a total of 8 devices may be used on a single bus system. When the A0, A1, or A2 inputs are left floating, the input internally defaults to zero. WP WP is the Write Protect pin. If the WP pin is tied to Vcc on the EEPROM, the entire array becomes Write Protected (Read only). When WP is tied to GND or left floating normal read/write operations are allowed to the device. 5 IS24C01B IS24C02B DEVICE OPERATION Stop Condition IS24C01B/02B features serial communication and supports a bi-directional 2-wire bus transmission protocol called I2CTM. The Stop condition is defined as a Low to High transition of SDA when SCL is High. All operations must end with a Stop condition. 2-WIRE BUS Acknowledge (ACK) The two-wire bus is defined as a Serial Data line (SDA), and a Serial Clock line (SCL). The protocol defines any device that sends data onto the SDA bus as a transmitter, and the receiving devices as receivers. The bus is controlled by Master device that generates the SCL, controls the bus access, and generates the Stop and Start conditions. The IS24C01B/02B is the Slave device on the bus. After a successful data transfer, each receiving device is required to generate an ACK. The Acknowledging device pulls down the SDA line. The Bus Protocol: - Data transfer may be initiated only when the bus is not busy - During a data transfer, the SDA line must remain stable whenever the SCL line is high. Any changes in the SDA line while the SCL line is high will be interpreted as a Start or Stop condition. The state of the SDA line represents valid data after a Start condition. The SDA line must be stable for the duration of the High period of the clock signal. The data on the SDA line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a Start condition and terminated with a Stop condition. Reset The IS24C01B/02B contains a reset function in case the 2-wire bus transmission is accidentally interrupted (eg. a power loss), or needs to be terminated mid-stream. The reset is caused when the Master device creates a Start condition. To do this, it may be necessary for the Master device to monitor the SDA line while cycling the SCL up to nine times. (For each clock signal transition to High, the Master checks for a High level on SDA.) Standby Mode Power consumption is reduced in standby mode. The IS24C01B/02B will enter standby mode: a) At Power-up, and remain in it until SCL or SDA toggles; b) Following the Stop signal if a no write operation is initiated; or c) Following any internal write operation. Start Condition The Start condition precedes all commands to the device and is defined as a High to Low transition of SDA when SCL is High. The EEPROM monitors the SDA and SCL lines and will not respond until the Start condition is met. 6 Integrated Silicon Solution, Inc. -- www.issi.com Rev. F 9/11/09 IS24C01B IS24C02B DEVICE ADDRESSING WRITE OPERATION The Master begins a transmission by sending a Start condition. The Master then sends the address of the particular Slave devices it is requesting. The Slave device (Fig. 5) address is 8 bits. Byte Write The four most significant bits of the Slave device address are fixed as 1010 for the IS24C01B/02B. The next three bits of the Slave address are specific for each of the EEPROM. The bit values enable access to multiple memory blocks or multiple devices. The IS24C01B/02B uses the three bits A0, A1, and A2 in a comparison with the hard-wired input values on the A0, A1, and A2 pins. Up to eight units may share the 2-wire bus. The last bit of the Slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. After the Master transmits the Start condition and Slave address byte (Fig. 5), the appropriate 2-wire Slave (eg. IS24C02B) will respond with ACK on the SDA line. The Slave will pull down the SDA on the ninth clock cycle, signaling that it received the eight bits of data. The selected EEPROM then prepares for a Read or Write operation by monitoring the bus. In the Byte Write mode, the Master device sends the Start condition and the Slave address information (with the R/W set to Zero) to the Slave device. After the Slave generates an ACK, the Master sends the byte address that is to be written into the address pointer of the IS24C01B/02B. After receiving another ACK from the Slave, the Master device transmits the data byte to be written into the address memory location. The IS24C01B/02B acknowledges once more and the Master generates the Stop condition, at which time the device begins its internal programming cycle. While this internal cycle is in progress, the device will not respond to any request from the Master device. Page Write The IS24C01B/02B is capable of 8-byte Page-Write operation. A Page-Write is initiated in the same manner as a Byte Write, but instead of terminating the internal Write cycle after the first data word is transferred, the Master device can transmit up to 7 more bytes. After the receipt of each data word, the EEPROM responds immediately with an ACK on SDA line, and the three lower order data word address bits are internally incremented by one, while the higher order bits of the data word address remain constant. If a byte address is incremented from the last byte of a page, it returns to the first byte of that page. If the Master device should transmit more than 8 bytes prior to issuing the Stop condition, the address counter will "roll over," and the previously written data will be overwritten. Once all 8 bytes are received and the Stop condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the IS24C01B/02B in a single Write cycle. All inputs are disabled until completion of the internal Write cycle. Acknowledge (ACK) Polling The disabling of the inputs can be used to take advantage of the typical Write cycle time. Once the Stop condition is issued to indicate the end of the host's Write operation, the IS24C01B/02B initiates the internal Write cycle. ACK polling can be initiated immediately. This involves issuing the Start condition followed by the Slave address for a Write operation. If the EEPROM is still busy with the Write operation, no ACK will be returned. If the IS24C01B/02B has completed the Write operation, an ACK will be returned and the host can then proceed with the next Read or Write operation. Integrated Silicon Solution, Inc. -- www.issi.com Rev. F 9/11/09 7 IS24C01B IS24C02B Read OPERATION Random Address Read Read operations are initiated in the same manner as Write operations, except that the (R/W) bit of the Slave address is set to "1". There are three Read operation options: current address read, random address read and sequential read. Selective Read operations allow the Master device to select at random any memory location for a Read operation. The Master device first performs a 'dummy' Write operation by sending the Start condition, Slave address and byte address of the location it wishes to read. After the IS24C01B/02B acknowledges the byte address, the Master device resends the Start condition and the Slave address, this time with the R/W bit set to one. The EEPROM then responds with its ACK and sends the data requested. The Master device does not send an ACK but will generate a Stop condition. (Refer to Figure 9. Random Address Read Diagram.) Current Address Read The IS24C01B/02B contains an internal address counter which maintains the address of the last byte accessed, incremented by one. For example, if the previous operation is either a Read or Write operation addressed to the address location n, the internal address counter would increment to address location n+1. When the EEPROM receives the Slave Addressing Byte with a Read operation (R/W bit set to "1"), it will respond an ACK and transmit the 8-bit data byte stored at address location n+1. The Master should not acknowledge the transfer but should generate a Stop condition so the IS24C01B/02B discontinues transmission. If 'n' is the last byte of the memory, the data from location '0' will be transmitted. (Refer to Figure 8. Current Address Read Diagram.) Sequential Read Sequential Reads can be initiated as either a Current Address Read or Random Address Read. After the IS24C01B/02B sends the initial byte sequence, the Master device now responds with an ACK, indicating it requires additional data from the IS24C01B/02B. The EEPROM continues to output data for each ACK received. The Master device terminates the sequential Read operation by pulling SDA High (no ACK) indicating the last data word to be read, followed by a Stop condition. The data output is sequential, with the data from address n followed by the data from address n+1,n+2 ... etc. The address counter increments by one automatically, allowing the entire memory contents to be serially read during sequential Read operation. When the memory address boundary of 127 or 255 (depending on the device) is reached, the address counter "rolls over" to address 0, and the device continues to output data. (Refer to Figure 10. Sequential Read Diagram). 8 Integrated Silicon Solution, Inc. -- www.issi.com Rev. F 9/11/09 IS24C01B IS24C02B Figure 1. Typical System Bus Configuration Vcc SDA SCL Master Transmitter/ Receiver IS24Cxx Figure 2. Output Acknowledge SCL from Master 1 8 9 Data Output from Transmitter tAA Data Output from Receiver tAA ACK STOP Condition SCL START Condition Figure 3. START and STOP Conditions SDA Integrated Silicon Solution, Inc. -- www.issi.com Rev. F 9/11/09 9 IS24C01B IS24C02B Figure 4. Data Validity Protocol Data Change SCL Data Stable Data Stable SDA Figure 5. Slave Address BIT 7 6 5 4 3 2 1 0 1 0 1 0 A2 A1 A0 R/W Figure 6. Byte Write SDA Bus Activity S T A R T Device Address M S B W R I T E Data Byte Address A C K * S T O P A C K A C K L M S S B B R/W * = Don't care bit for IS24C01B 10 Integrated Silicon Solution, Inc. -- www.issi.com Rev. F 9/11/09 IS24C01B IS24C02B Figure 7. Page Write SDA Bus Activity S T A R T W R I T E Device Address M S B Data (n) Byte Address (n) A C K A C K * Data (n+1) A C K S T O P Data (n+7) A C K A C K L S B R/W * = Don't care bit for IS24C01B Figure 8. Current Address Read S T A R T SDA Bus Activity R E A D Device Address S T O P Data A C K M S B L S B N O A C K R/W Figure 9. Random Address Read SDA Bus Activity S T A R T Device Address M S B W R I T E Byte Address (n) A C K * L S B R/W DUMMY WRITE A C K S T A R T Device Address R E A D S T O P Data n A C K N O A C K * = Don't care bit for IS24C01B Integrated Silicon Solution, Inc. -- www.issi.com Rev. F 9/11/09 11 IS24C01B IS24C02B Figure 10. Sequential Read Device Address SDA Bus Activity R E A D Data Byte n A C K Data Byte n+2 A C K Data Byte n+X A C K N O R/W 12 Data Byte n+1 A C K S T O P A C K Integrated Silicon Solution, Inc. -- www.issi.com Rev. F 9/11/09 IS24C01B IS24C02B AC WAVEFORMS Figure 11. Bus Timing tR tF tHIGH tLOW tSU:STO SCL tSU:STA tBUF tHD:DAT tHD:STA tSU:DAT SDAIN tAA tDH SDAOUT tSU:WP tHD:WP WP Figure 12. Write Cycle Timing SCL SDA 8th BIT ACK tWR WORD n STOP Condition Integrated Silicon Solution, Inc. -- www.issi.com Rev. F 9/11/09 START Condition 13 IS24C01B IS24C02B ABSOLUTE MAXIMUM RATINGS(1) Symbol Vs Vp Tbias Tstg Iout Parameter Supply Voltage Voltage on Any Pin Temperature Under Bias Storage Temperature Output Current Value -0.5 to +6.5 -0.5 to Vcc + 0.5 -55 to +125 -65 to +150 5 Unit V V C C mA Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS Industrial (Ta = -40oC to +85oC) Symbol Vol1 Vol2 Vih Vil Ili Ilo Parameter Test Conditions Output Low Voltage Vcc = 1.8V, Iol = 0.15 mA Output Low Voltage Vcc = 2.5V, Iol = 3 mA Input High Voltage Input Low Voltage Input Leakage Current Vin = Vcc max. Output Leakage Current Min. Max. -- 0.2 -- 0.4 Vcc x 0.7 Vcc + 0.5 -1.0 Vcc x 0.3 -- 3 -- 3 Unit V V V V A A Notes: Vil min and Vih max are reference only and are not tested. POWER SUPPLY CHARACTERISTICS Industrial (Ta = -40oC to +85oC) Symbol Icc1 Icc2 Isb1 Isb2 Isb3 Parameter Operating Current Operating Current Standby Current Standby Current Standby Current Test Conditions Read at 400 KHz (Vcc = 5V) Write at 400 KHz (Vcc = 5V) Vcc = 1.8V Vcc = 2.5V Vcc = 5.0V Min. -- -- -- -- -- Max. 2.0 3.0 1 2 6 Unit mA mA A A A CAPACITANCE(1,2) Symbol Cin Cout Parameter Input Capacitance Output Capacitance Conditions Vin = 0V Vout = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25C, f = 1 MHz, Vcc = 5.0V. 14 Integrated Silicon Solution, Inc. -- www.issi.com Rev. F 9/11/09 IS24C01B IS24C02B AC ELECTRICAL CHARACTERISTICS Industrial (Ta = -40oC to +85oC) Symbol fscl T tlow thigh tbuf tsu:sta tsu:sto thd:sta thd:sto tsu:dat thd:dat tsu:wp thd:wp tdh taa tr tf twr 1.8V Vcc < 2.5V (2) Parameter Min. Max. SCL Clock Frequency 0 100 (1) Noise Suppression Time -- 100 Clock Low Period 4.7 -- Clock High Period 4 -- Bus Free Time Before New Transmission(1) 4.7 -- Start Condition Setup Time 4 -- Stop Condition Setup Time 4 -- Start Condition Hold Time 4 -- Stop Condition Hold Time 4 -- Data In Setup Time 100 -- Data In Hold Time 0 -- WP pin Setup Time 4 -- WP pin Hold Time 4.7 -- Data Out Hold Time 100 -- (SCL Low to SDA Data Out Change) Clock to Output 100 3500 (SCL Low to SDA Data Out Valid) SCL and SDA Rise Time(1) -- 1000 SCL and SDA Fall Time(1) -- 300 Write Cycle Time -- 10 2.5V Vcc < 4.5V Min. Max. 0 400 -- 50 1.2 -- 0.6 -- 1.2 -- 0.6 -- 0.6 -- 0.6 -- 0.6 -- 100 -- 0 -- 0.6 -- 1.2 -- 50 -- 4.5V Vcc 5.5V(1) Min. Max. Unit 0 1000 KHz -- 50 ns 0.6 -- s 0.4 -- s 0.5 -- s 0.25 -- s 0.25 -- s 0.25 -- s 0.25 -- s 100 -- ns 0 -- ns 0.6 -- s 1.2 -- s 50 -- ns 50 900 50 400 ns -- -- -- 300 300 5 -- -- -- 300 100 5 ns ns ms Note: 1. This parameter is characterized but not 100% tested. 2. The timing is referenced to half Vcc level. Integrated Silicon Solution, Inc. -- www.issi.com Rev. F 9/11/09 15 IS24C01B IS24C02B ORDERING INFORMATION Industrial Range*: -40C to +85C Voltage Range Part Number* Package Type* (8-pin) 1.8V to 5.5V IS24C01B-2GLI-TR 150-mil SOIC (JEDEC) IS24C01B-2ZLI-TR 3 x 4.4 mm TSSOP IS24C02B-2GLI-TR 150-mil SOIC (JEDEC) IS24C02B-2ZLI-TR 3 x 4.4 mm TSSOP IS24C02B-2UDLI-TR 2 x 3 x 0.55mm UDFN IS24C02B-2DLI-TR 2 x 3 x 0.75mm DFN 1.8V to 5.5V * 1. Contact ISSI Sales Representatives for availability and other package information. 2. The listed part numbers are packed in tape and reel "-TR" (4K per reel). UDFN/DFN is 5K per reel. 3. For tube/bulk packaging, if any available, remove "-TR" at the end of the P/N. 4. Refer to ISSI website for related declaration document on lead free, RoHS, halogen free, or Green, whichever is applicable. 5. ISSI offers Industrial grade for Commercial applications (0oC to +70oC). 16 Integrated Silicon Solution, Inc. -- www.issi.com Rev. F 9/11/09 IS24C01B IS24C02B Integrated Silicon Solution, Inc. -- www.issi.com Rev. F 9/11/09 17 IS24C01B IS24C02B 18 Integrated Silicon Solution, Inc. -- www.issi.com Rev. F 9/11/09 IS24C01B IS24C02B Integrated Silicon Solution, Inc. -- www.issi.com Rev. F 9/11/09 19 IS24C01B IS24C02B 20 Integrated Silicon Solution, Inc. -- www.issi.com Rev. F 9/11/09