WIN860M6NHEI-300A1 - MICROSEMI

NAND Flash Memory

MT29F1G08ABADAWP, MT29F1G08ABBDAH4,

MT29F1G08ABBDAHC, MT29F1G16ABBDAH4,

MT29F1G16ABBDAHC, MT29F1G08ABADAH4

Features

• Open NAND Flash Interface (ONFI) 1.0-compliant1

• Single-level cell (SLC) technology

• Organization

– Page size x8: 2112 bytes (2048 + 64 bytes)

– Page size x16: 1056 words (1024 + 32 words)

– Block size: 64 pages (128K + 4K bytes)

– Device size: 1Gb: 1024 blocks

• Asynchronous I/O performance

–tRC/tWC: 20ns (3.3V), 25ns (1.8V)

• Array performance

– Read page: 25µs3

– Program page: 200µs (TYP, 3.3V and 1.8V)3

– Erase block: 700µs (TYP)

• Command set: ONFI NAND Flash Protocol

• Advanced command set

– Program page cache mode5

– Read page cache mode5

– One-time programmable (OTP) mode

– Read unique ID

– Internal data move

• Operation status byte provides software method for

detecting

– Operation completion

– Pass/fail condition

– Write-protect status

• Internal data move operations supported within the

device from which data is read

• Ready/busy# (R/B#) signal provides a hardware

method for detecting operation completion

• WP# signal: write protect entire device

• First block (block address 00h) is valid when ship-

ped from factory with ECC. For minimum required

ECC, see Error Management.

• Block 0 requires 1-bit ECC if PROGRAM/ERASE cy-

cles are less than 1000

• RESET (FFh) required as first command after pow-

er-on

• Alternate method of device initialization (Nand_In-

it) after power up4 (contact factory)

• Quality and reliability

– Data retention: 10 years

– Endurance: 100,000 PROGRAM/ERASE cycles

• Operating Voltage Range

– VCC: 2.7–3.6V

– VCC: 1.7–1.95V

• Operating temperature:

– Commercial: 0°C to +70°C

– Extended (ET): –40ºC to +85ºC

• Package

– 48-pin TSOP type 1, CPL2

– 63-ball VFBGA

Notes: 1. The ONFI 1.0 specification is available at

www.onfi.org.

2. CPL = Center parting line.

3. See Electrical Specifications for tR_ECC and

tPROG_ECC specifications.

4. Available only in the 1.8V VFBGA package.

5. Supported only with ECC disabled.

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Products and specifications discussed herein are subject to change by Micron without notice.

Part Numbering Information

Micron NAND Flash devices are available in different configurations and densities. Verify valid part numbers by

using Micron’s part catalog search at www.micron.com. To compare features and specifications by device type,

visit www.micron.com/products. Contact the factory for devices not found.

Figure 1: Marketing Part Number Chart

MT 29F 1G 08 A B B D A HC IT ES :D

Micron Technology

Product Family

29F = NAND Flash memory

Density

1G = 1Gb

Device Width

08 = 8-bit

16 = 16-bit

Level

A= SLC

Classification

Mark Die nCE RnB I/O Channels

B 1 1 1 1

Operating Voltage Range

A = 3.3V (2.7–3.6V)

B = 1.8V (1.7–1.95V)

Feature Set

D = Feature set D

Design Revision (shrink)

Production Status

Blank = Production

ES = Engineering sample

MS = Mechanical sample

QS = Qualification sample

Special Options

Blank

Operating Temperature Range

Blank = Commercial (0°C to +70°C)

IT = Industrial (–40°C to +85°C)

Speed Grade

Blank

Package Code

WP = 48-pin TSOP 1

HC = 63-ball VFBGA (10.5 x 13 x 1.0mm)

H4 = 63-ball VFBGA (9 x 11 x 1.0mm)

Interface

A = Async only

X = Premium lifecycle product (PLP)

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Contents

Important Notes and Warnings ......................................................................................................................... 8

General Description ......................................................................................................................................... 9

Signal Descriptions and Assignments ................................................................................................................ 9

Signal Assignments ......................................................................................................................................... 10

Package Dimensions ....................................................................................................................................... 13

Architecture ................................................................................................................................................... 16

Device and Array Organization ........................................................................................................................ 17

Asynchronous Interface Bus Operation ........................................................................................................... 19

Asynchronous Enable/Standby ................................................................................................................... 19

Asynchronous Commands .......................................................................................................................... 19

Asynchronous Addresses ............................................................................................................................ 21

Asynchronous Data Input ........................................................................................................................... 22

Asynchronous Data Output ......................................................................................................................... 23

Write Protect# ............................................................................................................................................ 24

Ready/Busy# .............................................................................................................................................. 24

Device Initialization ....................................................................................................................................... 29

Command Definitions .................................................................................................................................... 30

Reset Operations ............................................................................................................................................ 32

RESET (FFh) ............................................................................................................................................... 32

Identification Operations ................................................................................................................................ 33

READ ID (90h) ............................................................................................................................................ 33

READ ID Parameter Tables .............................................................................................................................. 34

READ PARAMETER PAGE (ECh) ...................................................................................................................... 36

Parameter Page Data Structure Tables ............................................................................................................. 37

READ UNIQUE ID (EDh) ................................................................................................................................ 40

Feature Operations ......................................................................................................................................... 41

SET FEATURES (EFh) .................................................................................................................................. 42

GET FEATURES (EEh) ................................................................................................................................. 43

Status Operations ........................................................................................................................................... 46

READ STATUS (70h) ................................................................................................................................... 47

Column Address Operations ........................................................................................................................... 48

RANDOM DATA READ (05h-E0h) ................................................................................................................ 48

RANDOM DATA INPUT (85h) ...................................................................................................................... 49

PROGRAM FOR INTERNAL DATA INPUT (85h) ........................................................................................... 49

Read Operations ............................................................................................................................................. 51

READ MODE (00h) ..................................................................................................................................... 52

READ PAGE (00h-30h) ................................................................................................................................ 52

READ PAGE CACHE SEQUENTIAL (31h) ...................................................................................................... 53

READ PAGE CACHE RANDOM (00h-31h) .................................................................................................... 54

READ PAGE CACHE LAST (3Fh) .................................................................................................................. 56

Program Operations ....................................................................................................................................... 57

PROGRAM PAGE (80h-10h) ......................................................................................................................... 57

PROGRAM PAGE CACHE (80h-15h) ............................................................................................................. 58

Erase Operations ............................................................................................................................................ 60

ERASE BLOCK (60h-D0h) ............................................................................................................................ 60

Internal Data Move Operations ....................................................................................................................... 61

READ FOR INTERNAL DATA MOVE (00h-35h) ............................................................................................. 61

PROGRAM FOR INTERNAL DATA MOVE (85h–10h) ..................................................................................... 64

One-Time Programmable (OTP) Operations .................................................................................................... 65

OTP DATA PROGRAM (80h-10h) ................................................................................................................. 66

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RANDOM DATA INPUT (85h) ...................................................................................................................... 67

OTP DATA PROTECT (80h-10) ..................................................................................................................... 68

OTP DATA READ (00h-30h) ......................................................................................................................... 70

Error Management ......................................................................................................................................... 72

Internal ECC and Spare Area Mapping for ECC ................................................................................................ 74

Electrical Specifications .................................................................................................................................. 76

Electrical Specifications – AC Characteristics and Operating Conditions ........................................................... 78

Electrical Specifications – DC Characteristics and Operating Conditions ........................................................... 81

Electrical Specifications – Program/Erase Characteristics ................................................................................. 83

Asynchronous Interface Timing Diagrams ....................................................................................................... 84

Revision History ............................................................................................................................................. 94

Rev. S – 1/18 ............................................................................................................................................... 94

Rev. R – 10/14 ............................................................................................................................................. 94

Rev. Q – 06/14 ............................................................................................................................................. 94

Rev. P – 04/14 ............................................................................................................................................. 94

Rev. O – 03/14 ............................................................................................................................................. 94

Rev. N – 01/14 ............................................................................................................................................. 94

Rev. M – 07/13 ............................................................................................................................................ 94

Rev. L – 10/12 ............................................................................................................................................. 94

Rev. K – 02/12 ............................................................................................................................................. 94

Rev. J – 12/11 .............................................................................................................................................. 94

Rev. I – 11/11 .............................................................................................................................................. 94

Rev. H – 09/11 ............................................................................................................................................. 94

Rev. G – 01/11 ............................................................................................................................................. 95

Rev. F – 12/10 ............................................................................................................................................. 95

Rev. E – 11/10 ............................................................................................................................................. 95

Rev. D – 06/10 ............................................................................................................................................. 95

Rev C – 04/10 ............................................................................................................................................. 95

Rev B – 03/10 .............................................................................................................................................. 95

Rev A – 02/10 .............................................................................................................................................. 95

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List of Tables

Table 1: Asynchronous Signal Definitions ......................................................................................................... 9

Table 2: Array Addressing (x8) ........................................................................................................................ 17

Table 3: Array Addressing (x16) ...................................................................................................................... 18

Table 4: Asynchronous Interface Mode Selection ............................................................................................ 19

Table 5: Command Set .................................................................................................................................. 30

Table 6: READ ID Parameters for Address 00h ................................................................................................. 34

Table 7: READ ID Parameters for Address 20h ................................................................................................. 35

Table 8: Parameter Page Data Structure .......................................................................................................... 37

Table 9: Feature Address Definitions .............................................................................................................. 41

Table 10: Feature Address 90h – Array Operation Mode ................................................................................... 42

Table 11: Feature Addresses 01h: Timing Mode ............................................................................................... 44

Table 12: Feature Addresses 80h: Programmable I/O Drive Strength ................................................................ 45

Table 13: Feature Addresses 81h: Programmable R/B# Pull-Down Strength ...................................................... 45

Table 14: Status Register Definition ................................................................................................................ 46

Table 15: Error Management Details .............................................................................................................. 72

Table 16: Absolute Maximum Ratings ............................................................................................................. 76

Table 17: Recommended Operating Conditions .............................................................................................. 76

Table 18: Valid Blocks .................................................................................................................................... 76

Table 19: Capacitance .................................................................................................................................... 77

Table 20: Test Conditions ............................................................................................................................... 77

Table 21: AC Characteristics: Command, Data, and Address Input (3.3V) ......................................................... 78

Table 22: AC Characteristics: Command, Data, and Address Input (1.8V) ......................................................... 78

Table 23: AC Characteristics: Normal Operation (3.3V) ................................................................................... 79

Table 24: AC Characteristics: Normal Operation (1.8V) ................................................................................... 79

Table 25: DC Characteristics and Operating Conditions (3.3V) ........................................................................ 81

Table 26: DC Characteristics and Operating Conditions (1.8V) ........................................................................ 82

Table 27: ProgramErase Characteristics .......................................................................................................... 83

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List of Figures

Figure 1: Marketing Part Number Chart ............................................................................................................ 2

Figure 2: 48-Pin TSOP – Type 1, CPL (Top View) .............................................................................................. 10

Figure 3: 63-Ball VFBGA, x8 (Balls Down, Top View) ........................................................................................ 11

Figure 4: 63-Ball VFBGA, x16 (Balls Down, Top View) ...................................................................................... 12

Figure 5: 48-Pin TSOP – Type 1, CPL ............................................................................................................... 13

Figure 6: 63-Ball VFBGA (HC) ........................................................................................................................ 14

Figure 7: 63-Ball VFBGA (H4) 9mm x 11mm ................................................................................................... 15

Figure 8: NAND Flash Die (LUN) Functional Block Diagram ............................................................................ 16

Figure 9: Array Organization – x8 ................................................................................................................... 17

Figure 10: Array Organization – x16 ................................................................................................................ 18

Figure 11: Asynchronous Command Latch Cycle ............................................................................................ 20

Figure 12: Asynchronous Address Latch Cycle ................................................................................................ 21

Figure 13: Asynchronous Data Input Cycles .................................................................................................... 22

Figure 14: Asynchronous Data Output Cycles ................................................................................................. 23

Figure 15: Asynchronous Data Output Cycles (EDO Mode) ............................................................................. 24

Figure 16: READ/BUSY# Open Drain .............................................................................................................. 25

Figure 17: tFall and tRise (3.3V VCC) ................................................................................................................ 26

Figure 18: tFall and tRise (1.8V VCC) ................................................................................................................ 26

Figure 19: IOL vs. Rp (VCC = 3.3V VCC) .............................................................................................................. 27

Figure 20: IOL vs. Rp (1.8V VCC) ....................................................................................................................... 27

Figure 21: TC vs. Rp ....................................................................................................................................... 28

Figure 22: R/B# Power-On Behavior ............................................................................................................... 29

Figure 23: RESET (FFh) Operation .................................................................................................................. 32

Figure 24: READ ID (90h) with 00h Address Operation .................................................................................... 33

Figure 25: READ ID (90h) with 20h Address Operation .................................................................................... 33

Figure 26: READ PARAMETER (ECh) Operation .............................................................................................. 36

Figure 27: READ UNIQUE ID (EDh) Operation ............................................................................................... 40

Figure 28: SET FEATURES (EFh) Operation .................................................................................................... 42

Figure 29: GET FEATURES (EEh) Operation .................................................................................................... 43

Figure 30: READ STATUS (70h) Operation ...................................................................................................... 47

Figure 31: RANDOM DATA READ (05h-E0h) Operation ................................................................................... 48

Figure 32: RANDOM DATA INPUT (85h) Operation ........................................................................................ 49

Figure 33: PROGRAM FOR INTERNAL DATA INPUT (85h) Operation .............................................................. 50

Figure 34: READ PAGE (00h-30h) Operation ................................................................................................... 53

Figure 35: READ PAGE (00h-30h) Operation with Internal ECC Enabled .......................................................... 53

Figure 36: READ PAGE CACHE SEQUENTIAL (31h) Operation ......................................................................... 54

Figure 37: READ PAGE CACHE RANDOM (00h-31h) Operation ....................................................................... 55

Figure 38: READ PAGE CACHE LAST (3Fh) Operation ..................................................................................... 56

Figure 39: PROGRAM PAGE (80h-10h) Operaton ............................................................................................. 58

Figure 40: PROGRAM PAGE CACHE (80h-15h) Operation (Start) ..................................................................... 59

Figure 41: PROGRAM PAGE CACHE (80h-15h) Operation (End) ...................................................................... 59

Figure 42: ERASE BLOCK (60h-D0h) Operation .............................................................................................. 60

Figure 43: READ FOR INTERNAL DATA MOVE (00h-35h) Operation ................................................................ 62

Figure 44: READ FOR INTERNAL DATA MOVE (00h–35h) with RANDOM DATA READ (05h–E0h) ..................... 62

Figure 45: INTERNAL DATA MOVE (85h-10h) with Internal ECC Enabled ........................................................ 63

Figure 46: INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT with Internal ECC Enabled ............ 63

Figure 47: PROGRAM FOR INTERNAL DATA MOVE (85h–10h) Operation ........................................................ 64

Figure 48: PROGRAM FOR INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT (85h) .................... 64

Figure 49: OTP DATA PROGRAM (After Entering OTP Operation Mode) ........................................................... 67

Figure 50: OTP DATA PROGRAM Operation with RANDOM DATA INPUT (After Entering OTP Operation Mode) ... 68

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Figure 51: OTP DATA PROTECT Operation (After Entering OTP Protect Mode) ................................................. 69

Figure 52: OTP DATA READ ........................................................................................................................... 70

Figure 53: OTP DATA READ with RANDOM DATA READ Operation ................................................................. 71

Figure 54: Spare Area Mapping (x8) ................................................................................................................ 74

Figure 55: Spare Area Mapping (x16) .............................................................................................................. 75

Figure 56: RESET Operation ........................................................................................................................... 84

Figure 57: READ STATUS Cycle ...................................................................................................................... 84

Figure 58: READ PARAMETER PAGE .............................................................................................................. 85

Figure 59: READ PAGE ................................................................................................................................... 85

Figure 60: READ PAGE Operation with CE# “Don’t Care” ................................................................................ 86

Figure 61: RANDOM DATA READ ................................................................................................................... 87

Figure 62: READ PAGE CACHE SEQUENTIAL ................................................................................................. 88

Figure 63: READ PAGE CACHE RANDOM ....................................................................................................... 89

Figure 64: READ ID Operation ....................................................................................................................... 90

Figure 65: PROGRAM PAGE Operation ........................................................................................................... 90

Figure 66: PROGRAM PAGE Operation with CE# “Don’t Care” ......................................................................... 91

Figure 67: PROGRAM PAGE Operation with RANDOM DATA INPUT ............................................................... 91

Figure 68: PROGRAM PAGE CACHE ............................................................................................................... 92

Figure 69: PROGRAM PAGE CACHE Ending on 15h ......................................................................................... 92

Figure 70: INTERNAL DATA MOVE ................................................................................................................ 93

Figure 71: ERASE BLOCK Operation ............................................................................................................... 93

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Important Notes and Warnings

Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,

including without limitation specifications and product descriptions. This document supersedes and replaces all

information supplied prior to the publication hereof. You may not rely on any information set forth in this docu-

ment if you obtain the product described herein from any unauthorized distributor or other source not authorized

by Micron.

Automotive Applications. Products are not designed or intended for use in automotive applications unless specifi-

cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib-

utor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,

costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of

product liability, personal injury, death, or property damage resulting directly or indirectly from any use of non-

automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and con-

ditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron

products are not designed or intended for use in automotive applications unless specifically designated by Micron

as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to in-

demnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'

fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage

resulting from any use of non-automotive-grade products in automotive applications.

Critical Applications. Products are not authorized for use in applications in which failure of the Micron compo-

nent could result, directly or indirectly in death, personal injury, or severe property or environmental damage

("Critical Applications"). Customer must protect against death, personal injury, and severe property and environ-

mental damage by incorporating safety design measures into customer's applications to ensure that failure of the

Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron

component for any critical application, customer and distributor shall indemnify and hold harmless Micron and

its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims,

costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of

product liability, personal injury, or death arising in any way out of such critical application, whether or not Mi-

cron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the

Micron product.

Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems,

applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL-

URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE

WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR

PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included

in customer's applications and products to eliminate the risk that personal injury, death, or severe property or en-

vironmental damages will result from failure of any semiconductor component.

Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential

damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal

or replacement of any products or rework charges) whether or not such damages are based on tort, warranty,

breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly

authorized representative.

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General Description

Micron NAND Flash devices include an asynchronous data interface for high-perform-

ance I/O operations. These devices use a highly multiplexed 8-bit bus (I/Ox) to transfer

commands, address, and data. There are five control signals used to implement the

asynchronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control

hardware write protection and monitor device status (R/B#).

This hardware interface creates a low pin-count device with a standard pinout that re-

mains the same from one density to another, enabling future upgrades to higher densi-

ties with no board redesign.

A target is the unit of memory accessed by a chip enable signal. A target contains one or

more NAND Flash die. A NAND Flash die is the minimum unit that can independently

execute commands and report status. A NAND Flash die, in the ONFI specification, is

referred to as a logical unit (LUN). There is at least one NAND Flash die per chip enable

signal. For further details, see Device and Array Organization.

This device has an internal 4-bit ECC that can be enabled using the GET/SET features.

See Internal ECC and Spare Area Mapping for ECC for more information.

Signal Descriptions and Assignments

Table 1: Asynchronous Signal Definitions

Signal1Type Description2

ALE Input Address latch enable: Loads an address from I/O[7:0] into the address register.

CE# Input Chip enable: Enables or disables one or more die (LUNs) in a target.

CLE Input Command latch enable: Loads a command from I/O[7:0] into the command register.

RE# Input Read enable: Transfers serial data from the NAND Flash to the host system.

WE# Input Write enable: Transfers commands, addresses, and serial data from the host system to the

NAND Flash.

WP# Input Write protect: Enables or disables array PROGRAM and ERASE operations.

I/O[7:0] (x8)

I/O[15:0] (x16)

I/O Data inputs/outputs: The bidirectional I/Os transfer address, data, and command infor-

mation.

R/B# Output Ready/busy: An open-drain, active-low output that requires an external pull-up resistor.

This signal indicates target array activity.

VCC Supply VCC: Core power supply

VSS Supply VSS: Core ground connection

NC – No connect: NCs are not internally connected. They can be driven or left unconnected.

DNU – Do not use: DNUs must be left unconnected.

Notes: 1. See Device and Array Organization for detailed signal connections.

2. See Asynchronous Interface Bus Operation for detailed asynchronous interface signal

descriptions.

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Signal Assignments

Figure 2: 48-Pin TSOP – Type 1, CPL (Top View)

R/B#

RE#

CE#

Vcc

Vss

CLE

ALE

WE#

WP#

x16

R/B#

RE#

CE#

Vcc

Vss

CLE

ALE

WE#

WP#

Vss1

DNU

I/O7

I/O6

I/O5

I/O4

Vcc1

DNU

Vcc

Vss

Vcc1

I/O3

I/O2

I/O1

I/O0

Vss1

x16

Vss

I/O15

I/O14

I/O13

I/O7

I/O6

I/O5

I/O4

I/O12

Vcc

DNU

Vcc

Vss

Vcc

I/O11

I/O3

I/O2

I/O1

I/O0

I/O10

I/O9

I/O8

Vss

Note: 1. These pins might not be bonded in the package; however, Micron recommends that the

customer connect these pins to the designated external sources for ONFI compatibility.

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Figure 3: 63-Ball VFBGA, x8 (Balls Down, Top View)

WP#

VCC1

DNU

VSS

R/B#

DNU

VCC

VCC I/O7

VSS

CLE

I/O3

WE#

VSS1

I/O5

I/O6

CE#

I/O4

ALE

RE#

I/O0

I/O1

I/O2

Note: 1. These pins might not be bonded inthe package; however, Micron recommends that the

customer connect these pins to the designated external sources for ONFI compatibility.

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Figure 4: 63-Ball VFBGA, x16 (Balls Down, Top View)

WP#

Vcc

DNU

I/O8

I/O9

Vss

ALE

RE#

Vcc

I/O0

I/O1

I/O2

R/B#

DNU

Vcc

I/O7

Vss

CLE

I/O10

I/O11

I/O3

WE#

Vss

I/O15

I/O14

I/O5

I/O6

CE#

I/O13

I/O12

Vcc

I/O4

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Package Dimensions

Figure 5: 48-Pin TSOP – Type 1, CPL

1.20 MAX

0.15 +0.03

-0.02

0.27 MAX

0.17 MIN

See detail A

18.40 ±0.08

20.00 ±0.25

Detail A

0.50 ±0.1

0.80

0.10 +0.10

-0.05

0.10

0.25

Gage

plane

0.25

for reference only

0.50 TYP

for reference

only

12.00 ±0.08

Plated lead finish:

100% Sn

Mold compound:

Epoxy novolac

Package width and length

do not include mold

protrusion. Allowable

protrusion is 0.25 per side.

Note: 1. All dimensions are in millimeters.

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Figure 6: 63-Ball VFBGA (HC)

Ball A1 ID

1.0 MAX

13 ±0.1

Ball A1 ID

0.8 TYP

10.5 ±0.1

0.65 ±0.05

Seating

plane

8.8 CTR

7.2 CTR

0.12 A

63X Ø0.45

Solder ball material:

SAC305 (96.5% Sn,

3% Ag, 0.5% Cu).

Dimensions apply to

solder balls post-

reflow on Ø0.4 SMD

ball pads.

0.25 MIN

0.8 TYP

10 9 8 7 6 5 4 3 2 1

Bottom side saw fiducials may or

may not be covered with soldermask.

Note: 1. All dimensions are in millimeters.

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Figure 7: 63-Ball VFBGA (H4) 9mm x 11mm

Ball A1 ID

Seating

plane

0.1 A

1.0 MAX

0.25 MIN

9 ±0.1

Ball A1 ID

(covered by SR)

8.8 CTR

Dimensions apply

to solder balls post-

reflow on Ø0.4 SMD

ball pads.

Solder ball material:

SAC305 (96.5% Sn,

3% Ag, 0.5% Cu). A

10 9 8 7 6 5 4 3 2 1

63X Ø0.45

11 ±0.1

0.8 TYP

7.2 CTR

Note: 1. All dimensions are in millimeters.

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Architecture

These devices use NAND Flash electrical and command interfaces. Data, commands,

and addresses are multiplexed onto the same pins and received by I/O control circuits.

The commands received at the I/O control circuits are latched by a command register

and are transferred to control logic circuits for generating internal signals to control de-

vice operations. The addresses are latched by an address register and sent to a row de-

coder to select a row address, or to a column decoder to select a column address.

Data is transferred to or from the NAND Flash memory array, byte by byte (x8) or word

by word (x16), through a data register and a cache register.

The NAND Flash memory array is programmed and read using page-based operations

and is erased using block-based operations. During normal page operations, the data

and cache registers act as a single register. During cache operations, the data and cache

registers operate independently to increase data throughput. The status register reports

the status of die operations.

Figure 8: NAND Flash Die (LUN) Functional Block Diagram

Address register

Data register

Cache register

Status register

Command register

CE#

VCC VSS

CLE

ALE

WE#

RE#

WP#

I/Ox

Control

logic

I/O

control

R/B#

Row decode

Column decode

NAND Flash

array

ECC

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Device and Array Organization

Figure 9: Array Organization – x8

Cache Register

Data Register

1024 blocks

per device

1 block

642048

2112 bytes

I/O7

I/O0

64 pages = 1 block

(128K + 4K) bytes

1 page = (2K + 64) bytes

1 block = (2K + 64) bytes x 64 pages

= (128K + 4K) bytes

1 device = (2K + 64) bytes x 64 pages

x 1024 blocks

= 1056Mb

Table 2: Array Addressing (x8)

Cycle I/O7 I/O6 I/O5 I/O4 I/OQ3 I/O2 I/O1 I/O0

First CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0

Second LOW LOW LOW LOW CA111CA10 CA9 CA8

Third BA7 BA6 PA5 PA4 PA3 PA2 PA1 PA0

Fourth BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8

Notes: 1. If CA11 is 1, then CA[10:6] must be 0.

2. Block address concatenated with page address = actual page address; CAx = column ad-

dress; PAx = page address; BAx = block address.

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Figure 10: Array Organization – x16

Cache Register

Data Register

1024 blocks

per device

1 block

321024

1056 words

I/O15

I/O0

64 pages = 1 block

(64K + 2K) words

1 page = (1K + 32) words

1 block = (1K + 32) words x 64 pages

= (64K + 2K) words

1 device = (1K + 32) words x 64 pages

x 1024 blocks

= 1056Mb

Table 3: Array Addressing (x16)

Cycle I/O[15:8] I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0

First LOW CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0

Second LOW LOW LOW LOW LOW LOW CA101CA9 CA8

Third LOW BA7 BA6 PA5 PA4 PA3 PA2 PA1 PA0

Fourth LOW BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8

Notes: 1. If CA10 is 1, then CA[9:5] must be 0.

2. Block address concatenated with page address = actual page address. CAx = column ad-

dress; PAx = page address; BAx = block address.

3. I/O[15:8] are not used during the addressing sequence and should be driven LOW.

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Asynchronous Interface Bus Operation

The bus on the device is multiplexed. Data I/O, addresses, and commands all share the

same pins. I/O[15:8] are used only for data in the x16 configuration. Addresses and

commands are always supplied on I/O[7:0].

The command sequence typically consists of a COMMAND LATCH cycle, address input

cycles, and one or more data cycles, either READ or WRITE.

Table 4: Asynchronous Interface Mode Selection

Mode1CE# CLE ALE WE# RE# I/Ox WP#

Standby2H X X X X X 0V/VCC

Command input L H L H X H

Address input L L H H X H

Data input L L L H X H

Data output L L L H X X

Write protect X X X X X X L

Notes: 1. Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW; X = VIH

or VIL.

2. WP# should be biased to CMOS LOW or HIGH for standby.

Asynchronous Enable/Standby

When the device is not performing an operation, the CE# pin is typically driven HIGH

and the device enters standby mode. The memory will enter standby if CE# goes HIGH

while data is being transferred and the device is not busy. This helps reduce power con-

sumption.

The CE# “Don’t Care” operation enables the NAND Flash to reside on the same asyn-

chronous memory bus as other Flash or SRAM devices. Other devices on the memory

bus can then be accessed while the NAND Flash is busy with internal operations. This

capability is important for designs that require multiple NAND Flash devices on the

same bus.

A HIGH CLE signal indicates that a command cycle is taking place. A HIGH ALE signal

signifies that an ADDRESS INPUT cycle is occurring.

Asynchronous Commands

An asynchronous command is written from I/O[7:0] to the command register on the ris-

ing edge of WE# when CE# is LOW, ALE is LOW, CLE is HIGH, and RE# is HIGH.

Commands are typically ignored by die (LUNs) that are busy (RDY = 0); however, some

commands, including READ STATUS (70h), are accepted by die (LUNs) even when they

are busy.

For devices with a x16 interface, I/O[15:8] must be written with zeros when a command

is issued.

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Figure 11: Asynchronous Command Latch Cycle

WE#

CE#

ALE

CLE

I/Ox COMMAND

tWP

tCH

tCS

tALH

tDH

tDS

tALS

tCLH

tCLS

Don’t Care

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Asynchronous Addresses

An asynchronous address is written from I/O[7:0] to the address register on the rising

edge of WE# when CE# is LOW, ALE is HIGH, CLE is LOW, and RE# is HIGH.

Bits that are not part of the address space must be LOW (see Device and Array Organiza-

tion). The number of cycles required for each command varies. Refer to the command

descriptions to determine addressing requirements.

Addresses are input on I/O[7:0] on x8 devices and on I/O[15:0] on x16 devices.

Figure 12: Asynchronous Address Latch Cycle

WE#

CE#

ALE

CLE

I/Ox Col

add 1

tWP tWH

tCS

tDH

tDS

tALS

tALH

tCLS

Col

add 2 Row

add 1 Row

add 2 Row

add 3

Don’t Care Undefined

tWC

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Asynchronous Data Input

Data is written to the cache register of the selected die (LUN) on the rising edge of WE#

when CE# is LOW, ALE is LOW, CLE is LOW, and RE# is HIGH.

Data input is ignored by die (LUNs) that are not selected or are busy (RDY = 0). Data is

written to the data register on the rising edge of WE# when CE#, CLE, and ALE are LOW,

and the device is not busy.

Data is input on I/O[7:0] on x8 devices and on I/O[15:0] on x16 devices.

Figure 13: Asynchronous Data Input Cycles

WE#

CE#

ALE

CLE

I/Ox

tWP tWP tWP

tWH

tALS

tDH

tDS tDH

tDS

tCLH

tCH

DIN M+1 DIN N

Don’t Care

tWC

DIN M

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Asynchronous Data Output

Data can be output from a die (LUN) if it is in a READY state. Data output is supported

following a READ operation from the NAND Flash array. Data is output from the cache

LOW, CLE is LOW, and WE# is HIGH.

If the host controller is using a tRC of 30ns or greater, the host can latch the data on the

rising edge of RE# (see the figure below for proper timing). If the host controller is using

a tRC of less than 30ns, the host can latch the data on the next falling edge of RE#.

Data is output on I/O[7:0] on x8 devices and on I/O[15:0] on x16 devices.

Figure 14: Asynchronous Data Output Cycles

CE#

RE#

I/Ox

tREH

tRP

tRR tRC

tCEA

tREA tREA tREA

Don’t Care

tRHZ

tCHZ

tRHZ

tRHOH

RDY

tCOH

DOUT DOUT DOUT

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Figure 15: Asynchronous Data Output Cycles (EDO Mode)

DOUT DOUT DOUT

CE#

RE#

I/Ox

RDY

tRR

tCEA

tREA

tRP tREH

tRC

tRLOH

tREA

tRHOH

tRHZ

tCOH

tCHZ

Don’t Care

Write Protect#

The write protect# (WP#) signal enables or disables PROGRAM and ERASE operations

to a target. When WP# is LOW, PROGRAM and ERASE operations are disabled. When

WP# is HIGH, PROGRAM and ERASE operations are enabled.

It is recommended that the host drive WP# LOW during power-on until V CC is stable to

prevent inadvertent PROGRAM and ERASE operations (see Device Initialization for ad-

ditional details).

WP# must be transitioned only when the target is not busy and prior to beginning a

command sequence. After a command sequence is complete and the target is ready,

WP# can be transitioned. After WP# is transitioned, the host must wait tWW before issu-

ing a new command.

The WP# signal is always an active input, even when CE# is HIGH. This signal should

not be multiplexed with other signals.

Ready/Busy#

The ready/busy# (R/B#) signal provides a hardware method of indicating whether a tar-

get is ready or busy. A target is busy when one or more of its die (LUNs) are busy

(RDY = 0). A target is ready when all of its die (LUNs) are ready (RDY = 1). Because each

die (LUN) contains a status register, it is possible to determine the independent status

of each die (LUN) by polling its status register instead of using the R/B# signal (see Sta-

tus Operations for details regarding die (LUN) status).

This signal requires a pull-up resistor, Rp, for proper operation. R/B# is HIGH when the

target is ready, and transitions LOW when the target is busy. The signal's open-drain

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driver enables multiple R/B# outputs to be OR-tied. Typically, R/B# is connected to an

interrupt pin on the system controller.

The combination of Rp and capacitive loading of the R/B# circuit determines the rise

time of the R/B# signal. The actual value used for Rp depends on the system timing re-

quirements. Large values of Rp cause R/B# to be delayed significantly. Between the 10%

and 90% points on the R/B# waveform, the rise time is approximately two time con-

stants (TC).

TC = R × C

Where R = Rp (resistance of pull-up resistor), and C = total capacitive load.

The fall time of the R/B# signal is determined mainly by the output impedance of the

R/B# signal and the total load capacitance. Approximate Rp values using a circuit load

of 100pF are provided in Figure 21 (page 28).

The minimum value for Rp is determined by the output drive capability of the R/B# sig-

nal, the output voltage swing, and VCC.

Rp = VCC (MAX) - VOL (MAX)

IOL + ΣIL

Where ΣIL is the sum of the input currents of all devices tied to the R/B# pin.

Figure 16: READ/BUSY# Open Drain

VCC

R/B#

Open drain output

IOL

VSS

Device

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Figure 17: tFall and tRise (3.3V VCC)

3.50

3.00

2.50

2.00

1.50

1.00

0.50

0.00

–1 0 2 4 0 2 4 6

tFall tRise

VCC 3.3V

Notes: 1. tFall and tRise calculated at 10% and 90% points.

2. tRise dependent on external capacitance and resistive loading and output transistor im-

pedance.

3. tRise primarily dependent on external pull-up resistor and external capacitive loading.

4. tFall = 10ns at 3.3V.

5. See TC values in Figure 21 (page 28) for approximate Rp value and TC.

Figure 18: tFall and tRise (1.8V VCC)

3.50

3.00

2.50

2.00

1.50

1.00

0.50

0.00

-1 0 2 4 0 2 4 6

tFall tRise

VCC1.8V

Notes: 1. tFall and tRise are calculated at 10% and 90% points.

2. tRise is primarily dependent on external pull-up resistor and external capacitive loading.

3. tFall ≈ 7ns at 1.8V.

4. See TC values in Figure 21 (page 28) for TC and approximate Rp value.

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Figure 19: IOL vs. Rp (VCC = 3.3V VCC)

3.50

3.00

2.50

2.00

1.50

1.00

0.50

0.00

0 2000 4000 6000 8000 10,000 12,000

IOL at VCC (MAX)

Rp (Ω)

I (mA)

Figure 20: IOL vs. Rp (1.8V VCC)

3.50

3.00

2.50

2.00

1.50

1.00

0.50

0.00

0 2000 4000 6000 8000 10,000 12,000

Rp (Ω)

I (mA)

IOL at VCC (MAX)

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Figure 21: TC vs. Rp

1200

1000

800

600

400

200

0 2000 4000 6000 8000 10,000 12,000

IOL at VCC (MAX)

RC = TC

C = 100pF

Rp (W)

TC (ns)

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Device Initialization

Micron NAND Flash devices are designed to prevent data corruption during power

transitions. VCC is internally monitored. (The WP# signal supports additional hardware

protection during power transitions.) When ramping V CC, use the following procedure

to initialize the device:

1. Ramp VCC.

2. The host must wait for R/B# to be valid and HIGH before issuing RESET (FFh) to

any target. The R/B# signal becomes valid when 50µs has elapsed since the begin-

ning the VCC ramp, and 10µs has elapsed since VCC reaches VCC,min.

3. If not monitoring R/B#, the host must wait at least 100µs after VCC reaches VCC,min.

If monitoring R/B#, the host must wait until R/B# is HIGH.

4. The asynchronous interface is active by default for each target. Each LUN draws

less than an average of 10mA (IST) measured over intervals of 1ms until the RESET

(FFh) command is issued.

5. The RESET (FFh) command must be the first command issued to all targets (CE#s)

after the NAND Flash device is powered on. Each target will be busy for 1ms after a

RESET command is issued. The RESET busy time can be monitored by polling

R/B# or issuing the READ STATUS (70h) command to poll the status register.

6. The device is now initialized and ready for normal operation.

Figure 22: R/B# Power-On Behavior

Reset (FFh)

is issued

50µs (MIN)

100µs (MAX)

Invalid

10µs

(MAX)

VCC ramp

starts

VCC

R/B#

VCC = VCC (MIN)

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Command Definitions

Table 5: Command Set

Command

Cycle #1

Number of

Valid

Address

Cycles

Data

Input

Cycles

Command

Cycle #2

Valid While

Selected LUN is

Busy1Notes

Reset Operations

RESET FFh 0 – – Yes

Identification Operation

READ ID 90h 1 – – No

READ PARAMETER PAGE ECh 1 – – No

READ UNIQUE ID EDh 1 – – No

Feature Operations

GET FEATURES EEh 1 – – No

SET FEATURES EFh 1 4 – No

Status Operations

READ STATUS 70h 0 – – Yes

Column Address Operations

RANDOM DATA READ 05h 2 – E0h No

RANDOM DATA INPUT 85h 2 Optional – No

PROGRAM FOR

INTERNAL DATA MOVE

85h 4 Optional – No 2

READ OPERATIONS

READ MODE 00h 0 – – No

READ PAGE 00h 4 – 30h No

READ PAGE CACHE SEQUEN-

TIAL

31h 0 – – No 3, 4

READ PAGE CACHE

RANDOM

00h 4 – 31h No 3, 4

READ PAGE CACHE LAST 3Fh 0 – – No 3, 4

Program Operations

PROGRAM PAGE 80h 4 Yes 10h No

PROGRAM PAGE CACHE 80h 4 Yes 15h No 3, 5

Erase Operations

ERASE BLOCK 60h 3 – D0h No

Internal Data Move Operations

READ FOR INTERNAL

DATA MOVE

00h 4 – 35h No 2

PROGRAM FOR INTERNAL

DATA MOVE

85h Optional 10h No

One-Time Programmable (OTP) Operations

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Table 5: Command Set (Continued)

Command

Cycle #1

Number of

Valid

Address

Cycles

Data

Input

Cycles

Command

Cycle #2

Valid While

Selected LUN is

Busy1Notes

OTP DATA LOCK BY PAGE

(ONFI)

80h 4 No 10h No 6

OTP DATA PROGRAM (ONFI) 80h 4 Yes 10h No 6

OTP DATA READ (ONFI) 00h 4 No 30h No 6

Notes: 1. Busy means RDY = 0.

2. Do not cross plane address boundaries when using READ for INTERNAL DATA MOVE and

PROGRAM for INTERNAL DATA MOVE.

3. These commands supported only with ECC disabled.

4. Issuing a READ PAGE CACHE series (31h, 00h-31h, 3Fh) command when the array is busy

(RDY = 1, ARDY = 0) is supported if the previous command was a READ PAGE (00h-30h)

or READ PAGE CACHE series command; otherwise, it is prohibited.

5. Issuing a PROGRAM PAGE CACHE (80h-15h) command when the array is busy (RDY = 1,

ARDY = 0) is supported if the previous command was a PROGRAM PAGE CACHE

(80h-15h) command; otherwise, it is prohibited.

6. OTP commands can be entered only after issuing the SET FEATURES command with the

feature address.

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Reset Operations

RESET (FFh)

The RESET command is used to put the memory device into a known condition and to

abort the command sequence in progress.

READ, PROGRAM, and ERASE commands can be aborted while the device is in the busy

state. The contents of the memory location being programmed or the block being

erased are no longer valid. The data may be partially erased or programmed, and is in-

valid. The command register is cleared and is ready for the next command. The data

The status register contains the value E0h when WP# is HIGH; otherwise it is written

with a 60h value. R/B# goes LOW for tRST after the RESET command is written to the

command register.

The RESET command must be issued to all CE#s as the first command after power-on.

The device will be busy for a maximum of 1ms.

Figure 23: RESET (FFh) Operation

Cycle type

I/O[7:0]

R/B#

tRST

tWB

Command

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Identification Operations

READ ID (90h)

The READ ID (90h) command is used to read identifier codes programmed into the tar-

get. This command is accepted by the target only when all die (LUNs) on the target are

idle.

Writing 90h to the command register puts the target in read ID mode. The target stays in

this mode until another valid command is issued.

When the 90h command is followed by an 00h address cycle, the target returns a 5-byte

identifier code that includes the manufacturer ID, device configuration, and part-spe-

cific information.

When the 90h command is followed by a 20h address cycle, the target returns the 4-byte

ONFI identifier code.

Figure 24: READ ID (90h) with 00h Address Operation

Cycle type

I/O[7:0]

tWHR

Command

90h 00h Byte 0 Byte 1 Byte 2 Byte 3

Address DOUT DOUT DOUT DOUT DOUT

Byte 4

Note: 1. See READ ID Parameter tables for byte definitions.

Figure 25: READ ID (90h) with 20h Address Operation

Cycle type

I/O[7:0]

tWHR

Command

90h 20h 4Fh 4Eh 46h 49h

Address DOUT DOUT DOUT DOUT

Note: 1. See READ ID Parameter tables for byte definitions.

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READ ID Parameter Tables

Table 6: READ ID Parameters for Address 00h

b = binary; h = hexadecimal

Options I/07 I/06 I/05 I/04 I/03 I/02 I/01 I/00 Value

Byte 0 – Manufacturer ID

Manufacturer Micron 0 0 1 0 1 1 0 0 2Ch

Byte 1 – Device ID

MT29F1G08ABADA 1Gb, x8, 3.3V 1 1 1 1 0 0 0 1 F1h

MT29F1G08ABBDA 1Gb, x8, 1.8V 1 0 1 0 0 0 0 1 A1h

MT29F1G16ABBDA 1Gb, x16, 1.8V 1 0 1 1 0 0 0 1 B1h

Byte 2

Number of die per CE 1 0 0 00b

Cell type SLC 0 0 00b

Number of simultaneously

programmed pages

1 0 0 00b

Interleaved operations be-

tween multiple die

Not supported 0 0b

Cache programming Supported 1 1b

Byte value MT29F1G08ABADA 1 0 0 0 0 0 0 0 80h

MT29F1G08ABBDA 1 0 0 0 0 0 0 0 80h

MT29F1G16ABBDA 1 0 0 0 0 0 0 0 80h

Byte 3

Page size 2KB 0 1 01b

Spare area size (bytes) 64B 1 1b

Block size (without spare) 128KB 0 1 01b

Organization x8 0 0b

x16 1 1b

Serial access

(MIN)

1.8V 25ns 0 0 0xxx0b

3.3V 20ns 1 0 1xxx0b

Byte value MT29F1G08ABADA 1 0 0 1 0 1 0 1 95h

MT29F1G08ABBDA 0 0 0 1 0 1 0 1 15h

MT29F1G16ABBDA 0 1 0 1 0 1 0 1 55h

Byte 4

Internal ECC level 4-bit ECC/512 (main) +

4 (spare) + 8 (parity)

bytes

1 0 10b

Planes per CE# 1 0 0 00b

Plane size 1Gb 0 0 0 000b

Internal ECC ECC disabled 0 0b

ECC enabled 1 1b

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Table 6: READ ID Parameters for Address 00h (Continued)

b = binary; h = hexadecimal

Options I/07 I/06 I/05 I/04 I/03 I/02 I/01 I/00 Value

Byte value MT29F1G08ABADA 0 0 0 0 0 0 1 0 02h

MT29F1G08ABBDA 0 0 0 0 0 0 1 0 02h

MT29F1G16ABBDA 0 0 0 0 0 0 1 0 02h

Table 7: READ ID Parameters for Address 20h

h = hexadecimal

Byte Options I/07 I/06 I/05 I/04 I/03 I/02 I/01 I/00 Value

0 “O” 0 1 0 0 1 1 1 1 4Fh

1 “N” 0 1 0 0 1 1 1 0 4Eh

2 “F” 0 1 0 0 0 1 1 0 46h

3 “I” 0 1 0 0 1 0 0 1 49h

4 Undefined X X X X X X X X XXh

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READ PARAMETER PAGE (ECh)

The READ PARAMETER PAGE (ECh) command is used to read the ONFI parameter page

programmed into the target. This command is accepted by the target only when all die

(LUNs) on the target are idle.

Writing ECh to the command register puts the target in read parameter page mode. The

target stays in this mode until another valid command is issued.

When the ECh command is followed by an 00h address cycle, the target goes busy for tR.

If the READ STATUS (70h) command is used to monitor for command completion, the

READ MODE (00h) command must be used to re-enable data output mode.

To insure data integrity, x8 devices contain at least eight copies of the parameter page,

and x16 devices contain at least four copies of the parameter page. Each parameter

page is 256 bytes. If the initial READ PARAMETER PAGE (ECh) command fails to retrieve

a correct copy of the parameter page, the command can be reissued until a correct copy

is retrieved. If desired, the RANDOM DATA READ (05h-E0h) command can be used to

change the location of data output.

Figure 26: READ PARAMETER (ECh) Operation

Cycle type

I/O[7:0]

R/B#

tWB tRtRR

Command Address DOUT

ECh 00h P00P10

DOUT DOUT

… P01

DOUT DOUT

P11…

DOUT

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Parameter Page Data Structure Tables

Table 8: Parameter Page Data Structure

h = hexadecimal

Byte Description Value

0–3 Parameter page signature 4Fh, 4Eh, 46h, 49h

4–5 Revision number 02h, 00h

6–7 Features supported MT29F1G08ABADA3W 10h, 00h

MT29F1G08ABBDA3W 10h, 00h

MT29F1G16ABBDA3W 11h, 00h

MT29F1G08ABADAWP 10h, 00h

MT29F1G08ABBDAHC 10h, 00h

MT29F1G16ABBDAHC 11h, 00h

MT29F1G08ABBDAH4 10h, 00h

MT29F1G16ABBDAH4 11h, 00h

MT29F1G08ABADAH4 10h, 00h

8–9 Optional commands supported 3Fh, 00h

10–31 Reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,

00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,

00h, 00h

32–43 Device manufacturer 4Dh, 49h, 43h, 52h, 4Fh, 4Eh, 20h, 20h, 20h, 20h,

20h, 20h

44–63 Device model MT29F1G08ABADA3W 4Dh, 54h, 32h, 39h, 46h, 31h, 47h, 30h, 38h, 41h,

42h, 41h, 44h, 41h, 33h, 57h, 20h, 20h, 20h, 20h

MT29F1G08ABBDA3W 4Dh, 54h, 32h, 39h, 46h, 31h, 47h, 30h, 38h, 41h,

42h, 42h, 44h, 41h, 33h, 57h, 20h, 20h, 20h, 20h

MT29F1G16ABBDA3W 4Dh, 54h, 32h, 39h, 46h, 31h, 47h, 31h, 36h, 41h,

42h, 42h, 44h, 41h, 33h, 57h, 20h, 20h, 20h, 20h

MT29F1G08ABADAWP 4Dh, 54h, 32h, 39h, 46h, 31h, 47h, 30h, 38h, 41h,

42h, 41h, 44h, 41h, 57h, 50h, 20h, 20h, 20h, 20h

MT29F1G08ABBDAHC 4Dh, 54h, 32h, 39h, 46h, 31h, 47h, 30h, 38h, 41h,

42h, 42h, 44h, 41h, 48h, 43h, 20h, 20h, 20h, 20h

MT29F1G16ABBDAHC 4Dh, 54h, 32h, 39h, 46h, 31h, 47h, 31h, 36h, 41h,

42h, 42h, 44h, 41h, 48h, 43h, 20h, 20h, 20h, 20h

MT29F1G08ABBDAH4 4Dh, 54h, 32h, 39h, 46h, 31h, 47h, 30h, 38h, 41h,

42h, 42h, 44h, 41h, 48h, 34h, 20h, 20h, 20h, 20h

MT29F1G16ABBDAH4 4Dh, 54h, 32h, 39h, 46h, 31h, 47h, 31h, 36h, 41h,

42h, 42h, 44h, 41h, 48h, 34h, 20h, 20h, 20h, 20h

MT29F1G08ABADAH4 4Dh, 54h, 32h, 39h, 46h, 31h, 47h, 30h, 38h, 41h,

42h, 41h, 44h, 41h, 48h, 34h, 20h, 20h, 20h, 20h

64 Manufacturer ID 2Ch

65–66 Date code 00h, 00h

67–79 Reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,

00h, 00h, 00h

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Table 8: Parameter Page Data Structure (Continued)

h = hexadecimal

Byte Description Value

80–83 Number of data bytes per page 00h, 08h, 00h, 00h

84–85 Number of spare bytes per page 40h, 00h

86–89 Number of data bytes per partial page 00h, 02h, 00h, 00h

90–91 Number of spare bytes per partial page 10h, 00h

92–95 Number of pages per block 40h, 00h, 00h, 00h

96–99 Number of blocks per unit 00h, 04h, 00h, 00h

100 Number of logical units 01h

101 Number of address cycles 22h

102 Number of bits per cell 01h

103–104 Bad blocks maximum per unit 14h, 00h

105–106 Block endurance 01h, 05h

107 Guaranteed valid blocks at beginning of target 01h

108–109 Block endurance for guaranteed valid blocks 00h, 00h

110 Number of programs per page 04h

111 Partial programming attributes 00h

112 Number of bits ECC bits 04h

113 Number of interleaved address bits 00h

114 Interleaved operation attributes 00h

115–127 Reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,

00h, 00h, 00h

128 I/O pin capacitance 0Ah

129–130 Timing mode support MT29F1G08ABADA3W 3Fh, 00h

MT29F1G08ABBDA3W 1Fh, 00h

MT29F1G16ABBDA3W 1Fh, 00h

MT29F1G08ABADAWP 3Fh, 00h

MT29F1G08ABBDAHC 1Fh, 00h

MT29F1G16ABBDAHC 1Fh, 00h

MT29F1G08ABBDAH4 1Fh, 00h

MT29F1G16ABBDAH4 1Fh, 00h

MT29F1G08ABADAH4 3Fh, 00h

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Table 8: Parameter Page Data Structure (Continued)

h = hexadecimal

Byte Description Value

131–132 Program cache timing

mode support

MT29F1G08ABADA3W 3Fh, 00h

MT29F1G08ABBDA3W 1Fh, 00h

MT29F1G16ABBDA3W 1Fh, 00h

MT29F1G08ABADAWP 3Fh, 00h

MT29F1G08ABBDAHC 1Fh, 00h

MT29F1G16ABBDAHC 1Fh, 00h

MT29F1G08ABBDAH4 1Fh, 00h

MT29F1G16ABBDAH4 1Fh, 00h

MT29F1G08ABADAH4 3Fh, 00h

133–134 tPROG (MAX) page program time 58h, 02h

135–136 tBERS (MAX) block erase time B8h, 0Bh

137–138 tR (MAX) page read time 19h, 00h

139–140 tCCS (MIN) 64h, 00h

141–163 Reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,

00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,

00h, 00h, 00h

164–165 Vendor-specific revision number 01h, 00h

166–253 Vendor-specific 01h, 00h, 00h, 02h, 04h, 80h, 01h, 81h, 04h, 01h,

02h, 01h,0Ah, 00h, 00h, 00h, 00h, 00h, 00h, 00h,

00h, 00h, 00h, 00h,00h, 00h, 00h, 00h, 00h, 00h,

00h, 00h, 00h, 00h, 00h, 00h,00h, 00h, 00h, 00h,

00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,00h, 00h,

00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,

00h, 00h,00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,

00h, 00h, 00h, 00h,00h, 00h, 00h, 00h

254–255 Integrity CRC Set at test

256–511 Value of bytes 0–255

512–767 Value of bytes 0–255

768+ Additional redundant parameter pages

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READ UNIQUE ID (EDh)

The READ UNIQUE ID (EDh) command is used to read a unique identifier programmed

into the target. This command is accepted by the target only when all die (LUNs) on the

target are idle.

Writing EDh to the command register puts the target in read unique ID mode. The tar-

get stays in this mode until another valid command is issued.

When the EDh command is followed by an 00h address cycle, the target goes busy for

tR. If the READ STATUS (70h) command is used to monitor for command completion,

the READ MODE (00h) command must be used to re-enable data output mode.

After tR completes, the host enables data output mode to read the unique ID. When the

asynchronous interface is active, one data byte is output per RE# toggle.

Sixteen copies of the unique ID data are stored in the device. Each copy is 32 bytes. The

first 16 bytes of a 32-byte copy are unique data, and the second 16 bytes are the comple-

ment of the first 16 bytes. The host should XOR the first 16 bytes with the second 16

bytes. If the result is 16 bytes of FFh, then that copy of the unique ID data is correct. In

the event that a non-FFh result is returned, the host can repeat the XOR operation on a

subsequent copy of the unique ID data. If desired, the RANDOM DATA READ (05h-E0h)

command can be used to change the data output location.

The upper eight I/Os on a x16 device are not used and are a “Don’t Care” for x16 devi-

ces.

Figure 27: READ UNIQUE ID (EDh) Operation

Cycle type

I/O[7:0]

R/B#

tWB tRtRR

Command Address DOUT

EDh 00h U00U10

DOUT DOUT

… U01

DOUT DOUT

U11…

DOUT

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Feature Operations

The SET FEATURES (EFh) and GET FEATURES (EEh) commands are used to modify the

target's default power-on behavior. These commands use a one-byte feature address to

determine which subfeature parameters will be read or modified. Each feature address

(in the 00h to FFh range) is defined in below. The SET FEATURES (EFh) command

writes subfeature parameters (P1–P4) to the specified feature address. The GET FEA-

TURES command reads the subfeature parameters (P1–P4) at the specified feature ad-

dress.

When a feature is set, by default it remains active until the device is power cycled. It is

volatile. Unless otherwise specified in the features table, once a device is set it remains

set, even if a RESET (FFh) command is issued. GET/SET FEATURES commands can be

used after required RESET to enable features before system BOOT ROM process.

Internal ECC can be enabled/disabled using SET FEATURES (EFh). The SET FEATURES

command (EFh), followed by address 90h, followed by four data bytes (only the first da-

ta byte is used) will enable/disable internal ECC.

The sequence to enable internal ECC with SET FEATURES is EFh(cmd)-90h(addr)-

08h(data)-00h(data)-00h(data)-00h(data)-wait(tFEAT).

The sequence to disable internal ECC with SET FEATURES is EFh(cmd)-90h(addr)-

00h(data)-00h(data)-00h(data)-00h(data)-wait(tFEAT). The GET FEATURES command

is EEh.

Table 9: Feature Address Definitions

Feature Address Definition

00h Reserved

01h Timing mode

02h–7Fh Reserved

80h Programmable output drive strength

81h Programmable RB# pull-down strength

82h–FFh Reserved

90h Array operation mode

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Table 10: Feature Address 90h – Array Operation Mode

Subfeature

Parameter Options 1/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Value Notes

Operation

mode option

Normal Reserved (0) 0 00h 1

OTP

operation

Reserved (0) 1 01h

OTP

protection

Reserved (0) 1 1 03h

Disable ECC Reserved (0) 0 0 0 0 00h 1

Enable ECC Reserved (0) 1 0 0 0 08h 1

Reserved Reserved (0) 00h

Note: 1. These bits are reset to 00h on power cycle.

SET FEATURES (EFh)

The SET FEATURES (EFh) command writes the subfeature parameters (P1–P4) to the

specified feature address to enable or disable target-specific features. This command is

accepted by the target only when all die (LUNs) on the target are idle.

Writing EFh to the command register puts the target in the set features mode. The target

stays in this mode until another command is issued.

The EFh command is followed by a valid feature address. The host waits for tADL before

the subfeature parameters are input. When the asynchronous interface is active, one

subfeature parameter is latched per rising edge of WE#.

After all four subfeature parameters are input, the target goes busy for tFEAT. The READ

STATUS (70h) command can be used to monitor for command completion.

Feature address 01h (timing mode) operation is unique. If SET FEATURES is used to

modify the interface type, the target will be busy for tITC.

Figure 28: SET FEATURES (EFh) Operation

Cycle type

I/O[7:0]

R/B#

tADL

Command Address

EFh FA

DIN DIN DIN DIN

P1 P2 P3 P4

tWB tFEAT

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GET FEATURES (EEh)

The GET FEATURES (EEh) command reads the subfeature parameters (P1–P4) from the

specified feature address. This command is accepted by the target only when all die

(LUNs) on the target are idle.

Writing EEh to the command register puts the target in get features mode. The target

stays in this mode until another valid command is issued.

When the EEh command is followed by a feature address, the target goes busy for tFEAT.

If the READ STATUS (70h) command is used to monitor for command completion, the

READ MODE (00h) command must be used to re-enable data output mode.

After tFEAT completes, the host enables data output mode to read the subfeature pa-

rameters.

Figure 29: GET FEATURES (EEh) Operation

Cycle type

I/Ox

R/B#

tWB tFEAT tRR

Command Address DOUT

EEh FA P1 P2

DOUT DOUT

P3 P4

DOUT

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Table 11: Feature Addresses 01h: Timing Mode

Subfeature

Parameter Options I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Value Notes

Timing mode Mode 0

(default)

Reserved (0) 0 0 0 00h 1, 2

Mode 1 Reserved (0) 0 0 1 01h 2

Mode 2 Reserved (0) 0 1 0 02h 2

Mode 3 Reserved (0) 0 1 1 03h 3

Mode 4 Reserved (0) 1 0 0 04h 3

Mode 5 Reserved (0) 1 0 1 05h 3

Reserved (0) 00h

Notes: 1. The timing mode feature address is used to change the default timing mode. The timing

mode should be selected to indicate the maximum speed at which the device will re-

ceive commands, addresses, and data cycles. The five supported settings for the timing

mode are shown. The default timing mode is mode 0. The device returns to mode 0

when the device is power cycled. Supported timing modes are reported in the parame-

ter page.

2. Supported for both 1.8V and 3.3V.

3. Supported for 3.3V only.

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Table 12: Feature Addresses 80h: Programmable I/O Drive Strength

Subfeature

Parameter Options I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Value Notes

I/O drive strength Full (default) Reserved (0) 0 0 00h 1

Three-quarters Reserved (0) 0 1 01h

One-half Reserved (0) 1 0 02h

One-quarter Reserved (0) 1 1 03h

Reserved (0) 00h

Note: 1. The programmable drive strength feature address is used to change the default I/O

drive strength. Drive strength should be selected based on expected loading of the

memory bus. This table shows the four supported output drive strength settings. The

default drive strength is full strength. The device returns to the default drive strength

mode when the device is power cycled. AC timing parameters may need to be relaxed if

I/O drive strength is not set to full.

Table 13: Feature Addresses 81h: Programmable R/B# Pull-Down Strength

Subfeature

Parameter Options I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Value Notes

R/B# pull-down

strength

Full (default) 0 0 00h 1

Three-quarters 0 1 01h

One-half 1 0 02h

One-quarter 1 1 03h

Reserved (0) 00h

Note: 1. This feature address is used to change the default R/B# pull-down strength. Its strength

should be selected based on the expected loading of R/B#. Full strength is the default,

power-on value.

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Status Operations

Each die (LUN) provides its status independently of other die (LUNs) on the same target

through its 8-bit status register.

After the READ STATUS (70h) command is issued, status register output is enabled. The

contents of the status register are returned on I/O[7:0] for each data output request.

When the asynchronous interface is active and status register output is enabled,

changes in the status register are seen on I/O[7:0] as long as CE# and RE# are LOW; it is

not necessary to toggle RE# to see the status register update.

While monitoring the status register to determine when a data transfer from the Flash

array to the data register (tR) is complete, the host must issue the READ MODE (00h)

command to disable the status register and enable data output (see Read Operations).

With internal ECC enabled, a READ STATUS command is required after completion of

the data transfer (tR_ECC) to determine whether an uncorrectable read error occurred.

Table 14: Status Register Definition

SR Bit Program Page

Program Page

Cache Mode Page Read

Page Read

Cache Mode Block Erase Description

7 Write protect Write protect Write protect Write protect Write protect 0 = Protected

1 = Not protected

6 RDY RDY1 cache RDY RDY1 cache RDY 0 = Busy

1 = Ready

5 ARDY ARDY2ARDY ARDY2ARDY Don't Care

4 – – – – – Don't Care

3 – – Rewrite

recommended3

– – 0 = Normal or uncorrecta-

ble

1 = Rewrite recommended

2 – – – – – Don't Care

1 FAILC (N - 1) FAILC (N - 1) Reserved – – Don't Care

0 FAIL FAIL (N) FAIL4– FAIL 0 = Successful PROGRAM/

ERASE/READ

1 = Error in PROGRAM/

ERASE

READ

Notes: 1. Status register bit 6 is 1 when the cache is ready to accept new data. R/B# follows bit 6.

2. Status register bit 5 is 0 during the actual programming operation. If cache mode is

used, this bit will be 1 when all internal operations are complete.

3. A status register bit defined as Rewrite Recommended signifies that the page includes

acertain number of READ errors per sector (512B (main) + 4B (spare) + 8B (parity). A re-

writeof this page is recommended. (Up to a 4-bit error has been corrected if internal

ECC was enabled.)

4. A status register bit defined as FAIL signifies that an uncorrectable READ error has oc-

curred.

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READ STATUS (70h)

The READ STATUS (70h) command returns the status of the last-selected die (LUN) on

a target. This command is accepted by the last-selected die (LUN) even when it is busy

(RDY = 0).

If there is only one die (LUN) per target, the READ STATUS (70h) command can be used

to return status following any NAND command.

Figure 30: READ STATUS (70h) Operation

Cycle type

I/O[7:0]

tWHR

Command DOUT

70h SR

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Column Address Operations

The column address operations affect how data is input to and output from the cache

registers within the selected die (LUNs). These features provide host flexibility for man-

aging data, especially when the host internal buffer is smaller than the number of data

bytes or words in the cache register.

When the asynchronous interface is active, column address operations can address any

byte in the selected cache register.

RANDOM DATA READ (05h-E0h)

The RANDOM DATA READ (05h-E0h) command changes the column address of the se-

lected cache register and enables data output from the last selected die (LUN). This

command is accepted by the selected die (LUN) when it is ready (RDY = 1; ARDY = 1). It

is also accepted by the selected die (LUN) during CACHE READ operations

(RDY = 1; ARDY = 0).

Writing 05h to the command register, followed by two column address cycles containing

the column address, followed by the E0h command, puts the selected die (LUN) into

data output mode. After the E0h command cycle is issued, the host must wait at least

tWHR before requesting data output. The selected die (LUN) stays in data output mode

until another valid command is issued.

Figure 31: RANDOM DATA READ (05h-E0h) Operation

Cycle type

I/O[7:0]

SR[6]

Command Address Address

05h

Command

E0hC1 C2

tWHR

tRHW

DOUT

Dk + 1

DOUT

Dk + 2

DOUT

Dn + 1

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RANDOM DATA INPUT (85h)

The RANDOM DATA INPUT (85h) command changes the column address of the selec-

ted cache register and enables data input on the last-selected die (LUN). This command

is accepted by the selected die (LUN) when it is ready (RDY = 1; ARDY = 1). It is also ac-

cepted by the selected die (LUN) during cache program operations

(RDY = 1; ARDY = 0).

Writing 85h to the command register, followed by two column address cycles containing

the column address, puts the selected die (LUN) into data input mode. After the second

address cycle is issued, the host must wait at least tADL before inputting data. The se-

lected die (LUN) stays in data input mode until another valid command is issued.

Though data input mode is enabled, data input from the host is optional. Data input

begins at the column address specified.

The RANDOM DATA INPUT (85h) command is allowed after the required address cycles

are specified, but prior to the final command cycle (10h, 11h, 15h) of the following com-

mands while data input is permitted: PROGRAM PAGE (80h-10h), PROGRAM PAGE

CACHE (80h-15h),and PROGRAM FOR INTERNAL DATA MOVE (85h-10h).

Figure 32: RANDOM DATA INPUT (85h) Operation

Cycle type

I/O[7:0]

RDY

Command Address Address

85h C1 C2

tADL

DIN

Dk + 1

DIN

Dk + 2

DIN

Dn + 1

As defined for PAGE

(CACHE) PROGRAM

As defined for PAGE

(CACHE) PROGRAM

PROGRAM FOR INTERNAL DATA INPUT (85h)

The PROGRAM FOR INTERNAL DATA INPUT (85h) command changes the row address

(block and page) where the cache register contents will be programmed in the NAND

Flash array. It also changes the column address of the selected cache register and ena-

bles data input on the specified die (LUN). This command is accepted by the selected

die (LUN) when it is ready (RDY = 1; ARDY = 1). It is also accepted by the selected die

(LUN) during cache programming operations (RDY = 1; ARDY = 0).

Write 85h to the command register. Then write two column address cycles and three

row address cycles. This updates the page and block destination of the selected device

for the addressed LUN and puts the cache register into data input mode. After the fifth

address cycle is issued the host must wait at least tADL before inputting data. The selec-

ted LUN stays in data input mode until another valid command is issued. Though data

input mode is enabled, data input from the host is optional. Data input begins at the

column address specified.

The PROGRAM FOR INTERNAL DATA INPUT (85h) command is allowed after the re-

quired address cycles are specified, but prior to the final command cycle (10h, 11h, 15h)

of the following commands while data input is permitted: PROGRAM PAGE (80h-10h),

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PROGRAM PAGE CACHE (80h-15h), and PROGRAM FOR INTERNAL DATA MOVE

(85h-10h). When used with these commands, the LUN address and plane select bits are

required to be identical to the LUN address and plane select bits originally specified.

The PROGRAM FOR INTERNAL DATA INPUT (85h) command enables the host to mod-

ify the original page and block address for the data in the cache register to a new page

and block address.

In devices that have more than one die (LUN) per target, the PROGRAM FOR INTERNAL

DATA INPUT (85h) command can be used with other commands that support inter-

leaved die (multi-LUN) operations.

The PROGRAM FOR INTERNAL DATA INPUT (85h) command can be used with the

RANDOM DATA READ (05h-E0h) command to read and modify cache register contents

in small sections prior to programming cache register contents to the NAND Flash ar-

ray. This capability can reduce the amount of buffer memory used in the host controller.

The RANDOM DATA INPUT (85h) command can be used during the PROGRAM FOR

INTERNAL DATA MOVE command sequence to modify one or more bytes of the origi-

nal data. First, data is copied into the cache register using the 00h-35h command se-

quence, then the RANDOM DATA INPUT (85h) command is written along with the ad-

dress of the data to be modified next. New data is input on the external data pins. This

copies the new data into the cache register.

Figure 33: PROGRAM FOR INTERNAL DATA INPUT (85h) Operation

Cycle type

I/O[7:0]

RDY

Command Address Address Address Address

85h C1 C2

tADL

DIN

Dk + 1

DIN

Dk + 2

Din

Dn + 1

As defined for PAGE

(CACHE) PROGRAM

As defined for PAGE

(CACHE) PROGRAM

R1 R2

Command

10h

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Read Operations

The READ PAGE (00h-30h) command, when issued by itself, reads one page from the

NAND Flash array to its cache register and enables data output for that cache register.

During data output the following commands can be used to read and modify the data in

the cache registers: RANDOM DATA READ (05h-E0h) and RANDOM DATA INPUT (85h).

Read Cache Operations

To increase data throughput, the READ PAGE CACHE series (31h, 00h-31h) commands

can be used to output data from the cache register while concurrently copying a page

from the NAND Flash array to the data register.

To begin a read page cache sequence, begin by reading a page from the NAND Flash ar-

ray to its corresponding cache register using the READ PAGE (00h-30h) command.

R/B# goes LOW during tR and the selected die (LUN) is busy (RDY = 0, ARDY = 0). After

tR (R/B# is HIGH and RDY = 1, ARDY = 1), issue either of these commands:

• READ PAGE CACHE SEQUENTIAL (31h) – copies the next sequential page from the

NAND Flash array to the data register

• READ PAGE CACHE RANDOM (00h-31h) – copies the page specified in this command

from the NAND Flash array to its corresponding data register

After the READ PAGE CACHE series (31h, 00h-31h) command has been issued, R/B#

goes LOW on the target, and RDY = 0 and ARDY = 0 on the die (LUN) for tRCBSY while

the next page begins copying data from the array to the data register. After tRCBSY,

R/B# goes HIGH and the die’s (LUN’s) status register bits indicate the device is busy

with a cache operation (RDY = 1, ARDY = 0). The cache register becomes available and

the page requested in the READ PAGE CACHE operation is transferred to the data regis-

ter. At this point, data can be output from the cache register, beginning at column ad-

dress 0. The RANDOM DATA READ (05h-E0h) command can be used to change the col-

umn address of the data output by the die (LUN).

After outputting the desired number of bytes from the cache register, either an addi-

tional READ PAGE CACHE series (31h, 00h-31h) operation can be started or the READ

PAGE CACHE LAST (3Fh) command can be issued.

If the READ PAGE CACHE LAST (3Fh) command is issued, R/B# goes LOW on the target,

and RDY = 0 and ARDY = 0 on the die (LUN) for tRCBSY while the data register is copied

into the cache register. After tRCBSY, R/B# goes HIGH and RDY = 1 and

ARDY = 1, indicating that the cache register is available and that the die (LUN) is ready.

Data can then be output from the cache register, beginning at column address 0. The

RANDOM DATA READ (05h-E0h) command can be used to change the column address

of the data being output.

For READ PAGE CACHE series (31h, 00h-31h, 3Fh), during the die (LUN) busy time,

tRCBSY, when RDY = 0 and ARDY = 0, the only valid commands are status operations

(70h) and RESET (FFh). When RDY = 1 and ARDY = 0, the only valid commands during

READ PAGE CACHE series (31h, 00h-31h) operations are status operations (70h), READ

MODE (00h), READ PAGE CACHE series (31h, 00h-31h), RANDOM DATA READ (05h-

E0h), and RESET (FFh).

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READ MODE (00h)

The READ MODE (00h) command disables status output and enables data output for

the last-selected die (LUN) and cache register after a READ operation (00h-30h,

00h-3Ah, 00h-35h) has been monitored with a status operation (70h). This command is

accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). It is also accepted by the

die (LUN) during READ PAGE CACHE (31h, 00h-31h) operations

(RDY = 1 and ARDY = 0).

READ PAGE (00h-30h)

The READ PAGE (00h–30h) command copies a page from the NAND Flash array to its

respective cache register and enables data output. This command is accepted by the die

(LUN) when it is ready (RDY = 1, ARDY = 1).

To read a page from the NAND Flash array, write the 00h command to the command

command. The selected die (LUN) will go busy (RDY = 0, ARDY = 0) for tR as data is

transferred.

To determine the progress of the data transfer, the host can monitor the target's R/B#

signal or, alternatively, the status operations (70h) can be used. If the status operations

are used to monitor the LUN's status, when the die (LUN) is ready

(RDY = 1, ARDY = 1), the host disables status output and enables data output by issuing

the READ MODE (00h) command. When the host requests data output, output begins

at the column address specified.

During data output the RANDOM DATA READ (05h-E0h) command can be issued.

When internal ECC is enabled, the READ STATUS (70h) command is required after the

completion of the data transfer (tR_ECC) to determine whether an uncorrectable read

error occurred. (tR_ECC is the data transferred with internal ECC enabled.)

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Figure 34: READ PAGE (00h-30h) Operation

Cycle type

I/O[7:0]

RDY

Command Address Address Address Address Command

tWB tRtRR

00h C1 C2 R1 R2 30h

DOUT

Dn + 1

DOUT

Dn + 2

Figure 35: READ PAGE (00h-30h) Operation with Internal ECC Enabled

I/O[7:0]

RDY

tR_ECC

00h70h30h00h Status

SR bit 0 = 0 READ successful

SR bit 1 = 1 READ error

DOUT (serial access)

Address Address Address Address

READ PAGE CACHE SEQUENTIAL (31h)

The READ PAGE CACHE SEQUENTIAL (31h) command reads the next sequential page

within a block into the data register while the previous page is output from the cache

(RDY = 1, ARDY = 1). It is also accepted by the die (LUN) during READ PAGE CACHE

(31h, 00h-31h) operations (RDY = 1 and ARDY = 0).

To issue this command, write 31h to the command register. After this command is is-

sued, R/B# goes LOW and the die (LUN) is busy (RDY = 0, ARDY = 0) for tRCBSY. After

tRCBSY, R/B# goes HIGH and the die (LUN) is busy with a cache operation

(RDY = 1, ARDY = 0), indicating that the cache register is available and that the specified

page is copying from the NAND Flash array to the data register. At this point, data can

be output from the cache register beginning at column address 0. The RANDOM DATA

READ (05h-E0h) command can be used to change the column address of the data being

output from the cache register.

The READ PAGE CACHE SEQUENTIAL (31h) command can be used to cross block

boundaries. If the READ PAGE CACHE SEQUENTIAL (31h) command is issued after the

last page of a block is read into the data register, the next page read will be the next logi-

cal block in which the 31h command was issued. Do not issue the READ PAGE CACHE

SEQUENTIAL (31h) to cross die (LUN) boundaries. Instead, issue the READ PAGE

CACHE LAST (3Fh) command.

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Figure 36: READ PAGE CACHE SEQUENTIAL (31h) Operation

Cycle type

I/O[7:0]

RDY

tWB tRCBSY tRR

Command DOUT DOUT DOUT Command DOUT

31h

tWB

Command

30h

tWB tRCBSY tRR

D0 … Dn 31h D0

Command Address x4

00h Page Address M

Page M Page M+1

READ PAGE CACHE RANDOM (00h-31h)

The READ PAGE CACHE RANDOM (00h-31h) command reads the specified block and

page into the data register while the previous page is output from the cache register.

This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). It is

also accepted by the die (LUN) during READ PAGE CACHE (31h, 00h-31h) operations

(RDY = 1 and ARDY = 0).

To issue this command, write 00h to the command register, then write n address cycles

to the address register, and conclude by writing 31h to the command register. The col-

umn address in the address specified is ignored. The die (LUN) address must match the

same die (LUN) address as the previous READ PAGE (00h-30h) command or, if applica-

ble, the previous READ PAGE CACHE RANDOM (00h-31h) command.

After this command is issued, R/B# goes LOW and the die (LUN) is busy

(RDY = 0, ARDY = 0) for tRCBSY. After tRCBSY, R/B# goes HIGH and the die (LUN) is busy

with a cache operation (RDY = 1, ARDY = 0), indicating that the cache register is availa-

ble and that the specified page is copying from the NAND Flash array to the data regis-

ter. At this point, data can be output from the cache register beginning at column ad-

dress 0. The RANDOM DATA READ (05h-E0h) command can be used to change the col-

umn address of the data being output from the cache register.

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Figure 37: READ PAGE CACHE RANDOM (00h-31h) Operation

Cycle type

I/O[7:0]

RDY

tWB tRCBSY tRR

Command DOUT DOUT DOUT

31h

tRR

tWB

Command

30h D0 … Dn

Command Address x4

00h

Command

00hPage Address M

Address x4

Page Address N

Command

00h

Page M

Cycle type

I/O[7:0]

RDY

DOUT Command DOUT

tWB tRCBSY tRR

Dn 31h D0

Command

00h

Address x4

Page Address P

Page N

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READ PAGE CACHE LAST (3Fh)

The READ PAGE CACHE LAST (3Fh) command ends the read page cache sequence and

copies a page from the data register to the cache register. This command is accepted by

the die (LUN) when it is ready (RDY = 1, ARDY = 1). It is also accepted by the die (LUN)

during READ PAGE CACHE (31h, 00h-31h) operations (RDY = 1 and ARDY = 0).

To issue the READ PAGE CACHE LAST (3Fh) command, write 3Fh to the command reg-

ister. After this command is issued, R/B# goes LOW and the die (LUN) is busy

(RDY = 0, ARDY = 0) for tRCBSY. After tRCBSY, R/B# goes HIGH and the die (LUN) is

ready (RDY = 1, ARDY = 1). At this point, data can be output from the cache register, be-

ginning at column address 0. The RANDOM DATA READ (05h-E0h) command can be

used to change the column address of the data being output from the cache register.

Figure 38: READ PAGE CACHE LAST (3Fh) Operation

Cycle type

I/O[7:0]

RDY

tWB tRCBSY tRR

Command Command DOUT DOUT DOUT

DOUT DOUT DOUT

31h

tWB tRCBSY tRR

D0 D0 … Dn

As defined for

READ PAGE CACHE

(SEQUENTIAL OR RANDOM)

… Dn3Fh

Page NPage Address N

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Program Operations

Program operations are used to move data from the cache or data registers to the NAND

array. During a program operation the contents of the cache and/or data registers are

modified by the internal control logic.

Within a block, pages must be programmed sequentially from the least significant page

address to the most significant page address (0, 1, 2, ….., 63). During a program opera-

tion, the contents of the cache and/or data registers are modified by the internal control

logic.

Program Operations

The PROGRAM PAGE (80h-10h) command programs one page from the cache register

to the NAND Flash array. When the die (LUN) is ready (RDY = 1, ARDY = 1), the host

should check the FAIL bit to verify that the operation has completed successfully.

Program Cache Operations

The PROGRAM PAGE CACHE (80h-15h) command can be used to improve program op-

eration system performance. When this command is issued, the die (LUN) goes busy

(RDY = 0, ARDY = 0) while the cache register contents are copied to the data register,

and the die (LUN) is busy with a program cache operation (RDY = 1, ARDY = 0. While

the contents of the data register are moved to the NAND Flash array, the cache register

is available for an additional PROGRAM PAGE CACHE (80h-15h) or PROGRAM PAGE

(80h-10h) command.

For PROGRAM PAGE CACHE series (80h-15h) operations, during the die (LUN) busy

times, tCBSY and tLPROG, when RDY = 0 and ARDY = 0, the only valid commands are

status operation (70h) and reset (FFh). When RDY = 1 and ARDY = 0, the only valid com-

mands during PROGRAM PAGE CACHE series (80h-15h) operations are status opera-

tion (70h), PROGRAM PAGE CACHE (80h-15h), PROGRAM PAGE (80h-10h), RANDOM

DATA INPUT (85h), PROGRAM FOR INTERNAL DATA INPUT (85h), and RESET (FFh).

PROGRAM PAGE (80h-10h)

The PROGRAM PAGE (80h-10h) command enables the host to input data to a cache reg-

ister, and moves the data from the cache register to the specified block and page ad-

dress in the array of the selected die (LUN). This command is accepted by the die (LUN)

when it is ready (RDY = 1, ARDY = 1). It is also accepted by the die (LUN) when it is busy

with a PROGRAM PAGE CACHE (80h-15h) operation (RDY = 1, ARDY = 0).

To input a page to the cache register and move it to the NAND array at the block and

page address specified, write 80h to the command register. Issuing the 80h to the com-

mand register clears all of the cache registers' contents on the selected target. Write n

address cycles containing the column address and row address. Data input cycles fol-

low. Serial data is input beginning at the column address specified. At any time during

the data input cycle the RANDOM DATA INPUT (85h) and PROGRAM FOR INTERNAL

DATA INPUT (85h) commands may be issued. When data input is complete, write 10h

to the command register. The selected LUN will go busy

(RDY = 0, ARDY = 0) for tPROG as data is transferred.

To determine the progress of the data transfer, the host can monitor the target's R/B#

signal or, alternatively, the status operation (70h) may be used. When the die (LUN) is

ready (RDY = 1, ARDY = 1), the host should check the status of the FAIL bit.

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When internal ECC is enabled, the duration of array programming time is t PROG_ECC.

During tPROG_ECC, the internal ECC generates parity bits when error detection is com-

plete.

Figure 39: PROGRAM PAGE (80h-10h) Operaton

Cycle type

I/O[7:0]

RDY

tADL

Command Address Address Address Address

80h

Command

10h

Command

70hC1 C2 R1 R2

DIN DIN DIN DIN

D0 D1 … Dn

DOUT

Status

tWB

tPROG or

tPROG_ECC

PROGRAM PAGE CACHE (80h-15h)

The PROGRAM PAGE CACHE (80h-15h) command enables the host to input data to a

cache register; copies the data from the cache register to the data register; then moves

the data register contents to the specified block and page address in the array of the se-

lected die (LUN). After the data is copied to the data register, the cache register is availa-

ble for additional PROGRAM PAGE CACHE (80h-15h) or PROGRAM PAGE (80h-10h)

commands. The PROGRAM PAGE CACHE (80h-15h) command is accepted by the die

(LUN) when it is ready (RDY =1, ARDY = 1). It is also accepted by the die (LUN) when

busy with a PROGRAM PAGE CACHE (80h-15h) operation (RDY = 1, ARDY = 0).

To input a page to the cache register to move it to the NAND array at the block and page

address specified, write 80h to the command register. Issuing the 80h to the command

address cycles containing the column address and row address. Data input cycles fol-

low. Serial data is input beginning at the column address specified. At any time during

the data input cycle the RANDOM DATA INPUT (85h) and PROGRAM FOR INTERNAL

DATA INPUT (85h) commands may be issued. When data input is complete, write 15h

to the command register. The selected LUN will go busy

(RDY = 0, ARDY = 0) for tCBSY to allow the data register to become available from a pre-

vious program cache operation, to copy data from the cache register to the data register,

and then to begin moving the data register contents to the specified page and block ad-

dress.

To determine the progress of tCBSY, the host can monitor the target's R/B# signal or, al-

ternatively, the status operation (70h) can be used. When the LUN’s status shows that it

is busy with a PROGRAM CACHE operation (RDY = 1, ARDY = 0), the host should check

the status of the FAILC bit to see if a previous cache operation was successful.

If, after tCBSY, the host wants to wait for the program cache operation to complete,

without issuing the PROGRAM PAGE (80h-10h) command, the host should monitor AR-

DY until it is 1. The host should then check the status of the FAIL and FAILC bits.

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Figure 40: PROGRAM PAGE CACHE (80h-15h) Operation (Start)

Cycle type

I/O[7:0]

RDY

tADL

Command Address Address Address Address

80h C1 C2 R1 R2

DIN DIN DIN DIN Command

D0 D1 … Dn 15h

tWB tCBSY

Cycle type

I/O[7:0]

RDY

tADL

Command Address Address Address Address

80h C1 C2 R1 R2

DIN DIN DIN DIN Command

D0 D1 … Dn 15h

tWB tCBSY

Figure 41: PROGRAM PAGE CACHE (80h-15h) Operation (End)

Cycle type

I/O[7:0]

RDY

tADL

Command Address Address Address Address

80h C1 C2 R1 R2

DIN DIN DIN DIN Command

D0 D1 … Dn 15h

tWB tCBSY

Cycle type

RDY

tADL

Command Address

As defined for

PAGE CACHE PROGRAM

Address Address Address

80h C1 C2 R1 R2

DIN DIN DIN DIN Command

D0 D1 … Dn 10h

tWB tLPROG

I/O[7:0]

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Erase Operations

Erase operations are used to clear the contents of a block in the NAND Flash array to

prepare its pages for program operations.

Erase Operations

The ERASE BLOCK (60h-D0h) command erases one block in the NAND Flash array.

When the die (LUN) is ready (RDY = 1, ARDY = 1), the host should check the FAIL bit to

verify that this operation completed successfully.

ERASE BLOCK (60h-D0h)

The ERASE BLOCK (60h-D0h) command erases the specified block in the NAND Flash

array. This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1).

To erase a block, write 60h to the command register. Then write two address cycles con-

taining the row address; the page address is ignored. Conclude by writing D0h to the

command register. The selected die (LUN) will go busy (RDY = 0, ARDY = 0) for tBERS

while the block is erased.

To determine the progress of an ERASE operation, the host can monitor the target's

R/B# signal, or alternatively, the status operation (70h) can be used. When the die

(LUN) is ready (RDY = 1, ARDY = 1) the host should check the status of the FAIL bit.

Figure 42: ERASE BLOCK (60h-D0h) Operation

Cycle type

I/O[7:0]

RDY

Command Address Address Command

tWB tBERS

D0h60h R1 R2

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Internal Data Move Operations

Internal data move operations make it possible to transfer data within a device from

one page to another using the cache register. This is particularly useful for block man-

agement and wear leveling.

The INTERNAL DATA MOVE operation is a two-step process consisting of a READ FOR

INTERNAL DATA MOVE (00h-35h) and a PROGRAM FOR INTERNAL DATA MOVE

(85h-10h) command. To move data from one page to another, first issue the READ FOR

INTERNAL DATA MOVE (00h-35h) command. When the die (LUN) is ready (RDY = 1,

ARDY = 1), the host can transfer the data to a new page by issuing the PROGRAM FOR

INTERNAL DATA MOVE (85h-10h) command. When the die (LUN) is again ready (RDY

= 1, ARDY = 1), the host should check the FAIL bit to verify that this operation comple-

ted successfully.

To prevent bit errors from accumulating over multiple INTERNAL DATA MOVE opera-

tions, it is recommended that the host read the data out of the cache register after the

READ FOR INTERNAL DATA MOVE (00h-35h) completes and prior to issuing the PRO-

GRAM FOR INTERNAL DATA MOVE (85h-10h) command. The RANDOM DATA READ

(05h-E0h) command can be used to change the column address. The host should check

the data for ECC errors and correct them. When the PROGRAM FOR INTERNAL DATA

MOVE (85h-10h) command is issued, any corrected data can be input. The PROGRAM

FOR INTERNAL DATA INPUT (85h) command can be used to change the column ad-

dress.

Between the READ FOR INTERNAL DATA MOVE (00h-35h) and PROGRAM FOR INTER-

NAL DATA MOVE (85h-10h) commands, the following commands are supported: status

operation (70h) and column address operations (05h-E0h, 85h). The RESET operation

(FFh) can be issued after READ FOR INTERNAL DATA MOVE (00h-35h), but the con-

tents of the cache registers on the target are not valid.

READ FOR INTERNAL DATA MOVE (00h-35h)

The READ FOR INTERNAL DATA MOVE (00h-35h) command is functionally identical to

the READ PAGE (00h-30h) command, except that 35h is written to the command regis-

ter instead of 30h.

Though it is not required, it is recommended that the host read the data out of the de-

vice to verify the data prior to issuing the PROGRAM FOR INTERNAL DATA MOVE

(85h-10h) command to prevent the propagation of data errors.

If internal ECC is enabled, the data does not need to be toggled out by the host to be

corrected and moving data can then be written to a new page without data reloading,

which improves system performance.

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Figure 43: READ FOR INTERNAL DATA MOVE (00h-35h) Operation

Cycle type

I/O[7:0]

RDY

Command AddressAddress Address Address Command

tWB tRtRR

00h C1 C2 R1 R2 35h

DOUT

Dn + 1

DOUT

Dn + 2

Address

Figure 44: READ FOR INTERNAL DATA MOVE (00h–35h) with RANDOM DATA READ (05h–E0h)

Cycle type

I/O[7:0]

RDY

Command Address Address Address Address Command

tWB tRtRR

00h C1 C2 R1 R2 35h

Cycle type

I/O[7:0]

RDY

Command Address Address Command

tWHR

05h C1 C2 E0h

… Dj + n

Dk + 1 Dk + 2

DOUT

DOUT DOUT DOUT

DOUT DOUT

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Figure 45: INTERNAL DATA MOVE (85h-10h) with Internal ECC Enabled

I/O[7:0]

R/B#

tR_ECC tPROG_ECC

00h 35h

Address

(4 cycles) Address

(4 cycles)

00h 85h 10h70h DOUT

Status

Source address Destination address

70h Status

SR bit 0 = 0 READ successful

SR bit 1 = 0 READ error

SR bit 0 = 0 READ successful

SR bit 1 = 0 READ error

00h

DOUT is optional

Figure 46: INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT with Internal ECC Enabled

I/O[7:0]

R/B#

tR_ECC tPROG_ECC

00h 35h

Address

(4 cycles) Address

(4 cycles)

00h 85h Data70h 70h

DOUT

Status

Source address

Column address 1, 2

(Unlimitted repetitions are possible)

Destination address

Address

(2 cycles)

85h 10hData

SR bit 0 = 0 READ successful

SR bit 1 = 0 READ error

DOUT is optional

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PROGRAM FOR INTERNAL DATA MOVE (85h–10h)

The PROGRAM FOR INTERNAL DATA MOVE (85h-10h) command is functionally iden-

tical to the PROGRAM PAGE (80h-10h) command, except that when 85h is written to the

command register, cache register contents are not cleared.

Figure 47: PROGRAM FOR INTERNAL DATA MOVE (85h–10h) Operation

Cycle type

I/O[7:0]

RDY

Command Address Address Address Address Command

tWB tPROG

85h C1 C2 R1 R2 10h

Figure 48: PROGRAM FOR INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT (85h)

Cycle type

I/O[7:0]

RDY

Command Address Address Address Address

tWB tPROG

85h C1 C2 R1 R2

Cycle type

I/O[7:0]

RDY

Command Address Address

tWHR

85h

Command

10hC1 C2

DIN

Di + 1

DIN

Dj + 1

DIN

Dj + 2

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One-Time Programmable (OTP) Operations

This Micron NAND Flash device offers a protected, one-time programmable NAND

Flash memory area. Thirty full pages (2112 bytes per page) of OTP data are available on

the device, and the entire range is guaranteed to be good. The OTP area is accessible

only through the OTP commands. Customers can use the OTP area any way they

choose; typical uses include programming serial numbers or other data for permanent

storage.

The OTP area leaves the factory in an unwritten state (all bits are 1s). Programming or

partial-page programming enables the user to program only 0 bits in the OTP area. The

OTP area cannot be erased, whether it is protected or not. Protecting the OTP area pre-

vents further programming of that area.

Micron provides a unique way to program and verify data before permanently protect-

ing it and preventing future changes. The OTP area is only accessible while in OTP oper-

ation mode. To set the device to OTP operation mode, issue the SET FEATURE (EFh)

command to feature address 90h and write 01h to P1, followed by three cycles of 00h to

P2-P4. For parameters to enter OTP mode, see Features Operations.

When the device is in OTP operation mode, all subsequent PAGE READ (00h-30h) and

PROGRAM PAGE (80h-10h) commands are applied to the OTP area. The OTP area is as-

signed to page addresses 02h-1Fh. To program an OTP page, issue the PROGRAM PAGE

(80h-10h) command. The pages must be programmed in the ascending order. Similarly,

to read an OTP page, issue the PAGE READ (00h-30h) command.

Protecting the OTP is done by entering OTP protect mode. To set the device to OTP pro-

tect mode, issue the SET FEATURE (EFh) command to feature address 90h and write

03h to P1, followed by three cycles of 00h to P2-P4.

To determine whether the device is busy during an OTP operation, either monitor R/B#

or use the READ STATUS (70h) command.

To exit OTP operation or protect mode, write 00h to P1 at feature address 90h.

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OTP DATA PROGRAM (80h-10h)

The OTP DATA PROGRAM (80h-10h) command is used to write data to the pages within

the OTP area. An entire page can be programmed at one time, or a page can be partially

programmed up to eight times. Only the OTP area allows up to eight partial-page pro-

grams. The rest of the blocks support only four partial-page programs. There is no

ERASE operation for OTP pages.

PROGRAM PAGE enables programming into an offset of an OTP page using two bytes of

the column address (CA[12:0]). The command is compatible with the RANDOM DATA

INPUT (85h) command. The PROGRAM PAGE command will not execute if the OTP

area has been protected.

To use the PROGRAM PAGE command, issue the 80h command. Issue n address cycles.

The first two address cycles are the column address. For the remaining cycles, select a

page in the range of 02h-00h through 1Fh-00h. Next, write from 1–2112 bytes of data.

After data input is complete, issue the 10h command. The internal control logic auto-

matically executes the proper programming algorithm and controls the necessary tim-

ing for programming and verification.

R/B# goes LOW for the duration of the array programming time (tPROG). The READ

STATUS (70h) command is the only valid command for reading status in OTP operation

mode. Bit 5 of the status register reflects the state of R/B#. When the device is ready,

read bit 0 of the status register to determine whether the operation passed or failed (see

Status Operations). Each OTP page can be programmed to 8 partial-page programming.

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RANDOM DATA INPUT (85h)

After the initial OTP data set is input, additional data can be written to a new column

address with the RANDOM DATA INPUT (85h) command. The RANDOM DATA INPUT

command can be used any number of times in the same page prior to the OTP PAGE

WRITE (10h) command being issued.

Figure 49: OTP DATA PROGRAM (After Entering OTP Operation Mode)

WE#

CE#

ALE

CLE

RE#

R/B#

I/Ox

Don’t Care

OTP data written

(following good status confirmation)

tWC

tWB tPROG

OTP DATA INPUT

command

PROGRAM

command

READ STATUS

command

1 up to m bytes

serial input

x8 device: m = 2112 bytes

x16 device: m = 1056 words

80h Col

add 1

Col

add 2

DIN

00h 10h 70h Status

OTP

page1

OTP address1

Note: 1. The OTP page must be within the 02h–1Fh range.

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Figure 50: OTP DATA PROGRAM Operation with RANDOM DATA INPUT (After Entering OTP Opera-

tion Mode)

WE#

CE#

ALE

CLE

RE#

R/B#

I/Ox

tWC

SERIAL DATA

INPUT command

Serial input

80h Col

add1

Col

add2

OTP

page1DIN

n + 1

tADL tADL

RANDOM DATA

INPUT command

Column address PROGRAM

command

READ STATUS

command

Serial input

85h Col

add1 70h Status

10h

tPROG

tWB

Don‘t Care

00h DIN

nCol

add2

DIN

n + 1

Note: 1. The OTP page must be within the 02h–1Fh range.

OTP DATA PROTECT (80h-10)

The OTP DATA PROTECT (80h-10h) command is used to prevent further programming

of the pages in the OTP area. To protect the OTP area, the target must be in OTP opera-

tion mode.

To protect all data in the OTP area, issue the 80h command. Issue n address cycles in-

cluding the column address, OTP protect page address and block address; the column

and block addresses are fixed to 0. Next, write 00h data for the first byte location and

issue the 10h command. R/B# goes LOW for the duration of the array programming

time, tPROG.

After the data is protected, it cannot be programmed further. When the OTP area is pro-

tected, the pages within the area are no longer programmable and cannot be unprotec-

ted.

The READ STATUS (70h) command is the only valid command for reading status in OTP

operation mode. The RDY bit of the status register will reflect the state of R/B#. Use of

the READ STATUS ENHANCED (78h) command is prohibited.

When the target is ready, read the FAIL bit of the status register to determine if the oper-

ation passed or failed.

If the OTP DATA PROTECT (80h-10h) command is issued after the OTP area has already

been protected, R/B# goes LOW for tOBSY. After tOBSY, the status register is set to 60h.

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Figure 51: OTP DATA PROTECT Operation (After Entering OTP Protect Mode)

WE#

CE#

ALE

CLE

RE#

R/B#

I/Ox

Don’t Care

tWC

tWB tPROG

OTP DATA

PROTECT command OTP address

OTP data protected1

PROGRAM

command READ STATUS

command

80h Col

00h

Col

00h 10h 70h Status

OTP

page 00h 00h

Note: 1. OTP data is protected following a good status confirmation.

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OTP DATA READ (00h-30h)

To read data from the OTP area, set the device to OTP operation mode, then issue the

PAGE READ (00h-30h) command. Data can be read from OTP pages within the OTP area

whether the area is protected or not.

To use the PAGE READ command for reading data from the OTP area, issue the 00h

command, and then issue five address cycles: for the first two cycles, the column ad-

dress; and for the remaining address cycles, select a page in the range of 02h-00h-00h

through 1Fh-00h-00h. Lastly, issue the 30h command. The PAGE READ CACHE MODE

command is not supported on OTP pages.

R/B# goes LOW (tR) while the data is moved from the OTP page to the data register. The

READ STATUS (70h) command is the only valid command for reading status in OTP op-

eration mode. Bit 5 of the status register reflects the state of R/B# (see Status Opera-

tions).

Normal READ operation timings apply to OTP read accesses. Additional pages within

the OTP area can be selected by repeating the OTP DATA READ command.

The PAGE READ command is compatible with the RANDOM DATA OUTPUT (05h-E0h)

command.

Only data on the current page can be read. Pulsing RE# outputs data sequentially.

Figure 52: OTP DATA READ

WE#

CE#

ALE

CLE

RE#

R/B#

I/Ox

Busy

00h 00h 30h

Col

add 1 Col

add 2

Don’t Care

OTP

page1

OTP address

DOUT

nDOUT

n + 1 DOUT

Note: 1. The OTP page must be within the 02h–1Fh range.

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Figure 53: OTP DATA READ with RANDOM DATA READ Operation

WE#

CE#

ALE

CLE

RE#

R/B#

I/Ox

Busy

Col

add 1 Col

add 2 OTP

page100h

00h

tAR

tRR

Don’t Care

tRC

DOUT

mDOUT

m + 1

Col

add 1 Col

add 2

05h E0h

tREA

tWHR

tCLR

DOUT

nDOUT

n + 1

30h

tWB

Column address n Column address m

Note: 1. The OTP page must be within the range 02h–1Fh.

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Error Management

Each NAND Flash die (LUN) is specified to have a minimum number of valid blocks

(NVB) of the total available blocks. This means the die (LUNs) could have blocks that

are invalid when shipped from the factory. An invalid block is one that contains at least

one page that has more bad bits than can be corrected by the minimum required ECC.

Additional blocks can develop with use. However, the total number of available blocks

per die (LUN) will not fall below NVB during the endurance life of the product.

Although NAND Flash memory devices could contain bad blocks, they can be used

quite reliably in systems that provide bad block management and error-correction algo-

rithms. This type of software environment ensures data integrity.

Internal circuitry isolates each block from other blocks, so the presence of a bad block

does not affect the operation of the rest of the NAND Flash array.

NAND Flash devices are shipped from the factory erased. The factory identifies invalid

blocks before shipping by attempting to program the bad block mark into every loca-

tion in the first page of each invalid block. It may not be possible to program every loca-

tion with the bad block mark. However, the first spare area location in each bad block is

guaranteed to contain the bad block mark. This method is compliant with ONFI Factory

Defect Mapping requirements. See the following table for the first spare area location

and the bad block mark.

System software should check the first spare area location on the first page of each

block prior to performing any PROGRAM or ERASE operations on the NAND Flash de-

vice. A bad block table can then be created, enabling system software to map around

these areas. Factory testing is performed under worst-case conditions. Because invalid

blocks could be marginal, it may not be possible to recover this information if the block

is erased.

Over time, some memory locations may fail to program or erase properly. In order to

ensure that data is stored properly over the life of the NAND Flash device, the following

precautions are required:

• Always check status after a PROGRAM or ERASE operation

• Under typical conditions, use the minimum required ECC (see table below)

• Use bad block management and wear-leveling algorithms

The first block (physical block address 00h) for each CE# is guaranteed to be valid

with ECC when shipped from the factory.

Table 15: Error Management Details

Description Requirement

Minimum number of valid blocks (NVB) per LUN 1004

Total available blocks per LUN 1024

First spare area location x8: byte 2048 x16: word 1024

Bad-block mark x8: 00h x16: 0000h

Minimum required ECC 4-bit ECC per 528 bytes of data

Minimum ECC with internal ECC enabled 4-bit ECC per 516 bytes (user data) + 8

bytes (parity data)

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Table 15: Error Management Details (Continued)

Description Requirement

Minimum required ECC for block 0 if PROGRAM/

ERASE cycles are less than 1000

1-bit ECC per 528 bytes

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Internal ECC and Spare Area Mapping for ECC

Internal ECC enables 5-bit detection and 4-bit error correction in 512 bytes (x8) or 256

words (x16) of the main area and 4 bytes (x8) or 2 words (x16) of metadata I in the spare

area. The metadata II area, which consists of two bytes (x8) and one word (x16), is not

ECC protected. During the busy time for PROGRAM operations, internal ECC generates

parity bits when error detection is complete.

During READ operations the device executes the internal ECC engine (5-bit detection

and 4-bit error correction). When the READ operaton is complete, read status bit 0 must

be checked to determine whether errors larger than four bits have occurred.

Following the READ STATUS command, the device must be returned to read mode by

issuing the 00h command.

Limitations of internal ECC include the spare area, defined in the figures below, and

ECC parity areas that cannot be written to. Each ECC user area (referred to as main and

spare) must be written within one partial-page program so that the NAND device can

calculate the proper ECC parity. The number of partial-page programs within a page

cannot exceed four.

Figure 54: Spare Area Mapping (x8)

Max Byte Min Byte

ECC Protected Area Description

Address Address

1FFh 000h Yes Main 0 User data

3FFh 200h Yes Main 1 User data

5FFh 400h Yes Main 2 User data

7FFh 600h Yes Main 3 User data

801h 800h No Reserved

803h 802h No User metadata II

807h 804h Yes Spare 0 User metadata I

80Fh 808h Yes Spare 0 ECC for main/spare 0

811h 810h No Reserved

813h 812h No User metadata II

817h 814h Yes Spare 1 User metadata I

81Fh 818h Yes Spare 1 ECC for main/spare 1

821h 820h No Reserved

823h 822h No User metadata II

827h 824h Yes Spare 2 User metadata I

82Fh 828h Yes Spare 2 ECC for main/spare 2

831h 830h No User data

833h 832h No User metadata II

837h 834h Yes Spare 3 User metadata I

83Fh 838h Yes Spare 3 ECC for main/spare 3

Bad Block ECC User Data

Information Parity (Metadata)

2 bytes 8 bytes 6 bytes

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Figure 55: Spare Area Mapping (x16)

Max word Min word

ECC Protected

Area

Description

Address Address

0FFh 000h Yes Main 0 User data

1FFh 100h Yes Main 1 User data

2FFh 200h Yes Main 2 User data

3FFh 300h Yes Main 3 User data

400h 400h No Reserved

401h 401h No User metadata II

403h 402h Yes Spare 0 User metadata I

407h 404h Yes Spare 0 ECC for main/spare 0

408h 408h No Reserved

409h 409h No User metadata II

40Bh 40Ah Yes Spare 1 User metadata I

40Fh 40Ch Yes Spare 1 ECC for main/spare 1

410h 410h No Reserved

411h 411h No User metadata II

413h 412h Yes Spare 2 User metadata I

417h 414h Yes Spare 2 ECC for main/spare 2

418h 418h No User data

419h 419h No User metadata II

41Bh 41Ah Yes Spare 3 User metadata I

41Fh 41Ch Yes Spare 3 ECC for main/spare 3

Bad Block ECC User Data

Information Parity (Metadata)

1 word 4 words 3 words

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Electrical Specifications

Stresses greater than those listed can cause permanent damage to the device. This is a

stress rating only, and functional operation of the device at these or any other condi-

tions above those indicated in the operational sections of this specification is not guar-

anteed. Exposure to absolute maximum rating conditions for extended periods can af-

fect reliability.

Table 16: Absolute Maximum Ratings

Voltage on any pin relative to VSS

Parameter/Condition Symbol Min Max Unit

Voltage Input 3.3V VIN –0.6 4.6 V

1.8V –0.6 2.4 V

VCC supply voltage 3.3V VCC –0.6 4.6 V

1.8V –0.6 2.4 V

Storage temperature TSTG –65 150 °C

Short circuit output current, I/Os – – 5 mA

Table 17: Recommended Operating Conditions

Parameter/Condition Symbol Min Typ Max Unit

Operating temperature Commercial TA0 – 70 °C

Industrial –40 – 85 °C

VCC supply voltage 3.3V VCC 2.7 3.3 3.6 V

1.8V 1.7 1.8 1.95 V

Ground supply voltage VSS 0 0 0 V

Table 18: Valid Blocks

Parameter Symbol Device Min Max Unit Notes

Valid block number NVB 3.3V/1.8V 1004 1024 blocks 1

Note: 1. Invalid blocks are blocks that contain one or more bad bits. The device may contain bad

blocks upon shipment. Additional bad blocks may develop over time; however, the total

number of available blocks will not drop below NVB during the endurance life of the

device. Do not erase or program blocks marked invalid by the factory.

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Table 19: Capacitance

Description Symbol Max Unit Notes

Input capacitance CIN 10 pF 1, 2

Input/output capacitance (I/O) CIO 10 pF 1, 2

Notes: 1. These parameters are verified in device characterization and are not 100% tested.

2. Test conditions: TC = 25°C; f = 1 MHz; VIN = 0V.

Table 20: Test Conditions

Parameter Value Notes

Input pulse levels 0.0V to VCC

Input rise and fall times 5ns

Input and output timing levels VCC/2

Output load 3.3V 1 TTL GATE and CL = 30pF 1

1.8V 1 TTL GATE and CL = 30pF 1

Note: 1. These parameters are verified in device characterization and are not 100% tested.

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Electrical Specifications – AC Characteristics and Operating Conditions

Table 21: AC Characteristics: Command, Data, and Address Input (3.3V)

Note 1 applies to all

Parameter Symbol Min Max Unit Notes

ALE to data start tADL 70 – ns 2

ALE hold time tALH 5 – ns

ALE setup time tALS 10 – ns

CE# hold time tCH 5 – ns

CLE hold time tCLH 5 – ns

CLE setup time tCLS 10 – ns

CE# setup time tCS 15 – ns

Data hold time tDH 5 – ns

Data setup time tDS 7 – ns

WRITE cycle time tWC 20 – ns 2

WE# pulse width HIGH tWH 7 – ns 2

WE# pulse width tWP 10 – ns 2

WP# transition to WE# LOW tWW 100 – ns

Notes: 1. Operating mode timings meet ONFI timing mode 5 parameters.

2. Timing for tADL begins in the address cycle, on the final rising edge of WE#, and ends

with the first rising edge of WE# for data input.

Table 22: AC Characteristics: Command, Data, and Address Input (1.8V)

Note 1 applies to all

Parameter Symbol Min Max Unit Notes

ALE to data start tADL 70 – ns 2

ALE hold time tALH 5 – ns

ALE setup time tALS 10 – ns

CE# hold time tCH 5 – ns

CLE hold time tCLH 5 – ns

CLE setup time tCLS 10 – ns

CE# setup time tCS 20 – ns

Data hold time tDH 5 – ns

Data setup time tDS 10 – ns

WRITE cycle time tWC 25 – ns 2

WE# pulse width HIGH tWH 10 – ns 2

WE# pulse width tWP 12 – ns 2

WP# transition to WE# LOW tWW 100 – ns

Notes: 1. Operating mode timings meet ONFI timing mode 4 parameters.

2. Timing for tADL begins in the address cycle on the final rising edge of WE#, and ends

with the first rising edge of WE# for data input.

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Table 23: AC Characteristics: Normal Operation (3.3V)

Note 1 applies to all

Parameter Symbol Min Max Unit Notes

ALE to RE# delay tAR 10 – ns

CE# access time tCEA – 25 ns

CE# HIGH to output High-Z tCHZ – 50 ns 2

CLE to RE# delay tCLR 10 – ns

CE# HIGH to output hold tCOH 15 – ns

Output High-Z to RE# LOW tIR 0 – ns

READ cycle time tRC 20 – ns

RE# access time tREA – 16 ns

RE# HIGH hold time tREH 7 – ns

RE# HIGH to output hold tRHOH 15 – ns

RE# HIGH to WE# LOW tRHW 100 – ns

RE# HIGH to output High-Z tRHZ – 100 ns 2

RE# LOW to output hold tRLOH 5 – ns

RE# pulse width tRP 10 – ns

Ready to RE# LOW tRR 20 – ns

Reset time (READ/PROGRAM/ERASE) tRST – 5/10/500 µs 3

WE# HIGH to busy tWB – 100 ns

WE# HIGH to RE# LOW tWHR 60 – ns

Notes: 1. AC characteristics may need to be relaxed if I/O drive strength is not set to full.

2. Transition is measured ±200mV from steady-state voltage with load. This parameter is

sampled and not 100% tested.

3. The first time the RESET (FFh) command is issued while the device is idle, the device will

go busy for a maximum of 1ms. Thereafter, the device goes busy for a maximum of 5µs.

Table 24: AC Characteristics: Normal Operation (1.8V)

Note 1 applies to all

Parameter Symbol Min Max Unit Notes

ALE to RE# delay tAR 10 – ns

CE# access time tCEA – 25 ns

CE# HIGH to output High-Z tCHZ – 50 ns 2

CLE to RE# delay tCLR 10 – ns

CE# HIGH to output hold tCOH 15 – ns

Output High-Z to RE# LOW tIR 0 – ns

READ cycle time tRC 25 – ns

RE# access time tREA – 22 ns

RE# HIGH hold time tREH 10 – ns

RE# HIGH to output hold tRHOH 15 – ns

RE# HIGH to WE# LOW tRHW 100 – ns

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Table 24: AC Characteristics: Normal Operation (1.8V) (Continued)

Note 1 applies to all

Parameter Symbol Min Max Unit Notes

RE# HIGH to output High-Z tRHZ – 65 ns 2

RE# LOW to output hold tRLOH 3 – ns

RE# pulse width tRP 12 – ns

Ready to RE# LOW tRR 20 – ns

Reset time (READ/PROGRAM/ERASE) tRST – 5/10/500 µs 3

WE# HIGH to busy tWB – 100 ns

WE# HIGH to RE# LOW tWHR 80 – ns

Notes: 1. AC characteristics may need to be relaxed if I/O drive strength is not set to full.

2. Transition is measured ±200mV from steady-state voltage with load. This parameter is

sampled and not 100% tested.

3. The first time the RESET (FFh) command is issued while the device is idle, the device will

be busy for a maximum of 1ms. Thereafter, the device is busy for a maximum of 5µs.

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Electrical Specifications – DC Characteristics and Operating Conditions

Table 25: DC Characteristics and Operating Conditions (3.3V)

Parameter Conditions Symbol Min Typ Max Unit Notes

Sequential READ current tRC = tRC (MIN); CE# = VIL;

IOUT = 0mA

ICC1 – 25 35 mA

PROGRAM current – ICC2 – 25 35 mA

ERASE current – ICC3 – 25 35 mA

Standby current (TTL) CE# = VIH;

WP# = 0V/VCC

ISB1 – – 1 mA

Standby current (CMOS) CE# = VCC - 0.2V;

WP# = 0V/VCC

ISB2 – 20 100 µA

Staggered power-up cur-

rent

Rise time = 1ms

Line capacitance = 0.1µF

IST – – 10 per die mA 1

Input leakage current VIN = 0V to VCC ILI – – ±10 µA

Output leakage current VOUT = 0V to VCC ILO – – ±10 µA

Input high voltage I/O[7:0], I/O[15:0],

CE#, CLE, ALE, WE#, RE#,

WP#

VIH 0.8 x VCC – VCC + 0.3 V

Input low voltage, all in-

puts

– VIL –0.3 – 0.2 x VCC V

Output high voltage IOH = –400µA VOH 0.67 x VCC – – V 3

Output low voltage IOL = 2.1mA VOL – – 0.4 V 3

Output low current VOL = 0.4V IOL (R/B#) 8 10 – mA 2

Notes: 1. Measurement is taken with 1ms averaging intervals and begins after VCC reaches

VCC(MIN).

2. IOL (RB#) may need to be relaxed if R/B pull-down strength is not set to full.

3. VOH and VOL may need to be relaxed if I/O drive strength is not set to full.

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Table 26: DC Characteristics and Operating Conditions (1.8V)

Parameter Conditions Symbol Min Typ Max Unit Notes

Sequential READ current tRC = tRC (MIN); CE# = VIL;

IOUT = 0mA

ICC1 – 13 20 mA 1, 2

PROGRAM current – ICC2 – 10 20 mA 1, 2

ERASE current – ICC3 – 10 20 mA 1, 2

Standby current (TTL) CE# = VIH;

WP# = 0V/VCC

ISB1 – – 1 mA

Standby current (CMOS) CE# = VCC - 0.2V;

WP# = 0V/VCC

ISB2 – 10 50 µA

Staggered power-up cur-

rent

Rise time = 1ms

Line capacitance = 0.1µF

IST – – 10 per die mA 3

Input leakage current VIN = 0V to VCC ILI – – ±10 µA

Output leakage current VOUT = 0V to VCC ILO – – ±10 µA

Input high voltage I/O[7:0], I/O[15:0],

CE#, CLE, ALE, WE#, RE#,

WP#

VIH 0.8 x VCC – VCC + 0.3 V

Input low voltage, all in-

puts

– VIL –0.3 – 0.2 x VCC V

Output high voltage IOH = –100µA VOH VCC - 0.1 – – V 4

Output low voltage IOL = +100µA VOL – – 0.1 V 4

Output low current (R/B#) VOL = 0.2V IOL (R/B#) 3 4 – mA 5

Notes: 1. Typical and maximum values are for single-plane operation only.

2. Values are for single-die operations. Values could be higher for interleaved-die opera-

tions.

3. Measurement is taken with 1ms averaging intervals and begins after VCC reaches

VCC(MIN).

4. Test conditions for VOH and VOL.

5. DC characteristics may need to be relaxed if R/B# pull-down strength is not set to full.

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Electrical Specifications – Program/Erase Characteristics

Table 27: ProgramErase Characteristics

Parameter Symbol Typ Max Unit Notes

Number of partial-page programs NOP – 4 cycles 1

BLOCK ERASE operation time tBERS 0.7 3 ms

Busy time for PROGRAM CACHE operation tCBSY 3 600 µs 2

Cache read busy time tRCBSY 3 25 µs

Busy time for SET FEATURES and GET FEATURES operations tFEAT – 1 µs

Busy time for OTP DATA PROGRAM operation if OTP is pro-

tected

tOBSY – 30 µs

PROGRAM PAGE operation time, internal ECC disabled tPROG 200 600 µs 8

PROGRAM PAGE operation time, internal ECC enabled tPROG_ECC 220 600 µs 3, 8

Data transfer from Flash array to data register, internal ECC

disabled

tR – 25 µs 6, 7

Data transfer from Flash array to data register, internal ECC

enabled

tR_ECC 45 70 µs 3, 5

Busy time for OTP DATA PROGRAM operation if OTP is pro-

tected, internal ECC enabled

tOBSY_ECC – 50 µs

Notes: 1. Four total partial-page programs to the same page. If ECC is enabled, then the device is

limited to one partial-page program per ECC user area, not exceeding four partial-page

programs per page.

2. tCBSY MAX time depends on timing between internal program completion and data-in.

3. Parameters are with internal ECC enabled.

4. Typical is nominal voltage and room temperature.

5. Typical tR_ECC is under typical process corner, nominal voltage, and at room tempera-

ture.

6. Data transfer from Flash array to data register with internal ECC disabled.

7. AC characteristics may need to be relaxed if I/O drive strength is not set to full.

8. Typical program time is defined as the time within which more than 50% of the pages

are programmed at nominal voltage and room temperature.

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Asynchronous Interface Timing Diagrams

Figure 56: RESET Operation

CLE

CE#

WE#

R/B#

I/O[7:0]

tRST

tWB

FFh

RESET

command

Figure 57: READ STATUS Cycle

RE#

CE#

WE#

CLE

I/O[7:0]

tRHZ

tWP

tWHR

tCLR

tCH

tCLS

tCS

tCLH

tDH

tRP

tCHZ

tDS tREA tRHOH

tIR

70h Status

output

Don’t Care

tCEA

tCOH

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Figure 58: READ PARAMETER PAGE

WE#

ALE

CLE

RE#

R/B#

ECh 00h

tR or tR_ECC

P00P10P2550P01

tWB

tRR

I/O[7:0]

tRP

tRC

Figure 59: READ PAGE

DOUT

N + 1

DOUT

WE#

CE#

ALE

CLE

RE#

RDY

I/Ox

tWC

Busy

00h 30h

tR or tR_ECC

tWB

tAR

tRR tRP

tCLR

tRC tRHZ

Don’t Care

Col

add 1

Col

add 2

Row

add 1

Row

add 2

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Figure 60: READ PAGE Operation with CE# “Don’t Care”

RE#

CE#

tREA tCHZ

tCOH

tCEA

RE#

CE#

ALE

CLE

I/Ox

I/Ox Out

RDY

WE#

Data output

tR or tR_ECC

Don’t Care

Address (4 cycles)00h 30h

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Figure 61: RANDOM DATA READ

WE#

CE#

ALE

CLE

RE#

RDY

I/Ox

tRHW

tRC

DOUT

M + 1

Col

add 1 Col

add 2

05h E0h

tREA

tCLR

DOUT

N - 1

DOUT

tWHR

Column address M

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Figure 62: READ PAGE CACHE SEQUENTIAL

tWC

WE#

CE#

ALE

CLE

RE#

RDY

I/Ox

Column address 0

Page address

Column address

00h

tCEA

tDS

tCLH

tCLS

tCS

tCH

tDH

tRR

tWB tR or tR_ECC

tRC

tREA

30h DOUT

31h

Col

add 2 Row

add 1 Row

add 2

00h

tRCBSY

Page address

Col

add 1

tRHW

DOUT

tCLH

tCH

tDS

tWB

tCLS

tCS

DOUT 31h

WE#

CE#

ALE

CLE

RE#

RDY

I/Ox

Column address 0

Page address

tRC

tREA

DOUT

tRHW

DOUT

Don’t Care

Column address 0

tCLH

tCH

tREA

tCEA

tRHW

tDS tRR

tRCBSY

tWB

Column address 0

DOUT

0DOUT 3Fh DOUT

0DOUT

tCLS

tCS

tRC

DOUT 31h

tRCBSY

DOUT

Page address

M + 1 Page address

M + 2

tDH

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Figure 63: READ PAGE CACHE RANDOM

tWC

WE#

CE#

ALE

CLE

RE#

RDY

I/Ox

Column address

00h

tDS

tCLH

tCLS

tCS

tCH

tDH tWB tR or tR_ECC

30h 00h

Col

add 2

Row

add 1

Row

add 2

00h

Page address

Col

add 1

Column address

00h

Col

add 2

Row

add 1

Row

add 2

Page address

Col

add 1

WE#

CE#

ALE

CLE

RE#

RDY

I/Ox

Don’t Care

Column address 0

tCH

tREA

tCEA tRHW

tDS

tDH

tRR

tRCBSY

tWB

Column address 0

DOUT

0DOUT 3Fh DOUT

0DOUT

tCS

tRC

31h

tRCBSY

DOUT

Page address

Column address

00h

Col

add 2

Row

add 1

Row

add 2

Page address

Col

add 1

tCLH

tCLS

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Figure 64: READ ID Operation

WE#

CE#

ALE

CLE

RE#

I/Ox

Address, 1 cycle

90h 00h or 20h Byte 2Byte 0 Byte 1 Byte 3 Byte 4

tAR

tREA

tWHR

Figure 65: PROGRAM PAGE Operation

WE#

CE#

ALE

CLE

RE#

RDY

I/Ox

tWC tADL

1 up to m byte

serial Input

80h Col

add 1 Col

add 2 Row

add 1 Row

add 2

DIN

M70h Status

10h

tPROG or

tPROG_ECC tWHR

tWB

Don’t Care

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Figure 66: PROGRAM PAGE Operation with CE# “Don’t Care”

Address (4 cycles) Data input 10h

WE#

CE#

tWP

tCH

tCS

Don’t Care

Data input80h

CLE

CE#

WE#

ALE

I/Ox

Figure 67: PROGRAM PAGE Operation with RANDOM DATA INPUT

WE#

CE#

ALE

CLE

RE#

RDY

i/Ox

tWC

Serial input

80h Col

add 1 Col

add 2 Row

add 1 Row

add 2

DIN

tADL tADL

CHANGE WRITE

COLUMN command

Column address READ STATUS

command

Serial input

85h

tPROG or

tPROG_ECC

tWB tWHR

Don’t Care

Col

add 1 Col

add 2

DIN

Q70h Status

10h

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Figure 68: PROGRAM PAGE CACHE

WE#

CE#

ALE

CLE

RE#

RDY

I/Ox 15h

tCBSY

tWB tWB tWHR

tLPROG

Col

add 1

80h 10h 70h Status

Col

add 2 Row

add 2

Row

add 1

Col

add 1 Col

add 2 Row

add 2

Row

add 1 DIN

DIN

Last page - 1 Last page

Serial input

tWC

Don’t Care

80h

tADL

Figure 69: PROGRAM PAGE CACHE Ending on 15h

WE#

CE#

ALE

CLE

RE#

I/Ox 15h Col

add 1

80h 15h 70h Status 70h Status70h Status Col

add 2 Row

add 2

Row

add 1

Col

add 1 Col

add 2 Row

add 2

Row

add 1

DIN

Last pageLast page – 1

Serial input

tWC

Don’t Care

80h

Poll status until:

I/O6 = 1, Ready

To verify successful completion of the last 2 pages:

I/O5 = 1, Ready

I/O0 = 0, Last page PROGRAM successful

I/O1 = 0, Last page – 1 PROGRAM successful

tADL

tWHR tWHR

tADL

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Figure 70: INTERNAL DATA MOVE

WE#

CE#

ALE

CLE

RE#

RDY

I/Ox

tWB

tPROG or

tPROG_ECC

tWB

Busy Busy

READ STATUS

command

tWC

Don’t Care

tADL

tWHR

Col

add 2 Row

add 1 Row

add 2 70h10h Status

Data

Col

add 1

00h Col

add 2 Row

add 1 Row

add 2 35h

(or 30h) Col

add 1

85h Data

Data Input

Optional

Figure 71: ERASE BLOCK Operation

WE#

CE#

ALE

CLE

RE#

RDY

I/O[7:0]

READ STATUS

command

Busy

Row address

60h Row

add 1 Row

add 2 70h Status

D0h

tWC

tBERS

tWB tWHR

Don’t Care

I/O0 = 0, Pass

I/O0 = 1, Fail

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Revision History

Rev. S – 1/18

• Added Important Notes and Warnings section for further clarification aligning to in-

dustry standards

Rev. R – 10/14

• Updated the x8 and x16 Array Organization figures

Rev. Q – 06/14

• Updated the NAND Flash Die (LUN) Functional Block Diagram

Rev. P – 04/14

• Updated the ONFI statement in the READ PARAMETER PAGE (ECh) section

Rev. O – 03/14

• In Feature Operations section, updated Table 11: Feature Addresses 01h: Timing Mode

Rev. N – 01/14

• Updated Figure 1: Marketing Part Number Chart

• Updated Figure 35: READ PAGE (00h-30h) Operation with Internal ECC Enabled

Rev. M – 07/13

• Updated Block Lock Feature and Lock Tight in Block Lock Feature

Rev. L – 10/12

• Updated part number chart with option X for product longevity program (PLP) under

Special Options

Rev. K – 02/12

• Updated ISB2 spec in 3.3V DC Characteristics and Operating Conditions table

Rev. J – 12/11

• Updated 63-ball package dimension drawing

Rev. I – 11/11

• Command Definitions topic, Command Set table: Changed OTP DATA LOCK BY

BLOCK (ONFI) to OTP DATA LOCK BY PAGE (ONFI)

• One-Time Programmable (OTP) Operations topic, OTP DATA PROTECT (80h-10) sec-

tion: Updated content

Rev. H – 09/11

• Removed Note 2 from Valid Blocks table in Electrical Specifications

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Rev. G – 01/11

• Byte 58 of MT29F1G08ABADAWP updated from 33h to 57h in Parameter Page Data

Structure Table

Rev. F – 12/10

• Updated status bit 1 under Program Page in Status Operations

Rev. E – 11/10

• Production status

• Added Endurance spec to Features

• Removed the words "or by factory (always enabled)" from the General Description

Rev. D – 06/10

• Added block endurance info back in to Parameter Page Data Structure Table

Rev C – 04/10

• Added part numbers to document

• Removed Endurance spec from Features and Parameter Page Data Structure Table

• Updated values in Parameter Page Data Structure Table

• Corrected commands in OTP operations

Rev B – 03/10

• Corrected typo in DC Electrical Tables

• Corrected Error Management

Rev A – 02/10

• Initial release; Preliminary status

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Micron and the Micron logo are trademarks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.

Although considered final, these specifications are subject to change, as further product development and data characterization some-

times occur.

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