8255A 8255A Programmable Peripheral Interface iAPX86 Family MILITARY INFORMATION DISTINCTIVE CHARACTERISTICS @ SMD/DESC qualified Direct bit set/reset capability easing control application interface @ Reduces system package count @ Improved DC driving capability @ 24 programmable |/O pins Completely TTL-compatible Fully compatible with the iAPX86 microprocessor family Improved timing characteristics GENERAL DESCRIPTION The 8255A is a general-purpose, programmable I/O device designed for use with iAPX Family microprocessors. It has 24 1/0 pins which may be individually programmed in two groups of twelve, and used in three major modes of operation. in the first mode, each group of twelve I/O pins may be programmed in sets of four and eight to be input or output. In Mode 1, the second mode, each group may be programmed to have eight lines of input or output. Of the remaining four pins, three are used for handshaking and interrupt control signals. The third mode of operation (Mode 2) is a bidirectional bus mode which uses eight lines for a bidirectional bus, and five lines, borrowing one from the other group, for handshaking. BLOCK DIAGRAM POWER +5V GROUP SUPPLIES | ___. enn Group = pont ie ~l oa C A PA7-PAy CONTROL (8) - GROUP A ALN 10 cS PORT C cc PC;-PC, UPPER (4) 4 BrOIRECTIONAL BUS] D7-Dp BUS K BUFFER 8-BIT INTERNAL DATA BUS GROUP KY vores Ke LOWER 3PCo (4) 4 RB -O WRO} AEAD/ GROUP GRouP A =] orn. Broth KCN ede (Sto PORT > Ay Loic CONTROL , Pe,-PB RESET ~ (8) BD003600 Publication # Rev. Amendment 07912 B 10 3-54 Issue Date: November 1987CONNECTION DIAGRAM Top View PA, jie \/ 40 {) PA, PA, LC] 2 39 [7] Pa, PA, (~13 38 [[] PA, Pay C4 37 [77 Pa; fo C5 36 [7] WA ts Cy6 35 [[] RESET GND C1] 7 34 [-10, A, C]8 33 (7), 4,0]9 32 { J] 0. Pe, [J 10 31 [7 Dg Pe, (11 30[[) b, Pc, [12 29 [1 Ds ec, (7) 13 28 [[) 0, PC, (J 14 27 {1} o; pe, (415 26 [7 Voc Pc, (_) 16 25 [] P68, Pe; (J 17 24 [} PBs PB, (J 18 23 [J PBs PB, (J 19 22 [) Pe, PB 20 21[7) PB, cD005401 Note: Pin 1 is marked for orientation. MILITARY ORDERING INFORMATION Standard Military Drawing (SMD)/DESC Products AMD products for Aerospace and Defense applications are available in several packages and operating ranges. Standard Military Drawing (SMD)/DESC products are fully compliant with MIL-STD-883C requirements. The order number (Valid Combination) for SMD/DESC products is formed by a combination of: a. Military Drawing Part Number b. Device Type c. Case Outline d. Lead Finish xX a. MILITARY DRAWING NO./DESCRIPTION 5962-87570 Programmable Peripheral Interface Valid Combinations 5962-8757001 Qx 962-8757002 5962-87570 OL Q x | LEAD FINISH X= Any Lead Finish Acceptable c. CASE OUTLINE Q = 40-Pin Ceramic DIP (CD 040) b. MILITARY DEVICE TYPE 01 = 2.5 MHz (8255A) 02 = 3.3 MHz (8255-5) Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations or to check for newly released valid combinations. Group A Tests Group A tests consist of Subgroups 1, 2, 3, 7, 8, 9, 10, 11. vssce8255A MILITARY ORDERING INFORMATION (Cont'd.) APL Products AMD products for Aerospace and Defense applications are available in several packages and operating ranges. APL (Approved Products List) products are fully compliant with MIL-STD-883C requirements. The order number (Valid Combination) for APL products is formed by a combination of: a. Device Number b. Speed Option (if applicable) c. Device Class d. Package Type e. Lead Finish B255A -5 /B Q A [| LEAD FINISH A=Hot Solder Dip d. PACKAGE TYPE Q = 40-Pin Ceramic DIP (CD 040) c. DEVICE CLASS /B=Class B b. SPEED OPTION Blank = 2.5 MHz -5 =3.9 MHz a. DEVICE NUMBER/DESCRIPTION 8255A Programmable Peripheral interface Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations or to check for newly released valid Valid Combinations combinations. 8255A 8255A-5 /BOA Group A Tests Group A tests consist of Subgroups 1, 2, 3, 7, 8, 9, 10, 11. 3-56ABSOLUTE MAXIMUM RATINGS Storage Temperature 0.00.00... .cccececeeeeees -65 to + 150C Vcc with Respect to Vgg -0.5 to 7.0 V All Signal Voltages with Respect to Vgg ......0.....cccceeeee -0.5 to +7.0 Vv Power Dissipation .......000000. 00 ccccccececcccsccceeececeeeeee 10W Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. 3 are tested unless otherwise noted} OPERATING RANGES Military (M) Devices Temperature (TC) .... 20.00 eecccceeeccceeeee -55 to 125C Supply Voltage (VoC) .......0ccceeeeeeseccevseees 5V + 10% Operating ranges define those limits between which the functionality of the device is guaranteed. DC CHARACTERISTICS over operating range (for SMD/DESC and APL Preducts, Group A, Subgroups 1, 2, Parameter Parameter Symbol Description Test Conditions Min. Max. Unit Virt Input Low Voltage Voc = 4.5 V ~0.5* 0.8 Vv Vint Input High Voltage Voc = 5.5 V 2.2 5.5* v Va_(DB) Output Low Voltage (Data Bus) lo. =2.5 mA, Voc = 5.5 V 0.45 v Vor(PER) Output Low Voltage (Peripheral Port) lo. = 1.7 MA, Voc = 5.5 V 0.45 v VonH(DB) Output High Voltage (Data Bus) low = -400 BA, Voc = v VoH(PER) Output High Voltage (Peripheral Port) 1on = - 20 c= 2.4 v lDAR Darlington Drive Current (Note 1) Ri = EXT = 1 -1.0 -4.0 mA icc Power Supply Current (Not (er P 120 mA Ue Input Load Curr cc to 0 V, Vog = 5.5 V 10 BA lOFL Outpyt aheoe Vout = Vcc to 0 V, Veco =5.5 V +10 BA CAPACITANCE ='GND = 0 V Parameter Parameter Symbol Description Test Conditions Min. Typ. Max. Unit Cintt Input Capacitance fe = 1 MHz 15 pF Cott \/O Capacitance Unmeasured pins returned to GND 25 pF Guaranteed by design; not tested. tGroup A, Subgroups 9, 10, 11 only are tested. ttNot included in Group A tests. Notes: 1. Available on any 8 pins from Port B and C. 2. Ic test conditions: the supply current is measured with loaded outputs while running AC patterns. SWITCHING TEST CIRCUIT TCO03850 This test circuit is the dynamic load of a Teradyne J941. 2.4 SWITCHING TEST WAVEFORM 20 rest _ = 2.0 ous og <~ POINTS~w. og AC testing: Inputs are driven at 2.4 V for a logic "1" and 0.45 V for a logic ''0." Timing measurements are made at 2.0 V for a logic "1" and 0.8 V for a logic ''0."" WF006351 See Section 6 of the MOS Micraprocessors and Peripherals Data Book {Order #09067A) for Thermat Characteristics Information. 3-57 vssze8255A SWITCHING CHARACTERISTICS over operating range (for SMD/DESC and APL Products, Group A, Subgroups 9, 10, 11 are tested unless otherwise noted) (Note 1) BUS PARAMETERS Parameter Parameter 82554 B255A-5 No. Symbol Description Min. Max. Min. Max. Unit READ 1 |tar Address Stable Before READ 0 0 ns 2 |tra Address Stable After READ 0 0 ns 3 /trR READ Pulse Width 300 300 ns 4 |trp Data Valid From READ (Note 1) 250 200 ns 5 |tpr Data Float After READ (Note 3) 10 150 10 100 ns 6 |trv Time Between READs and/or WRITEs B50 850 ns WRITE 7 |taw Address Stable Before WRITE 0 0 ns B itwa Address Stable After WRITE 20 20 ns 9 Itww WRITE Pulse Width 40) 300 ns 10 Itow Data Valid to WRITE (T.E.) 100 ns 11 Ftwo Data Valid After WRITE 30 ns OTHER TIMINGS 12 |twe WR = 1 to Output (Note 1) 350 350 ns 13 /trR Peripheral Data Before RD 0 0 ns 14 |tur Peripheral Data After RD 0 0 ns 15 |tak ACK Pulse Width . 300 300 ns 16 |tst STB Pulse Width , 500 500 ns 17 |tps 0 0 ns 18 |tpH 180 180 ns 19 |tap 300 300 ns 20 |tkp 20 250 20 250 ns 21 | twos WR =1 to OBF =0 (Note 1) 650 650 ns 22 | tacos ACK =0 to OBF =1 (Note 1) 350 350 ns 23 | tsiB STB =0 to IBF = 1 (Note 1} 300 300 ns 24 | trip RD =1 to IBF =0 (Note 1) 300 300 ns 25 | trit RD =0 to INTR =0 (Note 1) 400 400 ns 26 | tsit STB =1 to INTR=1 (Note 1) 300 300 ns 27 | talT ACK =1 to INTR=1 (Note 1) 350 350 ns 28 | twit WR = 1 to INTR =0 (Note 1) 450 450 ns Notes: 1. Test Conditions: Voc = 5.5 V and 4.5 V, Vi =2.4 V, ViL=.45 V, VoH =2.0 V, VoL =.8 V, C_=100 pF + 2. Perod of Reset pulse must be at least 50 ys during or after power on. Subsequent Reset pulse can be 500 ns min. 3. AC float timing parameters tpF and tkp are tested Logic 0 to float only. e wh