Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN74AVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES156E – DECEMBER 1998 – REVISED DECEMBER 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus
Family
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
DOC
(Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
D
Dynamic Drive Capability Is Equivalent to
Standard Outputs With IOH and IOL of
±24 mA at 2.5-V VCC
D
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
D
Ioff Supports Partial-Power-Down Mode
Operation
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and Thin Very
Small-Outline (DGV) Packages
description
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports,
AVC
Logic Family Technology and Applications
, literature number SCEA006, and
Dynamic Output Control (DOC
)
Circuitry Technology and Applications
, literature number SCEA009.
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
1531361191028568513417
TA = 25°C
Process = Nominal
IOL – Output Current – mA
VCC = 3.3 V
VCC = 2.5 V
VCC = 1.8 V
– Output Voltage – V
OL
V
2.8
2.4
2.0
1.6
1.2
0.8
0.4
–32
–48
–64–80–96–112–128
–144 –16
TA = 25°C
Process = Nominal
IOH – Output Current – mA
VCC = 3.3 V VCC = 2.5 V
VCC = 1.8 V
– Output Voltage – V
OH
V
1700 0
–160
Figure 1. Output Voltage vs Output Current
This 16-bit transparent D-type latch is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V
to 3.6-V VCC operation.
The SN74AVC16373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the
latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs
are latched at the levels set up at the D inputs.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1999, Texas Instruments Incorporated
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
SN74AVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES156E – DECEMBER 1998 – REVISED DECEMBER 1999
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly . The high-impedance state and the increased drive provide the capability to drive bus
lines without need for interface or pullup components. OE does not affect internal operations of the latch. Old
data can be retained or new data can be entered while the outputs are in the high-impedance state.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74AVC16373 is characterized for operation from –40°C to 85°C.
terminal assignments
DGG OR DGV PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
SN74AVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES156E – DECEMBER 1998 – REVISED DECEMBER 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
(each 8-bit latch)
INPUTS OUTPUT
OE LE DQ
L H H H
LHL L
LLX Q
0
H X X Z
logic symbol†
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
1OE
2OE
1EN
1
C3
48
1LE
3D
47
1D1 46
1D2 44
1D3 43
1D4
1Q1
2
1Q2
3
1Q3
5
1Q4
6
41
1D5 40
1D6 38
1D7 37
1D8
1Q5
8
1Q6
9
1Q7
11
1Q8
12
4D
36
2D1 35
2D2 33
2D3 32
2D4
2Q1
13
2Q2
14
2Q3
16
2Q4
17
30
2D5 29
2D6 27
2D7 26
2D8
2Q5
19
2Q6
20
2Q7
22
2Q8
23
2EN
24
C4
25
2LE
1
2
logic diagram (positive logic)
1OE
1LE
1D1
To Seven Other Channels
1Q1
2OE
2LE
2D1 2Q1
To Seven Other Channels
1
48
47
24
25
36 C1
1D 132
C1
1D
SN74AVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES156E – DECEMBER 1998 – REVISED DECEMBER 1999
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): DGG package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
SN74AVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES156E – DECEMBER 1998 – REVISED DECEMBER 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
MIN MAX UNIT
VCC
Su
pp
ly voltage
Operating 1.4 3.6
V
V
CC
S
u
ppl
y v
oltage
Data retention only 1.2
V
VCC = 1.2 V VCC
VCC = 1.4 V to 1.6 V 0.65 ×VCC
VIH High-level input voltage VCC = 1.65 V to 1.95 V 0.65 ×VCC V
VCC = 2.3 V to 2.7 V 1.7
VCC = 3 V to 3.6 V 2
VCC = 1.2 V GND
VCC = 1.4 V to 1.6 V 0.35 ×VCC
VIL Low-level input voltage VCC = 1.65 V to 1.95 V 0.35 ×VCC V
VCC = 2.3 V to 2.7 V 0.7
VCC = 3 V to 3.6 V 0.8
VIInput voltage 0 3.6 V
VO
Out
p
ut voltage
Active state 0 VCC
V
V
O
O
u
tp
u
t
v
oltage
3-state 0 3.6
V
†
VCC = 1.4 V to 1.6 V –2
IOHS
Static high level out
p
ut current†
VCC = 1.65 V to 1.95 V –4
mA
I
OHS
Static
high
-
le
v
el
o
u
tp
u
t
c
u
rrent†
VCC = 2.3 V to 2.7 V –8
mA
VCC = 3 V to 3.6 V –12
†
VCC = 1.4 V to 1.6 V 2
IOLS
Static low level out
p
ut current†
VCC = 1.65 V to 1.95 V 4
mA
I
OLS
Static
lo
w-
le
v
el
o
u
tp
u
t
c
u
rrent†
VCC = 2.3 V to 2.7 V 8
mA
VCC = 3 V to 3.6 V 12
∆t/∆vInput transition rise or fall rate VCC = 1.4 V to 3.6 V 5 ns/V
TAOperating free-air temperature –40 85 °C
†Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and VOH vs IOH
characteristics. Refer to the TI application reports,
AVC Logic Family Technology and Applications
, literature number SCEA006, and
Dynamic Output Control (DOC
) Circuitry T echnology and Applications
, literature number SCEA009.
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
SN74AVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES156E – DECEMBER 1998 – REVISED DECEMBER 1999
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP†MAX UNIT
IOHS = –100 µA1.4 V to 3.6 V VCC–0.2
IOHS = –2 mA, VIH = 0.91 V 1.4 V 1.05
VOH IOHS = –4 mA, VIH = 1.07 V 1.65 V 1.2 V
IOHS = –8 mA, VIH = 1.7 V 2.3 V 1.75
IOHS = –12 mA, VIH = 2 V 3 V 2.3
IOLS = 100 µA1.4 V to 3.6 V 0.2
IOLS = 2 mA, VIL = 0.49 V 1.4 V 0.4
VOL IOLS = 4 mA, VIL = 0.57 V 1.65 V 0.45 V
IOLS = 8 mA, VIL = 0.7 V 2.3 V 0.55
IOLS = 12 mA, VIL = 0.8 V 3 V 0.7
IIControl inputs VI = VCC or GND 3.6 V ±2.5 µA
Ioff VI or VO = 3.6 V 0±10 µA
IOZ VO = VCC or GND 3.6 V ±10 µA
ICC VI = VCC or GND, IO = 0 3.6 V 40 µA
Control in
p
uts
VI=V
CC or GND
2.5 V 3
Ci
Control
inp
u
ts
V
I =
V
CC
or
GND
3.3 V 3p
F
C
i
Data in
p
uts
VI=V
CC or GND
2.5 V 2.5
pF
Data
inp
u
ts
V
I =
V
CC
or
GND
3.3 V 2.5
Co
Out
p
uts
VO=V
CC or GND
2.5 V 6.5 p
F
C
o
Out uts
VO
=
VCC
or
GND
3.3 V 6.5
F
†Typical values are measured at VCC = 2.5 V and 3.3 V, TA = 25°C.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 2 through 5)
VCC = 1.2 V VCC = 1.5 V
± 0.1 V VCC = 1.8 V
± 0.15 V VCC = 2.5 V
± 0.2 V VCC = 3.3 V
± 0.3 V UNIT
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
twPulse duration, LE high 2.2 2 1.8 ns
tsu Setup time, data before LE↓1.7 1.2 1.1 0.9 0.8 ns
thHold time, data after LE↓2 1.1 1.1 1.1 1 ns
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 5)
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.2 V VCC = 1.5 V
± 0.1 V VCC = 1.8 V
± 0.15 V VCC = 2.5 V
± 0.2 V VCC = 3.3 V
± 0.3 V UNIT
(INPUT)
(OUTPUT)
TYP MIN MAX MIN MAX MIN MAX MIN MAX
td
D
Q
5.8 1.2 6.8 1 5.7 0.8 3.3 0.7 2.8
ns
t
pd LE
Q
7.2 1.4 8.3 1.1 6.6 0.8 4 0.7 3.2
ns
ten OE Q 7.4 1.6 8.8 1.6 6.7 1.4 4.3 0.7 3.4 ns
tdis OE Q 8.4 2.5 9.4 2.3 7.8 1.3 4.2 1.2 3.9 ns
SN74AVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES156E – DECEMBER 1998 – REVISED DECEMBER 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics, TA = 25°C
PARAMETER
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
UNIT
PARAMETER
TYP TYP TYP
UNIT
Cd
Power dissipation Outputs enabled
CL=0
f=10MHz
40 43 47 p
F
C
pd capacitance Outputs disabled
C
L =
0
,
f
=
10
MH
z20 22 24
pF
PARAMETER MEASUREMENT INFORMATION
VCC = 1.2 V AND 1.5 V ± 0.1 V
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
VOH
VOL
th
tsu
From Output
Under Test
CL = 15 pF
(see Note A)
LOAD CIRCUIT
S1 Open
GND
2 kΩ
2 kΩ
Output
Control
(low-level
enabling)
Output
W aveform 1
S1 at 2 × VCC
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + 0.1 V
VOH – 0.1 V
0 V
VCC
0 V
0 V
tw
VCC VCC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2 ns, tf ≤2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
0 V
VCC
VCC/2
tPHL
VCC/2 VCC/2 VCC
0 V
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
tPLH
2 × VCC
VCC
Figure 2. Load Circuit and Voltage Waveforms
SN74AVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES156E – DECEMBER 1998 – REVISED DECEMBER 1999
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
VOH
VOL
th
tsu
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1 Open
GND
1 kΩ
1 kΩ
Output
Control
(low-level
enabling)
Output
W aveform 1
S1 at 2 × VCC
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + 0.15 V
VOH – 0.15 V
0 V
VCC
0 V
0 V
tw
VCC VCC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
0 V
VCC
VCC/2
tPHL
VCC/2 VCC/2 VCC
0 V
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
tPLH
2 × VCC
VCC
Figure 3. Load Circuit and Voltage Waveforms
SN74AVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES156E – DECEMBER 1998 – REVISED DECEMBER 1999
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
VOH
VOL
th
tsu
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1 Open
GND
500 Ω
500 Ω
Output
Control
(low-level
enabling)
Output
W aveform 1
S1 at 2 × VCC
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + 0.15 V
VOH – 0.15 V
0 V
VCC
0 V
0 V
tw
VCC VCC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤2 ns, tf ≤2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
0 V
VCC
VCC/2
tPHL
VCC/2 VCC/2 VCC
0 V
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
tPLH
2 × VCC
VCC
Figure 4. Load Circuit and Voltage Waveforms
SN74AVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES156E – DECEMBER 1998 – REVISED DECEMBER 1999
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ±0.3 V
VOH
VOL
th
tsu
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1 2 × VCC
Open
GND
500 Ω
500 Ω
tPLH tPHL
Output
Control
(low-level
enabling)
Output
W aveform 1
S1 at 2 × VCC
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
VCC
0 V
VOH
VOL
0 V
VOL + 0.3 V
VOH – 0.3 V
0 V
VCC
0 V
0 V
VCC
0 V
tw
Input
VCC VCC
VCC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Output
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
VCC/2
VCC/2 VCC/2
VCC/2 VCC/2
VCC/2 VCC/2
VCC/2 VCC/2
VCC/2 VCC/2
VCC/2
VCC/2
Figure 5. Load Circuit and Voltage Waveforms
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