1
FEATURES
APPLICATIONS
RELATED DEVICES
DESCRIPTION/ORDERING INFORMATION
ADS5424-SP
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....................................................................................................................................................................................................... SLWS194 – MAY 2008
RAD-TOLERANT CLASS V, 14 BIT, 105 MSPS,ANALOG-TO-DIGITAL CONVERTER
•14 Bit Resolution •Military Temperature Range ( – 55 °C to 125 °CT
case
)•105 MSPS Maximum Sample Rate
•Rad-Tolerant : 100 kRad (Si) TID•SNR = 70 dBc at 105 MSPS and 50 MHz IF
•QML-V Qualified, SMD 5962-07206•SFDR = 78 dBc at 105 MSPS and 50 MHz IF•2.2 V
PP
Differential Input Range•5 V Supply Operation
•Single and Multichannel Digital Receivers•3.3 V CMOS Compatible Outputs
•Base Station Infrastructure•2.3 W Total Power Dissipation
•Instrumentation•2s Complement Output Format
•Video and Imaging•On-Chip Input Analog Buffer, Track and Hold,and Reference Circuit
•Clocking: CDC7005•52-Pin Ceramic Nonconductive Tie-BarPackage (HFG)
•Amplifiers: OPA695, THS4509
The ADS5424 is a 14 bit 105 MSPS analog-to-digital converter (ADC) that operates from a 5 V supply, whileproviding 3.3 V CMOS compatible digital outputs. The ADS5424 input buffer isolates the internal switching of theon-chip track and hold (T&H) from disturbing the signal source. An internal reference generator is also providedto further simplify the system design. The ADS5424 has outstanding low noise and linearity, over inputfrequency. With only a 2.2 V
PP
input range, ADS5424 simplifies the design of multicarrier applications, where thecarriers are selected on the digital domain.
The ADS5424 is available in a 52-pin ceramic nonconductive tie-bar package (HFG). The ADS5424 is built onstate of the art Texas Instruments complementary bipolar process (BiCom3) and is specified over full militarytemperature range ( – 55 °C to 125 °C T
case
)
Table 1. ORDERING INFORMATION
(1)
T
A
PACKAGE
(2)
ORDERING PART NUMBER TOP-SIDE MARKING
5962-0720601VXC– 55 °C to 125 °C T
case
52/ HFG 5962-0720601VXC
ADS5424MHFG-V
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com.(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
Reference
Timing
CLK+
OVR D[13:0]
CLK−
6
DMID DRY
VREF
AIN
AIN TH1
5 5
Σ
DAC2ADC2
ADC3
Σ
DAC1ADC1
A3
A1 TH2 TH3
C1
C2
AVDD DRVDD
GND
Digital Error Correction
A2
+
−
+
−
ABSOLUTE MAXIMUM RATINGS
ADS5424-SP
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
FUNCTIONAL BLOCK DIAGRAM
over operating temperature range (unless otherwise noted)
(1)
ADS5424 UNIT
AV
DD
to GND 6Supply voltage VDRV
DD
to GND 5Analog input to GND – 0.3 V to AV
DD
+ 0.3 VClock input to GND – 0.3 V to AV
DD
+ 0.3 VCLK to CLK ± 2.5 VDigital data output to GND – 0.3 V to DRV
DD
+ 0.3 VT
C
Characterized case operating temperature range – 55 °C to 125 °CT
J
Maximum junction temperature 150 °CT
stg
Storage temperature range – 65 °C to 150 °C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods maydegrade device reliability. These are stress ratings only and functional operation of the device at these or any other conditions beyondthose specified is not implied.
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RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS (Unchanged after 100 kRad)
ADS5424-SP
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....................................................................................................................................................................................................... SLWS194 – MAY 2008
MIN NOM MAX UNIT
SUPPLIES
AV
DD
Analog supply voltage 4.75 5 5.25 VDRV
DD
Output driver supply voltage 3 3.3 3.6 V
ANALOG INPUT
Differential input range 2.2 V
PP
V
CM
Input common mode voltage 2.4 V
DIGITAL OUTPUT
Maximum output load 10 pF
CLOCK INPUT
ADCLK input sample rate (sine wave) 30 105 MSPSClock amplitude, differential sine wave 3 V
PP
Clock duty cycle 50%T
C
Open case temperature range – 55 125 °C
Typical values at T
C
= 25 °C, Over full temperature range is T
C,MIN
= – 55 °C to T
C,MAX
= 125 °C, sampling rate = 105 MSPS,50% clock duty cycle, AV
DD
= 5 V, DRV
DD
= 3.3 V, – 1 dBFS differential input, and 3-V
PP
sinusoidal clock (unless otherwisenoted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 14 Bits
ANALOG INPUTS
Differential input range 2.2 V
pp
Differential input resistance See Figure 11 1 k Ω
Differential input capacitance See Figure 11 1.5 pFAnalog input bandwidth 570 MHz
INTERNAL REFERENCE VOLTAGES
V
REF
Reference voltage 2.38 2.4 2.41 V
DYNAMIC ACCURACY
No missing codes TestedDNL Differential linearity error f
IN
= 10 MHz – 0.98 ± 0.5 1.5 LSBT
C
= 25 °C andf
IN
= 10 MHz – 5.0 ± 3.0 +5.0 LSBT
C,MAXINL Integral linearity error
f
IN
= 10 MHz T
C
= T
C,MIN
– -6.9 +6.9 LSBOffset error – 1.5 0 1.5 %FSOffset temperature coefficient 0.0007 %FS/ °CGain error – 5 0.9 5 %FSGain temperature coefficient 0.006 %FS/ °C
POWER SUPPLY
V
IN
= full scale, f
IN
= 70I
AVDD
Analog supply current F
S
= 105 MSPS 355 410 mAMHz
V
IN
= full scale, f
IN
= 70I
DRVDD
Output buffer supply current F
S
= 105 MSPS 47 55 mAMHz
Total power with 10-pFPower dissipation load on each digital output F
S
= 105 MSPS 1.9 2.3 Wto ground, f
IN
= 70 MHzPower-up time F
S
= 105 MSPS 20 ms
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ELECTRICAL CHARACTERISTICS (Unchanged after 100 kRad) (continued)Typical values at T
C
= 25 °C, Over full temperature range is T
C,MIN
= – 55 °C to T
C,MAX
= 125 °C, sampling rate = 105 MSPS,50% clock duty cycle, AV
DD
= 5 V, DRV
DD
= 3.3 V, – 1 dBFS differential input, and 3-V
PP
sinusoidal clock (unless otherwisenoted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DYNAMIC AC CHARACTERISTICS
T
C
= 25 °C 70.5 72.4f
IN
= 10 MHz T
C
= T
C,MAX
71.0T
C
= T
C,MIN
70.5f
IN
= 30 MHz Full Temp Range 70.0 71.5f
IN
= 50 MHz 70.9SNR Signal-to-noise ratio T
C
= 25 °C 68.2 70.1 dBcf
IN
= 70 MHz T
C
= T
C,MAX
67.0T
C
= T
C,MIN
68.0f
IN
= 100 MHz 68.9f
IN
= 170 MHz 66.3f
IN
= 230 MHz 64.0T
C
= 25 °C 72.0 81.6f
IN
= 10 MHz
Full Temp Range 71.0T
C
= 25 °C 77.0 80.6f
IN
= 30 MHz T
C
= T
C,MAX
69.0T
C
= T
C,MIN
75.0f
IN
= 50 MHz 78.1SFDR Spurious free dynamic range dBcT
C
= 25 °C 68.0 82.6f
IN
= 70 MHz T
C
= T
C,MAX
69.0T
C
= T
C,MIN
67.0f
IN
= 100 MHz 82.5f
IN
= 170 MHz 68.0f
IN
= 230 MHz 65.4T
C
= 25 °C 68.6 71.3f
IN
= 10 MHz T
C
= T
C,MAX
68.3T
C
= T
C,MIN
68.2T
C
= 25 °C 69.4 70.2f
IN
= 30 MHz T
C
= T
C,MAX
67.0T
C
= T
C,MIN
69.4SINAD Signal-to-noise + distortion f
IN
= 50 MHz 69.9 dBcT
C
= 25 °C 65.8 69.7f
IN
= 70 MHz T
C
= T
C,MAX
64.6T
C
= T
C,MIN
65.0f
IN
= 100 MHz 68.6f
IN
= 170 MHz 64.0f
IN
= 230 MHz 61.1
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ELECTRICAL CHARACTERISTICS (Unchanged after 100 kRad) (continued)Typical values at T
C
= 25 °C, Over full temperature range is T
C,MIN
= – 55 °C to T
C,MAX
= 125 °C, sampling rate = 105 MSPS,50% clock duty cycle, AV
DD
= 5 V, DRV
DD
= 3.3 V, – 1 dBFS differential input, and 3-V
PP
sinusoidal clock (unless otherwisenoted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
T
C
= 25 °C 72.0 81.8f
IN
= 10 MHz
Full Temp Range 71.0T
C
= 25 °C 77.0 80.6f
IN
= 30 MHz T
C
= T
C,MAX
69.0T
C
= T
C,MIN
75.0f
IN
= 50 MHz 86.5HD2 Second harmonic dBcT
C
= 25 °C 68.0 85.0f
IN
= 70 MHz T
C
= T
C,MAX
69.0T
C
= T
C,MIN
67.0f
IN
= 100 MHz 86.1f
IN
= 170 MHz 93.0f
IN
= 230 MHz 71.0T
C
= 25 °C 72.0 81.6f
IN
= 10 MHz
Full Temp Range 71.0T
C
= 25 °C 77.0 81.3f
IN
= 30 MHz T
C
= T
C,MAX
69.0T
C
= T
C,MIN
75.0f
IN
= 50 MHz 78.1HD3 Third harmonic dBcT
C
= 25 °C 68.0 82.6f
IN
= 70 MHz T
C
= T
C,MAX
69.0T
C
= T
C,MIN
67.0f
IN
= 100 MHz 83.3f
IN
= 170 MHz 68.0f
IN
= 230 MHz 65.4f
IN
= 10 MHz Full Temp Range 75.0 85.5T
C
= 25 °C 80.0 83.8f
IN
= 30 MHz T
C
= T
C,MAX
74.0T
C
= T
C,MIN
80.0f
IN
= 50 MHz 87.0Worst other harmonic/spur (other than
T
C
= 25 °C 74.0 83.0 dBcHD2 and HD3)
f
IN
= 70 MHz T
C
= T
C,MAX
72.0T
C
= T
C,MIN
74.0f
IN
= 100 MHz 82.5f
IN
= 170 MHz 79.8f
IN
= 230 MHz 78.0
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DIGITAL CHARACTERISTICS (Unchanged after 100 kRad)
ADS5424-SP
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ELECTRICAL CHARACTERISTICS (Unchanged after 100 kRad) (continued)Typical values at T
C
= 25 °C, Over full temperature range is T
C,MIN
= – 55 °C to T
C,MAX
= 125 °C, sampling rate = 105 MSPS,50% clock duty cycle, AV
DD
= 5 V, DRV
DD
= 3.3 V, – 1 dBFS differential input, and 3-V
PP
sinusoidal clock (unless otherwisenoted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
T
C
= 25 °C 71.0 77.8f
IN
= 10 MHz
Full Temp Range 70.0T
C
= 25 °C 75.0 77.4f
IN
= 30 MHz T
C
= T
C,MAX
68.0T
C
= T
C,MIN
73.8f
IN
= 50 MHz 76.7THD Total harmonic distortion dBCT
C
= 25 °C 67.4 79.6f
IN
= 70 MHz T
C
= T
C,MAX
67.2T
C
= T
C,MIN
66.4f
IN
= 100 MHz 79.9f
IN
= 170 MHz 67.6f
IN
= 230 MHz 64.1T
C
= 25 °C 11.1 11.7f
IN
= 10 MHz T
C
= T
C,MAX
11.0T
C
= T
C,MIN
11.0T
C
= 25 °C 11.2 11.5ENOB Effective number of bits f
IN
= 30 MHz T
C
= T
C,MAX
10.8 BitsT
C
= T
C,MIN
11.2T
C
= 25 °C 10.6 11.4f
IN
= 70 MHz T
C
= T
C,MAX
10.4T
C
= T
C,MIN
10.5RMS idle channel noise Input pins tied together 0.9 LSB
Typical values at T
C
= 25 °C, Over full temperature range is T
C,MIN
= – 55 °C to T
C,MAX
= 125 °C, AV
DD
= 5 V, DRV
DD
= 3.3 V(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Digital Outputs
Low-level output voltage C
LOAD
= 10 pF
(1)
0.1 0.6 VHigh-level output voltage C
LOAD
= 10 pF
(1)
2.6 3.2 VOutput capacitance 3 pFDMID 1.65 1.8 V
(1) Equivalent capacitance to ground of (load + parasitics of transmission lines)
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TIMING CHARACTERISTICS
(1)
(Unchanged after 100 kRad)
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Typical values at T
C
= 25 °C, Over full temperature range, AV
DD
= 5 V, DRV
DD
= 3.3 V, sampling rate = 105 MSPS
PARAMETER MI TYP MAX UNITN
Aperture Time
t
A
Aperture delay 500 pst
J
Clock slope independent aperture uncertainty (jitter) 150 fsk
J
Clock slope dependent jitter factor 50 µV
Clock Input
t
CLK
Clock period 9.5 nst
CLKH
Clock pulse width high 4.75 nst
CLKL
Clock pulse width low 4.75 ns
Clock to DataReady (DRY)
t
DR
Clock rising 50% to DRY falling 50% 2.2 3.0 4.7 nst
DR
+t
C_DR
Clock rising 50% to DRY rising 50% nst
CLKH
t
C_DR_50%
Clock rising 50% to DRY rising 50% with 50% duty cycle
7.0 7.8 9.5 nsclock
Clock to DATA, OVR
(2)
t
r
Data V
OL
to data V
OH
(rise time) 0.6 nst
f
Data V
OH
to data V
OL
(fall time) 0.6 ns
CyclL Latency 3
esValid DATA
(3)
to clock 50% with 50% duty cycle clockt
su_c
1.8 3.6 ns(setup time)t
h_c
Clock 50% to invalid DATA
(3)
(hold time) 2.6 4.1 ns
DataReady (DRY)/DATA, OVR
(2)
Valid DATA
(3)
to DRY 50% with 50% duty cycle clockt
su(DR)_50%
0.9 1.40 ns(setup time)DRY 50% to invalid DATA
(3)
with 50% duty cycle clockt
h(DR)_50%
3.9 6.3 ns(hold time)
(1) All values obtained from design and characterization.(2) Data is updated with clock rising edge or DRY falling edge.(3) See V
OH
and V
OL
levels.
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N
N+1
N+2
N+3
N+4
NN−1N−2N−3
tA
tsu(C) th(C)
th(DR)
N + 1
NN + 2 N + 3 N + 4
tC_DR
tr
tCLK tCLKL
CLK, CLK
D[13:0], OVR
DRY
AIN
tCLKH
tDR
tsu(DR)
tf
ADS5424-SP
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Figure 1. Timing Diagram
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DEVICE INFORMATION
15 16
D3
D2
D1
D0(LSB)
DMID
GND
DRVDD
OVR
DNC
AVDD
GND
AVDD
GND
39
38
37
36
35
34
33
32
31
30
29
28
27
17
1
2
3
4
5
6
7
8
9
10
11
12
13
DRVDD
GND
VREF
GND
CLK
CLK
GND
AVDD
AVDD
GND
AIN
AIN
GND
18 19 20 21
HFGPACKAGE
(TOP VIEW)
51 50 49 48 47
52 46 44 43 42
45
22 23 24 25 26
41 40
14
DRY
D13(MSB)
D12
D11
D10
D9
D8
D7
D6
DRVDD
GND
D5
D4
AVDD
GND
AVDD
GND
AVDD
GND
C1
GND
AVDD
GND
C2
GND
AVDD
ADS5424-SP
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TERMINAL FUNCTIONS
TERMINAL
DESCRIPTIONNAME NO.
DRV
DD
1, 33, 43 3.3 V power supply, digital output stage only2, 4, 7, 10, 13, 15, 17,GND 19, 21, 23, 25, 27, 29, Ground34, 42VREF 3 2.4 V reference. Bypass to ground with a 0.1 µF microwave chip capacitor.CLK 5 Clock input. Conversion initiated on rising edgeCLK 6 Complement of CLK, differential input8, 9, 14, 16, 18, 22, 26,AV
DD
5 V analog power supply28, 30AIN 11 Analog inputAIN 12 Complement of AIN, differential analog inputC1 20 Internal voltage reference. Bypass to ground with a 0.1 µF chip capacitor.C2 24 Internal voltage reference. Bypass to ground with a 0.1 µF chip capacitor.DNC 31 Do not connectOVR 32 Overrange bit. A logic level high indicates the analog input exceeds full scale.DMID 35 Output data voltage midpoint. Approximately equal to (DV
CC
)/2D0 (LSB) 36 Digital output bit (least significant bit); two's complementD1 – D5, D6 – D12 37 – 41, 44 – 50 Digital output bits in two's complementD13 (MSB) 51 Digital output bit (most significant bit); two's complementDRY 52 Data ready output
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THERMAL CHARACTERISTICS
THERMAL NOTES
1.00
10.00
100.00
1000.00
80 90 100 110 120 130 140 150 160 170 180
Continuous Tj (°C)
Years estimated life
Electromigration Fail Mode
ADS5424-SP
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PARAMETER TEST CONDITIONS TYP UNIT
R
θJA
Junction-to-free-air thermal resistance Board Mounted, Per JESD 51-5 methodology 21.81 °C/WR
θJC
Junction-to-case thermal resistance MIL-STD-883 Test Method 1012 0.849 °C/W
This CQFP package has built-in vias that electrically and thermally connect the bottom of the die to a pad on thebottom of the package. To efficiently remove heat and provide a low-impedance ground path, a thermal land isrequired on the surface of the PCB directly underneath the body of the package. During normal surface mountflow solder operations, the heat pad on the underside of the package is soldered to this thermal land creating anefficient thermal path. Normally, the PCB thermal land has a number of thermal vias within it that provide athermal path to internal copper areas (or to the opposite side of the PCB) that provide for more efficient heatremoval. TI typically recommends an 11,9-mm
2
board-mount thermal pad. This allows maximum area for thermaldissipation, while keeping leads away from the pad area to prevent solder bridging. A sufficient quantity ofthermal/electrical vias must be included to keep the device within recommended operating conditions. This padmust be electrically at ground potential.
Figure 2. ADS5424 Estimated Device Life at Elevated Temperatures Electromigration Fail Mode
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DEFINITION OF SPECIFICATIONS
SNR +10Log10 PS
PN
SINAD +10Log10 PS
PN)PD
THD +10Log10 PS
PD
ADS5424-SP
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Temperature DriftAnalog Bandwidth
The temperature drift coefficient (with respect to gainThe analog input frequency at which the power of the
error and offset error) specifies the change perfundamental is reduced by 3 dB with respect to the
degree celsius of the parameter from T
MIN
or T
MAX
. Itlow-frequency value
is computed as the maximum variation of thatparameter over the whole temperature range dividedAperture Delay
by T
MAX
– T
MIN
.The delay in time between the rising edge of the inputsampling clock and the actual time at which the
Signal-to-Noise Ratio (SNR)sampling occurs
SNR is the ratio of the power of the fundamental (P
S
)to the noise floor power (P
N
), excluding the power atAperture Uncertainty (Jitter)
dc and in the first five harmonics.The sample-to-sample variation in aperture delay
Clock Pulse Width/Duty CycleThe duty cycle of a clock signal is the ratio of the timethe clock signal remains at a logic high (clock pulse
SNR is given either in units of dBc (dB to carrier)width) to the period of the clock signal. Duty cycle is
when the absolute power of the fundamental is usedtypically expressed as a percentage. A perfect
as the reference, or dBFS (dB to full scale) when thedifferential sine wave clock results in a 50% duty
power of the fundamental is extrapolated to thecycle.
converter ’ s full-scale range.Maximum Conversion Rate
Signal-to-Noise and Distortion (SINAD)The maximum sampling rate at which certified
SINAD is the ratio of the power of the fundamentaloperation is given. All parametric testing is performed
(P
S
) to the power of all the other spectral componentsat this sampling rate unless otherwise noted.
including noise (P
N
) and distortion (P
D
), but excludingdc.Minimum Conversion RateThe minimum sampling rate at which the ADCfunctions
Differential Nonlinearity (DNL)
SINAD is given either in units of dBc (dB to carrier)An ideal ADC exhibits code transitions at analog input
when the absolute power of the fundamental is usedvalues spaced exactly 1 LSB apart. DNL is the
as the reference, or dBFS (dB to Full Scale) when thedeviation of any single step from this ideal value,
power of the fundamental is extrapolated to themeasured in units of LSB.
converter ’ s full-scale range.Integral Nonlinearity (INL)
Total Harmonic Distortion (THD)INL is the deviation of the ADC transfer function from
THD is the ratio of the power of the fundamental (P
S
)a best-fit line determined by a least-squares curve fit
to the power of the first five harmonics (P
D
).of that transfer function, measured in units of LSB.
Gain ErrorGain error is the deviation of the ADC actual inputfull-scale range from its ideal value. Gain error is THD is typically given in units of dBc (dB to carrier).given as a percentage of the ideal input full-scale
Spurious-Free Dynamic Range (SFDR)range.
The ratio of the power of the fundamental to theOffset Error
highest other spectral component (either spur orThe offset error is the difference, given in number of harmonic). SFDR is typically given in units of dBc (dBLSBs, between the ADC's actual value average idle to carrier).channel output code and the ideal average idle
Two-Tone Intermodulation Distortionchannel output code. This quantity is often mapped
IMD3 is the ratio of the power of the fundamental (atinto mV.
frequencies f
1
, f
2
) to the power of the worst spectralcomponent at either frequency 2f
1
– f
2
or 2f
2
– f
1
).IMD3 is given either in units of dBc (dB to carrier)when the absolute power of the fundamental is usedas the reference, or dBFS (dB to full scale) when it isreferred to the full-scale range
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TYPICAL CHARACTERISTICS
AIN-Input Amplitude-dB
AC Performance -dB
f =92.16MSPS
f =70MHz
S
IN
ADS5424-SP
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Typical values are at T
A
= 25 °C, AV
DD
= 5 V, DRV
DD
= 3.3 V, differential input amplitude = – 1 dBFS, sampling rate = 105MSPS, 3 V
PP
sinusoidal clock, 50% duty cycle, 16k FFT points (unless otherwise noted)
AC PERFORMANCE AC PERFORMANCEvs vsINPUT AMPLITUDE (70 MHz) INPUT AMPLITUDE (170 MHz)
Figure 3. Figure 4.
AC PERFORMANCE AC PERFORMANCEvs vsCLOCK LEVEL (70 MHz) CLOCK LEVEL (170 MHz)
Figure 5. Figure 6.
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DRV -SupplyVoltage-V
DD
SFDR-Sprious-FreeDynamicRange-dBc
DRV -SupplyVoltage-V
DD
SNR-Signal-to-Noise-dBc
ADS5424-SP
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....................................................................................................................................................................................................... SLWS194 – MAY 2008
TYPICAL CHARACTERISTICS (continued)Typical values are at T
A
= 25 °C, AV
DD
= 5 V, DRV
DD
= 3.3 V, differential input amplitude = – 1 dBFS, sampling rate = 105MSPS, 3 V
PP
sinusoidal clock, 50% duty cycle, 16k FFT points (unless otherwise noted)
SPURIOUS-FREE DYNAMIC RANGE SIGNAL-TO-NOISE RATIOvs vsSUPPLY VOLTAGE AND AMBIENT TEMPERATURE SUPPLY VOLTAGE AND AMBIENT TEMPERATURE
Figure 7. Figure 8.
SNR SFDRvs vsINPUT FREQUENCY and SAMPLING FREQUENCY INPUT FREQUENCY and SAMPLING FREQUENCY
Figure 9. Figure 10.
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EQUIVALENT CIRCUITS
DRVDD
AIN BUF T/H
500 Ω
BUF
500 Ω
VREF
AVDD
BUF T/H
AVDD
AIN
AVDD
Bandgap VREF
25 Ω
−
+
1.2 kΩ
1.2 kΩ
CLK
1 kΩ
1 kΩ
AVDD
AVDD
CLK
Bandgap
Clock Buffer
ADS5424-SP
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Figure 11. Analog Input Figure 12. Digital Output
Figure 13. Clock Input Figure 14. Reference
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AVDD
Bandgap +
−DAC IOUTP
IOUTM
C1, C2
10 kΩ
DRVDD
10 kΩ
DMID
ADS5424-SP
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....................................................................................................................................................................................................... SLWS194 – MAY 2008
EQUIVALENT CIRCUITS (continued)
Figure 15. Decoupling Pin Figure 16. DMID Generation
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APPLICATION INFORMATION
THEORY OF OPERATION
INPUT CONFIGURATION
R0
50W
Z0
50W
1:1
ADT1−1WT
R
50W
AC Signal
Source ADS5424M
AIN
AIN
RT
100 Ω
+
−
OPA695
5 V
R1
400 Ω
ADS5424M
CIN
RIN
0.1 µF1:1
−5 V
R2
57.5 Ω
VIN
AV = 8V/V
(18 dB)
RS
100 Ω
1000 µF
RIN AIN
AIN
ADS5424-SP
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The ADS5424 is a 14 bit, 105 MSPS, monolithic pipeline analog to digital converter. Its bipolar analog coreoperates from a 5 V supply, while the output uses 3.3 V supply for compatibility with the CMOS family. Theconversion process is initiated by the rising edge of the external input clock. At that instant, the differential inputsignal is captured by the input track and hold (T&H) and the input sample is sequentially converted by a series ofsmall resolution stages, with the outputs combined in a digital correction logic block. Both the rising and thefalling clock edges are used to propagate the sample through the pipeline every half clock cycle. This processresults in a data latency of three clock cycles, after which the output data is available as a 14 bit parallel word,coded in binary 2's complement format.
The analog input for the ADS5424 (see Figure 11 ) consists of an analog differential buffer followed by a bipolartrack-and-hold. The analog buffer isolates the source driving the input of the ADC from any internal switching.The input common mode is set internally through a 500 Ωresistor connected from 2.4 V to each of the inputs.This results in a differential input impedance of 1 k Ω.
For a full-scale differential input, each of the differential lines of the input signal (pins 11 and 12) swingssymmetrically between 2.4 ± 0.55 V and 2.4 – 0.55 V. This means that each input is driven with a signal of up to2.4 ± 0.55 V, so that each input has a maximum signal swing of 1.1 V
PP
for a total differential input signal swing of2.2 V
PP
. The maximum swing is determined by the internal reference voltage generator eliminating any externalcircuitry for this purpose.
The ADS5424 obtains optimum performance when the analog inputs are driven differentially. The circuit inFigure 17 shows one possible configuration using an RF transformer with termination either on the primary or onthe secondary of the transformer. If voltage gain is required, a step-up transformer can be used. For higher gainsthat would require impractical higher turn ratios on the transformer, a single-ended amplifier driving thetransformer can be used (see Figure 18 ). Another circuit optimized for performance would be the one onFigure 19 , using the THS4304 or the OPA695. Texas Instruments has shown excellent performance on thisconfiguration up to 10 dB gain with the THS4304 and at 14 dB gain with the OPA695. For the best performance,they need to be configured differentially after the transformer (as shown) or in inverting mode for the OPA695(see SBAA113); otherwise, HD2 from the op amps limits the useful frequency.
Figure 17. Converting a Single-Ended Input to a Differential Signal Using RF Transformers
Figure 18. Using the OPA695 With the ADS5424
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49.9 Ω
−
+
THS4304
ADS5424M
1:1
5 V
CM RF
CM
VIN
From
50 Ω
Source
RG
CM
+
−
THS4304
5 V
CM RF
RG
VREF
AIN
AIN
2.7 pF
14-Bit
105 MSPS
AIN
AIN VREF
ADS5424M
+5V
THS4509
CM
348 Ω
348 Ω
100 Ω
100 Ω
69.8 Ω
VIN
From
50 Ω
Source
225 Ω
225 Ω
69.8 Ω49.9 Ω
49.9 Ω
0.22 µF 0.22 µF0.1 µF 0.1 µF
0.22 µF
ADS5424-SP
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....................................................................................................................................................................................................... SLWS194 – MAY 2008
Figure 19. Using the THS4304 With the ADS5424
Texas Instruments offers a wide selection of single-ended operational amplifiers (including the THS3201,THS3202 and OPA847) that can be selected depending on the application. An RF gain block amplifier, such asTexas Instrument's THS9001, also can be used with an RF transformer for high input frequency applications. Forapplications requiring dc-coupling with the signal source, instead of using a topology with three single-endedamplifiers, a differential input/differential output amplifier like the THS4509 (see Figure 20 ) can be used, whichminimizes board space and reduces the number of components.
Figure 20. Using the THS4509 With the ADS5424
On this configuration, the THS4509 amplifier circuit provides 10 dB of gain, converts the single-ended input todifferential, and sets the proper input common-mode voltage to the ADS5424.
The 225 Ωresistors and 2.7 pF capacitor between the THS4509 outputs and ADS5424 inputs (along with theinput capacitance of the ADC) limit the bandwidth of the signal to about 100 MHz ( – 3 dB).
For this test, an Agilent signal generator is used for the signal source. The generator is an ac-coupled 50 Ωsource. A bandpass filter is inserted in series with the input to reduce harmonics and noise from the signalsource.
Input termination is accomplished via the 69.8 Ωresistor and 0.22 µF capacitor to ground in conjunction with theinput impedance of the amplifier circuit. A 0.22 µF capacitor and 49.9 Ωresistor is inserted to ground across the69.8 Ωresistor and 0.22 µF capacitor on the alternate input to balance the circuit.
Gain is a function of the source impedance, termination, and 348 Ωfeedback resistor. See the THS4509 datasheet for further component values to set proper 50 Ωtermination for other common gains.
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CLOCK INPUTS
CLK
ADS5424M
CLK
Square Wave or
Sine Wave
0.01 µF
0.01 µF
CLK
ADS5424
M
CLK
0.1 µF1:4
Clock
Source
MA3X71600LCT−ND
ADS5424-SP
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Because the ADS5424 recommended input common-mode voltage is 2.4 V, the THS4509 is operated from asingle power supply input with V
S+
= 5 V and V
S –
= 0 V (ground). This maintains maximum headroom on theinternal transistors of the THS4509.
The ADS5424 clock input can be driven with either a differential clock signal or a single-ended clock input, withlittle or no difference in performance between both configurations. In low-input-frequency applications, wherejitter may not be a big concern, the use of single-ended clock (see Figure 21 ) could save cost and board spacewithout any trade-off in performance. When driven on this configuration, it is best to connect CLKM (pin 11) toground with a 0.01 µF capacitor, while CLKP is ac-coupled with a 0.01 µF capacitor to the clock source, asshown in Figure 22 .
Figure 21. Single-Ended Clock
Figure 22. Differential Clock
For jitter sensitive applications, the use of a differential clock has advantages (as with any other ADCs) at thesystem level. The first advantage is that it allows for common-mode noise rejection at the PCB level. A furtheranalysis (see Clocking High Speed Data Converters, SLYT075) reveals one more advantage. The followingformula describes the different contributions to clock jitter:
(Jittertotal)
2
= (EXT_jitter)
2
+ (ADC_jitter)
2
= (EXT_jitter)
2
+ (ADC_int)
2
+ (K/clock_slope)
2
The first term represents the external jitter, coming from the clock source, plus noise added by the system on theclock distribution, up to the ADC. The second term is the ADC contribution, which can be divided in two portions.The first does not depend directly on any external factor. The second contribution is a term inversely proportionalto the clock slope. The faster the slope, the smaller this term will be. As an example, the ADC jitter contributioncould be computed from a sinusoidal input clock of 3 V
pp
amplitude and Fs = 80 MSPS:
ADC_jitter = sqrt ((150 fs)
2
+ (5 ×10
– 5
/(1.5 ×2×PI ×80 ×10
6
))
2
) = 164 fs
The use of differential clock allows for the use of bigger clock amplitudes without exceeding the absolutemaximum ratings. This, on the case of sinusoidal clock, results on higher slew rates, which minimize the impactof the jitter factor inversely proportional to the clock slope.
Figure 23 shows this approach. The back-to-back Schottky can be added to limit the clock amplitude in caseswhere this would exceed the absolute maximum ratings, even when using a differential clock.
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CLK
ADS5424M
CLK
D
VBB
MC100EP16DT
50 Ω
100 nF
100 nF
50 Ω
113 Ω
Q
Q
D
100 nF
100 nF
100 nF
499 W499 W
DIGITAL OUTPUTS
POWER SUPPLIES
ADS5424-SP
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....................................................................................................................................................................................................... SLWS194 – MAY 2008
Figure 23. Differential Clock Using PECL Logic
Another possibility is the use of a logic based clock, as PECL. In this case, the slew rate of the edges will mostlikely be much higher than the one obtained for the same clock amplitude based on a sinusoidal clock. Thissolution would minimize the effect of the slope dependent ADC jitter. Nevertheless, observe that for theADS5424, this term is small and has been optimized. Using logic gates to square a sinusoidal clock may notproduce the best results as logic gates, which may not have been optimized to act as comparators, adding toomuch jitter while squaring the inputs.
The common-mode voltage of the clock inputs is set internally to 2.4 V using internal 1 k Ωresistors. It isrecommended to use an ac coupling, but if for any reason, this scheme is not possible, due to, for instance,asynchronous clocking, the ADS5424 presents a good tolerance to clock common-mode variation.
Additionally, the internal ADC core uses both edges of the clock for the conversion process. This means that,ideally, a 50% duty cycle should be provided.
The ADC provides 14 data outputs (D13 to D0, with D13 being the MSB and D0 the LSB), a data-ready signal(DRY, pin 52), and an out-of-range indicator (OVR, pin 32) that equals 1 when the output reaches the full-scalelimits.
The output format is two's complement. When the input voltage is at negative full scale (around – 1.1 Vdifferential), the output will be, from MSB to LSB, 10 0000 0000 0000. Then, as the input voltage is increased,the output switches to 10 0000 0000 0001, 10 0000 0000 0010 and so on until 11 1111 1111 1111 right beforemid-scale (when both inputs are tight together if we neglect offset errors). Further increases on input voltage,outputs the word 00 0000 0000 0000, to be followed by 00 0000 0000 0001, 00 0000 0000 0010 and so on untilreaching 01 1111 1111 1111 at full-scale input (1.1-V differential).
Although the output circuitry of the ADS5424 has been designed to minimize the noise produced by thetransients of the data switching, care must be taken when designing the circuitry reading the ADS5424 outputs.Output load capacitance should be minimized by minimizing the load on the output traces, reducing their lengthand the number of gates connected to them, and by the use of a series resistor with each pin. Typical numberson the data sheet tables and graphs are obtained with 100 Ωseries resistor on each digital output pin, followedby a 74AVC16244 digital buffer as the one used in the evaluation board.
The use of low noise power supplies with adequate decoupling is recommended, being the linear supplies thefirst choice versus switched ones, which tend to generate more noise components that can be coupled to theADS5424.
The ADS5424 uses two power supplies. For the analog portion of the design, a 5 V AV
DD
is used, while for thedigital outputs supply (DRV
DD
), we recommend the use of 3.3 V. All the ground pins are marked as GND,although AGND pins and DRGND pins are not tied together inside the package. Customers willing to experiment
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LAYOUT INFORMATION
ADS5424-SP
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with different grounding schemes should know that AGND pins are 4, 7, 10, 13, 15, 17, 19, 21, 23, 25, 27, and29, while DRGND pins are 2, 34, and 42. We recommend that both grounds are tied together externally, using acommon ground plane. That is the case on the production test boards and modules provided to customer forevaluation. To obtain the best performance, user should lay out the board to assure that the digital returncurrents do not flow under the analog portion of the board. This can be achieved without splitting the board andwith careful component placement and increasing the number of vias and ground planes.
Finally, notice that the metallic heat sink under the package is also connected to analog ground.
The evaluation board represents a good guideline of how to lay out the board to obtain the maximumperformance out of the ADS5424. General design rules for use of multilayer boards, single ground plane for both,analog and digital ADC ground connections, and local decoupling ceramic chip capacitors should be applied. Theinput traces should be isolated from any external source of interference or noise, including the digital outputs aswell as the clock traces. Clock also should be isolated from other signals, especially on applications where lowjitter is required, as high IF sampling.
Besides performance oriented rules, special care has to be taken when considering the heat dissipation out ofthe device. The thermal package information describes the T
JA
values obtained on the different configurations.
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