Preliminary 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD KS0090i INTRODUCTION The KS0090i is an LCD driver and controller LSI for liquid crystal dot matrix character display systems. It can display 2 or 3 lines of 12 characters with the 5 x 8 dots format. It is capable of interfacing with the IC serial mode. Voltage converter (2 or 3 times), voltage regulator, divider resistor and voltage follower OP AMP are built-in to the IC, and a low operation current of 50u,A is achieved. The slim shape of the chip makes it suitable for the COG module application and TCP. The KS0090i is an ideal solution for display on portable equipment such as hand- held phones. FEATURES Driver Outputs Common output: 26 common Segment output: 64 segment Icons: 128 horizontal icons, 24 x 4 vertical icons, 5 static icons * Applicable Panel Size Display Size Duty Output Content 2 line x 12 char 1/18 (12 characters + 4 segments for signal) x 2 + 128 icons + 5 static icons 3 line x 12 char 1/26 (12 characters + 4 segments for signal) x 3 + 128 icons + 5 static icons Internal Memory Character generator ROM (CGROM): 10,240 bits (256 characters x 5 x 8 dots) Character generator RAM (CGRAM): 160 bits (4 characters x 5 x 8 dots) Display data RAM (DDRAM): 288 bits (12 characters x 3 lines x 8 bits) Segment icon RAM (ICONRAM): 224 bits (12 x 2 x 5 bits + 2 x 4 bits + 24 x 4 bits) MPU Interface Serial interface mode: IC serial interface * Function Set Various instruction set: display control, power save, power control, function set... etc. COM/SEG bidirectional function (4 type LCD application available) Hardware reset (RES pin) Built-in Analog Circuit On-chip oscillator with an Internal resistor or external clock input Electronic volume for contrast control (32 or 64 steps) Voltage converter (2 or 3 times) / voltage regulator / voltage follower and bias circuit ELECTRONICSPreliminary KS0090i 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD Low Power Consumption 80.uA Max.: In normal mode for normal display operation 10pA Max.: In standby mode for displaying static icon 5uA Max.: In sleep mode when display is turned off * Operating Voltage Range Power supply voltage (VDD): 2.4 to 5.5 V LCD driving voltage (VLCD = VO - Vss): 11.0 V (positive process) Package Type Bumped chip or TCP available ELECTRONICSPreliminary 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD KS0090i BLOCK DIAGRAM RES > CK J COMSA Static Oscillator Timing Generator Driver | SEGSA-E COM1 : i COM24 Instruction 26-bit sc_| Po Ly | Instruction| __ shitt LJCommon|_, 7>| Register : Driver Serial | (IR) Decoder Register coms! 2 SDA <> Display Data Interface N RAM AA Address (DDRAM) Counter 36x8 bits 7 7 {| 7} }, ; SEG1 64-bit 64-bit Segment, SEG6O Shift Ky Latch . > xe Register Register| | Circuit | | river | segsi,2 A 8 A SEGS4, 5 (DR) Slave 8 7 A[6:0] <p Address 7 7 8/8 AA Vv viv vv y Character | | Character LCD Icon RAM Generator | | Generator ta Voltage (IGONRAM) RAM ROM (cGRAM)| | (cGRoM)| | COMeler Selector 244 bits 32 bytes | | 10240 bits a VDD > 5 5 GND Vv y (VSS) 4 Segment Data Conversion LCD Driving Power Circuit Voltage Converter Voltage Regulator Voltage Follower & Bias Resistor CAP1+ CAP1 CAP2+ CAP2 VOUT vo VR vo V1 V2 V3 V4 BID Figure 1. KS0090i Block Diagram ELECTRONICS26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD PAD CONFIGURATION Preliminary KS0090i ~ & o 2. Ee <t wt oO 3. ~eE g < ee) - 3. S w ~ x = = xX 5 = x x Er = = E = + = =. co ny - E = 6 & oe EFS oO 3. oO . os wt Oo ZB. Q - oO On oD = ey ~ oO HE DH Tx = Xx wee ec o Oo A > & NE GD & So @ fF GE O38 Or D3 5 Sg Eo oO x= c = Oo Ql 2o o a > On <= _ 3 = a oc On <x <x t ' 1 NOMTOTOMDDKROWTMNTOMOROWTOMNTODOANRONMTMNTODOKRONMNTMNTOMDWOKONWTONTO Ne ANAQHAN OHH KHKHKHHUKHHNHNOTTHTSTSTTTITITINMINNNNNANANANAANANANANNNr rrr rrr rrr ODOR OWTOANTOY 22200 OOO OOO OOO OOOO OO OOO OOO OOO UOO OOO UO OO UOO OOO UOOUOOUOOUUOUOOUOOUUOU OOVCOCO OW WWW WW WH WH WH WH WU LULU LULU LU LO Lo Lo WW WW WLLL OO OO OO We LO 2 2 2 2 ee eo Gb LL LL LL CC CD ZZZOOOCNNNNNNNNANDVNANNNDNNNNNNNDNNANNDNNNNNNNNNNNNNNNNNANNANNNNNNNNNNNANNDNNNNNNNNZZZ te eee ae No} _ - No NC] ~ Tne COoM21 ~ Tne COM20 | ~ Tne COM19] ~ _ comis| 9 . Come. COM17 . - COM7 COM16] | 2 o - come COM15 2 2 ~ | coms com14] ~ > 3 ~ | com4 cOMi3 a 3S ~ | coms COM12] = ~ | COM com11 | ~ oO > FE oa . 2 COMI0] ~ o x . COM1 - ~ COMS1 COMS . COMSA COMS2]~ - NC SEGSA]~ ~ Tne SEGSB]~ ~I ne SEGSC]~ ~I ne SEGSD]~ - SEGSE | ch =| errr ttttannaanaAYaoomnaAaAH00 o2oo7 TAA ONO MAQgVAZZWaAgOVAZ! t++t++ NANA 1 anonoa a fe ee Soi Cece >>> > C>>4ay O000 A6 AS A4 A3 A2 HAYITMONArroocoorEle LLOQONANNHNFR PPO eer ore >r>>> > ELECTRONICSPreliminary 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD KS0090i PAD LOCATION (UNIT: mm] Pad Pad Name _ Pad Pad Name _ Pad Pad Name _ 1 NC1 -3540 | 880 31 A5 -2430 |-1111 |61 | CAP2- 270 1111 2 NC2 -3540 | 790 32 A4 -2340 |-1111 |62 | CAP2- 360 1111 3 COM21 -3540 | 700 33 A3 2250 |-1111 |63 | CAP2- 450 1111 4 Com20 |-3540 |610 34 | A2 ~2160 |-1111 |64 | CAP2- 540 1111 5 COM19 3540 520 35 Al 2070 1111 65 CAP2+ 630 1111 6 COMi8 |-3540 | 430 36 AO -1980 |-1111 |66 | CAP2+ 720 1111 7 COM17. |-3540 | 340 37 Vpp -1890 |-1111 |67 | CAP2+ 810 1111 8 COM16 3540 250 38 Vpop 1800 1111 68 CAP2+ 900 1111 9 COM15 |-3540 | 160 39 Vpp -1710 |-1111 |69 | CAP1- 990 1111 10 |COM14 |-3540 |70 40 |Vss ~1620 |-1111 |70 | CAP1- 1080 1111 11 COM13. |-3540 | -20 4 Vss ~1530 |-1111 |71 | CAP1- 1170 1111 12 COM12 3540 110 42 Vss 1440 1111 72 CAP 1- 1260 1111 13 COM11 3540 200 43 V4 1350 1111 73 CAP1+ 1350 1111 14 COM10 3540 290 44 V4 1260 1111 74 CAP1+ 1440 1111 15 COM9 3540 380 45 V3 1170 1111 75 CAP1+ 1530 1111 16 COMS2 3540 470 46 V3 1080 1111 76 CAP1+ 1620 1111 17 SEGSA 3540 560 47 V2 990 1111 77 Vss 1710 1111 18 SEGSB 3540 650 48 V2 900 1111 78 Vss 1800 1111 19 SEGSC 3540 740 49 V1 810 1111 79 Vss 1890 1111 20 SEGSD 3540 830 50 V1 720 1111 80 BID 1980 1111 21 SEGSE 3540 920 51 vo 630 1111 81 Vop 2070 1111 22 NC3 3240 1111 52 vo 540 1111 82 Vop 2160 1111 23 NC4 3150 1111 53 vo 450 1111 83 Vop 2250 1111 24 NC5 3060 1111 54 vo 360 1111 84 CK 2340 1111 25 NC6 2970 1111 55 VR 270 1111 85 Vop 2430 1111 26 NC7 2880 1111 56 VR 180 1111 86 NC11 2520 1111 27 NC8 2790 1111 57 VOUT 90 1111 87 NC12 2610 1111 28 NCg 2700 1111 58 VOUT 0 1111 88 RES 2700 1111 29 NC10 2610 1111 59 VOUT 90 1111 89 Vop 2790 1111 30 A6 2520 1111 60 VOUT 180 1111 90 Vop 2880 1111 5 ELECTRONICSPreliminary KS0090i 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD (Unit: nm] Pad Pad Name _ Pad Pad Name _ Pad Pad Name _ 91 SCL 2970 1111 124 SEG4 2520 1070 157 SEG37 450 1070 92 SDA 3060 1111 125 SEG5 2430 1070 158 SEG38 540 1070 93 NC13 3150 1111 126 SEG6 2340 1070 159 SEG39 630 1070 94 NC14 3240 1111 127 SEG7 2250 1070 160 SEG40 -720 1070 95 NC15 3540 920 128 SEG8 2160 1070 161 SEG41 810 1070 96 NC16 3540 830 129 SEG9 2070 1070 162 SEG42 900 1070 97 NC17 3540 -740 130 SEG10 1980 1070 163 SEG43 990 1070 98 NC18 3540 650 131 SEG11 1890 1070 164 SEG44 1080 1070 99 NC19 3540 560 132 SEG12 1800 1070 165 SEG45 1170 1070 100 COMSA 3540 470 133 SEG13 1710 1070 166 SEG46 1260 1070 101 COMS1 3540 380 134 SEG14 1620 1070 167 SEG47 1350 1070 102 COM1 3540 290 135 SEG15 1530 1070 168 SEG48 1440 1070 103 COM2 3540 200 136 SEG16 1440 1070 169 SEG49 1530 1070 104 COM3 3540 -110 137 SEG17 1350 1070 170 SEG50 1620 1070 105 COM4 3540 -20 138 SEG18 1260 1070 171 SEG51 1710 1070 106 COM5 3540 70 139 SEG19 1170 1070 172 SEG52 1800 1070 107 COM6 3540 160 140 SEG20 1080 1070 173 SEG53 1890 1070 108 COM7 3540 250 141 SEG21 990 1070 174 SEG54 1980 1070 109 COM8 3540 340 142 SEG22 900 1070 175 SEG55 2070 1070 110 COMS1* 3540 430 143 SEG23 810 1070 176 SEG56 2160 1070 111 NG20 3540 520 144 SEG24 720 1070 177 SEG57 2250 1070 112 NC21 3540 610 145 SEG25 630 1070 178 SEG58 2340 1070 113 NCG22 3540 700 146 SEG26 540 1070 179 SEG59 2430 1070 114 NCG23 3540 790 147 SEG27 450 1070 180 SEG60 2520 1070 115 NCG24 3540 880 148 SEG28 360 1070 181 SEGS4 2610 1070 116 NCG25 3240 1070 149 SEG29 270 1070 182 SEGS5 2700 1070 117 NC26 3150 1070 150 SEG30 180 1070 183 COM24 2790 1070 118 NC27 3060 1070 151 SEG31 90 1070 184 COM23 2880 1070 119 SEGS1 2970 1070 152 SEG32 0 1070 185 COM22 2970 1070 120 SEGS2 2880 1070 153 SEG33 90 1070 186 NC28 3060 1070 121 SEG1 2790 1070 154 SEG34 -180 1070 187 NCG29 3150 1070 122 SEG2 2700 1070 155 SEG35 -270 1070 188 NC30 3240 1070 123 SEG3 2610 1070 156 SEG36 360 1070 NOTE: The COMS1 has two terminals (#101, #110), and these two COMS1 are the same signal at the same time. ELECTRONICSPreliminary 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD KS0090i PIN DESCRIPTION Table 1. Pin Description Name Description VDD Power | Power supply. Connect to MPU power supply pin. Vss 0 V (GND) vo /O | Bias voltage level for LCD driving. v1 Voltages have the following relationship; V2 VO2>V12V22>V32V4>Vss V3 When the built-in power circuit is on, the following voltages are given to pin V1 to V4 V4 using internal 1/5 bias resistors. LCD Bias V1 v2 V3 v4 (1/5) Bias | (4/5) vo | (3/5) Vo*([ (2/5) Vo__[ (1/5) Vo CAP1+ O Capacitor1+ connecting pin for the internal voltage converter. This pin connects the capacitor with CAP 1-. CAP 1- Capacitor1 connecting pin for the internal voltage converter. This pin connects the capacitor with CAP+. CAP2+ Capacitor2+ connecting pin for the internal voltage converter. When VOUT is 2 times boosting, this pin connects the capacitor with Vpop. When 3 times boosting, this pin connects the capacitor with CAP2-. CAP2- Capacitor2 connecting pin for the internal voltage converter. When VOUT is 2 times boosting, this pin is not used. When 3 times boosting, this pin connects the capacitor with CAP2+. VOUT /O |2or3 times DC/DC voltage converter output. This pin connects a capacitor with Vpp pin. VR | Voltage adjust pin. This pin gives a voltage between VO and Vss by resistance- division of voltage. ELECTRONICSPreliminary KS0090i 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD Table 1. Pin Description (Continued) Name O Description CK | External clock input pin. It must be fixed to High when the internal oscillation circuit is used. In the external clock mode, it is used as an external clock input pin. BID | SEG direction selection pin When BID = Low, SEGS1 > SEGS2 > SEG1 -...... SEG60 > SEGS4 > SEGS5 When BID = High, SEGS5 SEGS4 > SEG60 > . > SEG1 > SEGS2 > SEGS1 RES | Initialization is performed by edge sensing of the RES signal. When RES = Low: _J> _ When RES = High: L__4 SCL | I?C clock input SDA VO | \?C data signal A6 AO | Used as slave address for IC interface. This must be fixed to High or Low. This can be set arbitrary from 00h to 7Fh and the setting address is used as the slave address (identification code) in KS0090i. SEGS4, SEGS5 COM1 to COM24 O Common signal output for character display. COMS1, COMS2 O Common signal output for icon display. The COMS1 has two terminals, and these two COMS1 are the same signal at the same time. SEG1 to SEG60 O Segment signal output for character display. SEGS1, SEGS2 O Segment signal output for vertical icon display. COMSA Static common signal output for static icon display. SEGSA, B,C, D,E Static segment signal output for static icon display. ELECTRONICSPreliminary 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD KS0090i FUNCTION DESCRIPTION SYSTEM INTERFACE KS0090i has C serial interface mode. KS0090i is selected when the higher 7-bit of first byte, which is transferred from the MPU after the start procedure, matches the 7-bit slave address assigned to A6~A0 pin. During writing operation, two 8-bit registers, data register (DR) and instruction register (IR), are used. DR or IR register is selected by setting the RS flag of control bit. The data register(DR) is used as temporary data storage place for being written into DDRAM/CGRAM/ICONRAM, and one of these RAMs is selected by RAM address setting instruction. The Instruction register(IR) is used to store instruction code transferred from MPU. Table 2. I2C Serial Interface RES A6 ~ AO SCL SDA RESET A6 ~ AO I2C clock I?C data RES: MPU reset SCL: IC serial clock input SDA: IC serial data input/output A6 ~ AO: I7C slave address input I2C SERIAL MODE Allows serial data transfer conforming to the C serial interface protocol over the serial data line (SDA) and serial transfer clock line (SCL). Here, KSOO90i operates write mode only. Bit Transfer One data bit is transferred during each clock pulse. The data on the SDA line must be remain stable during the high period of the clock pulse. If SDA data line changes at this time, the IC serial interface will be transferred to start or stop condition. Start and Stop Conditions KS0090i initiates serial data transfer with a high-to-low transition of the data line when the clock is high. This is defined as the start condition. On the contrary, KS0090i finishes serial data transfer with a low-to-high transition of the data line when the clock is high, which is defined as the stop condition. Acknowledge From the start to the stop condition, the number of data bytes transferred from MPU to KS0090i is unlimited. Each byte formatted with eight bits is followed by an acknowledge bit (ACK). After receiving each 8-bit data, KSO090i pulls down SDA pin to a low level. At this time the MPU must be generates an extra clock pulse for acknowledge bit transferred from KS0090i to MPU. Therefore, if ACK is not returned, the data must be transferred again. A series of data bytes can be transferred so long as KSO0090i does not meet the stop condition. I2C Protocol KS0090i is selected when the higher 7-bit of first byte, which transferred from the MPU after the start procedure, matches the 7-bit slave address assigned to A6~A0 pin. After being selected, KSO090i receives the subsequent data strings. ELECTRONICSPreliminary KS0090i 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD The I?C bus configuration for KS0090i write mode is shown in following. SDA SCL Start Condition Stop Condition Figure 2. Definition of Start and Stop Conditions of SCL Data Line Change Stable: of Data Data valid allowed Figure 3. Bit Transfer Not Acknowledae SDA from MPU Ko Acknowledge SCL / 8 \ [9 \ Clock pulse for Start Condition Acknowledgement Figure 4. Acknowledgment on the [7C Interface 10 ELECTRONICSPreliminary 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD KS0090i DATA TRANSFERRING SEQUENCE 1. Control Byte Format Control Byte Format | CO RS | WB . . . . . . *: Dont care CO = 0: Last control byte, CO = 1: More control byte will follow RS = 0: Set Instruction register, RS = 1: Set data register WB = 0: Normal write operation, WB = 1: Unexpected read mode KS0090i provides write-only mode of IC interface. So if unexpected read happen, KS0090i makes SDA floated. ACK occur after passing 8 cycle of SCL. 2. Normal write operation Acknowledgement from KS0090i ! ! ! ! s R Dj] D] Dj Dj Dj D] DY DF A D| DD] Dj Dj] DD} D Bj B} B] By By By By B B) BB) By) By] B BIB] Js Tal alalalal lal JA\ Isto] 4 4 44 4Al7{ els] 4] ale} sto) Alo] S19) 4 474 Val zie] sta] ala] lol ANT Ale} s}4l3] 2] 1}o| OVS o C C Cid R K K 5 T CONTROL BYTE DATA BYTE CONTROL BYTE DATA BYTE \ J oN SN TaN / Slave address 2n 0 byte 1 byte n + 0 byte given by user to AO~A6 for KS0090i R/W CO1 WB CO2 WB CO1: The following byte will be a data byte. After data byte, KSO090i will look upon the next 8-bit as a control byte CO2: After this control byte, all the following bytes will be considered as a data byte before the stop procedure. 3. Unexpected read by setting R/W as 1 Acknowledgement from KS0090i When R/W is 1, SDA pin is floated. And only one ACK signal occur for matching the slave address field. The following bit of SDA will be ignored before the STOP procedure. So I?C block does not work. AO > lq AaADPridih vOAMN ; Slave address R/W 11 ELECTRONICSPreliminary KS0090i 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 4. Unexpected read mode by setting WB as 1 after R/W is set as 0 Acknowledgement from KS0090i \ ' ' ' ' 5 AR DJ Dj D} DD} Dj Dj o AR DO DI DID] OD DI B} B] B} BB] B| By B B} BB} BIB) B BIBI Is Thala alalalaal (Al Ist 179144 4Alz] 6/5] 4] 3/2] 1/0] 41s] 14 4 41 Sal zie] 5] 4] 3} a] 1 of Al 7 Ale] 5] 4] 3]2| 1]0/ 91S g C C Cd R K K K K KI 5 T CONTROL BYTE] | DATA BYTE 1 | [CONTROL BYTE| | DATA BYTE 2 \ J oN YN SN / Slave address given by user to AO~A6 for KS0090i R/W CO WB1 CO WB2 WB1: The following data byte will be ignored. And C block makes only ACK signal. WBz2: After this, the following data bytes will be written into data register(DR) as normal operation. S$ Slave 0} A] 100xxxxx | A] Command | A | 010xxxxx | A| Command |A|_....... Command | A|S T Address C Control C Byte C Control C Byte C Byte Cl} T A K Byte K | (Instruction) | K Byte K (Data) K (Data) K|O R P T Start byte RAM address setting Data write Next data write continuously Figure 5. MPU Write Data after Set RAM Address; Write Address, Write Data ADDRESS COUNTER (AC) The address counter (AC) in KS0090i stores the CGRAM / DDRAM / ICONRAM address, which is transferred from IR. After writing into CGRAM / DDRAM / ICONRAM, AC is automatically increased by 1. 12 ELECTRONICSPreliminary 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD KS0090i DISPLAY DATA RAM (DDRAM) DDRAM stores display data of maximum 36 x 8 bits (Max. 36 characters). DDRAM address is set in the address counter (AC) as a hexadecimal number. 1st ch. 12th ch. CcOM1 aes = 30 31 32 33 34 35 36 37 38 39 3A 3B 3C COM8 cOmg m= 40 44 42 43 44 45 46 47 48 49 4A 4B 4C COM14 SEG60 SEGS1,2 SEG1 (1) 2-line mode DDRAM address SEG S4,5 1st ch. 12th ch. CcOM1 = = 30 31 32 33 34 35 36 37 38 39 3A 3B 3C COM8 cOmg me =(4() 44 42 43 44 45 46 47 48 49 4A 4B 4C com16 COM17, mes (50 51 52 53 54 55 56 57 58 59 5A 5B 5C com24| SEG1 SEG60 SEGS1,2 (2) 3-line mode DDRAM address SEG S4,5 Figure 6. DDRAM Address 13 ELECTRONICSPreliminary KS0090i 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD CHARACTER GENERATOR ROM (CGROM) KS0090i has the character generator ROM (CGROM) consisting of up to 256 types of characters. Character size is 5 x 8 dots. The CG bit of the instruction table selects the 4 characters (00h to 03h) of CGROM or CGRAM. KS0090i CGROM is contact mask option ROM and compatible with customized ROM font. Figure 7. CGROM Character Code Table (F00) 14 ELECTRONICS26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD Preliminary KS0090i CHARACTER GENERATOR RAM (CGRAM) CGRAM contained in KS0090i enables the user to program the character pattern to display signals. When using CGRAM, the CG bit should be selected to High. CGRAM has up to four 5 x 8-dot characters. By writing font data to CGRAM, the user defined character can be used. Table 3. Relationship between Character Code (DDRAM) and Character Pattern (CGRAM) Character Code CGRAM Data (DDRAM Data) CGRAM Address (Character Pattern) Pattern D7 D6 D5 D4 D3 D2 D1 DO TAT AG AS AZ AB AZ AT AO TP7 PO PS PA PS PZ PT PO] Number 0000000 010000000 0/- - - 0 1 0 1 0 [Pattern 1 (00h) 0000000 71/---1010 1 0000001 0;/---0101 0 00000011/---101410 1 0000010 0;/---0101 0 000007107/---1410140 1 0000011 0/---0101 0 0000071 %1/---101410 1 0000000 110000 1% 0 0 0/- - - 0 0 0 0 0 [Pattern 2 (01h) 000010041/---1441 4 0000101 0/---0000 0 0000101 %1/---1441 4 00001%100;/---0000 0 00001%704/---14 41 4 0000111 0/---0000 0 00001474 4/---14 41 1 000000 1 01000 10 00 0/- - - 0 1 0 1 0 [Pattern 3 (02h) 000%100071/---0101 0 0001001 0;/---0101 0 000%10011/---0101 0 000%10%100;/---0101 0 000%10%7071/---0101 0 0001011 0/---0101 0 000107471 %1/---0101 0 000000 1 110 00 1 700 0/- - - 0 1 0 1 0 [Pattern 4 00011001 0101 0 000% 101 0 10101 000171011 10101 00011140 0 0101 0 0001711140 1 0101 0 00011141 0 10101 00071441 1 10101 (: Dont care) ELECTRONICS 15Preliminary KS0090i 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD SEGMENT ICON RAM (ICONRAM) ICONRAM has segment control data and segment pattern data. COMS1 Sit 1p S118 S119 4120 COMS2 - WN ~NO YT onan oe ~-ANOTW or ono wt nog QPePAe DAA DY oy NANNNH NANNNY oOo Figure 8. Relationship between ICONRAM and Icon Display Table 4. Relationship between ICONRAM Address and Display Pattern ICONRAM Address ICONRAM Bits High Order | Low Order D7 D6 D5 D4 D3 D2 D1 DO 0 - - - $1 $2 $3 $4 $5 1 - - - S6 S7 $8 $9 $10 6 A - - - $51 $52 $53 $54 $55 B - - - S56 $57 $58 $59 S60 Cc - - - SEGS1 | SEGS2 - SEGS4 | SEGS5 0 - - - S61 S62 S63 S64 S65 1 - - - S66 S67 S68 S69 $70 7 A - - - S111 $112 $113 S114 $115 B - - - S116 S117 S118 $119 $120 Cc - - - SEGS1 | SEGS2 - SEGS4 | SEGS5 (~: Dont care) 16 ELECTRONICSPreliminary 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD KS0090i STATIC ICON RAM (SI) KS0090i contains the static icon RAM to display the static icons in addition to the dynamic icons. Capacity of static icon RAM is 10 bits and is capable of displaying up to 5 icons. The following table shows the relationship between the static icon functions, static icon RAM address and written data (Blink frequency: 1 to 2 Hz). Table 5. Relationship between static icon RAM address and display pattern Static Icon Data Static Icon Function | nan Db4 | D3 | p2 | D1 | Do |SEGS Address | p7 | p6 | D5 B Cc D E (A) | (B) | (C) | (D) | (E) | -A Display On/O# 20h 0 1 0 1 0 C] Hi C] Hi C] Blink On/Ott 2th - - 1 1 1 0 0 || [| || || [| 20h = 0: Static icon off 4: Static icon on 21h = 0: Blink off 4: Blink on (20h data are inverted) COMSA > OGM Op wongmo~- ongmuo fF ounomuos mo gm op SEGMENTS FOR SIGNAL DISPLAY (FS) PH DY OG OO When DDRAM address is 3Ch: COM1 to COMB, 1 line 28 Ra 4Ch: COM9 to COM 16, 2 line th Tf 5Ch: COM17 to COM24, 3 line OS =0O0Ue SEGS1: Font 1st bit display ae SEGS2: Font 2nd bit display Sane8 SEGS4: Font 4th bit display ae SEGS5: Font 5th bit display ol 1d (Font 3rd bit is not displayed.) Example) RAM address = 3Ch, Data = 41h (CGROM font = A) SEGS1 SEGS2 SEGS4 SEGS5 com => > CONB rf tT? Figure 9. Segment for Signal Display " 17 ELECTRONICSPreliminary KS0090i 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD LOW POWER CONSUMPTION MODE KS0090i provides a standby mode and sleep mode to reduce power consumption during the standby period. Standby Mode (Power save bit on, Oscillation bit on) The standby mode can be switched on and off by the power save command. In the standby mode, only the static icon is displayed. 1. Liquid crystal display output COM1 to COM24, COMS1, COMS2: Vss level SEG1 to SEG60, SEGS1, 2, 4, 5: Vss level SEGSA, B, C, D, E, COMSA: Vpp or Vgg level (Can be turned on/off by static drivers) Use the static icon RAM for controlling the static icon display done with SEGSA, B, C, D, E, COMSA. 2. Written data in DDRAM, CGRAM, ICONRAM and registers remain at its previous value. 3. Operation mode is retained the same as it was prior to execution of the standby mode. The internal circuit for the dynamic display output is stopped. 4. The oscillation circuit for the static display must remain on. Sleep Mode (Power save on, Oscillation off) To enter the sleep mode, the power circuit and oscillation circuit should be turned off by the power save command and power control command. This mode helps reduce power consumption by reducing current to reset level. 1. Liquid crystal display output COM1 to COM24, COMS1, COMS2: Vgg level SEG1 to SEG60, SEGS1, 2, 4, 5: Vgg level SEGSA, B, C, D, E, COMSA: Veg level . Written data in DDRAM, CGRAM, ICONRAM and registers remain at its previous value. 3. Operation mode is retained as it was prior to execution of the sleep mode. All internal circuits are stopped. 4. Power circuit and oscillation circuit The built-in power supply circuit and oscillation circuit are turned off by the power save command and power control command. i] LCD DRIVER CIRCUIT LCD driver circuit has 26 common and 64 segment signals for driving LCD. Data from ICONRAM/CGRAM/ CGROM are transferred to 64-bit segment register serially, and then they are stored to 64-bit latch. For 2-line display mode, COM1 to COM16, COMS1, and COMS2 have 1/18 duty, and in 3-line mode, COM1 to COM 24, COMS1, and COMS2 have 1/26 duty ratio. SEG bidirectional function is selected by the BID input pin, and COM shift direction is selected by the function set instruction S bit. Table 6. SEG Data Shift Direction BID pin SEG Data Shift Direction Low SEGS1 > SEGS2 > SEG1-...... SEG60 > SEGS4 > SEGS5 High SEGS5 SEGS4 > SEG60 > ...... SEG1 > SEGS2 > SEGS1 18 ELECTRONICS26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD Preliminary KS0090i INSTRUCTION DESCRIPTION Table 7. Instruction Table Instruction Instruction Code Description RS |DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO Return 0 0 0 0 1 | DDRAM address is set to 30h from AC and cursor Home returns to 30h position if shifted. The contents of DDRAM are not changed. Display 0 0 0 1 1 Cc B D | Cursor/blink /display on/off Control C = 0: cursor off (default), C = 1: cursor on B = 0: blink off (default), B = 1: blink on D = 0: display off (default), D = 1: display on Power 0 0 1 0 0 OS _ PS | Power save/oscillation circuit. Save OS = 0: oscillator off (default), OS = 1: oscillator on PS = 0: power save off (default), PS = 1: power save on Power 0 0 1 0 1 0 VR VF_ VC | LCD power control Control VR = 0: voltage regulator off (default), 1: voltage regulator on VF = 0: voltage follower off (default), 1: voltage follower on VC = 0: voltage converter off (default), 1: voltage converter on Function 0 0 1 1 0 N2 Ni S CG | Display line mode. Set N2, N1 =0, 0: 2 line display mode (default), 0, 1: 3 line display mode Set shifting direction of COM S = 0: COM left shift (COM1 > COM24) (default), 1: COM right shift (COM24 > COM1) Select CGRAM or CGROM CG = 0: use CGROM (default), 1: use CGRAM RAM 0 1 AC6 ACS AC4 AC3 AC2 AC1 ACO | DDRAM/CGRAM/ICONRAM or register address. Address Set Write 1 |D7 D6 DS D4 D3 D2 D1 DO | Write DDRAM/CGRAM/ICONRAM or register data. Data EV Mode 0 0 0 0 0 0 0 0 EV | Electronic volume step EV = 0: 32 contrast-step (default), 1: 64 contrast-step Test Mode 0 0 0 0 0 * * * * | Instruction for IC chip test. Don't use this instruction. NOTES: (: Dont Care, *: Dont Use) 1. For the NOP instruction, when EV mode is 0 (32 contrast-step), the NOP instruction set is (000000000), and when EV mode is 1 (64 contrast-step), the NOP instruction set is (000000001). 2. Instruction execution time depends on the internal process time of KSO090i, therefore it is necessary to provide a time larger than one MPU interface cycle time (tc) between execution of two successive instructions. ELECTRONICS 19Preliminary KS0090i 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD RETURN HOME RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 0 0 0 0 1 - - - - (: Dont Care) Return home instruction field makes the cursor return home. DDRAM address is set to 30h into the address counter. Return cursor to first digit of the first line. The contents of DDRAM are not changed. DISPLAY CONTROL RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 0 0 0 1 1 Cc B - D (: Dont Care) Display control instruction field controls cursor / blink / display on / off. Cc Cursor on / off control bit H | Cursor is turned on. L | Cursor is disappeared in current display and cant blink (default). B Cursor blink on / off control bit H | When C = H, KS0090i makes LCD alternate between inverting display character and normal display character at the cursor position with about a half second. On the contrary, if C = Low, only a normal character is displayed regardless of the B flag. L | Blink is off (default). D Display on / off control bit H_ | Display is turned on L | Display is turned off, but display data remain in DDRAM (default). NOTE: Static icons driven by COMSA and SEGSA/B/C/D/E must be controlled by the static icon RAM. 20 ELECTRONICSPreliminary 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD KS0090i POWER SAVE RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 0 0 1 0 0 - - OSs PS (: Dont Care) Power save instruction field is used to control the oscillator and power save mode. OSs Oscillator on / off control bit H | Oscillator is turned on. L | Oscillator is turned off (default). PS Power save on/ off control bit H | Power save mode is turned on. L | Power save mode is turned off. (default) POWER CONTROL RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 0 0 1 0 1 0 VR VF vc Power control instruction filed sets voltage regulator / follower / converter on / off. VR Voltage regulator circuit control bit H_ | Voltage regulator is turned on. L | Voltage regulator is turned off (default). VF Voltage follower circuit control bit H_ | Voltage follower is turned on. L | Voltage follower is turned off (default). ve Voltage converter circuit control bit H | Voltage converter is turned on. L | Voltage converter is turned off (default). NOTE: The oscillator circuit must be turned on for the voltage converter circuit to be active. 21 ELECTRONICSPreliminary KS0090i 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD FUNCTION SET RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 0 0 1 1 0 N2 N1 Ss CG N2, N1 Display line mode instruction field selects 2-line or 3-line display mode L L | 2-Line display mode (default) L | H | 3-Line display mode S Data shift direction of common H | COM right shift (default) L | COM left shift Table 8. COM Data Shift Direction Mace $s COM Data Shift Direction 2 Line Mode | 0 (Left) COM1 ...... COM15 > COM16 > COMS1 >COMS2 > COM1 1 (Right) COM16 > COM15 -...... +> COM1 COMS1 > COMS2 > COM16 3 Line Mode | 0 (Left) COM1 ...... COM23 COM24 COMS1 COMS2 > COM1 1 (Right) COM24 > COM23 - ...... COM1 > COMS1 > COMS2 > COM24 CG CGRAM enable bit H | CGRAM can be accessed and you can use this RAM as a four special character area. (00h 03h = CGRAM font display) L | CGRAM is disabled. CGROM (00h to 03h) can be accessed and the additional current consumption is saved by using this mode (default). (00h 03h = CGROM font display) 22 ELECTRONICS26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD Preliminary KS0090i RAM ADDRESS SET RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 0 1 AC6 AC5 AC4 AC3 AC2 AC1 ACO RAM address set instruction field sets CGRAM / DDRAM / ICONRAM or register address. Each RAM is distinguished by a RAM address. Before writing data into the RAM, set the address by RAM address set instruction. Next, when data are written in succession, the address is automatically increased by 1. Table 9. RAM Address Mapping Address 0 1 2 3 4 5 6 7 8 9 A B Cc D E F 00h CGRAM (00h) CGRAM (01h) 10h CGRAM (02h) CGRAM (03h) 20h Sl Unused EV | TE Unused 30h DDRAM line 1 (30h to 3Bh) FS 40h DDRAM line 2 (40h to 4Bh) FS Unused 50h DDRAM line 3 (50h to 5Bh) FS 60h ICONRAM COMS1 Icon (60h 6Ch) 70h ICONRAM COMS2 Icon (70h 7Ch) Unused NOTE: Sl: Static icon register (20h, 21h). It is used for SEGS/B/C/D/E EV: Electronic volume register (28h) TE: Test register (29h) (Do not use.) FS: For signals: 1 line (8Ch), 2 line (4Ch), 3 line (6Ch). It is used for SEGS1/2/4/5. ELECTRONICS 23Preliminary KS0090i 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD WRITE DATA RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 1 D7 D6 D5 D4 D3 D2 D1 DO This instruction field makes KSO090i write binary 8-bit data to DDRAM / CGRAM / ICONRAM or register. The RAM adaress to be written into is determined by the previous RAM Address Set instruction. After writing operation, the address is automatically increased by 1. EV MODE RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 0 0 0 0 0 0 0 0 EV This instruction field selects between 2 electronic volume steps: 32 and 64 contrast-step. When the EV = Low, KS0090i selects 32 contrast-step (default), and when Electronic volume register (28h)= DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO - - - C4 C3 C2 C1 co When the EV = High, KS0090i selects 64 contrast-step. (: Dont Care) Electronic volume register (28h)= DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO - - C5 C4 C3 C2 C1 co (: Dont Care) 24 ELECTRONICS26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD Preliminary KS0090i INITIALIZING & POWER SAVE MODE SETUP HARDWARE RESET After reset by RES pin, KSO090i can be initialized the following state. 1. NOTE: Control Display on/off instruction C=0: Cursor off B=0: Blink off D=0: Display off . Power Save Set instruction OS=0: Oscillator off PS=0: Power save off . Power Control Set instruction VR=0: Voltage regulator off VF=0: Voltage follower off VC=0: Voltage converter off . Function Set instruction N2=0, N1=0: 2 line display mode S=0: COM left shift CG=0: CGRAM is not used . Return Home Address counter = 30h . Static icon RAM & electronic contrast control register Static icon RAM: 20h = (0, 0, 0, 0, 0), static icon off 21h = (0, 0, 0, 0, 0), blink off EV = 0: 32 contrast-step Electronic contrast control register: 28h = ((0),0, 0, 0, 0, 0), contrast high initialize by instruction. If initialization is not done by the RES pin at application, an unknown condition may result, in which case you can VDD RES Reset time tr 1 us Reset pulse width trw 10 pus Reset start time tRES 50 ns Figure 10. RESET Timing ELECTRONICS 25Preliminary KS0090i 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD INITIALIZING AND POWER SAVE MODE SETUP Initializing by Instruction | Power on ) When the power is stable Input of reset signal (RES pin) t Command status Initializing by hardware reset input status. Others are undefined. Waiting for 10 sec or more + Command input: (Asterisk indicates any command sequence.) 1. Function setup command (N2, N1, S, CG) 2. Electric volume register setup (28h) . Data: ((*),*,%*,*,%*,7) 3. Power save set command . PS: off (Power save) . OS: on (Oscillation) 4. Power control set command . VR, VF, VC: on 5. RAM address set command 6. Data writing (RAM clear) (DDRAM = 20h, CGRAM / ICONRAM = 00h) Waiting for 20 msec or more Command input: 7. Display control commands .D:on Data input 8. Static Icon Display commands 20h : ( * ; * ; * ; * ; * ) ?1 h : ( * ; * ; * ; * ; * ) | End of initialization ) NOTES: At command (5) and (6), the internal RAM should be cleared. To clear DDRAM and FS (segment for signal) Set address at 30h (first DDRAM) and then write 20h (space character code) 13 times Set address at 40h and write 20h for 13 times Set address at 50h and write 20h for 13 times To clear CGRAM, Set address at 00h(first CGRAM) and then write OOh(null data) 32 times To clear ICONRAM, Set address at 60h(first ICONRAM) and then write OOh(null data) 13 times Set address at 70h and write 00h for 13 times 26 ELECTRONICSPreliminary 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD KS0090i Standby Mode Set or Release by Instruction (a) Standby mode set (b) Standby mode release ( End of initialization ) ( Standby mode ) J 4 Command input 1. Power save (PS: Power save off, OS: OSC on) 2. Power control (VR, VF, VC are all on) Command input 7 1. Display control (D: off) Waiting for 20 msec or more 2. Power save (PS: Power save on, OS: OSC on) 4 3. Power control (VR, VF, VC are all off) Normal operation status (Power save is released (off) and oscillator is on) t Command input 1 3. Display control (D: on) ( Standby status ) y ( Return to normal operation ) Sleep Mode Set or Release by Instruction (a) Sleep mode set (b) Sleep mode release ( End of initialization ) ( Sleep mode ) J 4 Command input 1. Power save (PS: Power save off, OS: OSC on) 2. Power control (VR, VF, VC are all on) Command input 7 1. Display control (D: off) Waiting for 20 msec or more 2. Power save (PS: Power save on, OS: OSC off) 4 3. Power control (VR, VF, VC are all off) Normal operation status (Power save is released (off) and oscillator is on) t Command input 1 3. Display control (D: on) ( Enter the sleep mode ) y ( Return to normal operation ) 27 ELECTRONICSPreliminary KS0090i 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD LCD DRIVING POWER SUPPLY CIRCUIT The power supply circuit produces LCD panel driving voltage at low power consumption. The LCD driving power supply circuit consists of voltage converter (2 times or 3 times), voltage regulator, and voltage follower. It is controlled by power control instruction. Table 10. shows how the LCD driving power supply circuit works by power control instruction sets. Table 10. Power Supply Control Mode Set Vol Vol Vol VR vF ve] ouage | Voltage | Voltage | vouT Pin vRPin | V0, V1, V2, V3, V4 Regulator | Follower | Converter Pin 1 1 1 Enable Enable Enable Internal voltage | Used for voltage | Internal voltage output adjustment output 1 1 0 Enable Enable Disable External Used for voltage | Internal voltage voltage input adjustment output 0 1 0 Disable Enable Disable Open Open V1 V4: Internal voltage output VO: External voltage input 0 0 0 Disable Disable Disable Open Open V0 V4: External voltage input NOTE: Any other case which is not written in this table is prohibited. 28 ELECTRONICSPreliminary 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD KS0090i VOLTAGE CONVERTER If capacitors are connected between CAP1+ and CAP1-, CAP2+ and CAP2-, VDD and VOUT, VDD- VSS voltage is positively tripled and generated at VOUT terminal. When the voltage is doubled, open CAP2- and connect CAP2+ to VOUT terminal. This boosted voltage is used in the built-in voltage regulator circuit. VOUT * VDD ae Vbp t 2x VDD CAP2+ CAP2- VOUT Vss Figure 11. Two Times Boosting VDD CAP1+ 3 x VDD CAP1- CAP2+ VoD. _ CAP2- VOLIT VDD te VDD VOUT 4 Vss Figure 12. Three Times Boosting i 29 ELECTRONICSPreliminary KS0090i 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD VOLTAGE REGULATOR The voltage regulator circuit is used to obtain an appropriate LCD panel driving voltage. This voltage is obtained by adjusting resistors Ra and Rb as shown in equation (1), and by setting electronic contrast control data bits. See equation (2) or (3). The potential of VO pin can be adjusted within Var to VOUT. Vp_r is the internal constant voltage source of the chip and this value is 2.0V in the condition Vpp 2 2.4V. Voltage regulation by adjusting resistors Ra, Rb The internal Vper of voltage regulator has the temperature compensation function, and the temperature coefficient is approximately 0.05%/C at range 20C to +50C. Rb y % VOUT VR = vee Vss [| Inside Chip MTN? Figure 13. Voltage Regulator Circuit 30 ELECTRONICS26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD ELECTRONIC CONTRAST CONTROL (EV=0, 32 STEPS) Preliminary KS0090i For 32 contrast-step, EV flag of EV set mode instruction field should be set to Low. Then, electronic contrast control data bits 28h = (C4, C3, C2, C1, CO) can be valid. Voltage regulation is adjusted as 32-contrast step according to the value of Electronic Contrast Control data bits. LCD drive voltage VO has one of 32 voltage values if 5-bit data is set to the electronic contrast control register (RAM address 28h). When using the electronic contrast control function, you need to turn on the voltage regulator using power control instruction. vo = ( 1 + Bo Ra) Vey = Vrer no a 30, 31) For example Ra = 1 MQ, Rob = 2 MQ,n=OthenVO=6V Table 11. Electronic Contrast Control Register (32 Steps) No. C7 C6 C5 C4 C3 c2 C1 C0 no vo Contrast 0 - - - 0 0 0 0 0 0 (default) Maximum High 1 - - - 0 0 0 0 1 1o 2 - - - 0 0 0 1 0 2a 3 - - - 0 0 0 1 1 3a 30 - - - 1 1 1 1 0 30 o 31 - - - 1 1 1 1 1 310 Minimum Low (: Dont Care) = M7. GND Rb VR i VREF Inside Chip | Vss Figure 14. Electronic Contrast Control Circuit ELECTRONICS 31Preliminary KS0090i 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD ELECTRONIC CONTRAST CONTROL (EV=1, 64 STEPS) For 64 contrast-step, EV flag of EV set mode instruction field should be set to High. After this, electronic contrast control data bits 28h = (C5, C4, C3, C2, C1, CO) can be valid. Voltage regulation is adjusted as 64-contrast step according to the value of Electronic Contrast Control data bits. LCD drive voltage VO has one of 64 voltage values if 6-bit data is set to the electronic contrast control register (RAM address 28h). When using the electronic contrast control function, you must turn on the voltage regulator using power control instruction. Rb VO = (1 + Re x Vey eee eee eee (3) Vey = VaeF- nao (n = 0, 1, 2, ween 62, 63) Table 12. Electronic Contrast Control Register (64 Steps) No. C7 C6 C5 C4 C3 C2 C1 co na vo Contrast 0 - - 0 0 0 0 0 0 0 (default) Maximum High 1 - - 0 0 0 0 0 1 1a 2 - - 0 0 0 0 1 0 20 3 - - 0 0 0 0 1 1 3a 62 1 1 1 1 1 0 62 a 63 - - 1 1 1 1 1 1 63 a Minimum Low (: Dont Care) = Inside Chip l | 4 Vss J GND Figure 15. Electronic Contrast Control Circuit 32 ELECTRONICSPreliminary 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD KS0090i VOLTAGE GENERATOR CIRCUIT VbD (Typical 5V) Vbpb (Typical 3V) VpD VpbD CAP 1+ ; t= CAP i+ ae CAP1- qi C= cart- CAP2+ a=] CAP2+ 4 CAP2- T_| CAP2- VOUT VOUT Rb vo vo VR VR Ra Ra = GND GND at) Vo | Vo ai v1 ath v1 at V2 ot V2 oti V3 oalan V3 at V4 ot V4 Vss Vss GND GND Two times boosting Three times boosting Figure 16. When Built-in Power Supply is Used (VR, VF, VC = 1, 1, 1) VDD VbD VDD L___t vop L__ VDD L___| vpp CAP 1+ CAP 1+ CAP 1+ External CAP 1- CAP1- CAP1- CAP2+ CAP2+ CAP2+ Power CAP2- CAP2- CAP2- Supply >| VOUT VOUT VOUT yryr- Rb vo vo va vo [lyr VR VR Rast - 4 External] _ a Vo Power vo External[ >| GND 7777- tit V1 V1 V1 tt} v2 Supply ve Power +! V2 tH V3 HVv3 > V3 5 eH V4 eH V4 Supply | V4 Vss oo! Vss ic See Vss GND GND GND (VR,VF,VC = 1, 1, 0) (VR,VF,VC = 0, 1, 0) (VR,VF,VC = 0, 0, 0) * Reference setting values : C2 = 0.1 ~ 4.7uF Figure 17. When External Power Supply is Used 33 ELECTRONICSPreliminary KS0090i 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD MPU INTERFACE Pull Up Resistor vcc | VDD A6-A0> | A6-A0 MPU KSO090i PORT1 _ | SCL PORT2 | SDA RES | RES GND T vss RESETB TTT Figure 18. IC Serial Interfacing with Any Microprocessors. Example of IC operation: 2 line display Step Operation Display I?C Byte 1 Reset by using RES pin KS0090i reset 2 C start I?C initialized. No display appears. 3 Acknowledge (During the acknowledge Slave address for write cycle SDA will be pulled-down by the A6 A5 A4 A3 A2 At AO R/W Ack KS0090i) A6 A5 A4 AZ A2 At ADO O O 4 Send a control byte for function set Co RS WB Ack (Control byte sets RS High for instruction) 1 0 0 x x x x x 0 ome di . COM left shift and don't DB7 DB6 DBS DB4 DB3 DB2 DB1 DBO Ack -line display, eft shift and don't use CGRAM ) 0 1 1 0 0 0 0 0 0 6 Send a control byte for function set Co RS WB Ack (Control byte sets RS High for instruction) 1 0 0 x x x x x 0 7 Address set (for EV register (28H)) DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO Ack 1 0 1 0 1 0 0 O 90 8 Send a control byte for write data Co RS WB Ack (Control byte sets RS High for EV register) 1 1 0 -.~ x x x OQ 9 Set EV register to DBO-DB7 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO Ack DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 0 34 ELECTRONICSPreliminary 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD KS0090i 10 Send a control byte for power save set CO RS WB Ack (Control byte sets RS Low for instruction) 0 0 0 xx x x x 0 11 Power save set DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO Ack (OS: On , PS: off) 0 1 0 O x7. x 4 0 860 12 Power control set DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO Ack (VR, VF, VC: On) 0 1 0 O x7. x 4 0 860 13 RAM address set ( ADDR = 30H ) DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO Ack 0 1 0 O x%X. x 1 0 860 14 I7C start For writing data to DDRAM (RAM Clear: DDRAM=20H) Therefore a control byte is needed. 15 Slave address for write Slave address for write (During the acknowledge cycle SDA will be A6 A5 A4 A3 A2 At AO R/W Ack pulled-down by the KS0090i) A6 A5 A4 AZ A2 At AO OO O 16 Send a control byte for write data Co RS WB Ack (Control byte sets RS High for RAM Clear) 0 1 0 %.~ K x x x 0 17 Write null character to DDRAM DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO Ack (ADDR=30H, DB[7:0]=20H) 0 860 { 0 0 O0O 0 0 0 18 Repeat 32 times of step 16 for 2-line RAM data 19 I2C start For writing display instruction, a control byte is needed. 20 Slave address for write Slave address for write (During the acknowledge cycle SDA will be A6 AS A4 A3 A2 At AOD R/W Ack pulled-down by the KSO090i) A6 A5 A4 ASB A2 At ADO O O 21 Send a control byte for write instruction CO RS WB Ack (Control byte sets RS Low for display 1 0 0 x x x x x 0 instruction) 22 Return Home DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO Ack 0 1 1 0 0 0 0 0 0 23 Send a control byte for write instruction CO RS WB Ack (Control byte sets RS Low for display 1 00xx. x xk x 0 instruction) 24 Display Control DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO Ack 0 0 1 1 1 1 x 1 0 25 Send a control byte for write data CO RS WB Ack (Control byte sets RS High for display { { 0 xx x x x 0 instruction) 26 Write data A DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO Ack 0 1 0 0 0 0 0 1 0 27 I7C stop ELECTRONICS 35Preliminary KS0090i 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD APPLICATION INFORMATION FOR LCD PANEL CHIP BOTTOM AND LOWER VIEW (S (COM) = 0, BID (SEG) = 0) Figure 19. 36 ELECTRONICSPreliminary 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD KS0090i CHIP BOTTOM & UPPER VIEW (S (COM) = 1, BID (SEG) = 1) Figure 20. 37 ELECTRONICSPreliminary KS0090i 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD CHIP TOP & LOWER VIEW (S (COM) = 0, BID (SEG) = 1) $s EE GG 55 87 KS0090/KS0090-| TOP VIEW Figure 21. ELECTRONICSPreliminary 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD KS0090i CHIP TOP & UPPER VIEW (S (COM) = 1, BID (SEG) = 0) KS0090/KS0090-| TOP VIEW Figure 22. 39 ELECTRONICSPreliminary KS0090i 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD FRAME FREQUENCY 1/18 DUTY (2-LINE MODE) 1-line selection period [2] i7|ie|+] 2] ------ ji7|tel 1 fe] ------ li7fte] 1 [2] ------ 719 vo V1 COM1 V4 Vv Ss 1 Frame iL 1 Frame | is > >| 1-line selection period = 13 clocks One Frame = 13 x 18 x 43.2 us = 10.0 ms (1 clock = 43.2 us at fosc = 23.4 kHz) Frame frequency = 1/10.0 ms = 100 Hz 1/26 DUTY (3-LINE MODE) 1-line selection period 1] 2] cece eee eeee 25/261 | 2] ----- errr eee 25/26/ 1] 2] ------ Vo V1 COM1 V4 Vv. SS L 1 Frame la 1 Frame | l- ia "| 1-line selection period = 13 clocks One Frame = 13 x 26 x 29.5 us = 10.0 ms (1 clock = 29.5 us at fosc = 33.8 kHz) Frame frequency = 1/10.0 ms = 100 Hz 40 ELECTRONICSPreliminary 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD KS0090i ABSOLUTE MAXIMUM RATINGS Table 13. Absolute Maximum Ratings Characteristics Symbol Value Unit Power supply voltage Vpp 0.3to+7.0 V Power supply voltage (2) VO, VOUT 0.3 to + 13.0 V Power supply voltage (3) v1 ; V2, V3, V4 0.3 to VO V Operating temperature Topr 3010 +85 C Storage temperature Tst 55 to + 125 C NOTES: 1. Voltage greater than above may damage the circuit 2. Allthe voltage levels are based on Vgg = OV 3. Voltage level: VOUT > VO = Vpp 2 Vss V0 2V12V2>V32V4 2 Veg A ELECTRONICSPreliminary KS0090i 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS Table 14. DC Characteristics (Vpp = 2.4V to 3.6V, Ta = 30 to + 85C) Item Symbol Condition Min. Typ. Max. Unit Operating voltage Vop - 2.4 - 3.6 Vv Supply current lpp4 Display operation, - - 80 LA (Vpp = 3V, Ta= 25C) Vicp = 6 V without load No access from MPU Ipp2 Standby operation, - - 10 without load, Oscillation on, Power off lpp3 Sleep operation, - - 5 without load, Oscillation off, Power off Ipp4 Access operation from MPU - - 500 Feyc=200 kHz Input voltage Vin - 0.8Vpp - VDD Vv Input leakage current lie Vin = OV to Vpop -1 - 1 HA Ron resistance Rcom Ilo =+50pA - - 5 kQ RseG lo =+50 LA _ _ 10 Frame frequency feR Vpp =3 V, Ta = 25C 70 100 130 Hz External clock frequency feK Display of 2-line mode - 23.4 - kHz Display of 3-line mode - 33.8 - Voltage converter Vout2/3 | Ta = 25C, C1 =1 WF 95 99 - % Vpp 2 or 3 times Without load Voltage regulator VReEF Ta = 25C 1.94 2.0 2.06 Vv reference voltage LCD driving voltage Viep Viep = VO - Vss 4.0 - 11.0 42 ELECTRONICSPreliminary 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD KS0090i Table 15. DC Characteristics (Vpp = 3.6V to 5.5V, Ta = 30 to + 85C) Item Symbol Condition Min. Typ. Max. Unit Operating voltage Vop - 3.6 - 5.5 Vv Supply current Ipp1 Display operation, - - 100 LA (Vpp = 5V, Ta= 25C) Vip = 6 V without load No access from MPU Ipp2 Standby operation, - - 20 without load, Oscillation on, Power off Ipp3 Sleep operation, - - 10 without load, Oscillation off, Power off Ipp4 Access operation from MPU - - 1000 Feyc=200 kHz Input voltage Vin - 0.8Vpp - VDD Vv ViL _ Vss _ 0.2VDD Input leakage current ie Vin = OV to Vpp 1 - 1 LA Ron resistance Rcom lo =+50 uA - - 5 kQ RseG lo =+50 LA _ _ 10 Frame frequency fer Vop = 5 V, Ta = 25C 70 100 130 Hz External clock frequency fox Display of 2-line mode - 23.4 - kHz Display of 3-line mode - 33.8 - Voltage converter Voute | Ta=25C, C1 =1 ur 95 99 - % Vpp 2 times Without load Voltage regulator Veer Ta = 25C 1.94 2.0 2.06 Vv reference voltage LCD driving voltage Vicp Vip = V0- Vss 4.0 - 11.0 NOTE: When power supply (Vpp) range is 3.6 V to 5.5 V, the boosting of the voltage converter is only available 2 times. ELECTRONICS 43Preliminary KS0090i 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD AC CHARACTERISTICS (Vpp = 2.4V to 3.6V, Ta = 30 to + 85C) Mode Characteristic Symbol Min. Typ. Max. Unit SCL clock cycle time tse 2 - 20 us SCL clock high level width THIGH 500 - - SCL clock low level width tLlow 1000 - - SCL/SDA rise / fall time (CL=60pF) | tp, te - - 300 IC Serial Bus free time tBUF 1000 - - Interface Mode | START hold time tsTaH 500 - - ns START setup time tstas 500 - - SDA data setup time tpaTs 140 - - SDA data hold time tDATH 0 - - STOP setup time tstps 500 - - (Vpp = 3.6V to 5.5V, Ta = 30 to + 85C) Mode Characteristic Symbol Min. Typ. Max. Unit SCL clock cycle time tse. 2 - 20 us SCL clock high level width THIGH 500 - - SCL clock low level width tLlow 1000 - - SCL/SDA rise / fall time (CL=60pF) | tp, tr - - 300 IC Serial Bus free time tBuF 1000 - - Interface Mode | START hold time tsTAH 500 - - ns START setup time tsTas 500 - - SDA data setup time tpaTs 100 - - SDA data hold time tDATH 0 - - STOP setup time tstps 500 - - 44 ELECTRONICSPreliminary 26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD KS0090i STOP START RESTART SDA | [ | tour | _ EST < beet toaTH tetas >] toats lstps taicH SCL | > I< kq Figure 23. I2C Serial Interface Mode Timing ELECTRONICS