1
FEATURES DESCRIPTION
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC NC
NC
EN1
MR
RESET
EN2
VOUT1
VOUT1
VIN1
VIN1
VSENSE1/FB1
VSENSE2/FB2
VOUT2
VOUT2
VIN2
VIN2
PG1
PG2
GND
PWPPACKAGE
(TOPVIEW)
NC:Nointernalconnection
TPS70845, TPS70848TPS70851, TPS70858
TPS70802
SLVS301D JUNE 2000 REVISED DECEMBER 2007www.ti.com
DUAL-OUTPUT, LOW DROPOUT VOLTAGE REGULATORSWITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
23
Dual Output Voltages for Split-Supply
The TPS708xx is a low dropout voltage regulator withApplications
integrated SVS ( RESET, POR, or power on reset)and power good (PG) functions. These devices areIndependent Enable Functions (See Part
capable of supplying 250 mA and 125 mA byNumber TPS707xx for Sequenced Outputs)
regulator 1 and regulator 2 respectively. QuiescentOutput Current Range of 250 mA on Regulator
current is typically 190 µA at full load. Differentiated1 and 125 mA on Regulator 2
features, such as accuracy, fast transient response,Voltage Options: 3.3-V/2.5-V, 3.3-V/1.8-V,
SVS supervisory circuit (power on reset), manualreset input, and independent enable functions provide3.3-V/1.5-V, 3.3-V/1.2-V, and Dual Adjustable
a complete system solution.Outputs
Open Drain Power-On Reset with 120-ms DelayOpen Drain Power Good for Regulator 1 andRegulator 2Ultralow 190- µA (typ) Quiescent Current1- µA Input Current During StandbyLow Noise: 65 µV
RMS
Without BypassCapacitor
Quick Output Capacitor Discharge FeatureOne Manual Reset Input2% Accuracy Over Load and TemperatureUndervoltage Lockout (UVLO) Feature20-Pin PowerPAD™ TSSOP PackageThermal Shutdown Protection
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2000 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
TPS70851PWP
5V
0.1 Fm
0.1 Fm
10 Fm
10 Fm
EN1
MR MR
RESET
EN1
EN2
EN2
<0.7V
>2V
<0.7V
>2V
<0.7V
>2V
VOUT1
VIN1
VSENSE1
VSENSE2
VOUT2
VIN2
PG1 PG1
PG2 PG2
250kW
250kW
250kW
1.8V
3.3V
RESET
Core
I/O
DESCRIPTION (CONTINUED)
TPS70845, TPS70848TPS70851, TPS70858TPS70802
SLVS301D JUNE 2000 REVISED DECEMBER 2007
The TPS708xx family of voltage regulators offers very low dropout voltage and dual outputs. These devices haveextremely low noise output performance without using any added filter bypass capacitors and are designed tohave a fast transient response and be stable with 10- µF low ESR capacitors.
These devices have fixed 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and adjustable voltage options.Regulator 1 can support up to 250 mA, and regulator 2 can support up to 125 mA. Separate voltage inputs allowthe designer to configure the source power.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170 mV onregulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is avoltage-driven device, the quiescent current is very low and independent of output loading (maximum of 230 µAover the full range of output current and full range of temperature). This LDO family also features a sleep mode;applying a high signal to EN1 or EN2 (enable) shuts down regulator 1 or regulator 2, respectively. When a highsignal is applied to both EN1 and EN2, both regulators enter sleep mode, thereby reducing the input current to 2µA at T
J
= +25 °C.
For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulatoris turned off (disabled).
The PG1 pin reports the voltage condition at V
OUT1
. The PG1 pin can be used to implement a SVS ( RESET,POR, or power on reset) for the circuitry supplied by regulator 1. The PG2 pin reports the voltage conditions atV
OUT2
. The PG2 pin can be used to implement a SVS (power on reset) for the circuitry supplied by regulator 2.
The TPS708xx features a RESET (SVS, POR, or power on reset). RESET output initiates a reset in the event ofan undervoltage condition. RESET also indicates the status of the manual reset pin ( MR). When MR is in thelogic high state, RESET goes to a high impedance state after a 120-ms delay. To monitor V
OUT1
, the PG1 outputpin can be connected to MR. To monitor V
OUT2
, the PG2 output pin can be connected to MR.
The device has an undervoltage lockout UVLO circuit that prevents the internal regulators from turning on untilV
IN1
reaches 2.5V.
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ABSOLUTE MAXIMUM RATINGS
(1)
TPS70845, TPS70848TPS70851, TPS70858
TPS70802
SLVS301D JUNE 2000 REVISED DECEMBER 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
VOLTAGE (V)
(2)
PACKAGE- SPECIFIEDLEAD TEMPERATURE ORDERING TRANSPORTPRODUCT V
OUT1
V
OUT2
(DESIGNATOR) RANGE (T
J
) NUMBER MEDIA, QUANTITY
TPS70802PWP Tube, 70TPS70802 Adjustable Adjustable HTSSOP-20 (PWP) 40 °C to +125 °C
TPS70802PWPR Tape and Reel, 2000TPS70845PWP Tube, 70TPS70845 3.3 V 1.2 V HTSSOP-20 (PWP) 40 °C to +125 °C
TPS70845PWPR Tape and Reel, 2000TPS70848PWP Tube, 70TPS70848 3.3 V 1.5 V HTSSOP-20 (PWP) 40 °C to +125 °C
TPS70848PWPR Tape and Reel, 2000TPS70851PWP Tube, 70TPS70851 3.3 V 1.8 V HTSSOP-20 (PWP) 40 °C to +125 °C
TPS70851PWPR Tape and Reel, 2000TPS70858PWP Tube, 70TPS70858 3.3 V 2.5 V HTSSOP-20 (PWP) 40 °C to +125 °C
TPS70858PWPR Tape and Reel, 2000
(1) For the most current package and ordering information see the Package Option Addendum located at the end of this document, or seethe TI web site at www.ti.com .(2) For fixed 1.20 V operation, tie FB to OUT.
Over operating free-air temperature range (unless otherwise noted).
TPS708xx UNIT
Input voltage range: V
IN1
, V
IN2
(2)
0.3 to +7 VVoltage range at EN1, EN2 0.3 to +7 VOutput voltage range (V
OUT1
, V
SENSE1
) 5.5 VOutput voltage range (V
OUT2
, V
SENSE2
) 5.5 VMaximum RESET, PG1, PG2 voltage 7 VMaximum MR voltage V
IN1
VPeak output current Internally limited Continuous total power dissipation See Dissipation Ratings Table Operating virtual junction temperature range, T
J
40 to +150 °CStorage temperature range, T
stg
65 to +150 °CESD rating, HBM 2 kV
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltages are tied to network ground.
Copyright © 2000 2007, Texas Instruments Incorporated Submit Documentation Feedback 3
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DISSIPATION RATINGS
RECOMMENDED OPERATING CONDITIONS
TPS70845, TPS70848TPS70851, TPS70858TPS70802
SLVS301D JUNE 2000 REVISED DECEMBER 2007
DERATINGPACKAGE AIR FLOW (CFM) T
A
+25 °C T
A
= +70 °C T
A
= +85 °CFACTOR
0 3.067 W 30.67 mW/ °C 1.687 W 1.227 WPWP
(1)
250 4.115 W 41.15 mW/ °C 2.265 W 1.646 W
(1) This parameter is measured with the recommended copper heat sink pattern on a 4-layer PCB, 1 oz. copper on a 4-in by 4-in groundlayer. Simultaneous and continuous operation of both regulator outputs at full load may exceed the power dissipation rating of the PWPpackage. For more information, refer to TI technical brief SLMA002 .
Over operating temperature range (unless otherwise noted).
MIN MAX UNIT
Input voltage, V
I
(1)
(regulator 1 and 2) 2.7 6 VOutput current, I
O
(regulator 1) 0 500 mAOutput current, I
O
(regulator 2) 0 250 mAOutput voltage range (for adjustable option) 1.22 5.5 VOperating virtual junction temperature, T
J
40 +125 °C
(1) To calculate the minimum input voltage for maximum output current, use the following equation: V
I(min)
= V
O(max)
+ V
DO(max load)
.
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ELECTRICAL CHARACTERISTICS
(3) If V
O
< 1.8 V then V
Imax
= 6 V, V
Imin
= 2.7 V:
Lineregulation(mV)=(%/V)x Vox1000
(V 2.7)
100
-
Imax
If V
O
> 2.5 V then V
Imax
= 6 V, V
Imin
= V
O
+ 1 V:
x1000
[ V (V +1) ]
100
-
Imax o
Lineregulation(mV)=(%/V)x Vo
TPS70845, TPS70848TPS70851, TPS70858
TPS70802
SLVS301D JUNE 2000 REVISED DECEMBER 2007
Over recommended operating junction temperature range (T
J
= 40 °C to +125 °C), V
IN1
or V
IN2
= V
OUT(nom)
+ 1 V, I
O
= 1 mA,EN = 0 V, and C
OUT
= 33 µF (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
2.7 V < V
IN
< 6 V,
FB connected to V
O
1.22Reference
T
J
= +25 °Cvoltage
2.7 V < V
IN
< 6 V, FB connected to V
O
1.196 1.2442.7 V < V
IN
< 6 V, T
J
= +25 °C 1.21.2 V Output
2.7 V < V
IN
< 6 V, 1.176 1.2242.7 V < V
IN
< 6 V, T
J
= +25 °C 1.51.5 V OutputOutput
2.7 V < V
IN
< 6 V, 1.47 1.53V
O
Vvoltage
(1), (2)
2.8 V < V
IN
< 6 V, T
J
= +25 °C 1.81.8 V Output
2.8 V < V
IN
< 6 V, 1.764 1.8363.5 V < V
IN
< 6 V, T
J
= +25 °C 2.52.5 V Output
3.5 V < V
IN
< 6 V, 2.45 2.554.3 V < V
IN
< 6 V, T
J
= +25 °C 3.33.3 V Output
4.3 V < V
IN
< 6 V, 3.234 3.366Quiescent current (GND current) for See
(2)
T
J
= +25 °C 190regulator 1 and regulator 2, EN1 = EN2 µASee
(2)
230= 0 V
(1)
V
O
+ 1 V < V
IN
6 V, T
J
= +25 °C
(1)
0.01Output voltage line regulation ( V
O
/V
O
)
%Vfor regulator 1 and regulator 2
(3)
V
O
+ 1 V < V
IN
6 V
(1)
0.1Load regulation for V
OUT 1
and V
OUT2
T
J
= +25 °C 1 mVRegulator 1 65Output noiseV
n
BW = 300 Hz to 50 kHz, C
O
= 33 µF, T
J
= +25 °CµV
RMSvoltage
Regulator 2 65Regulator 1 1.6 1.9Output current limit V
OUT
= 0 V ARegulator 2 0.750 1Thermal shutdown junction temperature +150 °CRegulator 1 EN1 = V
IN
, EN2 = V
IN
T
J
= +25 °C 2I
I
Standby
µA(standby) current
Regulator 2 EN1 = V
IN
, EN2 = V
IN
6f = 1 kHz, C
OUT
= 33 µF,Regulator 1 T
J
= +25 °C
(1)
60Power-
I
OUT1
= 250 mAPSRR supply ripple dBf = 1 kHz, C
OUT
= 33 µF,rejection
Regulator 2 T
J
= +25 °C
(1)
50I
OUT2
= 125 mAUVLO threshold 2.4 2.65 V
RESET Terminal
Minimum input voltage for valid RESET I
(RESET)
= 300 µA, V
(RESET)
0.8 V 1.0 1.3 Vt
(RESET)
RESET pulse duration 80 120 160 msOutput low voltage V
IN
= 3.5 V, I
(RESET)
= 1 mA 0.15 0.4 VLeakage current V
(RESET)
= 6 V 1 µA
(1) Minimum input operating voltage is 2.7 V or V
O(typ)
+ 1 V, whichever is greater. Maximum input voltage = 6 V, minimum outputcurrent = 1 mA.(2) I
O
= 1 mA to 250 mA for Regulator 1 and 1 mA to 125 mA for Regulator 2.
Copyright © 2000 2007, Texas Instruments Incorporated Submit Documentation Feedback 5
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TPS70845, TPS70848TPS70851, TPS70858TPS70802
SLVS301D JUNE 2000 REVISED DECEMBER 2007
ELECTRICAL CHARACTERISTICS (continued)Over recommended operating junction temperature range (T
J
= 40 °C to +125 °C), V
IN1
or V
IN2
= V
OUT(nom)
+ 1 V, I
O
= 1 mA,EN = 0 V, and C
OUT
= 33 µF (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PG1/PG2 Terminal
Minimum input voltage for valid PGx I
(PGx)
= 300 µA, V
(PGx)
0.8 V 1.0 1.3 VTrip threshold voltage V
O
decreasing 92 95 98 %V
OUT
Hysteresis voltage Measured at V
O
0.5 %V
OUT
t
r(PGx)
Rising edge deglitch 30 µsOutput low voltage V
IN
= 2.7V, I
(PGx)
= 1 mA 0.15 0.4 VLeakage current V
(PGx)
= 6V 1 µA
EN1/EN2 Terminal
High-level ENx input voltage 2 VLow-level ENx input voltage 0.7 VInput current ( ENx) 1 1 µA
MR Terminal
High-level input voltage 2 VLow-level input voltage 0.7 VFalling edge delay Measured at V
O
140 µsPull-up current source 6 µA
V
OUT1
Terminal
I
O
= 250 mA, V
IN1
= 3.2 V T
J
= +25 °C 83Dropout voltage
(4)
mVI
O
= 250 mA, V
IN1
= 3.2 V 140Peak output current 2 ms pulse width 750 mADischarge transistor current V
OUT1
= 1.5 V 7.5 mA
V
OUT2
Terminal
Peak output current 2 ms pulse width 375 mADischarge transistor current V
OUT2
= 1.5 V 7.5 mA
FB Terminal
Input current: TPS70802 FB = 1.8 V 1 µA
(4) Input voltage (V
IN1
or V
IN2
) = V
O(typ)
100 mV. For 1.5-V, 1.8-V, and 2.5-V regulators, the dropout voltage is limited by input voltagerange. The 3.3-V regulator input is set to 3.2 V to perform this test.
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DEVICE INFORMATION
UVLO
Comp
+
-
+
-
Thermal
Shutdown
2.5V
+-
Current
Sense
Reference Vref
Vref
ENA_1
FB1
ENA_1
FallingEdge
Delay
0.95xVref
VSENSE1
0.95xVref
VSENSE2
RisingEdge
Deglitch
ENA_1
ENA_2
Current
Sense
+-
ENA_2
ENA_2
FB2
Vref
V (2Pins)
IN1
GND
EN1
EN2
VIN2 (2Pins)
PG1
MR
RESET
VIN1
PG1
Comp
RisingEdge
Deglitch
PG2
PG2
Comp
VOUT2 (2Pins)
+
-
10kW
VSENSE1
(seeNoteA)
V (2Pins)
OUT1
VSENSE2
(seeNoteA)
10kW
TPS70845, TPS70848TPS70851, TPS70858
TPS70802
SLVS301D JUNE 2000 REVISED DECEMBER 2007
Fixed Voltage Version
A. For most applications, V
SENSE1
and V
SENSE2
should be externally connected to V
OUT1
and V
OUT2
, respectively, asclose as possible to the device. For other implementations, refer to SENSE terminal connection discussion in theApplication Information section.
Copyright © 2000 2007, Texas Instruments Incorporated Submit Documentation Feedback 7
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UVLO
Comp
+
-
+
-
Thermal
Shutdown
2.5V
+-
Current
Sense
Reference Vref
Vref
ENA_1
ENA_1
FallingEdge
Delay
0.95xVref
FB1
0.95xVref
FB2
RisingEdge
Deglitch
ENA_1
ENA_2
Current
Sense
+-
ENA_2
ENA_2
FB2
Vref
V (2Pins)
IN1
GND
EN1
EN2
VIN2 (2Pins)
FB1
(seeNoteA)
PG1
MR
RESET
FB2
(seeNoteA)
VIN1
PG1
Comp
RisingEdge
Deglitch
PG2
PG2
Comp
VOUT1 (2Pins)
VOUT2 (2Pins)
+
-
TPS70845, TPS70848TPS70851, TPS70858TPS70802
SLVS301D JUNE 2000 REVISED DECEMBER 2007
Adjustable Voltage Version
A. For most applications, FB1 and FB2 should be externally connected to resistor dividers as close as possible to thedevice. For other implementations, refer to FB terminals connection discussion in the Application Informationsection.
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VIN1
VUVLO VUVLO
t
t
t
MR Input
RESET Output
120ms
Delay
120ms
Delay
VRES
Output
Undefined
Output
Undefined
VRES
NOTEA: V istheminimuminputvoltageforavalid.Thesymbol V isnotcurrentlylistedwithinEIAorJEDEC
standardsforsemiconductorsymbology.
RES RES
RESET
(seeNoteA)
TPS70845, TPS70848TPS70851, TPS70858
TPS70802
SLVS301D JUNE 2000 REVISED DECEMBER 2007
RESET Timing Diagram
PG1 Timing Diagram
Copyright © 2000 2007, Texas Instruments Incorporated Submit Documentation Feedback 9
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t
t
PG2
Output
VIN2
t
VIT+
(seeNoteA)
VOUT2
V
(seeNoteA)
Threshold
Voltage
IT-
NOTEA: V tripvoltageistypically5%lowerthantheoutputvoltage(95%V ).V toV isthehysteresisvoltage.
IT IT- -
O IT+
TPS70845, TPS70848TPS70851, TPS70858TPS70802
SLVS301D JUNE 2000 REVISED DECEMBER 2007
PG2 Timing Diagram (assuming V
IN1
already powered up)
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTIONNAME NO.
EN1 5 I Active low enable for V
OUT1
EN2 6 I Active low enable for V
OUT2
GND 8 GroundMR 4 I Manual reset input, active low, pulled up internallyNC 1, 11, 20 No connectionPG1 16 O Open drain output, low when V
OUT1
voltage is less than 95% of the nominal regulated voltagePG2 15 O Open drain output, low when V
OUT2
voltage is less than 95% of the nominal regulated voltageRESET 7 I Open drain output, SVS (power-on reset) signal, active lowV
IN1
2, 3 I Input voltage of regulator 1V
IN2
9, 10 I Input voltage of regulator 2V
OUT1
18, 19 O Output voltage of regulator 1V
OUT2
12, 13 O Output voltage of regulator 2V
SENSE2
/FB2 14 I Regulator 2 output voltage sense/regulator 2 feedback for adjustableV
SENSE1
/FB1 17 I Regulator 1 output voltage sense/regulator 1 feedback for adjustable
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Detailed Description
Pin Functions
Enable ( EN1, EN2)
Power-Good (PG1, PG2)
Manual Reset Pin
Sense (V
SENSE1
, V
SENSE2
)
TPS70845, TPS70848TPS70851, TPS70858
TPS70802
SLVS301D JUNE 2000 REVISED DECEMBER 2007
The TPS708xx low dropout regulator family provides dual regulated output voltages with independent enablefunctions. These devices provide fast transient response and high accuracy with small output capacitors, whiledrawing low quiescent current. Other features are integrated SVS (power-on reset, RESET) and power good(PG1, PG2) that monitor output voltages and provide logic output to the system. These differentiated featuresprovide a complete power solution.
The TPS708xx, unlike many other LDOs, features very low quiescent current that remains virtually constant evenwith varying loads. Conventional LDO regulators use a PNP pass element, the base current of which is directlyproportional to the load current through the regulator (I
B
= I
C
/β). The TPS708xx uses a PMOS transistor to passcurrent; because the gate of the PMOS is voltage-driven, operating current is low and stable over the full loadrange.
The EN terminals are inputs that enable or shut down each respective regulator. If EN is at a voltage high signal,the respective regulator is in shutdown mode. When EN goes to voltage low, the respective regulator is enabled.
The PG terminals are open drain, active high output terminals that indicate the status of each respectiveregulator. When V
OUT1
reaches 95% of its regulated voltage, PG1 goes to a high impedance state. When V
OUT2reaches 95% of its regulated voltage, PG2 goes to a high impedance state. Each PG goes to a low impedancestate when its respective output voltage is pulled below 95% (that is, goes to an overload condition) of itsregulated voltage. The open drain outputs of the PG terminals require a pull-up resistor.
MR is an active low input terminal used to trigger a reset condition. When MR is pulled to logic low, a POR( RESET) occurs. The terminal has a 6- µA pull-up current to V
IN1
.
The sense terminals of fixed-output options must be connected to the regulator outputs, and the connectionshould be as short as possible. Internally, the sense terminal connects to high-impedance, wide-bandwidthamplifiers through a resistor-divider network and noise pickup feeds through to the regulator output. It is essentialto route the sense connection in such a way as to minimize or avoid noise pickup. Adding RC networks betweensense terminals and V
OUT
terminals to filter noise is not recommended because these networks can cause theregulators to oscillate.
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FB1 and FB2
RESET Indicator
V
IN1
and V
IN2
V
OUT1
and V
OUT2
TPS70845, TPS70848TPS70851, TPS70858TPS70802
SLVS301D JUNE 2000 REVISED DECEMBER 2007
FB1 and FB2 are input terminals used for adjustable-output devices and must be connected to the externalfeedback resistor divider. FB1 and FB2 connections should be as short as possible. It is essential to route themin such a way as to minimize or avoid noise pickup. Adding RC networks between FB terminals and V
OUTterminals to filter noise is not recommended because these networks can cause the regulators to oscillate.
The TPS708xx features a RESET (SVS, POR, or power on reset). RESET can be used to drive power on resetcircuitry or a low-battery indicator. RESET is an active low, open drain output that indicates the status of themanual reset pin ( MR). When MR is in a high-impedance state, RESET goes to a high impedance state after a120-ms delay. To monitor V
OUT1
, the PG1 output pin can be connected to MR. To monitor V
OUT2
, the PG2 outputpin can be connected to MR. The open drain output of the RESET terminal requires a pull-up resistor. If RESETis not used, it can be left floating.
V
IN1
and V
IN2
are inputs to each regulator. Internal bias voltages are powered by V
IN1
.
V
OUT1
and V
OUT2
are output terminals of each regulator.
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TYPICAL CHARACTERISTICS
3.299
3.298
3.296
3.295
0 0.05 0.1 0.15
3.301
3.302
3.303
0.2 0.25
3.3
3.297
V =4.3V
T =+25 C
V
IN1
J
OUT1
°
I OutputCurrent A
O- -
V OutputVoltage V
O- -
1.799
1.797
1.796
1.795
0 0.025 0.05 0.075
1.800
1.801
1.802
0.1 0.125
1.798
V =2.8V
T =+25 C
V
IN2
J
OUT2
°
I OutputCurrent A
O- -
V OutputVoltage V
O- -
TPS70845, TPS70848TPS70851, TPS70858
TPS70802
SLVS301D JUNE 2000 REVISED DECEMBER 2007
Table of Graphs
FIGURE
vs Output current Figure 1 to Figure 3V
O
Output voltage
vs Junction temperature Figure 4 to Figure 5Ground current vs Junction temperature Figure 6PSRR Power-supply rejection ratio vs Frequency Figure 7 to Figure 10Output spectral noise density vs Frequency Figure 11 to Figure 14Z
O
Output impedance vs Frequency Figure 15 to Figure 18vs Temperature Figure 19 and Figure 20Dropout voltage
vs Input voltage Figure 21 and Figure 22Load transient response Figure 23 and Figure 24Line transient response (V
OUT1
)Figure 25Line transient response (V
OUT2
)Figure 26V
O
Output voltage vs Time (start-up) Figure 27 and Figure 28Equivalent series resistance (ESR) vs Output current Figure 30 to Figure 33
TPS70851 TPS70851OUTPUT VOLTAGE OUTPUT VOLTAGEvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 1. Figure 2.
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3.23
3.25
3.27
3.29
3.31
3.33
3.35
-40 -25 -10 5 20 35 50 65 80 95 110 125
IO=250mA
IO=1mA
V =4.3V
V
IN1
OUT1
V OutputVoltage V
O- -
T JunctionTemperature C- -
J°
1.198
1.197
1.196
1.195
0 0.025 0.05 0.075
1.199
1.200
1.201
0.1 0.125
V =2.7V
T =+25 C
V
IN2
J
OUT2
°
I OutputCurrent A
O- -
V OutputVoltage V
O- -
1.73
1.75
1.77
1.79
1.81
1.83
40 25 10 5 20 35 50 65 80 95 110 125
1.85
IO=1mA
IO=250mA
V =2.8V
V
IN2
OUT2
V OutputVoltage V
O- -
T JunctionTemperature C- -
J°
150
160
170
180
-40 -25 -10 5 20 35 50 65 80 95 110 125
190
200
210
Regulator1andRegulator2
I
I =125mA
OUT1
OUT2
=250mA
I
I =1mA
OUT1
OUT2
=1mA
T JunctionTemperature C- -
J°
GroundCurrent A- m
TPS70845, TPS70848TPS70851, TPS70858TPS70802
SLVS301D JUNE 2000 REVISED DECEMBER 2007
TPS70845 TPS70851OUTPUT VOLTAGE OUTPUT VOLTAGEvs vsOUTPUT CURRENT JUNCTION TEMPERATURE
Figure 3. Figure 4.
TPS70851 TPS70851OUTPUT VOLTAGE GROUND CURRENTvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 5. Figure 6.
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-60
-80
-9010 100 1 k 10 k
-40
-20
-10
100k 1 M
-30
-50
-70
I =10mA
C =22 F
O
Om
VOUT1
PSRR PowerSupplyRejectionRatio dB
- -
f Frequency Hz- -
-40
-60
-70
-90
10 100 1 k 10 k
-20
0
10
100k 1 M
-10
-30
-50
-80
I =250mA
C =22 F
V
O
O
OUT1
m
PSRR PowerSupplyRejectionRatio dB
- -
f Frequency Hz- -
-60
-80
-90
10 100 1 k 10 k
-40
-20
-10
100k 1 M
-30
-50
-70
I =10mA
C =22 F
V
O
O
OUT2
m
PSRR PowerSupplyRejectionRatio dB
- -
f Frequency Hz- -
-40
-60
-70
-90
10 100 1 k 10 k
-20
0
10
100k 1 M
-10
-30
-50
-80
I =150mA
C =22 F
V
O
O
OUT2
m
PSRR PowerSupplyRejectionRatio dB
- -
f Frequency Hz- -
TPS70845, TPS70848TPS70851, TPS70858
TPS70802
SLVS301D JUNE 2000 REVISED DECEMBER 2007
TPS70851 TPS70851POWER-SUPPLY REJECTION RATIO POWER-SUPPLY REJECTION RATIOvs vsFREQUENCY FREQUENCY
Figure 7. Figure 8.
TPS70851 TPS70851POWER-SUPPLY REJECTION RATIO POWER-SUPPLY REJECTION RATIOvs vsFREQUENCY FREQUENCY
Figure 9. Figure 10.
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0.01
0.1
1
10
100 1k 10k 100 k
f Frequency Hz- -
V =4.3V
V =3.3V
I =250mA
IN1
OUT1
O
OutputSpectralNoiseDensity - mV/ Hz
Ö
0.01
0.1
1
10
100 1 k 10 k 100 k
f Frequency Hz- -
V =4.3V
V =3.3V
I =10mA
IN1
OUT1
O
OutputSpectralNoiseDensity - mV/ Hz
Ö
0.01
0.1
1
10
100 1 k 10 k 100 k
f Frequency Hz- -
V =2.8V
V =1.8V
I =125mA
IN2
OUT2
O
OutputSpectralNoiseDensity - mV/ Hz
Ö
0.01
0.1
1
10
100 1 k 10 k 100
f Frequency Hz- -
V =2.8V
V =1.8V
I =10mA
IN2
OUT2
O
OutputSpectralNoiseDensity - mV/ Hz
Ö
TPS70845, TPS70848TPS70851, TPS70858TPS70802
SLVS301D JUNE 2000 REVISED DECEMBER 2007
OUTPUT SPECTRAL NOISE DENSITY OUTPUT SPECTRAL NOISE DENSITYvs vsFREQUENCY FREQUENCY
Figure 11. Figure 12.
OUTPUT SPECTRAL NOISE DENSITY OUTPUT SPECTRAL NOISE DENSITYvs vsFREQUENCY FREQUENCY
Figure 13. Figure 14.
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10 100 1 k 10 k
10
100
100k 1 M 10M
1
0.1
0.01
C =33 F
I =10mA
V =3.3V
T =+25
O
O
OUT1
J
m
C
°
Z OutputImpedance
O- - W
f Frequency- - Hz
10 100 1 k 10 k 100k 1 M 10M
10
1
0.1
0.01
C =33 F
T =+25
O
J
m
C
I =250mA
V =3.3V
O
OUT1
°
OutputImpedance - WZO-
f Frequency- - Hz
10 100 1 k 10 k
10
100
100k 1 M 10M
1
0.1
0.01
C =33 F
I =10mA
V =1.8V
T =+25
O
O
OUT2
J
m
C
°
Z OutputImpedance
O- - W
f Frequency- - Hz
10
1
0.1 10 100 1 k 10 k 100k 1 M 10M
C =33 F
I =125mA
V =1.8V
T =+25
O
O
OUT2
J
m
C
°
ZOutputImpedance
O- - W
f Frequency- - Hz
TPS70845, TPS70848TPS70851, TPS70858
TPS70802
SLVS301D JUNE 2000 REVISED DECEMBER 2007
OUTPUT IMPEDANCE OUTPUT IMPEDANCEvs vsFREQUENCY FREQUENCY
Figure 15. Figure 16.
OUTPUT IMPEDANCE OUTPUT IMPEDANCEvs vsFREQUENCY FREQUENCY
Figure 17. Figure 18.
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0
1
2
3
4
5
6
-40 -25 -10 5 20 35 50 65 80 95 110 125
IO=10mA
IO=0mA
C
V =3.2V
O
IN1
=33 Fm
DropoutVoltage -mV
T JunctionTemperature C- -
J°
-40 -25 -10 5 20 35 50 65 80 95 110 125
0
40
60
80
100
120
20
IO=250mA
C
V =3.2V
O
IN1
=33 Fm
T JunctionTemperature C- -
J°
DropoutVoltage -mV
0
20
40
80
100
120
2.5 3 3.5 4 4.5 5
140
60
I
V
O
OUT1
=250mA
DropoutVoltage -mV
V InputVoltage- -
IV
T +25 C=
J°
T +125 C=
J°
T 40 C= -
J°
0
50
100
150
200
250
2.5 3 3.5 4 4.5 5
I
V
O
OUT2
=125mA
DropoutVoltage -mV
V InputVoltage- -
IV
T +25 C=
J°
T +125 C=
J°
T 40 C= -
J°
TPS70845, TPS70848TPS70851, TPS70858TPS70802
SLVS301D JUNE 2000 REVISED DECEMBER 2007
TPS70851 TPS70851DROPOUT VOLTAGE DROPOUT VOLTAGEvs vsTEMPERATURE TEMPERATURE
Figure 19. Figure 20.
TPS70802 TPS70802DROPOUT VOLTAGE DROPOUT VOLTAGEvs vsINPUT VOLTAGE INPUT VOLTAGE
Figure 21. Figure 22.
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0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
20
250
0
0
-20
-40
C =33 F
T =+25 C
O
J
m
°
V =3.3V
OUT1
T Time s- - m
IOutput
O-Current mA-
D-
-
V Changein
OutputVoltage mV
O
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
20
0
125
0
-20
-40
-60
-80
C =33 F
T =+25 C
O
J
m
°
V =1.8V
OUT2
T Time s- - m
IOutput
O-Current mA-
D-
-
V Changein
OutputVoltage mV
O
0 20 40 60 80 100 120
2.8
140 160 180 200
0
10
-10
3.8
I
C =33 F
V
O
O
OUT2
=125mA
m
T Time s- - m
V Input
I-Voltage V-
D-
-
V Changein
OutputVoltage mV
O
0 20 40 60 80 100 120
5.3
4.3
140 160 180 200
0
50
-50
I
C =33 F
O
O
=250mA
m
VOUT1
T Time s- - m
V Input
I-Voltage V-
D -
-
V Changein
OutputVoltage mV
O
TPS70845, TPS70848TPS70851, TPS70858
TPS70802
SLVS301D JUNE 2000 REVISED DECEMBER 2007
LOAD TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE
Figure 23. Figure 24.
LINE TRANSIENT RESPONSE LINE TRANSIENT RESPONSE
Figure 25. Figure 26.
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0 2.0
0
2
3
1
0
5
0.2 1.81.61.41.21.00.4 0.6 0.8
V =3.3V
O
C =33 F
I =250mA
V =Standby
O
O
OUT2
m
EnableVoltage(EN1) V-V Output
OUT1 -Voltage
T Time s- - m
0 2.0
0
2
3
1
0
5
0.2 1.81.61.41.21.00.4 0.6 0.8
V =1.5V
C =33 F
I =125mA
V =Standby
O
O
O
OUT1
m
EnableVoltage(EN2) V-V Output
OUT2 -Voltage
T Time s- - m
IN
EN
OUT
GND
ESR
VIN
COUT
ToLoad
RL
+
TPS70845, TPS70848TPS70851, TPS70858TPS70802
SLVS301D JUNE 2000 REVISED DECEMBER 2007
OUTPUT VOLTAGE AND ENABLE VOLTAGE OUTPUT VOLTAGE AND ENABLE VOLTAGEvs vsTIME (START-UP) TIME (START-UP)
Figure 27. Figure 28.
Figure 29. Test Circuit for Typical Regions of Stability
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0 50 100 150 200 250
0.1
10
1
VO=3.3V
C =6.8 F
T =+25 C
O
J
m
°
ESR EquivalentSeriesResistance- - W
REGIONOFINSTABILITY
REGIONOFINSTABILITY
IO- -OutputCurrent mA
250mW
0.1
0.010 50 100 150 200 250
10
1
REGIONOF INSTABILITY
VO=3.3V
C =10 F
T =+25 C
O
J
m
°
50mW
ESR EquivalentSeriesResistance
- - W
IO- -OutputCurrent mA
REGIONOFINSTABILITY
0 25 50 75 100 125
REGIONOF INSTABILITY
0.1
1
10
VO=1.8V
C =6,8 F
T =+25 C
O
J
m
°
ESR EquivalentSeriesResistance
- - W
REGIONOFINSTABILITY
IO- -OutputCurrent mA
250mW
0.1
0.010 25 50 75 100 125
10
1
REGIONOF INSTABILITY
VO=1.8V
C =10 F
T =+25 C
O
J
m
°
ESR EquivalentSeriesResistance- - W
REGIONOFINSTABILITY
IO- -OutputCurrent mA
50mW
TPS70845, TPS70848TPS70851, TPS70858
TPS70802
SLVS301D JUNE 2000 REVISED DECEMBER 2007
TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITYEQUIVALENT SERIES RESISTANCE
(1)
EQUIVALENT SERIES RESISTANCE
(1)
vs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 30. Figure 31.
TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITYEQUIVALENT SERIES RESISTANCE
(1)
EQUIVALENT SERIES RESISTANCE
(1)
vs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 32. Figure 33.
(1)
Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, anyseries resistance added externally, and PWB trace resistance to C
O
.
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APPLICATION INFORMATION
Sequencing Timing Diagrams
VOUT2
VIN1
VIN2
VOUT1
VSENSE1
PG1
PG2
VSENSE2
VOUT2
VIN VOUT1
PG2
>2V
<0.7V
>2V
<0.7V
TPS708xxPWP
(FixedOutputOption)
0.1 Fm
0.1 Fm
10 Fm
10 Fm
250kW
250kW
EN1 EN1
EN2 EN2
RESET
RESET
MR MR
95%
95%
120ms
t1
MR
(PG2tiedto )MR
VOUT2
VOUT1
RESET
PG1
PG2
EN1
EN2
NOTES:A.t :TimeatwhichV isgreaterthanV and islogichigh.
B.Thetimingdiagramisnotdrawntoscale.
1 IN UVLO MR
TPS70845, TPS70848TPS70851, TPS70858TPS70802
SLVS301D JUNE 2000 REVISED DECEMBER 2007
This section provides a number of timing diagramsshowing how this device functions in differentconfigurations.
Application condition: V
IN1
and V
IN2
are tied to thesame fixed input voltage greater than V
UVLO
. PG2 istied to MR.
EN1 and EN2 are initially high; therefore, bothregulators are off, and PG1 and PG2 (tied to MR) areat logic low. Since MR is at logic low, RESET is alsoat logic low. When EN1 is taken to logic low, V
OUT1turns on. Later, when EN2 is taken to logic low, V
OUT2turns on. When V
OUT1
reaches 95% of its regulatedoutput voltage, PG1 goes to logic high. When V
OUT2reaches 95% of its regulated output voltage, PG2(tied to MR) goes to logic high. When V
IN1
is greaterthan V
UVLO
and MR (tied to PG2) is at logic high,RESET is pulled to logic high after a 120-ms delay.When EN1 and E N2 return to logic high, both devicespower down and both PG1, PG2 (tied to MR2), andRESET return to logic low.
Figure 34. Timing When V
OUT1
Is Enabled Before V
OUT2
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VOUT2
VIN1
VIN2
VOUT1
VSENSE1
PG1
PG2
VSENSE2
VOUT2
VIN VOUT1
PG2
2V
0.7V
>2V
<0.7V
>2V
<0.7V
0.1 Fm
0.1 Fm
10 Fm
10 Fm
250kW
250kW
250kW
TPS708xxPWP
(FixedOutputOption)
EN1 EN1
EN2 EN2
MR MR
RESET RESET
95%
95%
MR
VOUT2
VOUT1
RESET
PG1
PG2
EN1
EN2
120ms
t1
NOTES:A.t :TimeatwhichV isgreaterthanV and islogichigh.
B.Thetimingdiagramisnotdrawntoscale.
1 IN UVLO MR
TPS70845, TPS70848TPS70851, TPS70858
TPS70802
SLVS301D JUNE 2000 REVISED DECEMBER 2007
Application condition: V
IN1
and V
IN2
are tied to thesame fixed input voltage greater than V
UVLO
. MR isinitially logic high but is eventually toggled.
EN1 and EN2 are initially high; therefore, bothregulators are off, and PG1 and PG2 are at logic low.Since V
IN1
is greater than V
UVLO
and MR is at logichigh, RESET is also at logic high. When EN2 is takento logic low, V
OUT2
turns on. Later, when EN1 is takento logic low, V
OUT1
turns on. When V
OUT2
reaches95% of its regulated output voltage, PG2 goes tologic high. When V
OUT1
reaches 95% of its regulatedoutput voltage, PG1 goes to logic high. When MR istaken to logic low, RESET is taken low. When MRreturns to logic high, RESET returns to logic highafter a 120-ms delay.
Figure 35. Timing When MR is Toggled
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VOUT2
VIN1
VIN2
VOUT1
VSENSE1
PG1
PG2
VSENSE2
VOUT2
VIN VOUT1
PG2
>2V
<0.7V
>2V
<0.7V
TPS708xxPWP
(FixedOutputOption)
0.1 Fm
0.1 Fm
10 Fm
250kW
250kW
10 Fm
EN1 EN1
EN2 EN2
RESET RESET
MR
95%
95%
FAULTONVOUT1
NOTES:A.t :TimeatwhichV isgreaterthanV and islogichigh.
B.Thetimingdiagramisnotdrawntoscale.
1 IN UVLO MR
120ms
t1
MR
(PG1tiedto )MR
VOUT2
VOUT1
RESET
PG1
PG2
EN1
EN2
TPS70845, TPS70848TPS70851, TPS70858TPS70802
SLVS301D JUNE 2000 REVISED DECEMBER 2007
Application condition: V
IN1
and V
IN2
are tied tosame fixed input voltage greater than V
UVLO
. PG1 istied to MR.
EN1 and EN2 are initially high; therefore, bothregulators are off, and PG1 (tied to MR) and PG2 areat logic low. Since MR is at logic low, RESET is alsoat logic low. When EN2 is taken to logic low, V
OUT2turns on. Later, when EN1 is taken to logic low, V
OUT1turns on. When V
OUT2
reaches 95% of its regulatedoutput voltage, PG2 goes to logic high. When V
OUT1reaches 95% of its regulated output voltage, PG1goes to logic high. When V
IN1
is greater than V
UVLOand MR (tied to PG2) is at logic high, RESET ispulled to logic high after a 120-ms delay. When afault on V
OUT1
causes it to fall below 95% of itsregulated output voltage, PG1 (tied to MR) goes tologic low. Since MR is logic low, RESET goes to logiclow. V
OUT2
is unaffected.
Figure 36. Timing When There is a Fault on V
OUT1
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APPLICATION INFORMATION
Input Capacitor
Output Capacitor
TPS70845, TPS70848TPS70851, TPS70858
TPS70802
SLVS301D JUNE 2000 REVISED DECEMBER 2007
For a typical application, an input bypass capacitor (0.1 µF to 1 µF) is recommended. This capacitor will filter anyhigh frequency noise generated in the line. For fast transient conditions where droop at the input of the LDO mayoccur because of high inrush current, it is recommended to place a larger capacitor at the input as well. The sizeof this capacitor depends on the output current and response time of the main power supply, as well as thedistance to the V
I
pins of the LDO.
As with most LDO regulators, the TPS708xx requires an output capacitor connected between OUT and GND tostabilize the internal control loop. The minimum recommended capacitance values are 10- µF ceramic capacitorswith an ESR (equivalent series resistance) between 50-m and 2.5- or 6.8- µF tantalum capacitors with ESRbetween 250 m and 4 . Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic capacitorswith capacitance values greater than 10 µF are all suitable, provided they meet the requirements describedabove. Larger capacitors provide a wider range of stability and better load transient response. Table 1 gives apartial listing of surface-mount capacitors suitable for use with the TPS708xx for fast transient responseapplication.
This information, along with the ESR graphs, is included to assist in selection of suitable capacitance for userapplications. When necessary to achieve low height requirements along with high output current and/or high loadcapacitance, several higher ESR capacitors can be used in parallel to meet the guidelines above.
Table 1. Partial Listing of TPS708xx-Compatible Surface-Mount Capacitors
VALUE MANUFACTURER MAX ESR MFR PART NO.
22 µF Kemet 345 m 7495C226K0010AS33 µF Sanyo 100 m 10TPA33M47 µF Sanyo 100 m 6TPA47M68 µF Sanyo 45 m 10TPC68M
Copyright © 2000 2007, Texas Instruments Incorporated Submit Documentation Feedback 25
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ESR and Transient Response
RSER LESL C
-
-
+
LDO
VI
VESR
IOUT
RESR
COUT
RLOAD VOUT
+
TPS70845, TPS70848TPS70851, TPS70858TPS70802
SLVS301D JUNE 2000 REVISED DECEMBER 2007
LDOs typically require an external output capacitor for stability. In fast transient response applications, capacitorsare used to support the load current while the LDO amplifier is responding. In most applications, one capacitor isused to support both functions.
Besides its capacitance, every capacitor also contains parasitic impedances. These parasitic impedances areresistive as well as inductive. The resistive impedance is called equivalent series resistance (ESR), and theinductive impedance is called equivalent series inductance (ESL). The equivalent schematic diagram of anycapacitor can therefore be drawn as shown in Figure 37 .
Figure 37. ESR and ESL
In most cases one can neglect the effect of inductive impedance ESL. Therefore, the following applicationfocuses mainly on the parasitic resistance ESR.
Figure 38 shows the output capacitor and its parasitic resistances in a typical LDO output stage.
Figure 38. LDO Output Stage with Parasitic Resistances ESR
In steady state (dc state condition), the load current is supplied by the LDO (solid arrow) and the voltage acrossthe capacitor is the same as the output voltage (V
(CO)
= V
OUT
). This condition means no current is flowing into theC
O
branch. If I
OUT
suddenly increases (a transient condition), the following results occur:The LDO is not able to supply the sudden current need because of its response time. Therefore, capacitor C
Oprovides the current for the new load condition (dashed arrow). C
O
now acts like a battery with an internalresistance, ESR. Depending on the current demand at the output, a voltage drop occurs at R
ESR
. This voltageis shown as V
ESR
in Figure 38 .When C
O
is conducting current to the load, initial voltage at the load will be V
O
= V
(CO)
V
ESR
. As a result ofthe discharge of C
O
, the output voltage V
O
drops continuously until the response time t
1
of the LDO isreached and the LDO resumes supplying the load. From this point, the output voltage starts rising again untilit reaches the regulated voltage. This period is shown as t
2
in Figure 39 .
26 Submit Documentation Feedback Copyright © 2000 2007, Texas Instruments Incorporated
www.ti.com
ESR1
ESR2
ESR3
3
1
2
IOUT
VOUT
t1t2
TPS70845, TPS70848TPS70851, TPS70858
TPS70802
SLVS301D JUNE 2000 REVISED DECEMBER 2007
Figure 39. Correlation of Different ESRs and Their Influence on the Regulation of V
O
at a Load Step fromLow-to-High Output Current
Figure 39 also shows the impact of different ESRs on the output voltage. The left brackets show different levelsof ESRs where number 1 displays the lowest and number 3 displays the highest ESR.
From above, the following conclusions can be drawn:The higher the ESR, the larger the droop at the beginning of load transient.The smaller the output capacitor, the faster the discharge time and the greater the voltage droop during theLDO response period.
Copyright © 2000 2007, Texas Instruments Incorporated Submit Documentation Feedback 27
www.ti.com
Programming the TPS70802 Adjustable LDO Regulator
R1= V
V
OUT
REF
-1´R2
(
(
(1)
OUTPUTVOLTAGE
PROGRAMMINGGUIDE
VO
VI
OUT
FB
R1
R2
GND
EN
IN
<0.7V
>2.0 V
TPS70802
0.1 mF
+
OUTPUT
VOLTAGE R1 R2
2.5V
3.3V
3.6V
UNIT
31.6
51.1
59.0
30.1
30.1
30.1
kW
kW
kW
Regulator Protection
TPS70845, TPS70848TPS70851, TPS70858TPS70802
SLVS301D JUNE 2000 REVISED DECEMBER 2007
The output voltage of the TPS70802 adjustable regulators is programmed using external resistor dividers asshown in Figure 40 .
Resistors R1 and R2 should be chosen for approximately a 50- µA divider current. Lower value resistors can beused, but offer no inherent advantage and waste more power. Higher values should be avoided as leakagecurrents at the sense terminal increase the output voltage error. The recommended design procedure is tochoose R2 = 30.1 k to set the divider current at approximately 50 µA, and then calculate R1 using Equation 1 :
where:
V
REF
= 1.224 V typ (the internal reference voltage)
Figure 40. TPS70802 Adjustable LDO Regulator Programming
Both TPS708xx PMOS-pass transistors have built-in back diodes that conduct reverse currents when the inputvoltage drops below the output voltage (for example, during power-down). Current is conducted from the outputto the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may beappropriate.
The TPS708xx also features internal current limiting and thermal protection. During normal operation, theTPS708xx regulator 1 limits output current to approximately 1.6 A (typ) and regulator 2 limits output current toapproximately 750 mA (typ). When current limiting engages, the output voltage scales back linearly until theovercurrent condition ends. While current limiting is designed to prevent gross device failure, care should betaken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds+150 °C (typ), thermal-protection circuitry shuts it down. Once the device has cooled below +130 °C (typ),regulator operation resumes.
28 Submit Documentation Feedback Copyright © 2000 2007, Texas Instruments Incorporated
www.ti.com
Power Dissipation and Junction Temperature
PD(max) +TJmax*TA
RqJA
(2)
PD+ǒVI*VOǓ IO
(3)
TPS70845, TPS70848TPS70851, TPS70858
TPS70802
SLVS301D JUNE 2000 REVISED DECEMBER 2007
Specified regulator operation is assured to a junction temperature of +125 °C; the maximum junction temperatureshould be restricted to +125 °C under normal operating conditions. This restriction limits the power dissipation theregulator can handle in any given application. To ensure the junction temperature is within acceptable limits,calculate the maximum allowable dissipation, P
D(max)
, and the actual dissipation, P
D
, which must be less than orequal to P
D(max)
.
The maximum-power-dissipation limit is determined using the following equation:
where:
T
Jmax
is the maximum allowable junction temperatureR
θJA
is the thermal resistance junction-to-ambient for the package, that is, 32.6 °C/W for the 20-terminal PWP with noairflow.
T
A
is the ambient temperature
The regulator dissipation is calculated using:
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation triggers the thermalprotection circuit.
Copyright © 2000 2007, Texas Instruments Incorporated Submit Documentation Feedback 29
PACKAGE OPTION ADDENDUM
www.ti.com 30-Jul-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS70802PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS70802PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS70845PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS70845PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS70848PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS70848PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS70851PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS70851PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS70851PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS70851PWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS70858PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS70858PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
PACKAGE OPTION ADDENDUM
www.ti.com 30-Jul-2011
Addendum-Page 2
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS70851PWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS70851PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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