2017 Microchip Technology Inc. DS20005827A-page 1
HV257
Features
• Thirty-two Independent High-voltage Amplifiers
• 300V Operating Voltage
• 295V Output Voltage
• 2.2V/µs Typical Output Slew Rate
• Adjustable Output Current Source Limit
• Adjustable Output Current Sink Limit
• Internal Closed-loop Gain of 72V/V
• 12 MΩ Feedback Impedance
• Layout Ideal for Die Applications
Applications
• Microelectromechanical Systems (MEMS) Driver
• Piezoelectric Transducer Driver
• Optical Crosspoint Switches
(Using MEMS Technology)
General Description
The HV257 is a 32-channel, high-voltage
sample-and-hold amplifier array integrated circuit. It
operates on a single high-voltage supply, up to 300V,
and two low-voltage supplies, VDD and VNN.
All 32 sample-and-hold circuits share a common
analog input, VSIG
. The individual sample-and-hold
circuits are selected by a five-to-32 logic decoder. The
sampled voltage on the holding capacitor is buffered by
a low-voltage amplifier and is magnified by a
high-voltage amplifier with a closed-loop gain of 72V/V.
The internal closed-loop gain is set for an input voltage
range of 0V to 4.096V. The input voltage can be up to
5V, but the output will saturate. The maximum output
voltage swing is 5V below the VPP high-voltage supply.
The outputs can drive capacitive loads of up to
3000 pF.
The maximum output source and sink current can be
adjusted by using two external resistors. An external
RSOURCE resistor controls the maximum sourcing
current, and an external RSINK resistor controls the
maximum sinking current. The current limit is
approximately 12.5V divided by the external resistor
value. The setting is common for all 32 outputs. A
low-voltage silicon junction diode is made available to
help monitor the die temperature.
Package Type
100-lead MQFP
(Top view)
1
100
See Table 3-1 for pin information.
32-Channel High-Voltage Sample-and-Hold Amplifier Array
R
HVOUT0
AVNN
AVDD
S/H-0
5 to 32
Decoder
VSIG
A0
A1
A2
A3
EN
A4
R
S/H-1
HVOUT1
R
S/H-31
HVOUT31
VPP
AVDD
AVNN
AVNN
CH
-
+
-
+
Q0
Q1
Q31
HVOUT
Current
Sink
Limiting
To all HVOUT
amplifiers
RSOURCE
RSINK
DVDD
AVNN
DGND
AGND
VPP
AVDD
To internal VPP bus
To internal analog VDD bus
To internal analog VNN bus
To internal digital VDD bus
To internal digital VNN bus
DVDD
DVNN
AVDD
AVNN
CH
CH
BYP-VPP BYP-AVDD BYP-AVNN Anode Cathode
Bias Circuit
-
+
-
+
-
+
-
+
HVOUT
Current
Source
Limiting
To all HVOUT
amplifiers 71R
VPP
AVNN
71R
VPP
AVNN
71R
HV257
DS20005827A-page 2 2017 Microchip Technology Inc.
Functional Block Diagram
2017 Microchip Technology Inc. DS20005827A-page 3
HV257
Typical Application Circuit
VSIG
A0
EN
A3
A2
A4
HVOUT0
HV257 High Voltage
Power Supply
Low Voltage
Power Supply
32
DGND AGND
HVOUT1
MEMS
Array
y
y
x
x
HVOUT2
HVOUT3
HVOUT30
HVOUT31
A1
VNN
Low Voltage
Channel
Select
Sample
and Hold
High
Voltage
OpAmp
Array
RSOURCE
RSINK
Micro
Processor
DAC
HV257
DS20005827A-page 4 2017 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
High-voltage Supply, VPP ....................................................................................................................................... 310V
Analog Low-voltage Positive Supply, AVDD ................................................................................................................ 8V
Digital Low-voltage Positive Supply, DVDD ................................................................................................................. 8V
Analog Low-voltage Negative Supply, AVNN ............................................................................................................ –7V
Digital Low-voltage Negative Supply, DVNN ............................................................................................................ –7V
Logic Input Voltage.................................................................................................................................. –0.5V to DVDD
Analog Input Signal, VSIG ................................................................................................................................. 0V to 6V
Maximum Junction Temperature, TJ..................................................................................................................... 150°C
Storage Temperature, TS .................................................................................................................... –65°C to +150°C
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions above those
indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter Sym. Min. Typ. Max. Unit Conditions
High-voltage Positive Supply VPP 125 —300 V
Low-voltage Positive Supply VDD 6 — 7.5 V
Low-voltage Negative Supply VNN –4.5 —–6.5 V
VPP Supply Current IPP — — 0.8 mA VPP = 300V, All HVOUT = 0V, No load
VDD Supply Current IDD — — 5 mA VDD = 6V to 7.5V
VNN Supply Current INN –6 — — mA VNN = –4.5V to –6.5V
Operating Temperature Range TJ–10 —85 °C
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Over operating conditions unless otherwise noted
Parameter Sym. Min. Typ. Max. Unit Conditions
HVOUT Voltage Swing HVOUT 0 — VPP–5 V
Input Voltage Offset VINOS — — ±40 mV Input referred
Feedback Resistance from HVOUT
to Ground RFB 9.6 12 — MΩ
HVOUT Capacitive Load CLOAD 0 — 3000 pF
HVOUT Sourcing Current Limiting Range ISOURCE 50 —500 µA ISOURCE = 12.5V/RSOURCE
HVOUT Sinking Current Limiting Range ISINK 50 —500 µA ISINK = 12.5V/RSINK
External Resistance Range
for Setting Maximum Current Source RSOURCE 25 —250 kΩ
External Resistance Range for Setting
Maximum Current Sink RSINK 25 —250 kΩ
2017 Microchip Technology Inc. DS20005827A-page 5
HV257
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Over operating conditions unless otherwise noted
Parameter Sym. Min. Typ. Max. Unit Conditions
HVOUT Slew Rate Rise SR —2.2 —V/µs No load
HVOUT Slew Rate Fall — 2 — V/µs No load
HVOUT –3 dB Channel Bandwidth BW — 4 — kHz VPP = 300V
Open-loop Gain AO70 100 —dB
Closed-loop Gain AV68.4 72 75.6 V/V
DC Channel-to-channel Crosstalk CTDC –80 — — dB
Power Supply Rejection Ratio for VPP
,
VDD and VNN
PSRR –40 — — dB
SAMPLE AND HOLD
Acquisition Time tAQ — 4 — µs
Pedestal Voltage VPED — 1 — mV Input referred
Sample-and-Hold Switch Resistance RSW — 5 — kΩ
Sample-and-Hold Capacitor CH—10 12 pF
Voltage Droop Rate During Hold Time
Relative to Input VDROOP — 6 — V/s Output referred
Input Signal Voltage Range VSIG 0 — 5 V
VSIG Input Capacitance CSIG —33 —pF
LOGIC DECODER
Set-up Time-address to Enable tSU 75 — — ns
Hold Time-address to Enable Bar tH75 — — ns
Input Logic High Voltage VIH 2.4 — VDD V
Input Logic Low Voltage VIL 0 — 1.2 V
Input Logic High Current IIH — — 1 µA VIH = VDD
Input Logic Low Current IIL –1 — — µA VIL = 0V
Logic Input Capacitance CIN — — 15 pF
HV257
DS20005827A-page 6 2017 Microchip Technology Inc.
Timing Waveforms of
t
SU
t
H
Hold Step
(V
PEDESTAL
)
Hold Hold
Sample
A0-A4
EN
HVOpamp
t
R/F
Acquisition Window
Sample-and-Hold
DECODER FUNCTION TABLE
A4A3A2A1A0EN Selected S/H
L L L L L H 0
L L L L H H 1
L L L H L H 2
L L L H H H 3
↕↕↕↕↕↕↕
H H H H L H 30
H H H H H H 31
X X X X X L All Open
TEMPERATURE DIODE
Peak Inverse Voltage PIV — — 5 V Cathode to anode
Forward Diode Drop VF—0.6 — V IF = 100 µA, anode to cath-
ode at TA = 25°C
Forward Diode Current IF— — 100 µA Anode to cathode
VF Temperature Coefficient TC—–2.2 —mV/°C Anode to cathode
TEMPERATURE SPECIFICATIONS
Parameter Sym. Min. Typ. Max. Unit Conditions
TEMPERATURE RANGE
Maximum Junction Temperature TJ— — +150 °C
Storage Temperature TS–65 —+150 °C
PACKAGE THERMAL RESISTANCE
100-lead MQFP JA —39 —°C/W
AC ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Over operating conditions unless otherwise noted
Parameter Sym. Min. Typ. Max. Unit Conditions
2017 Microchip Technology Inc. DS20005827A-page 7
HV257
2.0 TYPICAL PERFORMANCE CURVES
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC)
RSINK (kΩ)
ISINK (µA)
600
500
400
300
200
100
0
25 150 250
min
max
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g. outside specified power supply range) and therefore outside the warranted range.
FIGURE 2-1: ISINK vs. RSINK.
min
max
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC)
RSOURCE (kΩ)
ISOURCE (µA)
600
500
400
300
200
100
025 150 250
FIGURE 2-2: ISOURCE vs. RSOURCE.
120
100
80
60
40
20
00 2.0 4.0
(”one RC” response to one volt input step) (V
PP
= 300V, V
DD
= 6.5V, V
NN
= 5.5V, T
A
= 25
O
C)
VSIG (V)
HVOUT (mV)
+85
O
C
+25
O
C
-10
O
C
FIGURE 2-3: Acquisition Window.
FIGURE 2-4: Temperature Diode vs.
Temperature.
700
600
500
400
300 1.0 20 40 60 80 100
Diode Biasing Current (μA)
Vf (mV)
(V
PP
= 300V, V
DD
= 6.5V, V
NN
= 5.5V)
-10
O
C
85
O
C
25
O
C
min
max
min
max
min
max
FIGURE 2-5: HVOUT Charge Injection vs.
VSIG
.
HVOUT (V/sec)
(VPP = 300V, VDD = 6.5V, VNN = 5.5V)
HVOUT Level (V)
3.0
2.0
1.0
0
-1.0
-2.0 0 150 280
-10OC
85OC
25OC
FIGURE 2-6: HVOUT Droop.
HV257
DS20005827A-page 8 2017 Microchip Technology Inc.
FIGURE 2-7:
Frequency (Hz)
-50
-40
-30
-20
-10
010 100 1k 10k 100k 1M
V
PP
PSRR (dB)
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC)
VPP PSRR vs. Frequency.
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC)
Frequency
V
DD
PSRR (dB)
-50
-40
-30
-20
-10
010 100 1k 10k 100k 1M
FIGURE 2-8: VDD PSRR vs. Frequency.
Frequency
VNN PSRR (dB)
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC)
-50
-40
-30
-20
-10
010 100 1k 10k 100k 1M
FIGURE 2-9: VNN PSRR vs. Frequency.
FIGURE 2-10:
3.5
3.0
2.5
2.0
1.5
-2.0
-2.5
-3.0
-3.5
-4.0
-4.5
1.0 2.0 3.0
VIN (Volts)
Input Offset (mV)
Offset at -10OC
Offset at 25OC
Offset at 85OC
(VPP = 300V, VDD = 6.5V, VNN = 5.5V )
Input Offset vs. VIN and
Temperature.
1.0 2.0 3.0
V
IN
(Volts)
Gain
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = -10O, +25O, +85OC )
73.97
73.96
73.95
73.94
73.93
72.74
72.73
72.72
72.71
72.70
72.69
FIGURE 2-11: Gain vs. VIN.
HV257DFG-5037047 Q3 Dev # 3, Channel 16
(VPP = 300V, VDD = 6.5V, VNN = -5.0V, VSIG = 1.0V, TA = 25OC)
73.030
73.028
73.026
73.024
73.022
73.020
73.018
73.016
73.014
Time (hours)
0 8
HVOUT (V)
FIGURE 2-12: HVOUT Drift.
2017 Microchip Technology Inc. DS20005827A-page 9
HV257
3.0 PIN DESCRIPTION
The details on the pins of HV257 are listed on
Table 3-1. Refer to Package Type for the location of
pins.
TABLE 3-1: PIN FUNCTION TABLE
Pin Number Pin Name Description
1HVOUT31 Amplifier output
2HVOUT30 Amplifier output
3HVOUT29 Amplifier output
4HVOUT28 Amplifier output
5HVOUT27 Amplifier output
6HVOUT26 Amplifier output
7HVOUT25 Amplifier output
8HVOUT24 Amplifier output
9HVOUT23 Amplifier output
10 HVOUT22 Amplifier output
11 HVOUT21 Amplifier output
12 HVOUT20 Amplifier output
13 HVOUT19 Amplifier output
14 HVOUT18 Amplifier output
15 HVOUT17 Amplifier output
16 HVOUT16 Amplifier output
17 HVOUT15 Amplifier output
18 HVOUT14 Amplifier output
19 HVOUT13 Amplifier output
20 HVOUT12 Amplifier output
21 HVOUT11 Amplifier output
22 HVOUT10 Amplifier output
23 HVOUT9 Amplifier output
24 HVOUT8 Amplifier output
25 HVOUT7 Amplifier output
26 HVOUT6 Amplifier output
27 HVOUT5 Amplifier output
28 HVOUT4 Amplifier output
29 HVOUT3 Amplifier output
30 HVOUT2 Amplifier output
31 HVOUT1 Amplifier output
32 HVOUT0 Amplifier output
33 VPP High-voltage positive supply. There are two pads.
34 NC No connection
35 NC No connection
HV257
DS20005827A-page 10 2017 Microchip Technology Inc.
36 NC No connection
37 NC No connection
38 NC No connection
39 AGND Analog ground. There are three pads. They need to be externally connected.
40 AVNN Analog low-voltage negative supply. This should be at the same potential as
DVNN. There are two pads.
41 NC No connection
42 AVDD Analog low-voltage positive supply. This should be at the same potential as
DVDD. There are two pads.
43 AGND Analog ground. There are three pads. They need to be externally connected.
44 DVNN Digital low-voltage negative supply. This should be at the same potential as
AVNN. There are two pads.
45 DVDD Digital low-voltage positive supply. This should be at the same potential as AVDD.
There are two pads.
46 NC No connection
47 NC No connection
48 NC No connection
49 NC No connection
50 NC No connection
51 NC No connection
52 NC No connection
53 NC No connection
54 NC No connection
55 NC No connection
56 NC No connection
57 NC No connection
58 NC No connection
59 NC No connection
60 NC No connection
61 NC No connection
62 NC No connection
63 NC No connection
64 NC No connection
65 NC No connection
66 NC No connection
67 NC No connection
68 NC No connection
69 NC No connection
70 NC No connection
71 NC No connection
TABLE 3-1: PIN FUNCTION TABLE (CONTINUED)
Pin Number Pin Name Description
2017 Microchip Technology Inc. DS20005827A-page 11
HV257
72 NC No connection
73 NC No connection
74 NC No connection
75 NC No connection
76 NC No connection
77 NC No connection
78 NC No connection
79 NC No connection
80 EN Active logic high input. Logic low will keep sample-and-hold switches open.
81 A0 Decoder logic input. Addressed channel will close the sample-and-hold switch.
Sample-and-hold switches for unaddressed channels are kept open.
82 A1 Decoder logic input. Addressed channel will close the sample-and-hold switch.
Sample-and-hold switches for unaddressed channels are kept open.
83 A2 Decoder logic input. Addressed channel will close the sample-and-hold switch.
Sample-and-hold switches for unaddressed channels are kept open.
84 A3 Decoder logic input. Addressed channel will close the sample-and-hold switch.
Sample-and-hold switches for unaddressed channels are kept open.
85 A4 Decoder logic input. Addressed channel will close the sample-and-hold switch.
Sample-and-hold switches for unaddressed channels are kept open.
86 DGND Digital ground
87 DVDD Digital low-voltage positive supply. This should be at the same potential as AVDD.
There are two pads.
88 DVNN Digital low-voltage negative supply. This should be at the same potential as
AVNN. There are two pads.
89 AGND Analog ground. There are three pads. They need to be externally connected.
90 VSIG Common input signal for all 32 sample-and-hold circuits.
91 AVDD Analog low-voltage positive supply. This should be at the same potential as
DVDD. There are two pads.
92 BYP-AVNN Internally generated reference voltage. An external low-voltage (1 nF–10 nF)
capacitor needs to be connected across AVNN and BYP-AVNN.
93 BYP-AVDD Internally generated reference voltage. An external low-voltage (1 nF–10 nF)
capacitor needs to be connected across AVDD and BYP-AVDD.
94 AVNN Analog low-voltage negative supply. This should be at the same potential as
DVNN. There are two pads.
95 Anode The anode side of a low-voltage silicon diode that can be used to monitor die
temperature.
96 Cathode The cathode side of a low-voltage silicon diode that can be used to monitor die
temperature.
97 RSINK The external resistor from RSINK to VNN that sets the output current sinking limit.
The current limit is approximately 12.5V divided by the RSINK resistor value.
98 RSOURCE
The external resistor from RSOURCE to VNN that sets the output current
sourcing limit. The current limit is approximately 12.5V divided by RSOURCE
resistor value.
TABLE 3-1: PIN FUNCTION TABLE (CONTINUED)
Pin Number Pin Name Description
HV257
DS20005827A-page 12 2017 Microchip Technology Inc.
99 BYP-VPP The internally generated reference voltage. An external low-voltage (1 nF–10 nF)
capacitor needs to be connected across VPP and BYP-VPP.
100 VPP High-voltage positive supply. There are two pads.
TABLE 3-1: PIN FUNCTION TABLE (CONTINUED)
Pin Number Pin Name Description
2017 Microchip Technology Inc. DS20005827A-page 13
HV257
3.1 Pad Configuration
HVOUT0
HVOUT1
HVOUT2
HVOUT3
HVOUT4
HVOUT5
HVOUT6
HVOUT7
HVOUT8
HVOUT9
HVOUT10
HVOUT11
HVOUT12
HVOUT13
HVOUT14
HVOUT15
HVOUT16
HVOUT17
HVOUT18
HVOUT19
HVOUT20
HVOUT21
HVOUT22
HVOUT23
HVOUT24
HVOUT25
HVOUT26
HVOUT27
HVOUT28
HVOUT29
HVOUT30
HVOUT31
VPP
Cathode
Anode
VPP
BYP-VPP
RSOURCE
RSINK
A4
A3
A2
A1
A0
EN
DVDD
DVNN
AGND
AGND
AVDD
AVNN
DVDD
DVNN
AGND
AVDD
AVNN
DGND
VSIG
Byp-AVNN
Byp-AVDD
Do Not Bond.
Leave Floating.
Do Not Bond.
For testing only.
FIGURE 3-1: Pad Configuration Drawing.
HV257
DS20005827A-page 14 2017 Microchip Technology Inc.
TABLE 3-2: PAD COORDINATES
Chip Size: 17160 µm X 5830 µm
Center of Die: 0,0
Pad Name X (µm) Y (µm)
VPP –8338.5 2708.5
HVOUT0 –7895 2305.5
HVOUT1 –7448.5 2305.5
HVOUT2 –7001.5 2305.5
HVOUT3 –6554.5 2305.5
HVOUT4 –6107.5 2305.5
HVOUT5 –5660.5 2305.5
HVOUT6 –5213.5 2305.5
HVOUT7 –4776.5 2305.5
HVOUT8 –4319.5 2305.5
HVOUT9 –3872.5 2305.5
HVOUT10 –3425.5 2305.5
HVOUT11 –2978.5 2305.5
HVOUT12 –2513.5 2305.5
HVOUT13 –2084.5 2305.5
HVOUT14 –1637.5 2305.5
HVOUT15 –1190.5 2305.5
HVOUT16 –743.5 2305.5
HVOUT17 –296.5 2305.5
HVOUT18 150 2305.5
HVOUT19 597.5 2305.5
HVOUT20 1044.5 2305.5
HVOUT21 1491.5 2305.5
HVOUT22 1938.5 2305.5
HVOUT23 2385.5 2305.5
HVOUT24 2832.5 2305.5
HVOUT25 3279.5 2305.5
HVOUT26 3726.5 2305.5
HVOUT27 4173.5 2305.5
HVOUT28 4620.5 2305.5
HVOUT29 5067.5 2305.5
HVOUT30 5514.5 2305.5
HVOUT31 5961.5 2305.5
VPP 6659 2709
BYP-VPP 7045 2709
RSOURCE 7489 2709
RSINK 7969 2709
CATHODE 8366 2709
ANODE 8366 2199
AVNN 8047 425
BYP-AVDD 8047 125.5
BYP-AVNN 8047 –135.5
AVDD 8047 –704.5
VSIG 8047 –1072.5
AGND 8047 –1424.5
DVNN 8066.5 –1590
DVDD 8066.5 –1958.5
DGND 7867 –2192
A4 7723 –2684
A3 7319 –2684
A2 6913 –2684
A1 6508.5 –2684
A0 6103.5 –2684
EN 5698 –2684
NC 5043.5 –2686
NC 4638.5 –2686
NC 4233.5 –2686
NC 3828.5 –2686
NC 3423.5 –2686
NC 3018.5 –2686
NC 2613.5 –2686
NC 2208.5 –2686
NC 1803.5 –2686
NC 1398.5 –2686
NC 993.5 –2686
NC 588.5 –2686
NC 183.5 –2686
NC –221.5 –2686
NC –626.5 –2686
NC –1031.5 –2686
NC –1436.5 –2686
NC –2412 –2686
NC –2817 –2686
NC –3222 –2686
NC –3627 –2686
NC –4032 –2686
NC –4437 –2686
NC –4842 –2686
NC –5247 –2686
NC –5652 –2686
NC –6052 –2686
NC –6462 –2686
TABLE 3-2: PAD COORDINATES
(CONTINUED)
Chip Size: 17160 µm X 5830 µm
Center of Die: 0,0
Pad Name X (µm) Y (µm)
2017 Microchip Technology Inc. DS20005827A-page 15
HV257
NC –6867 –2686
NC –7272 –2686
NC –7677 –2686
NC –8082 –2686
DVDD –8373 –2250.5
DVNN –8373 –1949
AGND –8367 –1561
AVDD –8387 –1143
AVNN –8338.5 577.5
AGND –8341 916.5
TABLE 3-2: PAD COORDINATES
(CONTINUED)
Chip Size: 17160 µm X 5830 µm
Center of Die: 0,0
Pad Name X (µm) Y (µm)
HV257
DS20005827A-page 16 2017 Microchip Technology Inc.
4.0 FUNCTIONAL DESCRIPTION
4.1 Power-up/Power-down Sequence
4.1.1 EXTERNAL DIODE PROTECTION
The device can be damaged due to improper
power-up/power-down sequence. To avoid this, please
follow the acceptable power-up/power-down
sequences in Tab l e 4-1 and Table 4-2 and add two
external diodes as shown in Figure 4-1. The first diode
is a high-voltage diode across VPP and VDD where the
anode of the diode is connected to VDD and the
cathode of the diode is connected to VPP
. Any
low-current high-voltage diode such as a 1N4004 will
be adequate. The second diode is a Schottky diode
across VNN and DGND where the anode of the Schottky
diode is connected to VNN and the cathode is
connected to DGND. Any low-current Schottky diode
such as a 1N5817 will be sufficient.
VDD VPP
1N4004 or similar
VNN DGND
1N5817 or similar
FIGURE 4-1: Diode Configuration.
4.1.2 RECOMMENDED
POWER-UP/POWER-DOWN
SEQUENCE
The HV257 needs all power supplies to be fully up and
all channels refreshed with VSIG = 0V to force all
high-voltage outputs to 0V. Before that time, the
high-voltage outputs may have temporary voltage
excursions above or below GND level, depending on
selected power-up sequence. To minimize the
excursions, the VDD and VNN power supplies should be
applied at the same time (or within a few
nanoseconds). In addition, all channels should be
continuously refreshed with VSIG = 0V, just before, and
while the VPP is ramping up. The suggested VPP ramp
up speed should be 10 milliseconds or longer and the
ramp-down should be 1 millisecond or longer.
TABLE 4-1: ACCEPTABLE POWER-UP SEQUENCES
Option 1 Option 2 Option 3
Step Description Step Description Step Description
1 VPP 1 VNN 1 VDD and VNN
2 VNN 2 VDD 2Inputs
3VDD 3VPP 3VPP
4Inputs and Anode 4Inputs and Anode 4Anode
TABLE 4-2: ACCEPTABLE POWER-DOWN SEQUENCES
Option 1 Option 2 Option 3
Step Description Step Description Step Description
1Inputs and Anode 1Inputs and Anode 1Anode
2 VDD 2 VPP 2 VPP
3VNN 3VDD 3Inputs
4 VPP 4 VNN 4 VNN and VDD
0V
VNN
6.5V
- 5.5V
0V
300V
0V
HVOUT
0V
VSIG
012 310 01
0V
EN
0V
6.5V
- 5.5V
0V
VDD
VPP
300V
0V
0V
A0 - A4
GND ± V offset x 72
0V
2017 Microchip Technology Inc. DS20005827A-page 17
HV257
FIGURE 4-2: Recommended Power-up/Power-down Timing.
VNN Before VDD
0V
-5.5V
6.5V
0V
0V
VPP
VDD
VNN
HVOUT
0V
VDD Before VNN
0V
-5.5V
0V
-5.5V
6.5V
0V
6.5V
0V
VPP
VDD
VNN
HVOUT
FIGURE 4-3: HVOUT Level at Power-up.
HV257
DS20005827A-page 18 2017 Microchip Technology Inc.
4.2 RSINK/RSOURCE
The VDD_BYP, VDD_BYP and VNN_BYP pins are
internal high-impedance-current mirror gate nodes
brought out to maintain stable opamp biasing currents
in noisy power supply environments. When 0.1 µF/25V
bypass capacitors are added between VPP_BYP and
VPP
, between VDD_BYP and VDD and between
VNN_BYP and VNN, they will force the high-impedance
gate nodes to follow the fluctuation of power lines. The
expected voltages at the VDD_BYP and VNN_BYP pins
are typically 1.5V from their respectful power supply.
The expected voltage at VPP_BYP is typically 3V below
VPP
.
BYP_VPP
HVOpamp
VDD
VPP
BYP_VNN
VNN
Set by RSOURCE
Set by RSINK
HVOUT0
BYP_VNN Cap
0.1µF/25V
Current limit
Current limit
To internal biasing HVOpamp
HVOUT31
BYP_VDD Cap
0.1µF/25V
BYP_VPP Cap
0.1µF/25V
BYP_VDD
FIGURE 4-4: Internal Reference Current Diagram.
2017 Microchip Technology Inc. DS20005827A-page 19
HV257
4.3 Ground Isolation
(AGND/DGND Isolation)
It is important that the AGND pin is connected to a
clean ground. The hold capacitors are internally
connected to the AGND, and any ground noise will
directly couple to the high-voltage outputs (with a gain
of 72). The analog and digital ground traces on the PCB
should be physically separated to reduce digital
switching noise, degrading the signal to noise
performance.
DGND
LVOpamp
AVDD VPP
AVNN
AGND1 (pins 89, 43)
VSIG
HVOpamp
HVOUT
1R
71R
AGND2 (pin 39)
EN, A
0
- A
4
DVDD DVNN
External bypass caps
C1 = 0.1µF / 500V
C2, C3, C4, C5 = 0.1µF / 25V:
C_hold
10pF C_comp C_comp
C2
C1
C4
C3
C5 C6
Single star GND
Sample
switch
DAC
FIGURE 4-5: AGND/DGND Ground Isolation.
HV257
DS20005827A-page 20 2017 Microchip Technology Inc.
5.0 PACKAGE MARKING INFORMATION
5.1 Packaging Information
Legend: XX...X Product Code or Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for product code or customer-specific information. Package may or
not include the corporate logo.
3
e
3
e
XXXXXXX
YYWWNNN
e3
HV257FG
1712463
e3
100-lead MQFP Example
100-Lead MQFP Package Outline (FG)
20.00x14.00mm body, 3.15mm height (max), 0.65mm pitch, 3.20mm footprint
Symbol A A1 A2 b D D1 E E1 e L L1 L2 șș
Dimension
(mm)
MIN 2.50* 0.00 2.50 0.22 22.95* 19.80* 16.95* 13.80* 0.65
BSC
0.73 1.60
REF
0.25
BSC
0O5O
NOM - - 2.70 - 23.20 20.00 17.20 14.00 0.88 - -
MAX 3.15 0.25 2.90 0.40 23.45* 20.20* 17.45* 14.20* 1.03 7O16O
JEDEC Registration MS-022, Variation GC-2, Issue B, Dec. 1996.
7KLVGLPHQVLRQLVQRWVSHFL¿HGLQWKH-('(&GUDZLQJ
Drawings are not to scale.
SD#DSPD 100MQFPFG V i F041309
1
100
Top View
Seating
Plane
Gauge
Plane
θ
L
L1
L2
View B
View B
θ1
b
e
Side View
A2
A
A1
E
E1
DD1
Seating
Plane
Note 1
(Index Area
E1/4 x D1/4)
Note:
1. $3LQLGHQWL¿HUPXVWEHORFDWHGLQWKHLQGH[DUHDLQGLFDWHG7KH3LQLGHQWL¿HUFDQEHDPROGHGPDUNLGHQWL¿HUDQHPEHGGHGPHWDOPDUNHURU
a printed indicator.
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
2017 Microchip Technology Inc. DS20005827A-page 21
HV257
HV257
DS20005827A-page 22 2017 Microchip Technology Inc.
NOTES:
2017 Microchip Technology Inc. DS20005827A-page 23
HV257
APPENDIX A: REVISION HISTORY
Revision A (September 2017)
• Converted Supertex Doc# DSFP-HV257
to Microchip DS20005827A
• Changed the part marking format
• Made minor text changes throughout the docu-
ment
HV257
DS20005827A-page 24 2017 Microchip Technology Inc.
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
Example:
a) HV257FG-G: 32-Channel High-Voltage
Sample-and-Hold Amplifier Array,
100-lead MQFP, 66/Tray
PART NO.
Device
Device: HV257 = 32-Channel High-Voltage Sample-and-Hold
Amplifier Array
Package: FG = 100-lead MQFP
Environmental: G = Lead (Pb)-free/RoHS-compliant Package
Media Type: (blank) = 66/Tray for a K6 Package
XX
Package
-
X - X
Environmental
Media Type
Options
2017 Microchip Technology Inc. DS20005827A-page 25
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory,
CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ,
KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST
Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo,
CodeGuard, CryptoAuthentication, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip Technology
Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2017, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-2184-9
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITYMANAGEMENTS
YSTEM
CERTIFIEDBYDNV
== ISO/TS16949==
DS20005827A-page 26 2017 Microchip Technology Inc.
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11/07/16