Exar Corporation 48720 Kato Road, Fremont CA, 94538 • ( 510) 668-7000 • FAX (510) 668-7017 • www.exar .co m
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
JANUARY 2007 REV. V1.2.0
GENERAL DESCRIPTION
The XRT86VL38 is an eight-channel 1.544 Mbit/s or
2.048 Mbit/s DS1/E1/J1 framer and LIU integrated
solution featuring R3 technology (Relayless,
Reconfigurable, Redun dancy). The physical interface
is optimized with internal impedance, and with the
patented pad structure, the XRT86VL38 provides
protection from power failures and hot swapping.
The XRT86VL38 contains an integrated DS1/E1/J1
framer and LI U which provide DS1/E1/J1 framing and
error accumulation in accordance with ANSI/ITU_T
specifications. Each framer has its own framing
synchronizer and transmit-receive slip buffers. The
slip buffers can be independently enabled or disabled
as required and can be configured to frame to the
common DS1/ E1/J1 signal formats.
Each Framer block contains its own Transmit and
Receive T1/E1/J1 Framing function. There are 3
Transmit HDLC controllers per channel which
encapsulate contents of the Transmit HDLC buffers
into LAPD Message frames. There are 3 Receive
HDLC controllers per channel which extract the
payload content of Receive LAPD Message frames
from the incoming T1/E1/J1 data stream and write the
contents into the Receive HDL C buffers. Each framer
also contains a Transmit and Overhead Data Input
port, which permits Data Link Terminal Equipment
direct access to the outbound T1/E1/J1 frames.
Likewise, a Receive Overhead output data port
permits Data Link Terminal Equipment direct access
to the Data Lin k bits of the inboun d T1/E1/J1 frames .
The X RT86VL38 f ull y me ets all of the l ate st T 1/E1/J1
specifications: ANSI T1/E1.107-1988, ANSI T1/
E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/
E1.408-1990, AT&T TR 62411 (12-90) TR54016, and
ITU G-703, G.704, G706 and G.733, AT&T Pub.
43801, and ETS 300 011, 300 233, JT G.703, JT
G.704, JT G706 , I.431. E xtensive tes t and d iagnostic
functions include Loop-backs, Boundary scan,
Pseudo Random bit sequence (PRBS) test pattern
generation, Performance Monitor, Bit Error Rate
(BER) meter, forced error insertion, and LAPD
unchannelized data payload processing according to
ITU-T standard Q.921.
Applicatio ns and Features (next page)
FIGURE 1. XRT86VL38 8-CHANNEL DS1 (T1/E 1/J1) FRAMER/LIU COMBO
Performance
Monitor
PRBS
Generator &
Analyser
HDLC/LAPD
Controllers
LI U &
Loopback
Control
DMA
Interface
Signaling &
Alarms JTAG
WR
ALE_AS
RD
RDY_DTACK
μP
Select
A[14:0]D[7:0]
Microprocessor
Interface
4
3
Tx Se rial
Clock
Rx Serial
Clock
8kHz sync
OSC
Back Plane
1.544-16.384 Mbit/s
Local PCM
Highway
ST-BUS
2-Frame
Slip Buffer
Elastic Stor e
Tx Se rial
Data In Tx LIU
Interface
2-Frame
Slip Buffer
Elastic Store
Rx LIU
Interface
Rx Framer
Rx Serial
Data Out
RTIP
RRING
TTIP
TRING
External Data
Link Controller
Tx Overhead In Rx Overhead Out
XRT86VL38
1 of 8-channels
Tx Framer
LLB LB
System (T erminal) Side
Line Side
1:1 Turns Ratio
1:2 Turns Ratio
Memory Intel/Motorola µP
Configuration, Control &
Stat us Monitor
RxLOS
TxON
INT
XRT86VL38
2
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1.2.0
APPLICATIONS
•High-Density T1/E1/J1 interfaces for Mu ltiplexers, Switches, LAN Routers and Digital Modems
•SON ET/SDH termina l or Add/Drop multiplexers (ADMs)
•T1/E1/J1 add/drop multiplexers (MUX)
•Channel Service Unit s (CSUs): T1/E1/J 1 and Fractional T1/E 1/J1
•Digital Access Cross-conn ec t System (DACs)
•Digital Cross-co nnect Systems (DCS)
•Frame Relay Switches and Acce ss Devices (FRADS)
•ISDN Primary Rate Interfaces (PRA)
•PBXs and PCM chann el bank
•T3 channelized access concentrators and M13 MUX
•Wireless base station s
•ATM equip ment with integrated DS1 interfaces
•Multichannel DS1 Test Equipment
•T1/E1/J1 Perform ance Moni toring
•Voice over packet gateways
•Routers
FEATURES
•Eight independent , full duplex DS1 Tx and Rx Framer/LI Us
•Two 512-bit (two-fra me) elastic store, PCM frame slip buffers (F IFO) on TX and Rx prov ide up to 8.192 MHz
asynchronous back plane connections with jitter and wander attenuation
•Supports input PCM and signaling data at 1.544, 2.048, 4.096 and 8.192 Mbits. Also supports 4-channel
multiplexed 12.352/16. 384 (HMVIP/H.100) Mbit/s on the back plane bus
•Programm able output clocks for Fractional T1/E1/J1
•Supp orts Channel Associated Signal ing (CAS)
•Supp orts Comm on Channel S igna lling (CCS)
•Supp orts ISDN Primary Rate Interface (ISDN PRI) signaling
•Extracts and inserts robbed bit signaling (RBS)
•3 Integrated HDLC controllers per channel for transmit and receive, each controller having two 96-byte
buffers (buffer 0 / buff er 1)
•HDLC Controllers Support SS7
•Timeslot assignabl e HDLC
•V5.1 or V5.2 In te r face
•Autom atic Performance Report Ge neration (PM ON Status) ca n be inserted into the transm it LAP D interface
every 1 secon d or fo r a single transmission
•Alarm Indication Signal with Cus tomer Installation signature (AIS-CI)
•Remote Alarm Indication with Customer Installation (RAI-CI)
•Gapped Clock interface m ode for Transmit and Receive.
XRT86VL38
3
REV. V1.2.0 OCTAL T1/E1/J1 FRAM ER/LIU COMBO - H ARDWARE DESCRIPTION
•Intel/Motorola and Power PC interfaces for confi guration, control and status monitoring
•Parallel search algorithm for fast fra me synchronizat ion
•W ide choice of T1 framing structures: SF/D4 , ESF, SLC®96, T1DM and N-Frame (non-signaling)
•Direct access to D and E channels for fast transm ission of data link information
•PRBS , QRSS , and Network Loop Code generation and det ection
•Program m able Interrupt output pin
•Supp orts programmed I/O and DMA modes of Read-Write access
•Each framer block encodes and decodes the T1/ E1/J1 Fr ame serial data
•Detects and forces Red (SAI), Yellow (RAI) and Blue (AIS) Alarms
•Detects OOF, LOF, LOS errors and COFA conditions
•Loopbacks: Local (LLB) and Line remote (LB)
•F ac ilitates Inv e rs e Mult iple x ing for AT M
•Performanc e monitor with one second polling
•Boun dary scan (IEEE 1149.1) JTAG test port
•Accepts external 8kHz Sync reference
•1.8V Inne r Core Voltage
•3.3V I/O operation with 5V tolerant inputs
•420-pin P BGA package or 484-p in STBGA pa ckage with -40°C to +85°C operation
ORDERING INFORMATION
PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE
XRT86VL38IB 42 0 Plast ic Ball Grid Array -40°C to +85°C
XRT86VL38IB484 484 Shrink Thin Ball Grid Array -40°C to +85°C
XRT86VL38
4
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1.2.0
420 BALL - PLASTIC BALL GRID ARRAY (BOTTOM VIEW, SEE PIN LIST FOR DESCRIPTION)
2625242322212019181716151413121110987654321
OOOOOOOOOOOOOOOOOOOOOOOOOOA
OOOOOOOOOOOOOOOOOOOOOOOOOOB
OOOOOOOOOOOOOOOOOOOOOOOOOOC
OOOOOOOOOOOOOOOOOOOOOOOOOOD
OOOOOOOOOOOOOOOOOOOOOOOOOOE
OOOOO OOOOOF
OOOOO OOOOOG
OOOOO OOOOOH
OOOOO OOOOOJ
OOOOO OOOOOK
OOOOO OOOOOL
OOOOO OOOOOM
OOOOO OOOOON
OOOOO OOOOOP
OOOOO OOOOOR
OOOOO OOOOOT
OOOOO OOOOOU
OOOOO OOOOOV
OOOOO OOOOOW
OOOOO OOOOOY
OOOOO OOOOOAA
OOOOOOOOOOOOOOOOOOOOOOOOOOAB
OOOOOOOOOOOOOOOOOOOOOOOOOOAC
OOOOOOOOOOOOOOOOOOOOOOOOOOAD
OOOOOOOOOOOOOOOOOOOOOOOOOOAE
OOOOOOOOOOOOOOOOOOOOOOOOOOAF
XRT86VL38
5
REV. V1.2.0 OCTAL T1/E1/J1 FRAM ER/LIU COMBO - H ARDWARE DESCRIPTION
484 BALL - SHRINK THIN BALL GRID ARRAY (BOTTOM VIEW - SEE PIN LIST FOR DESCRIPTION)
22212019181716151413121110987654321
OOOOOOOOOOOOOOOOOOOOOOA
OOOOOOOOOOOOOOOOOOOOOOB
OOOOOOOOOOOOOOOOOOOOOOC
OOOOOOOOOOOOOOOOOOOOOOD
OOOOOOOOOOOOOOOOOOOOOOE
OOOOOOOOOOOOOOOOOOOOOOF
OOOOOOOOOOOOOOOOOOOOOOG
OOOOOOOOOOOOOOOOOOOOOOH
OOOOOOOOOOOOOOOOOOOOOO J
OOOOOOOOOOOOOOOOOOOOOOK
OOOOOOOOOOOOOOOOOOOOOOL
OOOOOOOOOOOOOOOOOOOOOOM
OOOOOOOOOOOOOOOOOOOOOON
OOOOOOOOOOOOOOOOOOOOOOP
OOOOOOOOOOOOOOOOOOOOOOR
OOOOOOOOOOOOOOOOOOOOOOT
OOOOOOOOOOOOOOOOOOOOOOU
OOOOOOOOOOOOOOOOOOOOOOV
OOOOOOOOOOOOOOOOOOOOOOW
OOOOOOOOOOOOOOOOOOOOOOY
OOOOOOOOOOOOOOOOOOOOOOAA
OOOOOOOOOOOOOOOOOOOOOOAB
XRT86VL38
I
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1.2.0
LIST OF PARAGRAPHS
1. 0 PIN LI ST S ......... ..... .............. ..... ....... ..... .............. ..... ....... .... ............... .... ....... ..... ....... ................................6
2. 0 PIN DESCRIP TIONS .... ..... .............. ..... .............. ..... ....... .... ..... ....... ..... ..... ....... ..... .............. ....................14
XRT86VL38
II
REV. V1.2.0 OCTAL T1/E1/J1 FRAM ER/LIU COMBO - H ARDWARE DESCRIPTION
LIST OF FIGURES
Figure 1.: XRT86VL38 8-channel DS1 (T1/E1/J1) Framer/LIU Combo ............................................................................. 1
Fig u re 2. : I T U G. 703 P ul se Te mp lat e ... ... ..... .. ..... .. ..... ... ..... .. .. ..... ... ..... .. ..... .. ..... ... ..... .. .. ..... ... ..... .. ...................................58
Figure 3.: DSX-1 Pulse Template (normalized amplitude) ..............................................................................................59
XRT86VL38
III
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1.2.0
LIST OF TABLES
Tab l e 1 :: 4 2 0 Ba ll Li st by Ball Num b e r .. ..... .. ..... ... ..... .. ..... .. ... ..... .. ..... .. ..... ... .... ... ..... .. ... ..... .. ..... .. ........................................6
Tab l e 2 :: 4 8 4 Ba ll Li st by Ball Num b e r .. ..... .. ..... ... ..... .. ..... .. ... ..... .. ..... .. ..... ... .... ... ..... .. ... ..... .. ..... .. ......................................10
Tab l e 3 :: P in Des c riptio n Str u c tu re ..... .. ..... .. ... ..... .. ..... .. ..... ... ..... .. ..... .. ... ..... .. ..... .. ..... ... ..... .. .. ...........................................14
Tab l e 4 :: E1 Re c e iv er El ec tr ic a l C ha r a ct er is tics .. ..... .. ..... .. ..... ... .... ... .. ..... ... .... ... ..... .. ..... ... .... ... .. ..... .................................55
Table 5:: T1 Receiver Electrical Characteristics ..............................................................................................................56
Tab l e 6 :: E1 Tra n s m it te r E le c tr ical Ch a ra c te r is tic s ... .. .. ..... ... ..... .. ..... .. ..... ... .. ..... .. ..... ... ..... .. ..... .. ... ...................................56
Table 7:: E1 Transmi t Ret urn Loss Requirement ............ .. .. ..... ....... ............... .. .................... .. ..........................................57
Tab l e 8 :: T 1 Tran s m it te r E le c tric al Cha ra c te rist ic s ... .... ... .. ..... ... .... ... ..... .. ..... .. ..... ... .. ..... ... .... ... ..... .. .................................57
Tab l e 9 :: T ra n s mit Puls e Mas k S p e ci fic a tion .. ..... .. ..... .. ..... ... ..... .. .. ..... ... ..... .. ..... .. ..... ... ..... .. .. ..... ... ...................................58
Table 10:: DSX1 Interface Isolated pulse mask and corner points ..................................................................................59
Tab l e 1 1: : A C Ele c tr ic a l Cha r ac t er isti cs ... .. ..... .. ..... ... .... ... .. ..... ... .... ... ..... .. ..... .. ..... ... ..... .. ... .... ... ........................................60
XRT86VL38
6
REV. V1.2.0 OCTAL T1/E1/J1 FRAM ER/LIU COMBO - H ARDWARE DESCRIPTION
1.0 PIN LIST S
TABLE 1: 420 BALL LIST
BY BALL NUMBER
PIN PIN NAME
A1 DVDD18
A2 DGND
A3 AGND
A4 MCLKIN
A5 TMS
A6 RXSERCLK0
A7 TCK
A8 RXCHCLK0
A9 TXSYNC0
A10 RXCHN0_4
A11 TXSERCLK0
A12 TXCHCLK0
A13 TXCHN0_2
A14 RXCHCLK1
A15 RXCHN1_2
A16 RXLOS1
A17 TXMSYNC1
A18 TXOH1
A19 TXOHCLK1
A20 TXCHN1_3
A21 TXCHN1_4
A22 RXCHN2_0
A23 RXCASYNC2
A24 RXCHCLK2
A25 VDD
A26 RXCHN2_4
B1 VDDPLL18
B2 GNDPLL
B3 NC
B4 AVDD18
B5 E1MCLKOUT
B6 TDO
B7 TRST
B8 RXCRCSYNC0
B9 RXOHCLK0
B10 TXMSYNC0
B11 TEST
B12 TXCHN0_1
B13 RXSERCLK1
B14 RXSER1
B15 RXOH1
B16 RXCHN1_3
B17 VSS
B18 NC
B19 TXCHN1_2
B20 RXLOS2
B21 GPIO1_3
B22 RXCHN2_1
B23 NC
B24 TXSYNC2
B25 VSS
B26 TXCHCLK2
C1 VDDPLL18
C2 VDDPLL18
C3 GNDPLL
C4 NC
C5 ANALOG
C6 VSS
C7 RXSER0
C8 VDD
C9 RXCHN0_2
C10 RXCHN0_3
C11 RXOH0
TABLE 1: 420 BALL LIST
BY BALL NUMBER
PIN PIN NAME
C12 TXOH0
C13 VSS
C14 TXCHN0_4
C15 VDD
C16 TXSYNC1
C17 RXCHN1_4
C18 TXCHN1_0
C19 TXSERCLK1
C20 RXSERCLK2
C21 RXSER2
C22 RXCHN2_2
C23 RXCHN2_3
C24 TXMSYNC2
C25 VSS
C26 TXCHN2_2
D1 RTIP0
D2 RVDD0
D3 VDDPLL18
D4 JTAG_RING
D5 RxTSEL
D6 T1MCLKOUT
D7 TDI
D8 RXCHN0_0
D9 RXSYNC0
D10 VSS
D11 TXSER0
D12 TXCHN0_0
D13 RXCRCSYNC1
D14 RXCHN1_0
D15 RXSYNC1
D16 RXOHCLK1
D17 TXSER1
TABLE 1: 420 BALL LIST
BY BALL NUMBER
PIN PIN NAME
D18 TXCHN1_1
D19 RXSYNC2
D20 VSS
D21 RXOH2
D22 TXSERCLK2
D23 NC
D24 VDD18
D25 TXCHN2_1
D26 RXSER3
E1 RRING0
E2 RGND0
E3 GNDPLL
E4 GNDPLL
E5 NC
E6 SENSE
E7 aTEST
E8 RXLOS0
E9 RXCHN0_1
E10 RXCASYNC0
E11 TXOHCLK0
E12 VDD18
E13 TXCHN0_3
E14 RXCHN1_1
E15 RXCASYNC1
E16 NC
E17 TXCHCLK1
E18 VDD18
E19 NC
E20 RXCRCSYNC2
E21 RXOHCLK2
E22 NC
E23 TXSER2
TABLE 1: 420 BALL LIST
BY BALL NUMBER
PIN PIN NAME
XRT86VL38
7
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1.2.0
E24 TXOHCLK2
E25 TXCHN2_4
E26 TXOH2
F1 RTIP1
F2 RVDD1
F3 TTIP0
F4 TVDD0
F5 JTAG_TIP
F22 TXCHN2_0
F23 TXCHN2_3
F24 VDD
F25 RXCHCLK3
F26 RXOH3
G1 RRING1
G2 RGND1
G3 TTIP1
G4 TRING0
G5 NC
G22 GPIO1_2
G23 RXSYNC3
G24 RXOHCLK3
G25 RXCRCSYNC3
G26 RXCHN3_0
H1 RTIP2
H2 RVDD2
H3 TVDD1
H4 TRING1
H5 TGND0
H22 VSS
H23 RXCASYNC3
H24 RXLOS3
H25 RXSERCLK3
TABLE 1: 420 BALL LIST
BY BALL NUMBER
PIN PIN NAME
H26 RXCHN3_1
J1 RRING2
J2 RGND2
J3 TTIP2
J4 TVDD2
J5 TGND1
J22 TXCHCLK3
J23 RXCHN3_2
J24 VDD18
J25 TXOH3
J26 RXCHN3_3
K1 RTIP3
K2 RVDD3
K3 TTIP3
K4 TRING2
K5 TGND2
K22 TXSYNC3
K23 TXOHCLK3
K24 TXSERCLK3
K25 RXCHN3_4
K26 TXSER3
L1 RRING3
L2 RGND3
L3 TVDD3
L4 TRING3
L5 TGND3
L22 TXCHN3_0
L23 VSS
L24 TXMSYNC3
L25 TXCHN3_1
L26 CS
M1 RTIP4
TABLE 1: 420 BALL LIST
BY BALL NUMBER
PIN PIN NAME
M2 RVDD4
M3 TTIP4
M4 TRING4
M5 TGND4
M22 TXCHN3_2
M23 WR
M24 TXCHN3_3
M25 DATA7
M26 TXCHN3_4
N1 RRING4
N2 RGND4
N3 TVDD4
N4 NC
N5 TGND5
N22 ADDR14
N23 ADDR13
N24 DATA6
N25 DATA5
N26 VDD
P1 RTIP5
P2 RVDD5
P3 TTIP5
P4 TRING5
P5 NC
P22 ADDR11
P23 BLAST
P24 DATA4
P25 ADDR12
P26 VSS
R1 RRING5
R2 RGND5
R3 TVDD5
TABLE 1: 420 BALL LIST
BY BALL NUMBER
PIN PIN NAME
R4 TRING6
R5 TGND6
R22 ALE
R23 ADDR9
R24 ADDR10
R25 PTYPE2
R26 INT
T1 RTIP6
T2 RVDD6
T3 TTIP6
T4 TVDD6
T5 TGND7
T22 ADDR7
T23 VDD18
T24 ADDR8
T25 DATA2
T26 DATA3
U1 RRING6
U2 RGND6
U3 TTIP7
U4 TRING7
U5 NC
U22 ADDR2
U23 ADDR3
U24 ADDR4
U25 ADDR5
U26 ADDR6
V1 RTIP7
V2 RVDD7
V3 TVDD7
V4 NC
V5 NC
TABLE 1: 420 BALL LIST
BY BALL NUMBER
PIN PIN NAME
XRT86VL38
8
REV. V1.2.0 OCTAL T1/E1/J1 FRAM ER/LIU COMBO - H ARDWARE DESCRIPTION
V22 VSS
V23 DBEN
V24 RDY
V25 ADDR0
V26 ADDR1
W1 RRING7
W2 RGND7
W3 NC
W4 NC
W5 NC
W22 iADDR
W23 PTYPE0
W24 DATA1
W25 RD
W26 PTYPE1
Y1 VSS
Y2 VDD
Y3 TXON
Y4 RESET
Y5 E1OSCCLK
Y22 RXOHCLK4
Y23 ACK0
Y24 ACK1
Y25 PCLK
Y26 DATA0
AA1 VSS
AA2 8KEXTOSC
AA3 NC
AA4 NC
AA5 NC
AA22 RXOH4
AA23 VSS
TABLE 1: 420 BALL LIST
BY BALL NUMBER
PIN PIN NAME
AA24 REQ1
AA25 VDD
AA26 fADDR
AB1 LOP
AB2 TXCHCLK7
AB3 8KSYNC
AB4 TXCHN7_4
AB5 TXSERCLK7
AB6 RXSERCLK7
AB7 RXSER7
AB8 RXCHN7_0
AB9 TXSER6
AB10 TXCHN6_0
AB11 RXSYNC6
AB12 RXSERCLK6
AB13 RXCHN6_1
AB14 TXCHN5_3
AB15 TXSER5
AB16 TXOHCLK5
AB17 RXCHN5_2
AB18 GPIO0_2
AB19 VSS
AB20 VDD18
AB21 TXSER4
AB22 RXCHN4_4
AB23 VSS
AB24 RXCHCLK4
AB25 RXCRCSYNC4
AB26 REQ0
AC1 T1OSCCLK
AC2 TXOH7
AC3 TXCHN7_3
TABLE 1: 420 BALL LIST
BY BALL NUMBER
PIN PIN NAME
AC4 VDD
AC5 TXCHN7_0
AC6 RXSYNC7
AC7 RXCHN7_1
AC8 TXMSYNC6
AC9 RXCASYNC6
AC10 TXOHCLK6
AC11 VDD
AC12 RXLOS6
AC13 RXCHN6_0
AC14 TXCHN5_4
AC15 TXCHN5_0
AC16 VSS
AC17 RXCHN5_3
AC18 RXSER5
AC19 RXSERCLK5
AC20 TXCHN4_2
AC21 TXMSYNC4
AC22 VSS
AC23 RXCHN4_3
AC24 VDD18
AC25 RXSER4
AC26 RXLOS4
AD1 VDD18
AD2 TXCHN7_2
AD3 TXCHN7_1
AD4 RXLOS7
AD5 RXCRCSYNC7
AD6 VSS
AD7 VDD18
AD8 TXSYNC6
AD9 VSS
TABLE 1: 420 BALL LIST
BY BALL NUMBER
PIN PIN NAME
AD10 TXCHCLK6
AD11 GPIO0_0
AD12 RXCHN6_3
AD13 GPIO0_1
AD14 TXOH5
AD15 TXCHN5_1
AD16 TXMSYNC5
AD17 RXCHN5_4
AD18 RXCHN5_0
AD19 TXCHN4_4
AD20 GPIO0_3
AD21 TXCHN4_0
AD22 TXCHCLK4
AD23 VDD
AD24 RXCASYNC4
AD25 RXCHN4_0
AD26 RXSERCLK4
AE1 TXOHCLK7
AE2 VSS
AE3 TXSER7
AE4 TXSYNC7
AE5 RXCHN7_3
AE6 TXSERCLK6
AE7 RXOHCLK7
AE8 TXCHN6_4
AE9 TXCHN6_2
AE10 RXCRCSYNC6
AE11 RXCHCLK6
AE12 RXSER6
AE13 RXOHCLK6
AE14 RXOH6
AE15 TXCHN5_2
TABLE 1: 420 BALL LIST
BY BALL NUMBER
PIN PIN NAME
XRT86VL38
9
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1.2.0
AE16 TXCHCLK5
AE17 RXOH5
AE18 VDD
AE19 RXCASYNC5
AE20 TXCHN4_3
AE21 RXCHCLK5
AE22 GPIO1_0
AE23 TXSERCLK4
AE24 GPIO1_1
AE25 RXCHN4_1
AE26 RXSYNC4
AF1 NC
AF2 TXMSYNC7
AF3 RXCHN7_4
AF4 RXCHN7_2
AF5 RXCHCLK7
AF6 RXCASYNC7
AF7 RXOH7
AF8 TXCHN6_3
AF9 TXCHN6_1
AF10 TXOH6
AF11 RXCHN6_4
AF12 RXCHN6_2
AF13 VSS
AF14 VDD18
AF15 TXSERCLK5
AF16 TXSYNC5
AF17 RXOHCLK5
AF18 RXCHN5_1
AF19 RXSYNC5
AF20 RXLOS5
AF21 RXCRCSYNC5
TABLE 1: 420 BALL LIST
BY BALL NUMBER
PIN PIN NAME
AF22 TXCHN4_1
AF23 TXOHCLK4
AF24 TXSYNC4
AF25 TXOH4
AF26 RXCHN4_2
TABLE 1: 420 BALL LIST
BY BALL NUMBER
PIN PIN NAME
XRT86VL38
10
REV. V1.2.0 OCTAL T1/E1/J1 FRAM ER/LIU COMBO - H ARDWARE DESCRIPTION
TABLE 2: 484 BALL LIST
BY BALL NUMBER
PIN PIN NAME
A2 AVDD_LV
A4 E1MCLKOUT
A5 MCLKIN
A6 TRST
A7 RXCHN0_0
A8 RXSYNC0
A9 TXMSYNC0
A10 TXOHCLK0
A11 TXCHN0_1
A12 RXSERCLK1
A13 TXCHN0_4
A14 RXOH1
A15 RXCHN1_3
A16 TXCHCLK1
A17 TXOHCLK1
A18 RXSYNC2
A19 GPIO1_3
A20 RXCRCSYNC2
A21 RXOHCLK2
B1 VDDPLL18
B3 AGND
B5 DGND
B6 TMS
B7 RXSER0
B8 RXCRCSYNC0
B9 TXSYNC0
B10 RXCHN0_4
B11 TXCHN0_0
B12 RXCRCSYNC1
B13 RXCHN1_0
B14 RXCASYNC1
B15 TXMSYNC1
B16 TXOH1
B17 TXSERCLK1
B18 RXSERCLK2
B19 RXCHN2_0
B20 RXCHCLK2
B21 RXCHN2_4
B22 TXOHCLK2
C1 VDDPLL18
C2 JTAG_RING
C6 RXTSEL
C7 ATEST
C8 RXLOS0
C9 RXCHN0_1
C10 RXCASYNC0
C11 TXSERCLK0
C12 TXCHCLK0
C13 RXCHN1_1
C14 RXLOS1
C15 TXSER1
C16 TXCHN1_0
C17 TXCHN1_3
C18 RXCASYNC2
C19 RXCHN2_1
C20 TXSYNC2
C21 TXCHN2_0
C22 TXCHN2_4
D1 GNDPLL18
D2 VDDPLL18
D3 GNDPLL18
D4 ANALOG
D8 TDO
TABLE 2: 484 BALL LIST
BY BALL NUMBER
PIN PIN NAME
D9 RXSERCLK0
D10 RXCHN0_2
D11 RXOH0
D12 TXCHN0_2
D13 RXCHN1_2
D14 RXOHCLK1
D15 TXCHN1_1
D16 RXLOS2
D17 RXSER2
D18 RXOH2
D19 RXCHN2_3
D20 TXSER2
D21 TXCHN2_3
D22 RXSYNC3
E1 RVDD0
E2 GNDPLL18
E3 VDDPLL18
E4 GNDPLL18
E5 JTAG_TIP
E6 SENSE
E9 TDI
E10 RXCHCLK0
E11 RXCHN0_3
E12 TEST
E13 TXOH0
E14 RXSER1
E15 RXCHCLK1
E16 RXSYNC1
E17 TXSERCLK2
E18 TXMSYNC2
E19 TXCHCLK2
E20 TXCHN2_1
TABLE 2: 484 BALL LIST
BY BALL NUMBER
PIN PIN NAME
E21 TXOH2
E22 RXOHCLK3
F1 TRING0
F2 TVDD0
F3 TTIP_0
F4 RGND0
F5 DVDD18
F9 T1MCLKOUT
F10 TCK
F11 RXOHCLK0
F12 TXSER0
F13 TXCHN0_3
F14 TXSYNC1
F15 TXCHN1_2
F16 RXCHN1_4
F17 RXCHN2_2
F19 TXCHN2_2
F20 RXSER3
F21 RXCASYNC3
F22 RXLOS3
G1 TVDD1
G2 RTIP0
G3 RRING0
G4 TGND0
G17 TXCHN1_4
G18 GPIO1_2
G19 RXCHCLK3
G20 RXCRCSYNC3
G21 RXCHN3_1
G22 TXCHCLK3
H1 RRING1
H2 RTIP1
TABLE 2: 484 BALL LIST
BY BALL NUMBER
PIN PIN NAME
XRT86VL38
11
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1.2.0
H3 RGND1
H4 TTIP1
H5 RVDD1
H18 RXOH3
H19 RXCHN3_0
H20 RXSERCLK3
H21 RXCHN3_3
H22 TXOHCLK3
J1 TRING2
J2 TVDD2
J3 TTIP2
J4 RGND2
J5 TRING1
J6 TGND1
J18 TXOH3
J19 RXCHN3_2
J20 TXSYNC3
J21 TXSERCLK3
J22 RXCHN3_4
K1 TTIP3
K2 RGND3
K3 RRING2
K4 RTIP2
K5 TGND2
K6 RVDD2
K17 TXCHN3_1
K18 TXSER3
K19 TXCHN3_0
K20 TXMSYNC3
K21 CS
K22 TXCHN3_2
L1 RRING3
TABLE 2: 484 BALL LIST
BY BALL NUMBER
PIN PIN NAME
L2 RTIP3
L3 TVDD3
L4 TRING3
L5 TGND3
L6 RVDD3
L17 TXCHN3_4
L18 ADDR13
L19 TXCHN3_3
L20 WR
L21 DATA7
L22 ADDR14
M1 RRING4
M2 RTIP4
M3 TRING4
M4 RGND4
M5 TTIP4
M6 TVDD4
M7 RVDD4
M17 BLAST
M18 ADDR11
M19 ADDR12
M20 DATA5
M21 DATA6
M22 DATA4
N1 TVDD5
N2 TTIP5
N3 RGND5
N4 RVDD5
N5 TGND4
N17 ADDR1
N18 DATA3
N19 ADDR9
TABLE 2: 484 BALL LIST
BY BALL NUMBER
PIN PIN NAME
N20 ADDR10
N21 PTYPE2
N22 INT
P1 RGND6
P2 RRING5
P3 RTIP5
P4 TGND5
P5 TRING5
P18 ADDR0
P19 ADDR7
P20 ADDR8
P21 DATA2
P22 ALE
R1 TGND6
R2 TRING6
R3 TVDD6
R4 TTIP6
R5 RVDD6
R18 iADDR
R19 RDY
R20 ADDR4
R21 ADDR5
R22 ADDR6
T1 TTIP7
T2 RTIP6
T3 RRING6
T4 RGND7
T5 RVDD7
T18 fADDR
T19 DATA0
T20 PTYPE1
T21 ADDR2
TABLE 2: 484 BALL LIST
BY BALL NUMBER
PIN PIN NAME
T22 ADDR3
U1 TVDD7
U2 TRING7
U3 RRING7
U4 RTIP7
U5 8KEXTOSC
U7 TXCHN7_4
U8 RXLOS7
U9 TXSERCLK6
U10 TXSER6
U11 TXOH6
U12 RXOH6
U13 TXOHCLK5
U14 RXCHN5_0
U15 TXCHN4_1
U16 GPIO0_3
U17 TXMSYNC4
U18 RXCHCLK4
U19 REQ0
U20 DATA1
U21 RD
U22 DBEN
V1 TGND7
V2 LOP
V3 T1OSCCLK
V4 E1OSCCLK
V5 TXCHCLK7
V6 TXOHCLK7
V7 TXSERCLK7
V8 TXCHN7_1
V9 RXCRCSYNC7
V10 RXOH7
TABLE 2: 484 BALL LIST
BY BALL NUMBER
PIN PIN NAME
XRT86VL38
12
REV. V1.2.0 OCTAL T1/E1/J1 FRAM ER/LIU COMBO - H ARDWARE DESCRIPTION
V11 TXCHCLK6
V12 RXCHN6_1
V13 TXSYNC5
V14 RXCHN5_3
V15 GPIO0_2
V16 RXSERCLK5
V17 RXCASYNC4
V18 RXOH4
V19 RXOHCLK4
V20 PTYPE0
V21 ACK1
V22 PCLK
W1 TXON
W2 8KSYNC
W3 TXSER7
W4 TXCHN7_0
W5 TXMSYNC7
W6 RXSERCLK7
W7 RXCHN7_4
W8 RXCHN7_1
W9 TXCHN6_4
W10 RXCASYNC7
W11 TXCHN6_0
W12 RXSERCLK6
W13 TXCHN5_2
W14 RXCHN5_4
W15 RXLOS5
W16 TXCHN4_0
W17 TXOH4
W18 RXCHN4_2
W19 RXSER4
W20 RXSERCLK4
TABLE 2: 484 BALL LIST
BY BALL NUMBER
PIN PIN NAME
W21 RXLOS4
W22 ACK0
Y1 RESET
Y2 TXCHN7_3
Y3 RXSYNC7
Y4 RXCHN7_2
Y5 RXCHCLK7
Y6 RXOHCLK7
Y7 RXCHN7_0
Y8 RXCASYNC6
Y9 RXCRCSYNC6
Y10 RXLOS6
Y11 GPIO0_1
Y12 TXCHN5_3
Y13 TXCHCLK5
Y14 RXOH5
Y15 RXSYNC5
Y16 TXCHN4_2
Y17 TXSYNC4
Y18 TXSERCLK4
Y19 RXCHN4_4
Y20 RXSYNC4
Y21 RXCRCSYNC4
Y22 REQ1
AA1 TXOH7
AA2 TXSYNC7
AA3 RXCHN7_3
AA4 TXSYNC6
AA5 TXCHN6_2
AA6 RXSYNC6
AA7 TXOHCLK6
AA8 RXCHCLK6
TABLE 2: 484 BALL LIST
BY BALL NUMBER
PIN PIN NAME
AA9 RXSER6
AA10 RXCHN6_0
AA11 TXOH5
AA12 TXSERCLK5
AA13 TXSER5
AA14 RXOHCLK5
AA15 RXSER5
AA16 TXCHN4_4
AA17 RXCRCSYNC5
AA18 GPIO1_0
AA19 TXCHCLK4
AA20 GPIO1_1
AA21 RXCHN4_1
AA22 RXCHN4_0
AB1 TXCHN7_2
AB2 RXSER7
AB3 TXMSYNC6
AB4 TXCHN6_3
AB5 TXCHN6_1
AB6 GPIO0_0
AB7 RXCHN6_4
AB8 RXCHN6_3
AB9 RXCHN6_2
AB10 RXOHCLK6
AB11 TXCHN5_4
AB12 TXCHN5_1
AB13 TXCHN5_0
AB14 TXMSYNC5
AB15 RXCHN5_2
AB16 RXCHN5_1
AB17 RXCASYNC5
AB18 TXCHN4_3
TABLE 2: 484 BALL LIST
BY BALL NUMBER
PIN PIN NAME
AB19 RXCHCLK5
AB20 TXOHCLK4
AB21 TXSER4
AB22 RXCHN4_3
POWER PINS
Pin Pin Name
G11 VDD18
G14 VDD18
G16 VDD18
J17 VDD18
P17 VDD18
T8 VDD18
T10 VDD18
T12 VDD18
T14 VDD18
T17 VDD18
G10 VDD
G12 VDD
G15 VDD
H17 VDD
L16 VDD
R17 VDD
T7 VDD
T9 VDD
T11 VDD
T13 VDD
T15 VDD
GROUND PINS
Pin Pin Name
F6 VSS
G6 VSS
G7 VSS
TABLE 2: 484 BALL LIST
BY BALL NUMBER
PIN PIN NAME
XRT86VL38
13
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1.2.0
G8 VSS
G9 VSS
G13 VSS
H6 VSS
H7 VSS
H16 VSS
J7 VSS
J16 VSS
K7 VSS
K16 VSS
L7 VSS
M16 VSS
N6 VSS
N7 VSS
N16 VSS
P6 VSS
P7 VSS
P16 VSS
R6 VSS
R7 VSS
R16 VSS
T6 VSS
T16 VSS
U6 VSS
H8 VSS
H9 VSS
H10 VSS
H11 VSS
H12 VSS
H13 VSS
H14 VSS
H15 VSS
TABLE 2: 484 BALL LIST
BY BALL NUMBER
PIN PIN NAME
J8 VSS
J9 VSS
J10 VSS
J11 VSS
J12 VSS
J13 VSS
J14 VSS
J15 VSS
K8 VSS
K9 VSS
K10 VSS
K11 VSS
K12 VSS
K13 VSS
K14 VSS
K15 VSS
L8 VSS
L9 VSS
L10 VSS
L11 VSS
L12 VSS
L13 VSS
L14 VSS
L15 VSS
M8 VSS
M9 VSS
M10 VSS
M11 VSS
M12 VSS
M13 VSS
M14 VSS
M15 VSS
TABLE 2: 484 BALL LIST
BY BALL NUMBER
PIN PIN NAME
N8 VSS
N9 VSS
N10 VSS
N11 VSS
N12 VSS
N13 VSS
N14 VSS
N15 VSS
P8 VSS
P9 VSS
P10 VSS
P11 VSS
P12 VSS
P13 VSS
P14 VSS
P15 VSS
R8 VSS
R9 VSS
R10 VSS
R11 VSS
R12 VSS
R13 VSS
R14 VSS
R15 VSS
NO CONNECT PINS
A1 NC
A3 NC
A22 NC
B2 NC
C3 NC
C4 NC
C5 NC
TABLE 2: 484 BALL LIST
BY BALL NUMBER
PIN PIN NAME
D5 NC
D6 NC
D7 NC
E7 NC
E8 NC
F7 NC
F8 NC
G5 NC
B4 NC
F18 NC
TABLE 2: 484 BALL LIST
BY BALL NUMBER
PIN PIN NAME
XRT86VL38
14
REV. V1.2.0 OCTAL T1/E1/J1 FRAM ER/LIU COMBO - H ARDWARE DESCRIPTION
2.0 PIN DESCRIPTI ONS
There are six type s of pins defined throughout this pin description and the corresponding symbol is presented
in tabl e bel ow. The per-channel pin is i ndicated by the channel number or the letter ’ n’ whi ch is appended at the
end of the signal name, for example, TxSERn, where "n" indicates channels 0 to 7. All output pins are "tri-
stated" upon hardware RESET.
The structure of the p in description is divided into fourteen groups, as presented in the table below
TABLE 3: PIN DESCRIPTION STRUCTURE
SECTION PAGE NUMBER
Transmi t System Side Inter-
face page 15
Transmit Overhead Inter-
face page 23
Receive Overhead Interface page 25
Receive System Side I nter-
face page 26
Receive Li ne Interface page 34
Transmit Line Interface page 35
Timing Inter face page 36
GP IO In te rfac e page 38
JTAG Interface page 39
Microprocessor Interface page 40
Power Pi ns (3. 3V) page 49
Power Pi ns (1. 8V) page 50
Ground Pins page 51
No Connect Pi ns page 53
SYMBOL PIN TYPE
I Input
OOutput
I/O Bidirectional
GND Ground
PWR Power
NC No Connect
XRT86VL38
15
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1.2.0
TRANSMIT SYSTEM SIDE INTER FACE
SIGNAL NAME 420 PKG
BALL#484 PKG
BALL # TYPE OUTPUT
DRIVE(MA) DESCRIPTION
TxSER0/
TxPOS0
TxSER1/
TxPOS1
TxSER2/
TxPOS2
TxSER3/
TxPOS3
TxSER4/
TxPOS4
TxSER5/
TxPOS5
TxSER6/
TxPOS6
TxSER7/
TxPOS7
D11
D17
E23
K26
AB21
AB15
AB9
AE3
F12
C15
D20
K18
AB21
AA13
U10
W3
I - Transmit Seri al Data I nput (TxSERn)/Transmit Posit ive
Digi tal Input (TxPOSn) :
The exact function of these pins depends on the mode of
operation selected, as described below.
DS1/E1 Mode - TxSERn
These pins function as the transmit serial data input on t he
system side int erface, whi ch are latched on t he rising edge of
the TxSERCLKn pin. Any payload dat a applied to this pin will
be inserted in to an outbound DS1/E1 fr ame and output to the
li ne. In DS1 mod e, the framing ali gnm ent bits, facility data link
bit s, CRC-6 bits, and sig naling information can al so be
inserted fr om thi s input pin if configured appropri ately. In E1
mode, all data intended to be transported via Time Slots 1
through 15 and Time slots 17 through 31 must be applied to
this input pin. Data int ended for Time Sl ots 0 and 16 can also
be applied to this input pin If configured accordingly.
DS1 or E1 High-Speed Multiplexed Mode* - TxSERn
In thi s mode, these pins are used as the hi gh-speed multi -
plexed data input pin on th e system side. Hig h-speed multi -
plexed data of channels 0-3 must be appli ed to TxSER0 and
high-speed m ultiplexed data of channels 4-7 must be applied
to TxSER4 i n a byte or bi t-int erleav ed way. The f ramer l atches
in th e multiplex ed data on TxSER0 and TxSER4 usin g TxM-
SYNC/TxINCLK and demulti plexes thi s data into 4 seri al
streams. The LIU bl ock will then output the data to the line
interface usi ng TxSERCLKn.
DS1 or E1 Framer Bypass Mode - TxPOSn
In this m ode, TxSERn is used for the positive digital input pin
(TxPOSn) to t he LIU.
NOTE:
1. *High-speed multiplexed modes include (For T1/E1)
16.384MHz HMVIP, H.100, Bit-multiplexed modes,
and (For T1 only) 12.352MHz Bit-multiplexed mode.
2. In DS1 high-speed modes, the DS-0 data is mapped
into an E1 frame by ignoring every fourth time slot
(don’t care).
3. These 8 pins are internally pulled “High” for each
channel.
XRT86VL38
16
REV. V1.2.0 OCTAL T1/E1/J1 FRAM ER/LIU COMBO - H ARDWARE DESCRIPTION
TxSERCLK0/
TxLINECLK0
TxSERCLK1/
TxLINECLK1
TxSERCLK2/
TxLINECLK2
TxSERCLK3/
TxLINECLK3
TxSERCLK4/
TxLINECLK4
TxSERCLK5/
TxLINECLK5
TxSERCLK6/
TxLINECLK6
TxSERCLK7/
TxLINECLK7
A11
C19
D22
K24
AE23
AF15
AE6
AB5
C11
B17
E17
J21
Y18
AA12
U9
V7
I/O 12 Transmit Serial Clock ( TxSERCLKn)/Transmit Line Clock
(TxSERCLKn):
The exact function of these pins depends on the mode of
operation selected, as described below.
In Base-Rate Mode (1.544M Hz/2.048MHz) - TxSERCLKn:
This clock signal is used by the transmit serial interface to
latch the cont ents on the TxSERn pins i nto the T1/E1 f ramer
on the r ising edge of the TxS E RCL Kn. These pins c an be con-
figured as inp ut or output as described below.
When TxSERCLKn is confi gured as Input:
These pins will be inputs if the TxSERCLK is chosen as the
timing sour ce for the transmit framer. Users must provide a
1.544 MHz cl ock rat e t o this input pin for T1 mode of oper ation,
and 2. 048MHz clock r ate in E1 mode.
When TxSERCLKn is confi gured as Output:
These pins will be outputs if either the re covered l ine clock or
the MCLK PLL is chosen as the timing source for the T1/E1
transmit fram er. The transmit fra me r will output a 1.5 44M Hz
cloc k rate i n T1 mode of operat ion, and a 2.048M Hz cloc k rate
in E1 mode.
DS1/E1 Hig h-Speed Back plane Modes* - TxSERCLKn as
INPUT ONLY
In thi s mode, TxSERCLK is an opti onal clock si gnal input
which is used as the timing source for the tran sm it li ne inter-
face, and is only requi red if TxSERCLK is chosen as the tim-
ing source for t he tr ansm it framer. If TxSERCLK i s chosen as
the timing source, system equipment should provide
1.544MHz (For T1 mode) or 2. 048M Hz (For E1 mode) to the
TxSERCLKn pins on each channel. TxSERCLK is not
required if either the recover ed clock or M CLK PLL is chosen
as the timing sour ce of the device.
High speed or m ultipl exed data is l atched i nto th e devic e us ing
the TxMSYNC/TxINCLK high-speed cl ock signal.
DS1 or E1 Framer Bypass Mode - TxLINECLKn
In thi s mode, TxSERCLKn is used as the t ransmi t l ine clock
(Tx L IN E C L K ) to th e LIU .
NOTE: *High-speed backplane modes include (For T1/E1)
2.048MVIP, 4.096MHz, 8.192MHz, 16.384MHz
HMVIP, H.100, Bit-multiplexed modes, and (For T1
only) 12.352MHz Bit-multiplexed mode.
NOTE: In DS1 high-speed modes, the DS-0 data is mapped
into an E1 frame by ignoring every fourth time slot
(don’t care).
NOTE: These 8 pins are internally pulled “High” for each
channel.
TRANSMIT SYSTEM SIDE INTER FACE
SIGNAL NAME 420 PKG
BALL#484 PKG
BALL # TYPE OUTPUT
DRIVE(MA) DESCRIPTION
XRT86VL38
17
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1.2.0
TxSYNC0/
TxNEG0
TxSYNC1/
TxNEG1
TxSYNC2/
TxNEG2
TxSYNC3/
TxNEG3
TxSYNC4/
TxNEG4
TxSYNC5/
TxNEG5
TxSYNC6/
TxNEG6
TxSYNC7/
TxNEG7
A9
C16
B24
K22
AF24
AF16
AD8
AE4
B9
F14
C20
J20
Y17
V13
AA4
AA2
I/O 12 Transmit Single Frame Sync Pulse ( TxSYNCn) / Transmit
Negati ve Digital Input (TxNEGn):
The exact function of these pins depends on the mode of
operation selected, as described below.
DS1/E1 Base Rate Mode (1.544MHz/ 2.048M Hz) - TxSYNCn:
These TxSYNCn pins are used to indicat e the single f rame
boundary withi n an outbound T1/E1 frame. In both DS1 or E1
mod e, the single frame boundary repeats every 125 microsec-
o nds (8kHz) .
In DS1/E1 base rate, TxSYNCn can be configured as either
input or output as described below.
When TxSYNCn is configured as an Input:
Users must provide a signal which must pulse "High" for one
peri od of TxSERCLK during th e fi rst bit of an outbou nd DS1/
E1 frame. It is impera tive t hat the TxSYNC input si gnal be syn-
chronized with the TxSERCLK i nput signal .
When TxSYNCn is configured as an Output:
The transmit T1/ E 1 fr am er wi ll output a signal which pulses
"High" for one period of TxSERCLK dur ing the first bit of an
outbound DS1/E1 fra me.
DS1/E1 Hig h-Speed Backplane Modes* - TxSYNCn as
INPUT ONLY:
In this m ode, TxSYNCn must be an input regardless of the
clock source that is chosen to be the timing source for the
transmit fram er. In 2.048MVIP/4.096/8.192MHz high-speed
mod es, TxSYNCn pi ns must be pul sed ’Hig h’ for one perio d of
TxSERCLK duri ng the firs t bit of the out boun d T 1/E1 frame. In
HMVIP mode, TxSYNC0 and TxS YNC4 must be puls ed ’High ’
for 4 clock cycles of the TxMSYNC/TxINCLK signal in the
position of t he fi rst tw o and the l ast two bits of a multi plexed
frame. In H.100 mode, TxSYNC0 and TxSYNC4 m ust be
pulsed ’High’ f or 2 c lock cycles of the TxMSYNC/TxI NCLK sig-
nal i n the position of the first and the last bi t of a multiplexed
frame.
DS1 or E1 Framer Bypass Mode - TxNEGn
In this m ode, TxSYNCn is used as the negative digital input
pin ( T xNEG) to t he LIU.
NOTE: *High-speed backplane modes include (For T1/E1)
2.048MVIP, 4.096MHz, 8.192MHz, 16.384MHz
HMVIP, H.100, Bit-multiplexed modes, and (For T1
only) 12.352MHz Bit-multiplexed mode.
NOTE: In DS1 high-speed modes, the DS-0 data is mapped
into an E1 frame by ignoring every fourth time slot
(don’t care).
NOTE: These 8 pins are internally pulled “Low” for each
channel.
TRANSMIT SYSTEM SIDE INTER FACE
SIGNAL NAME 420 PKG
BALL#484 PKG
BALL # TYPE OUTPUT
DRIVE(MA) DESCRIPTION
XRT86VL38
18
REV. V1.2.0 OCTAL T1/E1/J1 FRAM ER/LIU COMBO - H ARDWARE DESCRIPTION
TxMSYNC0/
TxINCLK0
TxMSYNC1/
TxINCLK1
TxMSYNC2/
TxINCLK2
TxMSYNC3/
TxINCLK3
TxMSYNC4/
TxINCLK4
TxMSYNC5/
TxINCLK5
TxMSYNC6/
TxINCLK6
TxMSYNC7/
TxINCLK7
B10
A17
C24
L24
AC21
AD16
AC8
AF2
A9
B15
E18
K20
U17
AB14
AB3
W5
I/O 12 M u lt ifram e Syn c Pu l se (T x M SY N C n ) / Tra n s m it Inpu t
Clock (T xINCLKn)
The exact function of these pins depends on the mode of
operation selected, as described below.
DS1/E1 Base Rate Mode (1.544MHz/2.048MHz) - TxM-
SYNCn
In thi s mode, these pins are used to in dicate the mult i-fra me
boundary withi n an outbound DS1/E1 fr am e.
In DS1 ESF mode, TxMSYNCn repeats every 3ms.
In DS1 SF mode, TxMSYNCn repeats every 1.5m s.
In E1 mode, TxMSYNCn repeats every 2ms.
If TxMSYNCn is configured as an input , TxMSYNC n must
puls e "High" f or one period of TxSERCLK dur ing the firs t bit of
an out bound DS1/E1 multi-frame. It is imperative that the
TxMSYNC input si gnal be synchronized with the TxSERCLK
input signal .
If TxMSYNCn is configured as an output, the transmit section
of the T1/E1 framer will output and pulse TxMSYNC "High" f or
one peri od of TxSERCLK during t he fi rst bit of an outbound
DS1/E1 fram e.
DS1/E1 Hig h-Speed Backplane Modes* - (T xINCLKn as
INPUT ONLY)
In thi s mode, this pi n mus t be used as the high- speed input
clock pin (TxI NCLKn) for the back plane interface to latch in
high-speed or multiplexed data on the TxSERn pin. The fre-
quency of TxI NCL K is pr esented in the t able below.
NOTES:
1. *High-speed backplane modes include (For T1/E1)
2.048MVIP, 4.096MHz, 8.192MHz, 16.384MHz
HMVIP, H.100, Bit-multiplexed modes, and (For T1
only) 12.352MHz Bit-multiplexed mode.
2. In DS1 high-speed modes, the DS-0 data is mapped
into an E1 frame by ignoring every fourth time slot
(don’t care).
3. These 8 pins are internally pulled “Low” for each
channel.
TRANSMIT SYSTEM SIDE INTER FACE
SIGNAL NAME 420 PKG
BALL#484 PKG
BALL # TYPE OUTPUT
DRIVE(MA) DESCRIPTION
OPERATION MODE FREQUENCY OF
TXINCLK(MHZ)
2.048MVIP non-multiplexed 2.048
4.096MHz non-multiplexed 4.096
8.192MHz non-multiplexed 8.192
12.352MHz Bit -multiplexed
(DS1 ONLY) 12.352
16.384MHz Bit -multiplexed 16.384
16.384 HMVIP Byt e-multiplexed 16.384
16.384 H.100 Byte-mul tiplexed 16.384
XRT86VL38
19
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1.2.0
TxCHCLK0
TxCHCLK1
TxCHCLK2
TxCHCLK3
TxCHCLK4
TxCHCLK5
TxCHCLK6
TxCHCLK7
A12
E17
B26
J22
AD22
AE16
AD10
AB2
C12
A16
E19
G22
AA19
Y13
V11
V5
O 8 Tr ansmit Channel Clock Output Signal (TxCHCLKn):
The exact function of this pin depends on whether or not the
transmit fr am er enables the transm it fractional/s ignaling i nter-
face to input f ractional data, as described below.
If t ransm it fract ional/si gnaling interface is di sabled:
This pin indi cates the boundary of each ti me slot of an out-
bound DS1 /E1 frame. In T1 m ode, e ach of thes e ou tput pins i s
a 192k Hz cl ock whi ch pu lses " High" durin g the LSB of each 24
time slots. In E1 mode, each of these output pi ns is a 256kHz
clock which pul ses "High" dur ing the LSB of each 32 time
slots. The Terminal Equipment can use this cl ock signal to
sample the TxCHN0 through Tx CHN4 time slot identifier pins
to determine whi ch time slot i s being processed.
If t ransm it fract ional/signaling i nterf ace is enabled:
TxCHCLKn i s the f ractional interface clock which either out-
put s a c lock si gna l for the tim e slot that has be en confi gured t o
input fract ional data, or outp uts an enable signal for the frac-
tional tim e slot so that fract ional data can be clocked into the
device using the TxSERCLK pin.
NOTE: Transmit fractional interface can be enabled by
programming to bit 4 - TxFr1544/TxFr2048 bit from
register 0xn120 to ‘1’.
TRANSMIT SYSTEM SIDE INTER FACE
SIGNAL NAME 420 PKG
BALL#484 PKG
BALL # TYPE OUTPUT
DRIVE(MA) DESCRIPTION
XRT86VL38
20
REV. V1.2.0 OCTAL T1/E1/J1 FRAM ER/LIU COMBO - H ARDWARE DESCRIPTION
TxCHN0_0/
TxSIG0
TxCHN1_0/
TxSIG1
TxCHN2_0/
TxSIG2
TxCHN3_0/
TxSIG3
TxCHN4_0/
TxSIG4
TxCHN5_0/
TxSIG5
TxCHN6_0/
TxSIG6
TxCHN7_0/
TxSIG7
D12
C18
F22
L22
AD21
AC15
AB10
AC5
B11
C16
C21
K19
W16
AB13
W11
W4
I/O 8Transmi t Time Slot Octet I dentifi er Out put 0 ( TxCHNn_0) /
Transmit Serial Signaling Input (TxSIGn):
The exact function of these pins depends on whether or not
the tr ansmit framer enables the transmi t fractional/signali ng
interfac e, as described below:
If t ransm it fract ional/si gnaling interface is di sabled -
TxCHNn_0:
These out put pins (Tx CHNn_4 throug h TxCHNn_0) ref lect t he
five-bit binary value of the current tim e slot being pr ocessed
by the transm it ser ial interface. Terminal Equipment can use
the TxCHCLK to sample the five output pin s of each channel
in order to ide nti fy the ti me slot being processed. This pin indi-
cates the Least Si gnificant Bit (LSB) of the ti m e slot channel
being pro ces se d.
If t ransm it fract ional/signaling i nterface is enabled -
TxSIGn:
These pins can be use d to input robbed-bit signaling data to
be inserted within an outbound DS1 frame or to input Channel
Associated Signaling (CAS) data within an outbound E1
frame, as described below.
T1 Mode: Sign aling data ( A ,B,C,D) of each channel must be
provided on bit 4, 5,6,7 of each time slot on t he TxSIG pin if 16 -
code signaling is used. If 4- code signaling is sele cted, signal-
ing data (A,B) of each channel must be provided on bi t 4, 5 of
each time slot on th e T xSIG pi n. If 2-code si gnaling is
selected, signaling data (A) o f each channel must be provided
on bit 4 of each time sl ot on the TxSIG pin.
E1 Mode: Signali ng data i n E1 mode can be provided on the
TxSIGn pins on a time-s lot-basi s as in T1 mode, or it can be
provided on time slot 16 only via the TxSIGn i nput pi ns. In the
lat ter case, signaling dat a (A,B ,C,D) of chann el 1 an d cha nnel
17 mus t be in serted on the TxSIGn pin durin g ti me slot 16 of
fra me 1, signal ing dat a ( A,B,C, D) of channe l 2 and c hannel 18
mus t be in serted on the TxSIGn pin durin g ti me slot 16 of
frame 2...etc. The CAS multiframe Alignments bits (0000 bits)
and the extra bits/alarm bit (xyxx) must be inserted on the
TxSIGn pin during t ime slot 16 of fram e 0.
NOTE: Transmit fractional interface can be enabled by
programming to bit 4 - TxFr1544/TxFr2048 bit from
register 0xn120 to ‘1’.
NOTE: These 8 pins are internally pulled “Low” for each
channel.
TRANSMIT SYSTEM SIDE INTER FACE
SIGNAL NAME 420 PKG
BALL#484 PKG
BALL # TYPE OUTPUT
DRIVE(MA) DESCRIPTION
XRT86VL38
21
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1.2.0
TxCHN0_1/
TxFrTD0
TxCHN1_1/
TxFrTD1
TxCHN2_1/
TxFrTD2
TxCHN3_1/
TxFrTD3
TxCHN4_1/
TxFrTD4
TxCHN5_1/
TxFrTD5
TxCHN6_1/
TxFrTD6
TxCHN7_1/
TxFrTD7
B12
D18
D25
L25
AF22
AD15
AF9
AD3
A11
D15
E20
K17
U15
AB12
AB5
V8
I/O 8Transmi t Time Slot Octet I dentifi er Out put 1 ( TxCHNn_1) /
Transmit Seri al Fractional Input (TxFrTDn):
The exact function of these pins depends on whether or not
the tr ansmit framer enables the transmi t fractional/signali ng
interfac e, as described below:
If t ransm it fract ional/si gnaling interface is di sabled -
TxCHNn_1
These output signals (TxCHNn_4 through TxCHNn_0) reflect
the fi ve-bi t binary val ue of the current time slot being pro-
cessed by the transmit ser ial interface. Terminal Equipment
can use the TxCHCLK t o sample the five outp ut pi ns of each
channe l in order to ident ify th e t ime slot bei ng pro cessed. This
pin i ndicates Bit 1 of the time slot channel bei ng processed.
If t ransm it fract ional/signaling i nterf ace is enabled -
TxFrTDn
These pins are used as the fractional dat a input pins to input
fraction al DS1/ E1 payload data which will be inserted wit hin
an outbound DS1/E1 fr am e. In this mode, ter m inal equip me nt
can use either TxCHCLK or TxSERCL K to cl ock i n fraction al
DS1/E1 payload data depending on the fra me r configura tion.
NOTES:
1. Transmit fractional/Signaling interface can be
enabled by programming to bit 4 - TxFr1544/
TxFr2048 bit fr om register 0xn120 to ‘1’.
2. These 8 pins are internally pulled “Low” for each
channel.
TxCHN0_2/
Tx32MHz0
TxCHN1_2/
Tx32MHz1
TxCHN2_2/
Tx32MHz2
TxCHN3_2/
Tx32MHz3
TxCHN4_2/
Tx32MHz4
TxCHN5_2/
Tx32MHz5
TxCHN6_2/
Tx32MHz6
TxCHN7_2/
Tx32MHz7
A13
B19
C26
M22
AC20
AE15
AE9
AD2
D12
F15
F19
K22
Y16
W13
AA5
AB1
O 8 Transmi t Time Slot Octet Identifi er Output 2 (TxCHNn_2) /
Transmit 32.678MHz Clock Ou tput (Tx32MHZ):
The exact function of these pins depends on whether or not
the tr ansmit framer enables the transmi t fractional/signali ng
interfac e, as described below:
If t ransm it fract ional/si gnaling interface is di sabled -
TxCHNn_2
These output signals (TxCHNn_4 through TxCHNn_0) reflect
the fi ve-bi t binary val ue of the current time slot being pro-
cessed by the transmit ser ial interface. Terminal Equipment
can use the TxCHCLK t o sample the five outp ut pi ns of each
channe l in order to ident ify th e t ime slot bei ng pro cessed. This
pin i ndicates Bit 2 of the time slot channel bei ng processed.
If t ransm it fract ional/signaling i nterf ace is enabled -
Tx32MHz
These pins are used to output a 32.678MHz clo ck reference
which is derived from the MCLKIN input pin.
NOTE: Transmit fractional interface can be enabled by
programming to bit 4 - TxFr1544/TxFr2048 bit from
register 0xn120 to ‘1’.
TRANSMIT SYSTEM SIDE INTER FACE
SIGNAL NAME 420 PKG
BALL#484 PKG
BALL # TYPE OUTPUT
DRIVE(MA) DESCRIPTION
XRT86VL38
22
REV. V1.2.0 OCTAL T1/E1/J1 FRAM ER/LIU COMBO - H ARDWARE DESCRIPTION
TxCHN0_3/
TxOHSYNC0
TxCHN1_3/
TxOHSYNC1
TxCHN2_3/
TxOHSYNC2
TxCHN3_3/
TxOHSYNC3
TxCHN4_3/
TxOHSYNC4
TxCHN5_3/
TxOHSYNC5
TxCHN6_3/
TxOHSYNC6
TxCHN7_3/
TxOHSYNC7
E13
A20
F23
M24
AE20
AB14
AF8
AC3
F13
C17
D21
L19
AB18
Y12
AB4
Y2
O
O
8Transmit T ime Sl ot Oct et Identifier Output 3 (TxCHNn_3) /
Transmit Overhead Synchronization Pul se (TxOHSYNCn):
The exact function of these pins depends on whether or not
the tr ansmit framer enables the transmi t fractional/signali ng
interfac e, as described below:
If t ransm it fract ional/si gnaling interface is di sabled -
TxCHNn_3
These output signals (TxCHNn_4 through TxCHNn_0) reflect
the fi ve-bi t binary val ue of the current time slot being pro-
cessed by the transmit ser ial interface. Terminal Equipment
can use the TxCHCLK t o sample the five outp ut pi ns of each
channe l in order to ident ify th e t ime slot bei ng pro cessed. This
pin i ndicates Bit 3 of the time slot channel bei ng processed.
If t ransm it fract ional/signaling i nterf ace is enabled -
TxOHSYNCn
These pins are used to output an Overhead Synch roni zati on
Pulse which indicates the first bit of each m ulti-frame.
NOTE: Transmit fractional interface can be enabled by
programming to bit 4 - TxFr1544/TxFr2048 bit from
register 0xn120 to ‘1’.
TxCHN0_4
TxCHN1_4
TxCHN2_4
TxCHN3_4
TxCHN4_4
TxCHN5_4
TxCHN6_4
TxCHN7_4
C14
A21
E25
M26
AD19
AC14
AE8
AB4
A13
G17
C22
L17
AA16
AB11
W9
U7
O 8 Transmit Time Slot Oc tet Identifi er O utput-Bit 4
(TxCHNn_4):
These output signals (TxCHNn_4 through TxCHNn_0) reflect
the fi ve-bi t binary val ue of the current time slot being pro-
cessed by the transmit ser ial interface. Terminal Equipment
can use the TxCHCLK t o sample the five outp ut pi ns of each
channe l in order to ident ify th e t ime slot bei ng pro cessed. This
pin i ndicates the Most Signi fi cant Bit (MSB) of the tim e slot
channel being process ed.
TRANSMIT SYSTEM SIDE INTER FACE
SIGNAL NAME 420 PKG
BALL#484 PKG
BALL # TYPE OUTPUT
DRIVE(MA) DESCRIPTION
XRT86VL38
23
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1.2.0
TRANSMIT OVERHEAD INTERFACE
SIGNAL NAME 420 PKG
BALL # 484 PKG
BALL # TYPE OUTPUT
DRIVE(MA) DESCRIPTION
TxOH0
TxOH1
TxOH2
TxOH3
TxOH4
TxOH5
TxOH6
TxOH7
C12
A18
E26
J25
AF25
AD14
AF10
AC2
E13
B16
E21
J18
W17
AA11
U11
AA1
I - Transmit Overhead Input (TxOHn):
The exact functio n of the se pins depends on the mode
of operation selected, as described below.
DS1 Mode
These pins operate as the source of Datalink b its which
will be inserted into the Dat alink bit s withi n an outbound
DS1 frame if the f ramer is configured accordingly.
Datalink Equipment can provide data to this input pi n
using the TxOHCLKn clo ck at ei ther 2kHz or 4kHz
depending on the transmit datalink bandwidth selected.
NOTE: This input pin will be disabled if the framer is
using the Transmit HDLC Controller, or the
TxSER input as the source for the Data Link
Bits.
E1 Mode
These pins operate as the source of Data li nk bits or Sig -
nalin g bits depending on the fra me r configuration, as
described below.
Sourcing Datali nk bits f rom TxOHn:
The E1 transmit fr amer will output a clock edge on TxO-
HCLKn for each S a bit that has been confi gured t o carry
datalink in formation. Terminal equi pm ent can then use
TxOHCLKn to provi de data li nk bits on TxOH n to be
inserted into the Sa bits within an outbound E1 frame.
Sourcing Signaling bit s from TxOHn:
Users must provide si gnaling data on TxOHn pi ns on
time slo t 16 only. Signaling data (A,B,C,D) of channel 1
and channel 17 must be inserted on the TxOHn pin dur-
ing ti me slot 16 of frame 1, signaling data (A,B,C,D) of
channel 2 and channel 18 must be inserted on the
TxOHn pin dur i ng time slot 16 of frame 2. ..et c. The CAS
multiframe Alignments bits (0000 bits) and the extra
bits/ala rm bit (xyxx) must be inserted on the TxOHn pin
during time slot 16 of frame 0.
NOTE: These 8 pins ar e internally pulled “Low” for each
channel.
XRT86VL38
24
REV. V1.2.0 OCTAL T1/E1/J1 FRAM ER/LIU COMBO - H ARDWARE DESCRIPTION
TxOHCLK0
TxOHCLK1
TxOHCLK2
TxOHCLK3
TxOHCLK4
TxOHCLK5
TxOHCLK6
TxOHCLK7
E11
A19
E24
K23
AF23
AB16
AC10
AE1
A10
A17
B22
H22
AB20
U13
AA7
V6
O 8 Transmit OH Serial Clock Output Signal(TxOHCLKn)
This pin funct ions as an overhead out put clock sign al for
the tra nsm it overhead interf ace, and its functi on is
explai ned below.
DS1 Mode
If t he TxOH pins hav e been configured to be the sou rce
for Dat alink bits, the DS1 transm it fr am er wi ll provide a
clock edge for each Data Link Bit. In DS1 ESF mode,
the TxOHCLK can either be a 2kHz or 4kHz output sig-
nal dependi ng on the selection of Dat a Link Bandwidth
(Register 0xn10A).
Data Li nk Eq uipment c an provi de dat a to t he TxO Hn pin
on the ri sing edge of TxOHCLK. The framer latches the
data on the falling edge of this clock signal.
E1 Mode
If t he TxOH pins hav e been configured to be the sou rce
for Dat a Link bits , t he E1 transmit fram er wi ll provide a
clock edge for each National Bit (Sa bi ts) that has been
configured to carry data link information. (Register
0xn10A)
TRANSMIT OVERHEAD INTERFACE
SIGNAL NAME 420 PKG
BALL # 484 PKG
BALL # TYPE OUTPUT
DRIVE(MA) DESCRIPTION
XRT86VL38
25
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1.2.0
RECEIVE OVERHEAD I NTERFACE
SIGNAL NAME 420 PKG
BALL # 484 PKG
BALL # TYPE OUTPUT
DRIVE(MA) DESCRIPTION
RxOH0
RxOH1
RxOH2
RxOH3
RxOH4
RxOH5
RxOH6
RxOH7
C11
B15
D21
F26
AA22
AE17
AE14
AF7
D11
A14
D18
H18
V18
Y14
U12
V10
O 8 Receive Overhead Output ( R xOHn):
These pin s funct io n as the Rec eive Over head output, or
Receive Si gnaling Output depending on the recei ve
framer configur ation, as described below.
DS1 Mode
If the RxOH pin s have been configured as t he destina-
tion for the Data Li nk bits wit hin an inbound DS1 frame,
datalink bi ts will be output to the RxOHn pins at eit her
2kHz or 4kHz depending on the Recei ve datalink band-
width selected. (Register 0xn10C).
If configured appropriately, signaling information in the
receive signal ing array register s (Registe rs 0xn50 0-
0xn51F) can also be output t o the RxOHn output pins.
E1 Mode
These output pins will always o utput the contents of the
Nationa l Bi ts (Sa4 through Sa8) if these Sa bits have
been confi gured to carry Data Link information (Regi ster
0xn10C). The Recei ve Overhead Out put Interface will
provi de a cloc k edge on RxOHCLKn for each Sa bit car-
rying Data Link information.
If configured appropriately, signaling information in the
receive signal ing array register s (Registe rs 0xn50 0-
0xn51F) can also be output t o the RxOHn output pins.
RxOHCLK0
RxOHCLK1
RxOHCLK2
RxOHCLK3
RxOHCLK4
RxOHCLK5
RxOHCLK6
RxOHCLK7
B9
D16
E21
G24
Y22
AF17
AE13
AE7
F11
D14
A21
E22
V19
AA14
AB10
Y6
O 8 Receive Overhead Clock Output (RxOHCLKn):
This p in f unct ions as an over head output cloc k s ignal f or
the receive overhead interface, and its function is
explai ned below.
DS1 Mode
If the RxOH pin s have been configured t o be the desti-
nation for Datalink bi ts, the DS1 transmit framer will out-
put a clock edge for each Data Link Bit. I n DS1 ESF
mode, the RxOHCLK can either be a 2kHz or 4kHz out-
put signal dependi ng on the selecti on of Data Link
Bandwidth (Register 0xn10C).
Data Link Equipment can clock out datalink bits on the
RxOHn pin using this cl ock signal.
E1 Mode
The E1 receiv e framer provides a clock edge for each
National Bit (Sa bits) that is confi gured to carry data li nk
information.
Data Link Equipment can clock out datalink bits on the
RxOHn pin using this cl ock signal.
XRT86VL38
26
REV. V1.2.0 OCTAL T1/E1/J1 FRAM ER/LIU COMBO - H ARDWARE DESCRIPTION
RECEIVE SYSTEM SIDE INTERFACE
SIGNAL NAME 420 PKG
BALL#484 PKG
BALL # TYPE OUTPUT
DRIVE (MA) DESCRIPTION
RxSYNC0/
RxNEG0
RxSYNC1/
RxNEG1
RxSYNC2/
RxNEG2
RxSYNC3/
RxNEG3
RxSYNC4/
RxNEG4
RxSYNC5/
RxNEG5
RxSYNC6/
RxNEG6
RxSYNC7/
RxNEG7
D9
D15
D19
G23
AE26
AF19
AB11
AC6
A8
E16
A18
D22
Y20
Y15
AA6
Y3
I/O 12 Receive Single Frame Sync Pulse (RxSYNCn):
The exact function of these pi ns depends on the mode of
operation selected, as described below.
DS1/E1 Base Rate Mode (1.544MHz/2.048MHz) -
RxSYNCn:
These RxSYNCn pins are used to indicate the single
frame boundary with in an i nbound T1/E1 f rame. In both
DS1 or E1 mode, the si ngle frame boundary repeats
every 125 m icroseconds (8kH z).
In DS1/E1 base r ate, RxSYNCn can be confi gured as
either input or output depending on t he slip buffer con figu-
rati on as described below.
When RxSYNCn is configured as an Input:
Users must provide a signal whic h mus t pul se "High" fo r
one peri od of RxSERCLK an d re peats e very 125 μS. The
receive seria l In terface will output th e fi rst bit of an
inbound DS1/E1 frame during the provid ed RxSYNC
pulse.
NOTE: It is imperative that the RxSYNC input signal be
synchronized wit h the RxSERCLK input signal.
When RxSYNCn is configured as an Ou tput :
The receive T1/E1 fram er will output a si gnal which
pulses "High" for o ne perio d of RxSERCLK dur ing t he fir st
bit of an inbound DS1/E1 frame.
DS1/E1 Hig h-Speed Backplane Modes* - RxSYNCn as
INPU T ONLY:
In this mode, RxSYNCn must be an input regardless of
the slip buffer configuration. In 2. 048MVIP/4.096/
8.192MHz high-speed modes, RxSYNCn pi ns m ust be
pulsed ’High’ for one period of RxSERCLK during the first
bit of the in bound T1/E1 fram e. In HMVIP mode,
RxSYNCn must be pulsed ’High’ for 4 clock cycles of the
RxSERCLK signal in t he position of the first two and the
last two bits of a multiplexed frame. In H.100 mode,
RxSYNCn must be pulsed ’High’ for 2 clock cycles of the
RxSERCLK signal in t he position of t he first and the l ast
bit of a multi plexed frame.
DS1 or E1 Framer Bypass Mode - RxNEGn
In this mod e, RxSYNCn i s used as the Receive negative
digi tal output pin (RxNEG) from the LIU.
NOTE: *High-speed backplane modes include (For T1/
E1) 2.048MVIP, 4.096MHz, 8.192MHz,
16.384MHz HMVIP, H.100, Bit-multiplexed
modes, and (For T1 only) 12.352MHz Bit-
multi plexed mode.
NOTE: In DS1 high-speed modes, the DS-0 data is
mapped int o an E1 frame by ignoring every four th
time slot (don’ t car e ).
NOTE: These 8 pins are internally pulled “Low” for each
channel.
XRT86VL38
27
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1.2.0
RxCRCSYNC0
RxCRCSYNC1
RxCRCSYNC2
RxCRCSYNC3
RxCRCSYNC4
RxCRCSYNC5
RxCRCSYNC6
RxCRCSYNC7
B8
D13
E20
G25
AB25
AF21
AE10
AD5
B8
B12
A20
G20
Y21
AA17
Y9
V9
O12 Receive Multiframe Sync Pulse (RxCRCSYNCn):
The RxCRCSYNCn pins are used to indicate the recei ve
multi -frame boundary. These pins pulse "Hi gh" for one
perio d of RxSERCLK when the f irst bit of an inbound
DS1/E1 Mul ti-fr ame i s being output on the RxCRCSYNCn
pin.
•In DS1 ESF mode, RxCRCSYNCn repe ats every 3m s
•In DS1 SF mode, RxCRCSYNCn repe ats every 1.5ms
•In E1 mode, RxCRCSYNCn re peats every 2ms.
RxCASYNC0
RxCASYNC1
RxCASYNC2
RxCASYNC3
RxCASYNC4
RxCASYNC5
RxCASYNC6
RxCASYNC7
E10
E15
A23
H23
AD24
AE19
AC9
AF6
C10
B14
C18
F21
V17
AB17
Y8
W10
O12 Receive CAS Multiframe Sync Pulse (RxCASYNCn):
- E1 Mode Only
The RxCASYNCn pins are used to i ndicate the E1 CAS
Multi f-frame boundary. These pins pul se "High" for one
perio d of RxSERCLK when th e fi rst bit of an E1 CAS
Multi -f rame is being out put on the RxCASYNCn pin.
RECEIVE SYSTEM SIDE INTERFACE
SIGNAL NAME 420 PKG
BALL#484 PKG
BALL # TYPE OUTPUT
DRIVE (MA) DESCRIPTION
XRT86VL38
28
REV. V1.2.0 OCTAL T1/E1/J1 FRAM ER/LIU COMBO - H ARDWARE DESCRIPTION
RxSERCLK0/
RxLINECLK0
RxSERCLK1/
RxLINECLK1
RxSERCLK2/
RxLINECLK2
RxSERCLK3/
RxLINECLK3
RxSERCLK4/
RxLINECLK4
RxSERCLK5/
RxLINECLK5
RxSERCLK6/
RxLINECLK6
RxSERCLK7/
RxLINECLK7
A6
B13
C20
H25
AD26
AC19
AB12
AB6
D9
A12
B18
H20
W20
V16
W12
W6
I/O 12 Receive Serial Clock Signal (RxSERCLKn) / Receive
Line Clock (RxLINECLKn):
The exact function of these pi ns depends on the mode of
operation selected, as described below.
In Base-Rate Mode (1.544MHz/2.048MHz) - RxSER-
CLKn:
These pins are used as the rec eive serial clock on the
system side inter face which can be configured as either
input or output. The receive ser ial interface outputs data
on RxSERn on the rising edge of RxSERCLKn.
When RxSERCLKn is configu red as Inp ut:
These pins will be input s if the slip buffer on the Receive
path is enabled. System side equipment must provide a
1.544MHz clock rate to this input pin for T1 mode of ope r -
ation, and 2.048MHz cl ock rate in E1 mode.
When RxSERCLKn is configu red as Output:
These pi ns will be outputs if slip buffer is bypassed. The
receive framer will output a 1.544MHz clock rate in T1
mode of operation, and a 2.048MHz clock rate in E1
mode.
DS1/E1 High-Speed Backplane Modes* - (RxSERCLK
as INPUT ONLY)
In thi s mod e, t his pin must be used as the high-speed
input clock for the backplane i n ter face to output high-
speed or mult iplexed data on the RxSERn pin. The fre-
quency of RxSERCLK i s presented in the table below.
NOTES:
1. *High-speed backplane modes include (For T1/
E1) 2.048MVIP, 4.096MHz, 8.192MHz,
16.384MHz HMVIP, H.100, Bit-multiplexed
modes, and (For T1 only) 12.352MHz Bit-
multi plexed mode.
2. For DS1 high-speed modes, the DS-0 data is
mapped into an E1 frame by ignoring every
fo u rth time slot (don ’t care).
RECEIVE SYSTEM SIDE INTERFACE
SIGNAL NAME 420 PKG
BALL#484 PKG
BALL # TYPE OUTPUT
DRIVE (MA) DESCRIPTION
OPERATION MODE FREQUENCY OF
RXSERCLK(MHZ)
2.048MVIP non-multi plexed 2.048
4.096MHz non-multiplexed 4.096
8.192MHz non-multiplexed 8.192
12.352MHz Bit-mul tiplex ed
(DS1 ONLY) 12.352
16.384MHz Bit-mul tiplex ed 16.384
16.384 HMVIP Byte-multiplexed 16.384
16.384 H.100 Byte-mul ti plexe d 16.384
XRT86VL38
29
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1.2.0
RxSERCLK0/
RxLINECLK0
RxSERCLK1/
RxLINECLK1
RxSERCLK2/
RxLINECLK2
RxSERCLK3/
RxLINECLK3
RxSERCLK4/
RxLINECLK4
RxSERCLK5/
RxLINECLK5
RxSERCLK6/
RxLINECLK6
RxSERCLK7/
RxLINECLK7
A6
B13
C20
H25
AD26
AC19
AB12
AB6
D9
A12
B18
H20
W20
V16
W12
W6
I/O 12 (Continued)
DS1 or E1 Framer Bypa ss Mo de - RxLINECLKn
In this mode, RxSERCLKn is used as the Receive Line
Clock out put pin (RxLi neClk) from the LIU.
NOTE: These 8 pins are internally pulled “High” for each
channel.
RxSER0/
RxPOS0
RxSER1/
RxPOS1
RxSER2/
RxPOS2
RxSER3/
RxPOS3
RxSER4/
RxPOS4
RxSER5/
RxPOS5
RxSER6/
RxPOS6
RxSER7/
RxPOS7
C7
B14
C21
D26
AC25
AC18
AE12
AB7
B7
E14
D17
F20
W19
AA15
AA9
AB2
O12 Receive Serial Data Output (RxSERn):
The exact function of these pi ns depends on the mode of
operation selected, as described below.
DS1/E1 Mode - RxSERn
These pi ns function as the receive serial data output on
the syst em side int erfac e, which ar e updated on th e risi ng
edge of the RxSERCLKn pin. All the framing alignment
bits, fa cil ity data li nk bit s, CRC bits, and signaling informa-
tion will also be extracted to this output pin.
DS1 or E1 Hi gh-Sp eed Multiplexe d Mode* - RxSERn
In this mode, these pin s are us ed as the high- speed multi-
plexed data output pin on the system side. High-speed
multi plexed data of channels 0-3 will outp ut on RxSER0
and high-speed multiplexed data of channels 4-7 will out-
put on RxSER4 in a byte or bit-interleaved way. The
framer outputs t he multiplexed data on RxSER0 and
RxSER4 using th e high-spe ed input clock (Rx SERCLKn) .
DS1 or E1 Framer Bypass Mode
In this mod e, RxSERn i s used as the positi ve digit al out-
put pin (Rx PO Sn) f rom the LIU.
NOTE: *High-speed multiplexed modes include (For T1/
E1) 16.384MHz HMVIP, H.100, Bit-multiplexed
modes, and (For T1 only) 12.352MHz Bit-
multi plexed mode.
NOTE: In DS1 high-speed modes, the DS-0 data is
mapped int o an E1 frame by ignoring every four th
time slot (don’ t car e ).
RECEIVE SYSTEM SIDE INTERFACE
SIGNAL NAME 420 PKG
BALL#484 PKG
BALL # TYPE OUTPUT
DRIVE (MA) DESCRIPTION
XRT86VL38
30
REV. V1.2.0 OCTAL T1/E1/J1 FRAM ER/LIU COMBO - H ARDWARE DESCRIPTION
RxCHN0_0/
RxSig0
RxCHN1_0/
RxSig1
RxCHN2_0/
RxSig2
RxCHN3_0/
RxSig3
RxCHN4_0/
RxSig4
RxCHN5_0/
RxSig5
RxCHN6_0/
RxSig6
RxCHN7_0/
RxSig7
D8
D14
A22
G26
AD25
AD18
AC13
AB8
A7
B13
B19
H19
AA22
U14
AA10
Y7
O 8 Receive Ti me Slot Octet I dentifie r Output (Rx CHNn_0)
/ Receive Ser ial Signaling Output (RxSI G n):
The exact functio n of these pins depends on whether or
not the re ceive framer enables the receive f ractional /sig-
nali ng int erface, as described below:
If receive fract ional/si gnalin g interface is di sabled -
RxCHNn_0:
These output pins (RxCHNn _4 thr ough RxCHNn_0)
refl ect the fiv e-bit binary value of the current t ime slot
being output by the receive serial inte rface. Syst em
equipment can use the RxCHCLKn to sample t he five out-
put pins of each channel to identify the time slot being out-
put on these pins. RxCHNn_0 indicates the Least
Signi fi cant Bit (LSB) of the t ime slot channel being output.
If receive fract ional/signaling interface is enabled -
RxSIGn:
These pi ns can be used to output robbed-bit signaling
data wi thin an inbound DS1 frame or to output Channel
Associated Signal ing (CAS) dat a wit hin an inbound E1
frame, as described below.
T1 Mode: Signal ing data (A,B,C,D) of each channel wi ll
be output on bit 4,5,6, 7 of each t ime slo t on the RxSI G pin
if 16-code signaling is used. If 4-code signaling is
selected, si gnaling data (A,B) of each chann el wi ll be out-
put on bit 4, 5 of each time slot on the RxSIG pin. If 2-
code si gnaling is selected, signaling data (A) of each
channel will be output on bit 4 of each time slot on the
RxSIG pin.
E1 Mode: Signal ing dat a in E1 mode will be out put on the
RxSIGn pins on a time-s lot-basi s as in T1 mode, or i t can
be output on ti me slot 16 onl y v ia the RxSIGn out put pins .
In the la tter case, si gnali ng data (A,B, C ,D) of channel 1
and channel 17 will be output on the RxSIGn pin during
time sl ot 16 of frame 1, sig naling data (A,B,C,D) of chan-
nel 2 and channel 18 wi ll be output on t he RxSIGn pin
during t ime slot 16 of frame 2...etc . The CAS mult if rame
Align me nts bits (0000 bits) and th e extr a bits/alarm bit
(xyxx) wi ll be o utpu t on the RxSIGn p in d uring t ime slot 1 6
of frame 0.
NOTE: Receive Fractional/signaling interface can be
enabled by programming to bit 4 - RxFr1544/
RxFr2048 bit from reg ister 0xn122 to ‘1’.
RECEIVE SYSTEM SIDE INTERFACE
SIGNAL NAME 420 PKG
BALL#484 PKG
BALL # TYPE OUTPUT
DRIVE (MA) DESCRIPTION
XRT86VL38
31
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1.2.0
RxCHN0_1/
RxFrTD0
RxCHN1_1/
RxFrTD1
RxCHN2_1/
RxFrTD2
RxCHN13_1/
RxFrTD3
RxCHN4_1/
RxFrTD4
RxCHN5_1/
RxFrTD5
RxCHN6_1/
RxFrTD6
RxCHN7_1/
RxFrTD7
E9
E14
B22
H26
AE25
AF18
AB13
AC7
C9
C13
C19
G21
AA21
AB16
V12
W8
O 8 Receive Time Slot Octet Ident ifier Output Bit 1
(RxCHNn_1) / Recei ve Serial Fract ional Output
(RxFrTDn):
The exact functio n of these pins depends on whether or
not the re ceive framer enables the receive f ractional /sig-
nali ng int erface, as described below:
If receive fract ional/si gnalin g interface is di sabled -
RxCHNn_1:
These output pins (RxCHNn _4 thr ough RxCHNn_0)
refl ect the fiv e-bit binary value of the current t ime slot
being output by the receive serial inte rface. Syst em
equipment can use the RxCHCLKn to sample t he five out-
put pins of each channel to identify the time slot being out-
put on thes e pins. RxCHNn_1 indi cates Bit 1 of the ti me
slot channel being output.
If receive fract ional/signaling interface is enabled -
RxFrTDn:
These pi ns are used as the fractional data output pins to
output f ractional DS1/E1 pay load data wit hin an inbound
DS1/E1 frame. In this mode, system equipment can use
eithe r RxCHCLK or RxSERCLK to clock out f ractiona l
DS1/E1 payload data depending on the framer configura-
tion.
NOTE: Receive Fractional/Signaling interface can be
enabled by programming to bit 4 - RxFr1544/
RxFr2048 bit from reg ister 0xn122 to ‘1’.
RxCHN0_2/
RxCHN0
RxCHN1_2/
RxCHN1
RxCHN2_2/
RxCHN2
RxCHN3_2/
RxCHN3
RxCHN4_2/
RxCHN4
RxCHN5_2/
RxCHN5
RxCHN6_2/
RxCHN6
RxCHN7_2/
RxCHN7
C9
A15
C22
J23
AF26
AB17
AF12
AF4
D10
D13
F17
J19
W18
AB15
AB9
Y4
O 8 Receive Time Slot Octet Identifi er Ou tput-Bit 2
(RxCHNn_2) / Receive Time Slot Id enti fier Serial Out-
put (RxCHNn):
The exact functio n of these pins depends on whether or
not the re ceive framer enables the receive f ractional /sig-
nali ng int erface, as described below:
If receive fract ional/si gnalin g interface is di sabled -
RxCHNn_2:
These output pins (RxCHNn _4 thr ough RxCHNn_0)
refl ect the fiv e-bit binary value of the current t ime slot
being output by the receive serial inte rface. Syst em
equipment can use the RxCHCLKn to sample t he five out-
put pins of each channel to identify the time slot being out-
put on thes e pins. RxCHNn_2 indi cates Bit 2 of the ti me
slot channel being output.
If receive fract ional/signaling interface is enabled -
RxCHNn
These pi ns serially output the five-bit binary value of the
time sl ot being output by the recei ve serial i nterface.
NOTE: Receive Fractional/Signaling interface can be
enabled by programming to bit 4 - RxFr1544/
RxFr2048 bit from reg ister 0xn122 to ‘1’.
RECEIVE SYSTEM SIDE INTERFACE
SIGNAL NAME 420 PKG
BALL#484 PKG
BALL # TYPE OUTPUT
DRIVE (MA) DESCRIPTION
XRT86VL38
32
REV. V1.2.0 OCTAL T1/E1/J1 FRAM ER/LIU COMBO - H ARDWARE DESCRIPTION
RxCHN0_3/
Rx8KHZ0
RxCHN1_3/
Rx8KHZ1
RxCHN2_3/
Rx8KHZ2
RxCHN3_3/
Rx8KHZ3
RxCHN4_3/
Rx8KHZ4
RxCHN5_3/
Rx8KHZ5
RxCHN6_3/
Rx8KHZ6
RxCHN7_3/
Rx8KHZ7
C10
B16
C23
J26
AC23
AC17
AD12
AE5
E11
A15
D19
H21
AB22
V14
AB8
AA3
O 8 Receive Time Slot Octet Identifi er Ou tput-Bit 3
(RxCHNn_3) / Receive 8KHz Clock Output (Rx8KHZn):
The exact functio n of these pins depends on whether or
not the re ceive framer enables the receive f ractional /sig-
nali ng int erface, as described below:
If receive fract ional/si gnalin g interface is di sabled -
RxCHNn_3:
These output pins (RxCHNn _4 thr ough RxCHNn_0)
refl ect the fiv e-bit binary value of the current t ime slot
being output by the receive serial inte rface. Syst em
equipment can use the RxCHCLKn to sample t he five out-
put pins of each channel to identify the time slot being out-
put on thes e pins. RxCHNn_3 indi cates Bit 3 of the ti me
slot channel being output.
If receive fract ional/signaling interface is enabled -
Rx8KHZn:
These pins output a reference 8KHz clock signal derived
from the MCLKIN input.
NOTE: Receive Fractional/Signaling interface can be
enabled by programming to bit 4 - RxFr1544/
RxFr2048 bit from reg ister 0xn122 to ‘1’.
RxCHN0_4/
RxSCLK0
RxCHN1_4/
RxSCLK1
RxCHN2_4/
RxSCLK2
RxCHN3_4/
RxSCLK3
RxCHN4_4/
RxSCLK4
RxCHN5_4/
RxSCLK5
RxCHN6_4/
RxSCLK6
RxCHN7_4/
RxSCLK7
A10
C17
A26
K25
AB22
AD17
AF11
AF3
B10
F16
B21
J22
Y19
W14
AB7
W7
O 8 Receive Time Slot Octet Identifi er Ou tput-Bit 4
(RxCHNn_4) / Receive Recovered Line Clock Output
(RxSCLKn):
The exact functio n of these pins depends on whether or
not the re ceive framer enables the receive f ractional /sig-
nali ng int erface, as described below:
If receive fract ional/si gnalin g interface is di sabled -
RxCHNn_4:
These output pins (RxCHNn _4 thr ough RxCHNn_0)
refl ect the fiv e-bit binary value of the current t ime slot
being output by the receive serial inte rface. Syst em
equipment can use the RxCHCLKn to sample t he five out-
put pins of each channel to identify the time slot being out-
put on these pins. RxCHNn_4 indicates the Most
Signi fi cant Bit (MSB) of the time slot channel being out-
put.
If receive fract ional/signaling interface is enabled -
Receive Recovered Line Clock Output (RxSCLKn):
These pi ns output the recovered T1/E1 line clock
(1.544MHz in T1 mode and 2.048M Hz in E1 mode) for
each channel.
NOTE: Receive Fractional/Signaling interface can be
enabled by programming to bit 4 - RxFr1544/
RxFr2048 bit from reg ister 0xn122 to ‘1’.
RECEIVE SYSTEM SIDE INTERFACE
SIGNAL NAME 420 PKG
BALL#484 PKG
BALL # TYPE OUTPUT
DRIVE (MA) DESCRIPTION
XRT86VL38
33
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1.2.0
RxCHCLK0
RxCHCLK1
RxCHCLK2
RxCHCLK3
RxCHCLK4
RxCHCLK5
RxCHCLK6
RxCHCLK7
A8
A14
A24
F25
AB24
AE21
AE11
AF5
E10
E15
B20
G19
U18
AB19
AA8
Y5
O 8 Receive Channel Clock Output (RxCHCLKn):
The exact functio n of this pin depen ds on whether or not
the r eceive fram er ena ble s the recei ve fr action al/si gnali ng
interface to output fractional data, as described below.
If receive fract ional/si gnalin g interface is di sabled:
This pi n indi cates the boundary of each tim e slot of an
inbound DS1/E1 fr am e. In T1 mo de, each of t hese output
pins is a 192kHz clock which pulses "Hi gh" during the
LSB of each 24 time slot s. In E1 mode , each of these out-
put pins is a 256kHz clock which pulses "Hi gh" during the
LSB of each 32 time slots. System Equipment can use
this clock signal to sample the RxCHN0 through RxCHN4
time slot identifier pins to determine whi ch time slot is
being output.
If receive fract ional/signaling interface is enabled:
RxCHCLKn is the fractional interfa ce clock which ei ther
outputs a clock signal f or the time slot that has been con-
figur ed to output fr actional data, or output s an enable sig-
nal for the fr actional time slo t so th at fr actional data can
be clocked out of the device usin g the RxSERCLK pi n.
NOTE: Receive fractional interface can be enabled by
programming to bit 4 - RxFr1544/RxFr2048 bit
from regi ster 0xn122 to ‘1’.
RECEIVE SYSTEM SIDE INTERFACE
SIGNAL NAME 420 PKG
BALL#484 PKG
BALL # TYPE OUTPUT
DRIVE (MA) DESCRIPTION
XRT86VL38
34
REV. V1.2.0 OCTAL T1/E1/J1 FRAM ER/LIU COMBO - H ARDWARE DESCRIPTION
RECEIVE LINE INTERFACE
SIGNAL NAME 420 PKG
BALL#484 PKG
BALL # TYPE OUTPUT
DRIVE (MA) DESCRIPTION
RTIP0
RTIP1
RTIP2
RTIP3
RTIP4
RTIP5
RTIP6
RTIP7
D1
F1
H1
K1
M1
P1
T1
V1
G2
H2
K4
L2
M2
P3
T2
U4
I - Receive Positi ve Analog Input (RTIPn):
RTIP is t he positive diff erential input from the l ine inter-
face. This i nput pin, alo ng wit h the RRI NG input pin, func-
tions as the “Receive DS1/ E1 Line Signal” input for the
XRT86VL38 devic e.
The user is expected to connect thi s signal and the
RRING input signal to a 1:1 transformer for proper opera-
tion. The c ent er t ap of t he rece ive t ran sformer s hould h ave
a bypass capacitor of 0.1μF to ground (Chip Si de) to
improve long haul appl ication receive capabilities.
RRING0
RRING1
RRING2
RRING3
RRING4
RRING5
RRING6
RRING7
E1
G1
J1
L1
N1
R1
U1
W1
G3
H1
K3
L1
M1
P2
T3
U3
I - Receive Negative Anal og Input (RRINGn):
RRING is the negative dif ferenti al input from the l ine inter -
face. This input pin, along with the R TIP i nput pin, fun c-
tions as the “Receive DS1/ E1 Line Signal” input for the
XRT86VL38 devic e.
The user is expected to connect thi s signal and the RTIP
input signal to a 1:1 tr ansforme r for proper oper ation. The
center tap of the receive transformer should have a
bypass capacitor of 0.1μF to ground (Chip Side) to
improve long haul appl ication receive capabilities.
RxLOS_0
RxLOS_1
RxLOS_2
RxLOS_3
RxLOS_4
RxLOS_5
RxLOS_6
RxLOS_7
E8
A16
B20
H24
AC26
AF20
AC12
AD4
C8
C14
D16
F22
W21
W15
Y10
U8
O 4 Receive Loss of Signal Output Indicator (RLOSn):
The XRT86VL38 devic e wil l assert this out put pin (i.e.,
toggle i t “high”) anytime (and for the durat ion that) the
Receive DS1/ E1 Framer or LIU block declares the LOS
defect condition.
Conversel y, the XRT 86VL38 dev ice will nega te this outpu t
pin (i.e., toggl e it “l ow”) anytime (and for the duration that)
the Recei ve DS 1/E1 Framer or LI U block i s NOT declar ing
the LOS defect condition.
This outp ut pi n wil l toggle “High” (declar e LOS) if the
Receive Fr am er or the Receive LIU block associated with
Channel N determ ines that an RLOS condi ti on occurs. In
other wor ds, this pin is OR-ed with t he LIU RLOS and the
Framer RLOS bit . If eit her the LIU RLOS or the Frame r
RLOS bit associated with channel N pulses high, the cor-
respondi ng RLO S pin of that particul ar channel wil l be set
to “ High”.
XRT86VL38
35
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1.2.0
RxTSEL D5 C6 I - Receive Termin ation Control (RxTSEL):
Upon power up, the receivers are in "High" impedance.
Switching to internal termination can be selected through
the microprocessor interface by programming the appro-
priate channel register. However, to switch control to the
hardware pin, RxTCNTL must be programmed to "1" in the
appropriate global register (0x0FE2). Once control has
been granted to the hardware pin, it must be pulled "High"
to switch to interna l termination .
NOTE: Internally pulled "Low" with a 50kΩ resistor.
TRANSMIT LINE INTERF ACE
SIGNAL NAME 420 PKG
BALL#484 PKG
BALL # TYPE DESCRIPTION
TTIP0
TTIP1
TTIP2
TTIP3
TTIP4
TTIP5
TTIP6
TTIP7
F3
G3
J3
K3
M3
P3
T3
U3
F3
H4
J3
K1
M5
N2
R4
T1
OTran s m it P osi tive An alo g Ou tpu t (T TIP n ) :
TTIP is the positive di fferential output to the line interface. This out-
put pin, along with the co rr esponding TRING output pi n, function as
the Transm it DS1/E1 output si gnal driver s for the XRT86VL38
device.
The user is expected to connect thi s signal and the corresponding
TRING output signal to a 1:2 st ep up tr ansforme r for proper opera-
tion.
This out put pin will be tri-stated whenever the user set s the “TxON”
input pi n or register bit (0xnF02, bit 3) t o “0”.
NOTE: This pin should have a series line capacitor of 0.68
μ
F for DC
blocki ng purposes.
TRING0
TRING1
TRING2
TRING3
TRING4
TRING5
TRING6
TRING7
G4
H4
K4
L4
M4
P4
R4
U4
F1
J5
J1
L4
M3
P5
R2
U2
OTr ansmit Negative Analog Output (TRINGn):
TRING is the negative differential output to the line interface. This
output pin, along wit h the corresponding TTIP output pin, funct ion as
the Transm it DS1/E1 output si gnal driver s for the XRT86VL38
device.
The user is expected to connect thi s signal and the corresponding
TRING output signal to a 1:2 st ep up tr ansforme r for proper opera-
tion.
NOTE: This output pin will be tri-stated whenever the user sets the
“TxON” in put pin or register bit (0xnF02, bit 3) to “0”.
RECEIVE LINE INTERFACE
SIGNAL NAME 420 PKG
BALL#484 PKG
BALL # TYPE OUTPUT
DRIVE (MA) DESCRIPTION
RxTSEL (pin) Rx Termination
External
Internal
0
1
Note: RxTCNTL (bit) must be set to "1"
XRT86VL38
36
REV. V1.2.0 OCTAL T1/E1/ J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TxON Y3 W1 ITra nsmit ter On
This in put pi n permits the user to ei ther enable or di sable the Trans-
mit Outp ut Driver wit hin the Transmit DS1/E1 LI U Block. If the TxON
pin is pulled “Low”, all 8 Channels are tri-stated. When this pin is
pulled ‘High’, turning on or off the transmitters will be determined by
the appropriat e channel re gisters (address 0x0Fn2, bit 3)
LOW = Disables the T ransmi t Output Dr iver wit hin the Transmit DS1/
E1 LIU Block. In this setting, the TTIP a nd TRING output pins of all 8
channels will be tri-stated.
HIGH = Enabl es the Trans mit Output Dr iv er within the Transmi t DS1/
E1 LIU Block. In this setti ng, the correspond ing TTIP and T R ING out-
pu t pi ns w ill b e enabled or disabl ed by progra mming the appropriate
channel register. (address 0x0Fn2, bi t 3)
NOTE: Whenever the transmitters are turned off, the TTIP and
TRING output pins will be tri-stated.
TIMING INTERFACE
SIGNAL NAME 420 PKG
BALL#484 PKG
BALL # TYPE OUTPUT
DRIVE (MA) DESCRIPTION
MCLKIN A4 A5 I - Master Clock Input :
This pin is used to provi de the ti ming referenc e for the int er-
nal master clock of the device. The frequency of this clock
is programmable from 8kHz to 16.384MHz in register
0x0FE9.
E1MCLKnOUT B5 A4 O12 LIU E1 Output Clock Reference
This output pin is defaulted to 2.048MHz, but can be pro-
grammed to 4.096MHz, 8.192M Hz, or 16.384MHz in r egis-
ter 0x0FE4.
T1MCLKnOUT D6 F9 O12 LI U T1 Output Clock Refer ence
This out put pin is defau lt ed to 1.544MHz , but can be pro-
gramme d to ou tpu t 3.08 8MHz, 6. 176MHz, or 12 .352 MHz in
regis ter 0x0FE4.
E1OSCCLK Y5 V4 O 8 Framer E1 Output Clock Reference
This out put pin is defau lt ed to 2.048MHz , but can be pro-
gramme d to 65.536MHz in regi ster 0x011E.
T1OSCCLK AC1 V3 O 8 Framer T1 Output Clock Reference
This out put pin is defau lt ed to 1.544MHz , but can be pro-
grammed to output 49.408MHz in register 0x011E.
8KSYNC AB3 W2 O 8 8kHz Clock Output Re fer ence
This pi n is an out put reference of 8kHz based on the
MCLKIN input. Therefore, th e duty cycle of th is out put is
determined by the tim e period of the input clock ref erence.
TRANSMIT LINE INTERF ACE
SIGNAL NAME 420 PKG
BALL#484 PKG
BALL # TYPE DESCRIPTION
XRT86VL38
37
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWA RE DESCRIPTION REV. V1.2.0
8KEXTOSC AA2 U5 I - External Oscillator Select
For normal operation, this pin should not be used, o r pulled
“Low”.
This pin is internally pulled “Low” with a 50kΩ resi stor.
ANALOG C5 D4 OFactory Test Mode Pin
NOTE: For Internal Use Only
LOP AB1 V2 I - Loss of Power for E1 Only
This is a Loss of Power pin i n the E1 applica tion onl y. Upon
detecting LOP in E1 mode, the device will aut omatically
transmit the Sa5 and Sa6 bit t o a different pattern, so that
the Receive t erminal can detect a power failure in the net-
work.
Please see regist er 0xn131 for the T ransmit SA contr ol.
SENSE E6 E6 ONOTE: For Internal Use Only
TIMING INTERFACE
SIGNAL NAME 420 PKG
BALL#484 PKG
BALL # TYPE OUTPUT
DRIVE (MA) DESCRIPTION
XRT86VL38
38
REV. V1.2.0 OCTAL T1/E1/ J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
GPIO INTERFACE
SIGNAL NAME 420 PKG
BALL#484PKG
BALL # TYPE OUTPUT
DRIVE (MA) DESCRIPTION
GPIO1_3
GPIO1_2
GPIO1_1
GPIO1_0
B21
G22
AE24
AE22
A19
G18
AA20
AA18
I/O 8General Purpose Input/ Output Pins
Each of these pins can be configured to function as either
a general-purpose input or output pin. The exa ct functi on
of these pins depend on whet her these GPIO pins are
configured as input or outpu t pi ns as follows.
If GPIO1_n pi ns are configured as i nput pins:
The state of these input pins can be mo nitored by reading
the GPIO1_n Control Bits (Bit 3- 0) within the “G eneral Pur-
pose Input/Output 1 Control Regi ster (address 0x4102) .
If GPIO1_n pi ns are configured as out put pins:
The state of these output pins can be control led by writing
the appropriate value into th e GPIO 1_n Control Bits (Bit 3-
0) within t he “General Purpose Input/O utput 1 Control
Register (addr ess 0x4102).
Final ly, users can configure a given GPIO1_n pin to be an
input pi n by setting the corres ponding GPI O1_nDIR Bit
(fr om Bit 7- 4), wit hin the “General Purpose I nput/Output 1
Control Register (a ddress 0x41 02) to ‘0’.
Conversely, users can configure the GPIO1_ n pin to be
an output pin by sett ing t he corresponding GPI O1 _nDIR
Bit (from Bit 7-4), within the “General Purpose Input/Out-
put 1 Control Register (address 0x4102) to ‘1’.
GPIO0_3
GPIO0_2
GPIO0_1
GPIO0_0
AD20
AB18
AD13
AD11
U16
V15
Y11
AB6
I/O 8General Purpose Input/ Output Pins
Each of these pins can be configured to function as either
a general-purpose input or output pin. The exa ct functi on
of these pins depend on whet her these GPIO pins are
configured as input or outpu t pi ns as follows.
If GPIO0_n pi ns are configured as i nput pins:
The state of these input pins can be mo nitored by reading
the GPIO0_n Control Bits (Bit 3- 0) within the “G eneral Pur-
pose Input/Output 0 Control Regi ster (address 0x0102) .
If GPIO0_n pi ns are configured as out put pins:
The state of these output pins can be control led by writing
the appropriate value into th e GPIO 0_n Control Bits (Bit 3-
0) within t he “General Purpose Input/O utput 0 Control
Register (addr ess 0x0102).
Final ly, users can configure a given GPIO0_n pin to be an
input pi n by setting the corres ponding GPI O0_nDIR Bit
(fr om Bit 7- 4), wit hin the “General Purpose I nput/Output 0
Control Register (a ddress 0x01 02) to ‘0’.
Conversely, users can configure the GPIO0_ n pin to be
an output pin by sett ing t he corresponding GPI O0 _nDIR
Bit (from Bit 7-4), within the “General Purpose Input/Out-
put 0 Control Register (address 0x0102) to ‘1’.
XRT86VL38
39
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWA RE DESCRIPTION REV. V1.2.0
JTAG INTERFACE
The XRT86VL38 device’s JTAG features comply with the IEEE 1149.1 standard. Please refer to the ind ustry
specification for addit ional informat ion on boundary scan oper ations.
SIGNAL NAME 420 PKG
BALL#484PKG
BALL # TYPE OUTPUT
DRIVE (MA) DESCRIPTION
TCK A7 F10 I - Te st cl ock: Boundary Scan Test clock input:
The TCLK signal is the clock for the TAP controller, and it
generate s the boundary scan data register clocking. The
data on TMS and TDI is loaded on the posit ive edge of
TC K. Data is observed at TDO on the fal ling edge of TCK.
TMS A5 B6 I - Test Mode Select: Boundar y Scan Test Mode Select
input.
The TMS signal cont rols the transiti ons of the TAP con-
troller in conj uncti on with the rising edge of the te st clock
(TCK).
NOTE: For normal operation this pin must be pulled
’High’.
TDI D7 E9 I - Test Dat a In: Boundary Scan Test data in put
T he TDI si gnal is the ser ial test data input.
NOTE: This pin is inter nal ly pulled ’ high’.
TDO B6 D8 O 8 Test Data Out: Boundary Scan Test data output
T he TDO signal is the serial test data output.
TRST B7 A6 I - Test Reset Input :
The TRST signal (Active Low) asynchronously resets the
TAP con troller to the Test-Lo gic-Reset state.
NOTE: This pin is inter nal ly pulled ’ high’
TEST B11 E12 I - Factory Test Mode Pin
NOTE: This pin is internally pulled ’low’, and should be
pulled ’low’ fo r norma l oper at io n.
aTEST E7 C7 I - Factory Test Mode Pin
NOTE: This pin is internally pulled ’low’, and should be
pulled ’low’ fo r norma l oper at io n.
JTAG_Ring D4 C2 I - JT AG_Ring Test Pin
JTAG_Tip F5 E5 I - JT AG_Tip Test Pin
XRT86VL38
40
REV. V1.2.0 OCTAL T1/E1/ J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
MICROPROCESSOR INTERFACE
SIGNAL NAME 420 PKG
BALL#484PKG
BALL # TYPE OUTPUT
DRIVE (MA) DESCRIPTION
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
Y26
W24
T25
T26
P24
N25
N24
M25
T19
U20
P21
N18
M22
M20
M21
L21
I/O 8Bidirectional Microprocessor Data Bus
These pins are used to dri ve and receive dat a over th e bi-
directional data bus, whenever th e Microprocessor per-
forms READ or WRITE oper ations wi th the Microp rocesso r
Inter face of the XRT86VL38 device.
When DMA interface is enabled, these 8-bit bidirectional
data bus is also used by t he T1/E1 Framer or the ext ernal
DMA Controller for storing and retrieving information.
REQ0 AB26 U19 O 8 DMA Cycle Request Output—DMA Controller 0 (Write):
These output pins are use d to indicat e that DMA tr ansfer s
(Write) are requested by the T1/E1 Fr amer.
On the t ransmit side (i.e., To transmit data from external
DMA controller to HDLC buffer s wit hi n the XRT86VL38 ),
DMA transfers ar e only requested when the tr ansm it buffer
status bits i ndicate that there is space for a complete m es-
sage or cell.
The DMA Write cyc le start s by T1/E 1 Framer asserting th e
DMA Request (REQ0) ‘low’, then the exter nal DMA control-
ler s hould drive the DMA Acknowledge (ACK0) ‘low’ to indi-
cate that it is ready to start the transfer. The ex ternal DMA
controller should place new dat a on the Microprocess or
data bus each time the Write Signal is Strobed low if the
WR is confi gured as a W ri te Strobe. If WR is c onfi gured as
a direction signal, then the exter nal DMA controller would
place new data on the Microprocessor data bus each time
t h e R ead S i g nal (RD) is Strobed low.
The Framer asserts this outp ut pin (toggl es it "Low") when
at least one of t he Transmit HDLC buf fers are empty and
can receive one more HDLC message.
The Framer negat es thi s outpu t pin ( toggl es it “ High” ) when
the HDLC buffer can no longer receive another HDLC mes-
sage.
XRT86VL38
41
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWA RE DESCRIPTION REV. V1.2.0
REQ1 AA24 Y22 O 8 DMA Cycle Request Output—DMA Contr oller 1 (Read) :
These output pins are us ed to in dicate that DMA transfers
(Read) are requested by the T1/E1 Framer.
On the recei ve side (i.e ., To tr ansm it data f rom HDLC buff-
ers within t he XRT86VL38 to ex ter nal DMA Controller),
DMA transfers are onl y requested when the receive buffer
contains a comp lete message or cell .
The DMA Read cycle starts by T1/E1 Fram er asserti ng the
DMA Request (REQ1) ‘low’, then the exter nal DMA control-
ler s hould drive the DMA Acknowledge (ACK1) ‘low’ to indi-
cate that it is r eady to receive the data. The T1/E1 Framer
should pl ace new data on the Microprocessor data bus
each time t he Read Signal is S trobed low if the RD is co n-
figur ed as a Rea d S trob e. If RD is configured as a direction
signal , then t he T1/E1 Fr amer would place new data on the
Microprocessor data bus each time t he W rite Sign al (WR)
is Strobed low.
The Framer asserts this outp ut pin (toggl es it "Low") when
one of the Receive HDLC buffer contains a complete
HDLC message that needs to be read by the µC/µP.
The Framer negat es thi s outpu t pin ( toggl es it “ High” ) when
the Receive HDLC buffers are depleted.
INT R26 N22 O 8 Interrupt Request Output:
This act ive-low out put signal will be asserted when the
XRT86VL38 device is r equesting i nterrupt servi ce fr om the
Microprocessor. Thi s output pin should typically be con-
nected to the “Interrupt Request” input of the Microproces-
sor.
The Framer will assert this active "Low" output (toggles it
"Low"), to t he local µP, anytime it requires in terrupt service.
MICROPROCESSOR INTERFACE
SIGNAL NAME 420 PKG
BALL#484PKG
BALL # TYPE OUTPUT
DRIVE (MA) DESCRIPTION
XRT86VL38
42
REV. V1.2.0 OCTAL T1/E1/ J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
PCLK Y25 V22 I - Microprocessor Clock Input:
This clo ck input signal is onl y used if the Microprocessor
Inter face has been co nfi gured to operate in the Synchro-
nous Modes (e. g., Power PC 403 Mode). If the Micropro-
cessor In terfa ce is configur ed to operat e in this mode, then
it will use this clock signal to do t he fol lowing.
1. To sample the CS, WR/R/W, A[14:0], D[7:0], RD/DS
and DBEN input pins, and
2. To update the state of the D[7:0] and the RDY/
DTACK output signals.
NOTES:
1. The Microprocessor Interface can work with
PCLK frequencies ranging up to 33MHz.
2. This pin is inactive if the user has configured the
Microprocessor Interface to operate in either the
Intel-Asynchronous or the Motorola-
Asynchronous Modes. In this case, the user
should t ie this pin to GND.
When DMA interface is enabled, the PCLK inpu t pin i s also
used by the T1/E1 Framer to latch in or latch out re ceive or
output data respectively.
iADDR W22 R18 I - This Pin Must be Tied “Low” f or Normal Operation .
This pin is internall y pulled “High ” with a 50k
Ω
resistor.
fADDR AA26 T18 I - This Pi n Mu st be Ti ed “High” for Normal Operation.
This pin is internally pulled “Low” with a 50k
Ω
resistor.
PTYPE0
PTYPE1
PTYPE2
W23
W26
R25
V20
T20
N21
I - M icroprocessor Type Input:
These input pins permi t the user to specify which type of
Microprocessor/Microcontroller to be interfaced to the
XRT86VL38 device. The following table presents t he three
different microprocessor types that the XRT86VL38 sup-
ports.
NOTE: These pins are internally pulled “Low” with a 50k
Ω
resistor.
MICROPROCESSOR INTERFACE
SIGNAL NAME 420 PKG
BALL#484PKG
BALL # TYPE OUTPUT
DRIVE (MA) DESCRIPTION
0
1
1
μPType0
0
0
0
0
0
1
μPType1
μPType2
68H C11, 80 51, 80C1 88
MOTOROL A 68K
IBM POWER PC 403
MICROPROCESSOR
TYPE
XRT86VL38
43
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWA RE DESCRIPTION REV. V1.2.0
RDY V24 R19 O12 Ready/Data Transfer Acknowledge Output:
The exact behavior of thi s pin depends upon the type of
Microprocessor/Microcontroller the XRT86VL38 has been
configured to operate in, as defined by the PTYPE[ 2:0]
pins.
Intel Asynchronous M ode - RDY - Read y O u tp u t
T i s out put pin will functi on as t he “act i ve-low” READY out -
put.
During a REA D or WRIT E cycl e, the Microprocessor Int er-
face block will toggle t his out put pin to the logic low level,
ONLY when the Micr oprocessor Interface is rea dy to com-
plete or ter minate t he current RE AD or WRITE cycle. Once
the Microprocessor has determined that this input pin has
toggled to the logic “low” level, then it is now safe for it to
move on and exec ute the next READ or WRITE cycl e.
If (during a READ or WRITE cycle) the Microprocessor
Interface block is holding this outp ut pin at a logic “high”
level , th en the Microprocessor is expected to exte nd thi s
READ or WRITE cycle, unt il it detec ts this output pin b ein g
toggled to the logic low level.
Motorola Asynchronous M ode - DTACK - Data T ransf er
Acknowledge Output
T i s output pin will function as the “act i ve-low” DTACK out -
put.
During a REA D or WRIT E cycl e, the Microprocessor Int er-
face block will toggle t his out put pin to the logic low level,
ONLY when the Micr oprocessor Interface is rea dy to com-
plete or ter minate t he current RE AD or WRITE cycle. Once
the Microprocessor has determined that this input pin has
toggled to the logic “low” level, then it is now safe for it to
move on and exec ute the next READ or WRITE cycl e.
If (during a READ or WRITE cycle) the Microprocessor
Interface block is holding this outp ut pin at a logic “high”
level , th en the Microprocessor is expected to exte nd thi s
READ or WRITE cycle, unt il it detec ts this output pin b ein g
toggled to the logic low level.
MICROPROCESSOR INTERFACE
SIGNAL NAME 420 PKG
BALL#484PKG
BALL # TYPE OUTPUT
DRIVE (MA) DESCRIPTION
XRT86VL38
44
REV. V1.2.0 OCTAL T1/E1/ J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
RDY V24 R19 O12 (Con’t)
Power PC 403 Mode - RDY Ready Output:
This output pi n will function as the “act i ve-high” READY
output.
During a REA D or WRIT E cycl e, the Microprocessor Int er-
face blo ck wil l toggle this output pin to the logic high level,
ONLY when the Micr oprocessor Interface is ready to com-
plete or ter minate t he current RE AD or WRITE cycle. Once
the Microprocessor has sampled this signal being at the
logic “hi gh” level upon the risi ng edge of PCLK, then it is
now safe for it to move on and execute the next READ or
WRITE cycl e.
If (during a READ or WRITE cycle) the Microprocessor
Interface block is holding this outp ut pin at a logic “low”
level , th en the Microprocessor is expected to exte nd thi s
READ or WRITE cycle, until it samples this output pin
being at the log ic low lev el .
NOTE: The Microprocessor Interface will update the state
of this output pin upon the rising edge of PCLK.
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
V25
V26
U22
U23
U24
U25
U26
T22
T24
R23
R24
P22
P25
N23
N22
P18
N17
T21
T22
R20
R21
R22
P19
P20
N19
N20
M18
M19
L18
L22
I - Microprocessor Interface Addre ss Bus Input
These pins permit t he Microprocessor to identify on-chip
regis ters and Buffer/Memor y locati ons within the
XRT86VL38 device whenever it performs READ and
WRITE operations with the XRT86VL38 device.
NOTE: These pins are internally pulled “Low” with a 50k
Ω
resistor, except ADDR[8:14].
DBEN V23 U22 I - Data Bus Enable Input pin.
This act iv e-low in put pi n per mits the user to either enable
or tri-s t ate the Bi-Direc tional D ata Bus pins (D[7:0]), as
descri bed bel ow.
•Setting this input pin “low” enables the Bi-directional
Data bus.
•Setting this input pin “high” tri-states the Bi-directional
Data Bus.
MICROPROCESSOR INTERFACE
SIGNAL NAME 420 PKG
BALL#484PKG
BALL # TYPE OUTPUT
DRIVE (MA) DESCRIPTION
XRT86VL38
45
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWA RE DESCRIPTION REV. V1.2.0
ALE R22 P22 I - Address Latch Enable Input Addr ess Strobe
The exact behavior of thi s pin depends upon the type of
Microprocessor/Microcontroller the XRT86VL38 has been
configured to operate in, as defined by the PTYPE[ 2:0]
pins.
Intel-Asy nchronous Mode - ALE
This act iv e-hi gh i nput pin is used to latch th e a ddre ss
(present at the Microp rocessor Int erface Address Bus pins
(A[14: 0] ) in to the XR T86VL38 Micr oproces sor Int erf ace
block and t o indicate the start of a READ or WRITE cycl e.
Pulling t his input pin “ high” enables the input bus d rivers f or
the Address Bus input pins (A[14:0]). The contents of the
Address Bus wi ll be latched into the XR T86VL38 Micropro -
cessor Inter fa ce circui try, upon the falling edge of thi s inp ut
signal.
Motorola-Asynchronous (68K) Mode - AS
This act iv e-low in put pi n is used to latch the data resi di ng
on the Addres s Bus, A[ 14: 0] i nto the Micr opr ocessor I nt er-
face circuitry of the XRT86VL38 device.
Pulling t hi s input pin “low” enabl es the input bus dri ver s for
the Address Bus input pins. The contents of the Address
Bus will be latched into the Microprocessor Interface cir-
cuitry, upon the rising edge of this signal.
Power PC 403 Mode - No Function - Tie to GND:
This input pin has no r ole nor f unction an d should be tied t o
GND.
CS L26 K21 I - M icroprocessor Interface—Chip Select Input:
The user must assert this act ive low signa l in order to
select the Mic roprocessor Interfac e for READ and WRITE
operations between the Microp roc essor and th e
XRT8 6VL38 on-chip reg is ter s and buf fer/mem or y loca-
tions.
MICROPROCESSOR INTERFACE
SIGNAL NAME 420 PKG
BALL#484PKG
BALL # TYPE OUTPUT
DRIVE (MA) DESCRIPTION
XRT86VL38
46
REV. V1.2.0 OCTAL T1/E1/ J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
RD W25 U21 I - Microprocessor Interface—Read Strobe Input:
The exact behavior of thi s pin depends upon the type of
Micropr ocessor/Microcontroller the Framer has been con-
figured to operat e in , as defined by the PTYPE[ 2:0 ] pi ns.
Intel-Asy nchronous Mode - RD - READ Strobe Input:
This input pi n wil l funct i on as the RD (Active Low R ead
S t robe) input si gnal from the Microproces sor. Once t hi s
activ e-low si gnal is asserted, then the XRT86VL38 devi ce
will plac e the content s of th e addressed register (or buf fer
locat ion ) on the
Microprocessor Interface Bi-directional data bus (D[7:0]).
When this si gnal is neg ated, then the Data Bus will be tri-
stated.
Motorola-Asynchronous (68K) Mode - DS - Da ta
Strobe:
This input pi n wil l funct i on as the DS (Data S trobe) input
signal.
Power PC 4 03 Mode - WE - Wr ite Enable I nput :
This input pi n wil l funct i on as the WE (Write Enable) input
pin.
Anytime t he Microprocessor Int erf ace samples this active-
low input signal (along with CS and WR/R/W) also being
asserted (at a logic low level) upon the rising edge of
PCLK, then the Microprocessor Interf ace w ill (upon the
very same ri si ng edge of PCLK) latch the
content s on the Bi-Direc ti onal Data Bus (D[7: 0]) into the
“target” on-chip register or buffer location within the
XRT8 6VL38 device.
WR M23 L20 I - M icroprocessor Interface—Write Strobe Input
The exact behavior of thi s pin depends upon the type of
Microprocessor/Microcontroller the XRT86VL38 has been
configured to operate in, as defined by the PTYPE[ 2:0]
pins.
Intel-Asy nchronous Mode - WR - Write Strobe Input:
This input pi n func tions as the WR (Ac tive Low WR ITE
S t robe) input si gnal from the Microproces sor. Once t hi s
activ e-low signal is asserted, then the in put buff ers (associ-
ated with the Bi-Di rectiona l Dat a Bus pi n, D[7:0]) will be
enabled.
The Microprocessor Interfa ce will latch the co ntents on t he
Bi-Directional Data Bus (into the “ t arget” regist er or
address l ocat ion, within t he XRT86VL38) upon the risin g
edge of this in put pin.
Motorola-Asynchronous Mode - R/W - Read/Write
Operati on Identification I nput Pin:
This pin is fun ct ion all y equi valent to the “R/W” input pin. In
the Motorola M ode, a “READ” operatio n occurs i f thi s pin i s
held at a logic “1” , coinc ident to a f alling ed ge of the RD/ DS
(Data Strobe) input pin. Similarly a WRITE operation
occurs i f th is pin is at a logi c “0”, coinc ident to a fall ing edge
of the RD/ DS (Dat a Strobe) input pin.
MICROPROCESSOR INTERFACE
SIGNAL NAME 420 PKG
BALL#484PKG
BALL # TYPE OUTPUT
DRIVE (MA) DESCRIPTION
XRT86VL38
47
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWA RE DESCRIPTION REV. V1.2.0
WR M23 L20 I - (Con’t)
Power PC 403 Mode - R/W - Read/Write Operation Iden-
tification Input:
This input pi n will function as the “Read/Write Opera ti on
Identif ication Input ” pi n.
Anytime t he Microprocessor Int erf ace samples this input
signal at a logic "Hi gh" (while also sampling the CS in put
pin “Low” ) upon the risi ng edge of PCLK, then the Mi cro -
processor Int erf ace will (upon the ver y same rising ed ge of
PCLK) latch the content s of the Address Bus (A[14: 0] ) in to
the Microprocess or Interface circuitry , in prepara tion f or this
forthcoming READ operation. At some point (later in t his
READ operati on) the Microprocessor wi l l al so assert the
DBEN/OE input pin, and the Microprocessor Interface will
then plac e the con tents of the “t arget” re gis ter (or address
locat ion within t he XRT86VL38 device) upon the Bi-Di rec -
tional Data Bus pins (D[ 7: 0]) , where it can be read by the
Microprocessor.
Anytime t he Microprocessor Int erf ace samples this input
signal at a logic "Low" (while also sam pling the CS input
pin a logic “Low”) upon the rising edge of PCLK, then the
Micropr ocessor I nt erf ace wil l (u pon the ve ry same rising
edge of PCLK) latch the contents of the Address Bus
(A[14: 0] ) in to th e Microprocessor Inte rf ace ci rcuitr y, in
prepar ation for the for th com in g WRITE operation . At som e
point (later in this WRITE ope rat i on) t he Micr oproces sor
will also assert the RD/DS/WE input pin, and the Mic ropro-
cessor I nterface will then latch the conte nts of the Bi-Di rec-
tional Data Bus (D[7: 0]) into the content s of the “target ”
register or buffer locat ion (within the XRT86VL38).
MICROPROCESSOR INTERFACE
SIGNAL NAME 420 PKG
BALL#484PKG
BALL # TYPE OUTPUT
DRIVE (MA) DESCRIPTION
XRT86VL38
48
REV. V1.2.0 OCTAL T1/E1/ J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
ACK0
ACK1
Y23
Y24
W22
V21
I - DMA Cycle Acknow l edge In put— DM A Controll er 0
(Write):
The external D M A Controller will assert this i nput p in “Low”
when the fol lo w ing two condi tions are met :
1. After the DMA Controller, within the Framer has
assert ed (t oggl ed “Low”), the Re q_0 output sign al.
2. When the external DMA Controller is ready to
transfer data from external memory to the selected
Tr ansmit HDLC buffer.
At this point, the DMA tran sfer between the external mem-
ory and the selected Transmit HDLC buffer ma y begin.
After completion of the DMA cycle, the external DMA Con-
trolle r will negate this input pin af t er th e DMA Cont roller
within the Fr am er has negated the Req_0 outpu t pi n. The
external DMA Controller must do this in order to acknowl-
edge the end of the DMA cyc le.
DMA Cycle Acknowledge Input— DM A Controll er 1
(Read):
The extern al DMA Controller ass erts this inp ut pin “Low”
when the fol lo w ing two condi tions are met :
1. After the DMA Controller, within the Framer has
assert ed (t oggled "Low" ), the Req_1 output signal.
2. When the external DMA Controller is ready to
transfer data fr om the sele ct ed R ecei ve HDLC buffer
to external memory.
At this point, the DMA tran sfer between th e sele cte d
Receive HDLC buffer and the external mem ory may begin.
After completion of the DMA cycle, the external DMA Con-
trolle r will negate this input pin af t er th e DMA Cont roller
within the Fr am er has negated the Req_1 outpu t pi n. The
extern al DMA Co ntr ol le r will do this in order to acknowl-
edge the end of the DMA cyc le.
NOTE: This pin is internally pulled “High” with a 50k
Ω
resistor.
MICROPROCESSOR INTERFACE
SIGNAL NAME 420 PKG
BALL#484PKG
BALL # TYPE OUTPUT
DRIVE (MA) DESCRIPTION
XRT86VL38
49
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWA RE DESCRIPTION REV. V1.2.0
BLAST P23 M17 I - Last Cycle of Burst Indicator Input:
If the M icroproce ssor Interf ace is ope rating i n the In tel-I96 0
Mode, then th is input pin is used to ind ic ate (to the Micro-
processor Interface block) that the current data transfer is
the last data trans fer wit hin the cur rent burst operat i on.
The Micropr ocessor s hould asse rt this input pin (by tog-
gling it “Low”) in or der to denot e tha t the current READ or
WRITE operati on ( w ithin a BURST operatio n) is the last
operation of this BURST operation.
NOTES:
1. If the user has configured the Microprocessor
Interfac e to o pera te in t he Intel -Asy nchronou s, the
Motorola-Asynchronous or the Power PC 403
Mode, then he/she should tie this input pin to
GND.
2. This pin is internally pulled “High” with a 50k
Ω
resistor.
RESET Y4 Y1 I - Hardwar e Reset Input
Reset is an acti ve low input. If this pin i s pulled “ Low ” f or
more than 10μS, the device will be reset. When this occurs,
all o utpu t wi ll be ‘ tr i-sta ted’, and all i nternal regi sters will be
reset to their default values.
POWER SUPPLY PINS (3 .3 V)
SIGNAL NAME 420 PKG
BALL#484PKG
BALL # TYPE DESCRIPTION
VDD Y2
AC4
AC11
AE18
AD23
AA25
N26
F24
A25
C15
C8
G10
G12
G15
H17
L16
R17
T7
T9
T11
T13
T15
PWR F ram er Block Pow er Supply (I /O)
RVDD D2
F2
H2
K2
M2
P2
T2
V2
E1
H5
K6
L6
M7
N4
R5
T5
PWR Re ceiv er Anal og Power Suppl y for LIU Section
MICROPROCESSOR INTERFACE
SIGNAL NAME 420 PKG
BALL#484PKG
BALL # TYPE OUTPUT
DRIVE (MA) DESCRIPTION
XRT86VL38
50
REV. V1.2.0 OCTAL T1/E1/ J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TVDD F4
H3
J4
L3
N3
R3
T4
V3
F2
G1
J2
L3
M6
N1
R3
U1
PWR Transmi tter Anal og Power Suppl y for LIU Section
POWER SUPPLY PINS (1.8V)
SIGNAL NAME 420 PKG
BALL#484PKG
BALL # TYPE DESCRIPTION
VDD18 AD1
AD7
AF14
AB20
AC24
T23
J24
D24
E18
E12
G11
G14
G16
J17
P17
T8
T10
T12
T14
T17
PWR Framer Block Power Supply
DVDD18 A1 F5 PWR Digital Power Supp ly for LIU Section
AVDD18 B4 A2 PWR Analog Power Supply for LIU Section
VDDPLL18 D3
C2
B1
C1
B1
C1
D2
E3
PWR Analog Power Supply for PLL
POWER SUPPLY PINS (3 .3 V)
SIGNAL NAME 420 PKG
BALL#484PKG
BALL # TYPE DESCRIPTION
XRT86VL38
51
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWA RE DESCRIPTION REV. V1.2.0
GROUND PINS
SIGNAL NAME 420 PKG
BALL#484PKG
BALL # TYPE DESCRIPTION
VSS Y1
AA1
AE2
AD6
AD9
AF13
AC16
AB19
AC22
AB23
AA23
V22
P26
L23
H22
C25
B25
D20
B17
C13
D10
C06
F6
G6
G7
G8
G9
G13
H6
H7
H16
J7
J16
K7
K16
L7
M16
N6
N7
N16
P6
P7
P16
R6
R7
R16
T6
T16
U6
H8-H15
J8-J15
K8-K15
L8-L15
M8-M15
N8-N15
P8-P15
R8-R15
GND Fram er Block Ground
DGND A2 B5 GND Digital Ground for LIU Section
AGND A3 B3 GND Analog Ground for LIU Secti on
XRT86VL38
52
REV. V1.2.0 OCTAL T1/E1/ J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
RGND E2
G2
J2
L2
N2
R2
U2
W2
F4
H3
J4
K2
M4
N3
P1
T4
GND Receive r Analo g Ground for LIU Section
TGND H5
J5
K5
L5
M5
N5
R5
T5
G4
J6
K5
L5
N5
P4
R1
V1
GND Transmitter Anal og Ground for LIU Section
GNDPLL18 C3
E4
E3
B2
D3
E4
D1
E2
GND Analog Ground for PLL
GROUND PINS
SIGNAL NAME 420 PKG
BALL#484PKG
BALL # TYPE DESCRIPTION
XRT86VL38
53
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWA RE DESCRIPTION REV. V1.2.0
NO CONNECT PINS
SIGNAL NAME 420 PKG
BALL#484PKG
BALL # TYPE DESCRIPTION
NC B3
B18
B23
C4
D23
E5
E16
E19
E22
G5
N4
P5
U5
V4
V5
W3
W4
W5
AA3
AA4
AA5
AF1
A1
A3
A22
B2
C3
C4
C5
D5
D6
D7
E7
E8
F7
F8
G5
B4
F18
NC No Connection
XRT86VL38
54
REV. V1.2.0 OCTAL T1/E1/ J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
ELECT R ICAL CHARACTERISTICS
Absolute Maximums
Power Supply.....................................................................
VDDIO .. ................................................ -0.5V to +3.465V
VDDCORE...............................................-0.5V to +1. 890V
Powe r Rating STBGA and PBGA Package..... ............. 2.4
St orage Temperature ...............................-65°C to 150°C I nput Logic Sig nal Voltag e (Any Pi n) ... .... . .- 0. 5V to + 5.5V
Operati ng Te mperat ure Range..... ........ ....-40°C to 85°C ESD Protection (HBM)...........................................>2000V
Supply Voltage .... .... .......... .... GND-0.5V to +VDD + 0.5V Input C urr ent (Any Pi n) ... .. ........ .... ........ .... . .. .... .. + 100mA
DC ELECTRICAL CHARACTE RISTICS
Tes t Con ditions: TA = 25 ° C, VDDIO = 3.3V + 5% , VD DCORE = 1.8V + 5% unless otherwis e specified
SYMBOL PARAMETER MIN. TYP. MAX. UNITS CONDITIONS
ILL Dat a Bus T ri -Sta te Bus Leakage Current -10 +10 µA
VIL Input Low vol tage 0.8 V
VIH Input High Voltage 2.0 VDD V
VOL Output Low Voltage 0.0 0.4 V IOL = -1.6mA
VOH Output High Voltage TBD VDD V
IOC Open Drain Output Leakage Current µA
IIH Input High Voltage Current -10 10 µA VIH = VDD
IIL Input Low Voltage Current -10 10 µA VIL = G N D
XRT86VL38 P OWER CONSUMPTION
Test Conditions: TA = 25°C, VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5%, Internal termination, unless otherwise
specified
MODE IMPEDANCE MIN. TYP. MAX. UNITS CONDITIONS
T1 100Ω2.21 WQRSS Pattern with All 8
Channels on
E1 75Ω2.07 WQRSS Pattern with All 8
Channels on
E1 120Ω1.93 WQRSS Pattern with All 8
Channels on
XRT86VL38
55
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWA RE DESCRIPTION REV. V1.2.0
TABLE 4: E1 RECEIVER ELECTRICAL CHARACTERISTICS
VDDIO = 3.3V + 5% , V DD CORE = 1.8V + 5%, TA= -40° to 85°C, unless otherwise speci fied
PARAMETER MIN. TYP. MAX. UNIT TEST CONDITIONS
Receiver loss of signal:
Number of consecutive zeros before
RLOS is set
Input signal level at RLOS
RLOS De-asserted
15
12.5
32
20 dB
% ones
Cable attenuation @1024kHz
ITU-G.775, ETSI 300 233
R ece iv e r Sen s it iv ity
(Short Haul with cabl e l oss) 11 dB With nomi nal pul se amplitude of 3.0V
for 120Ω and 2.37V for 75Ω applica-
tion.
Receiver Sensi t ivi ty
(Long Haul wi th cable loss) 043 dB With nomi nal pul se amplitude of 3.0V
for 120Ω and 2.37V for 75Ω applica-
tion.
Input Impe dance 15 kΩ
Input Jitte r Tolerance:
1 Hz
10kHz-100kHz 37
0.3 UIpp
UIpp ITU G.823
Recove red Clock Jit ter
T r ansfer Corner Frequency
Peaking Ampl it ude -20 0.5 kHz
dB ITU G.736
Jitter Attenuator Corner Fre-
quency (-3dB curve) (JABW=0)
(JABW=1) -10
1.5 -Hz
Hz ITU G.736
Return Loss:
51kHz - 102kH z
102kHz - 2048kHz
2048kHz - 3072kHz
12
8
8
- - dB
dB
dB
ITU-G.703
XRT86VL38
56
REV. V1.2.0 OCTAL T1/E1/ J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TABLE 5: T1 RECEIVER ELECTRICAL CHARACTERISTICS
VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5%, TA=-40° to 85°C, unless other wise specified
PARAMETER MIN. TYP. MAX. UNIT TEST CONDITIONS
Receiver loss of signal:
Number of consecutiv e zeros before
RLOS is set
Input signal level at RLOS
RLOS Clea r
15
12.5
175
20
-
-
-
dB
% ones
Cable attenuation @772kHz
ITU-G.775, ETSI 300 233
Receiver Sensitivity
(Short Haul with cable loss) 12 -dB With n omina l pulse amp litude of 3.0V
for 1 00Ω term inatio n
Receiver Sensitivity
(Long Haul with cable loss)
Normal
Extended 0
0
-
36
45 dB
dB
With n omina l pulse amp litude of 3.0V
for 1 00Ω te rmin at io n
Input Impedance 15 -kΩ
Jitter Tol erance:
1Hz
10kHz - 100kHz 138
0.4 -
--
-UIpp AT&T Pub 62411
Recovered Clock Jitter
Transfer Corner Frequency
Peaking Amplitude -
-10 -
0.1 KHz
dB TR-TSY-000499
Jitter Attenuator Corner Frequency
(-3dB curve) - 6 Hz AT&T Pub 62411
Return Loss:
51kHz - 102kHz
102kH z - 2048k Hz
2048kH z - 3072kHz
-
-
-
14
20
16
-
-
-
dB
dB
dB
TABLE 6: E1 T RANSMITTER ELECTRICAL CHARACTERISTICS
VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5%, TA=-40° to 85°C, unless other wise specified
PARAMETER MIN. TYP. MAX. UNIT TEST CONDITIONS
AMI Output Pulse Ampl itude:
75Ω Application
120Ω Application 2.13
2.70 2.37
3.00 2.60
3.30 V
V
1:2 transformer
Output Pulse W id th 224 244 264 ns
Output Pulse W idth Ratio 0.95 -1.05 - ITU-G.703
Output Pulse Am pl itude Ratio 0.95 -1.05 - ITU -G.7 03
XRT86VL38
57
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWA RE DESCRIPTION REV. V1.2.0
Jitter Added by the Transm it t er Output -0.025 0.05 UIpp Broad Band wit h jit ter fr ee TCLK
appli ed to the input.
Output Return Loss:
51kHz -102kHz
102kHz-2048kHz
2048kHz-3072kHz
15
9
8
-
-
-
-
-
-
dB
dB
dB
ETSI 300 166
TABLE 7: E1 TRANSMIT RETURN LOSS REQUIREMENT
FREQUENCY RETURN LOSS
ETS 300166
51-102kHz 6dB
102-2048kHz 8dB
2048-3072kHz 8dB
TABLE 8: T1 TRANSMITTER ELECTRICAL CHARACTERISTICS
VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5%, TA=-40 ° to 85°C, unless otherwise speci fied
PARAMETER MIN. TYP. MAX. UNIT TEST CONDITIONS
AMI Output Pulse Ampl itude: 2.4 3.0 3.60 V1:2 transf ormer me asured at DSX-1.
Output Pulse W id th 338 350 362 ns ANSI T1.102
Output Pulse W idth Imbal ance - - 20 -ANSI T1.102
Output Pulse Am pl itude Imbal ance - - +200 mV ANSI T1.102
Jitter Added by the Transm it t er Output -0.025 0.05 UIpp Broad Band wit h jit ter fr ee TCLK
appli ed to the input.
Output Return Loss:
51kHz -102kHz
102kHz-2048kHz
2048kHz-3072kHz
-
-
-
17
12
10
-
-
-
dB
dB
dB
TABLE 6: E1 T RANSMITTER ELECTRICAL CHARACTERISTICS
VDDIO = 3.3V + 5% , VDDCORE = 1.8 V + 5%, TA=-40° to 85°C, unless other wise specifie d
PARAMETER MIN.TYP.MAX.UNIT TEST CONDITIONS
XRT86VL38
58
REV. V1.2.0 OCTAL T1/E1/ J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
FIGURE 2. ITU G.703 PULSE TEMPLATE
TABLE 9: TRANSMIT PULSE MASK SPECIFICATION
Test Load Imp edance 75Ω Resistive (Coax) 120Ω Resistiv e (t w ist ed Pair)
Nominal Peak Voltag e of a Mark 2.37V 3.0V
Peak voltage of a Space (no Mark) 0 + 0. 237V 0 + 0.3V
Nominal Pulse width 244ns 244ns
Ratio of Positive and Negati ve Pulses Imbala nce 0. 95 to 1.0 5 0.95 to 1.05
10% 10%
10%10%
10% 10%
269 ns
(244 + 25)
194 ns
(244–50)
244 ns
219 ns
(244 – 25)
488 ns
(244 + 244)
0%
50%
20%
V = 100%
Nominal puls
e
Note – V corresponds to the nominal peak value.
20%
20%
XRT86VL38
59
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWA RE DESCRIPTION REV. V1.2.0
FIGURE 3. DSX-1 PULSE TEMPLATE (NORMALIZED AMPLITUDE)
TABLE 10: DSX1 INTERFACE ISOLATED PULSE MASK AND CORNER POINTS
MINIMUM CURVE MAXIMUM CURVE
TIME (UI) NORMALIZED AMPLITUDE TIME (UI) NORMALIZED AMPLITUDE
-0.77 -.05V -0.77 .05V
-0.23 -.05V -0.39 .05V
-0.23 0.5V -0.27 .8V
-0.15 0.95V -0.27 1.15V
0.0 0.95V -0.12 1.15V
0.15 0.9V 0.0 1.05V
0.23 0.5V 0.27 1.05V
0.23 -0.45V 0.35 -0.07V
0.46 -0.45V 0.93 0.05V
0.66 -0.2V 1.16 0.05V
0.93 -0.05V
1.16 -0.05V
XRT86VL38
60
REV. V1.2.0 OCTAL T1/E1/ J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TABLE 11: AC ELECTRICAL CHARACTERISTICS
VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5%, TA=25°C, UNLESS OTHERWISE SPECIFIED
PARAMETER SYMBOL MIN. TYP. MAX. UNITS
MCLKIN Clock Duty Cycle 40 -60 %
MCLKI N Clock Toleranc e -±50 -ppm
XRT86VL38
61
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWA RE DESCRIPTION REV. V1.2.0
ORDERING INFORMATION
PRODUCT NUMBER PACKAGE OPERATING TEMPERATURE RANGE
XRT86VL38IB 420 Plastic Ball Grid Array -40°C to +85 °C
XRT86VL38IB484 484 Shrink Thin Ball Grid Array -40°C to +85 °C
PACKAGE DIMENSIONS FOR 420 PLAS TIC BALL GRID ARRAY
SYMBOL MIN MAX MIN MAX
A 0.085 0.098 2.16 2.50
A1 0.020 0.028 0.50 0.70
A2 0.020 0.024 0.51 0.61
A3 0.045 0.047 1.15 1.19
D 1.370 1.386 34.80 35.20
D1 1.2500 BSC 31.75 BSC
E 1.370 1.386 34.80 35.20
E1 1.2500 BSC 31.75 BSC
b 0.024 0.035 0.60 0.90
e 0.0500 BSC 1.27 TYP.
INCHES
MILLIMETERS
Note: The control dimens ion is in millim eter.
E
420 Plastic Ball G rid Array
(35.0 mm x 35.0 mm , PBGA)
R ev. 1.0 0
XRT86VL38
62
REV. V1.2.0 OCTAL T1/E1/ J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
PACKAGE DIMENSIONS FOR 484 SHRINK THIN BA LL GRID ARRAY
4
E
484 Shrink Thin Ball Grid Ar ray
(23.0 mm x 23 .0 mm, STBGA)
Rev. 1.00
SYMBOL MIN MAX MIN MAX
A 0.071 0.082 1.80 2.08
A1 0.019 0.022 0.47 0.57
A2 0.019 0.022 0.48 0.56
A3 0.033 0.037 0.85 0.95
D 0.898 0.913 22.80 23.20
D1 0.8268 BSC 21.00 BSC
E 0.898 0.913 22.80 23.20
E1 0.8268 BSC 21.00 BSC
b 0.024 0.028 0.60 0.70
e 0.0394 BSC 1.00 BSC
INCHES
MILLIMETERS
Note: Th e control dimension is i n mil lim eter.
63
NOTICE
EXAR Corporation r es erv es t he right to m ak e c hanges to the produc ts c ontained in t his publication in or der t o
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and m ay vary depen ding upon a user’s specif ic applicat ion. Whi le the informat ion in this publi cation
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected t o cause failure of the life support system or
to significantly affect its safety or eff ectiveness. Products are not authorized for use in such applications unless
EXAR Corp oration r eceives, in writing, assurances to its sat isfaction that: (a) the risk of i njury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the ci rcums tances.
Copyright 2007 E XAR Corpor at ion
Datasheet January 2007.
Reproduct ion, in part or whole, wit hout the prior written c ons ent of EXAR Corpor at ion is prohibit ed.
XRT86VL38
REV. V1.2.0 OCTAL T1/E1/ J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
P4.
REV I SION H IST O R Y
REVISION # DATE DESCRIPTION
V1.2.0 January 29, 2007 Relea sed to production.
