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e2v semiconductors SAS 2014
EV12DS130AZP
EV12DS130BZP
Low Power 12-bit 3 Gsps Digital to Analog
Converter with 4/2:1 Multiplexer
Datasheet
Main Features
•12-bit Resolution
•3 Gsps Guaranteed Conversion Rate
•7 GHz Analog Output Bandwidth
•4:1 or 2:1 integrated Parallel MUX (Selectable)
•Selectable Output Modes for performance optimization:
Return to Zero, Non Return to Zero, Narrow Return to Zero, RF
•Low Latency Time: 3.5 Clock Cycles
•1.4 Watt Power Dissipation in MUX 4:1 Mode
•Functions
– Selectable MUX Ratio 4:1 (Full Speed), 2:1 (Half Speed)
– Triple Majority Voting
– User-friendly Functions:
- Gain Adjustment
- Input Data Check Bit (FPGA Timing Check)
- Setup Time and Hold Time Violation Flags (STVF, HTVF)
- Clock Phase Shift Select for Synchronization with DSP (PSS[2:0])
- Output Clock Division Selection (Possibility to Change the Division Ratio of the DSP Clock)
- Input Under Clocking Mode
- Diode for Die junction Temperature Monitoring
•LVDS Differential Data input and DSP Clock Output
•Analog Output Swing: 1Vpp Differential (100 Differential Impedance)
•External Reset for Synchronization of Multiple MuxDACs
•Power Supplies: 3.3 V (Digital), 3.3V & 5.0V (Analog)
•FpBGA Package (15 × 15 mm Body Size, 1 mm Pitch)
Performances
Broadband: NPR at –14 dB Loading Factor, (See Section 7.2.7 ”NPR Performance” on page 57)
•1st Nyquist (NRTZ): NPR = 51.3 dB 10.0 Bit Equivalent at Fs = 3 Gsps
•1st Nyquist (NRTZ): NPR = 55.7 dB 10.8 Bit Equivalent at Fs = 1.5 Gsps
•2nd Nyquist (NRTZ or RTZ): NPR = 44.6 dB 8.9 Bit Equivalent at Fs = 3 Gsps
•3rd Nyquist (RF): NPR = 42.5 dB 8.6 Bit Equivalent at Fs = 3 Gsps
Single Tone: (see Section 5. ”Functional Description” on page 16)
•Performances Characterized for Fout from 100 MHz to 4500 MHz and from 2 Gsps to 3.2 Gsps
•Performance Industrially Screened Over 3 Nyquist Zones at 3 Gsps for Selected Fout.
Step Response
•Full Scale Rise /Fall Time 50 ps
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Applications
•Direct Digital Synthesis for Broadband Applications (L-S and Lower C Band)
•Automatic Test Equipment (ATE)
•Arbitrary Waveform Generators
•Radar Waveform Signal Synthesis
•DOCSIS V3.0 Systems
1. Block Diagram
Figure 1-1. Simplified Block Diagram
2. Description
The EV12DS130A/B is a 12-bit 3 Gsps DAC with an integrated 4:1 or 2:1 multiplexer, allowing easy
interface with standard LVDS FPGAs thanks to user friendly features as OCDS, PSS.
It embeds different output modes (RTZ, NRZ, narrow RTZ, RF) that allow performance optimizations
depending on the working Nyquist zone.
The Noise Power Ratio (NPR) performance, over more than 900 MHz instantaneous bandwidth, and the
high linearity (SFDR, IMD) over full 1st Nyquist zone at 3 Gsps (NRZ feature), make this product well
suited for high-end applications such as arbitrary waveform generators and broadband DDS systems.
1st
M/S
2:1 or
4:1
MUX
2nd M/S
DAC
Core
(NRZ,
NRTZ,
RTZ,
RF)
DSP CLOCK
PHASE SHIFT
CLOCK
DIV/X
CLOCK
BUFFER
PSS[2:0]
DSP
DSPN
24
2
24
24
24
2
CLK, CLKN
Port Select
24 2
Latches Latches
MODE
[1:0]
MUX
STVF
HTVF
SYNC,
SYNCN
FPGA
GA
A
B
C
D
24
24
24
24
OUT,
OUTN
DIODE
4 data
ports (12-
bit
differential)
IDC_P
IDC_N
OCDS[1:0]
FPGA
TIMING
2
2
3
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3. Electrical Characteristics
3.1 Absolute Maximum Ratings
Notes: 1. Absolute maximum ratings are limiting values (referenced to GND = 0V), to be applied individually, while other parameters
are within specified operating conditions. Long exposure to maximum rating may affect device reliability.
2. All integrated circuits have to be handled with appropriate care to avoid damages due to ESD. Damage caused by
inappropriate handling or storage could range from performance degradation to complete failure.
3. Maximum ratings enable active inputs with DAC powered off.
4. Maximum ratings enable floating inputs with DAC powered on.
5. DSP clock and STVF, HTVF output buffers must not be shorted to ground nor positive power supply.
Table 3-1. Absolute Maximum Ratings
Parameter Symbol Value Unit
Positive Analog supply voltage VCCA5 6.0 V
Positive Analog supply voltage VCCA3 4.0 V
Positive Digital supply voltage VCCD 4.0 V
Digital inputs (on each single-ended input) and IDC, SYNC, signal
Port P = A, B, C, D [P0..P11],
[P0N.. P11N]
IDC_P, IDC_N
SYNC, SYNCN
VIL
VIH
Digital Input maximum Differential mode swing
GND–0.3
VCCA3
2.0
V
V
Vpp
Master clock input (on each single-ended input)
VIL
VIH
Master Clock Maximum Differential mode swing
CLK, CLKN 1.5
3.5
2.5
V
V
Vpp
Control functions inputs
VIL
VIH
MUX,
MODE[0..1],
PSS[0..2],
OCDS[0..1]
–0.4V
VCCD + 0.4
V
V
Gain Adjustment function GA –0.3V, VCCA3 + 0.3 V
Maximum Junction Temperature Tj 170 °C
Storage Temperature Tstg –65 to 150 °C
Electrostatic discharge immunity
ESD Classification
ESD HBM 1000
Class 1B
V
4
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3.2 Recommended Conditions of Use
Notes: 1. For low temperature it is recommended to operate at maximum analog supplies (VCCA3) level.
2. The rise time of any power supplies (VCCD, VCCA5, VCCA3) shall be <10ms.
For EV12DS130A, in order to obtain the guaranteed performances and functionality, the following rules shall be followed
when powering the devices (See Section 8.9 ”Power Up Sequencing” on page 70)
For EV12DS130B, no specific power up sequence nor power supplies relationships are required.
3. Analog output is in differential. Single-ended operation is not recommended. Guaranteed performance is only in differential
configuration.
4. No power-down sequencing is required.
Table 3-2. Recommended Conditions of Use
Parameter Symbol Comments Recommended Value Unit Note
Positive analog supply voltage VCCA5 5.0 V (2)(4)
Positive analog supply voltage VCCA3 3.3 V (1)(2)(4)
Positive digital supply voltage VCCD 3.3 V (2)(4)
Digital inputs (on each single-ended input)
and IDC, SYNC, signal
Port P = A, B, C, D
VIL
VIH
Differential mode swing
[P0..P11],
[P0N.. P11N]
IDC_P, IDC_N
SYNC, SYNCN
1.075
1.425
700
V
V
mVpp
(3)
Master clock input power level
(Differential mode) PCLK 3dBm
(3)
Control functions inputs MUX, OCDS,
PSS, MODE, PSS
VIL
VIH
0
VCCD
V
V
Gain Adjustment function GA Range 0
VCCA3
V
Operating Temperature Range Tc Tj
Commercial “C”
grade
Industrial “V” grade
Tc > 0°C / Tj < 90°C
Tc > –40°C / Tj < 110°C °C
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3.3 Electrical Characteristics
Values in the tables below are based on our conditions of measurement in room temperature for typical
power supply (VCCA5 = 5.0V, VCCA3 =3.3V, V
CCD = 3.3V), typical swing and in MUX4:1 otherwise
specified.
Table 3-3. Electrical Characteristics
Parameter Symbol Min Typ Max Unit Note
Test
Level(2)
RESOLUTION 12 bit
POWER REQUIREMENTS
Power Supply voltage
- Analog
- Analog
- Digital
VCCA5
VCCA3
VCCD
4.75
3.15
3.15
5
3.3
3.3
5.25
3.45
3.45
V
V
(7)(8) 1
Power Supply current (4:1 MUX)
- Analog
- Analog
- Digital
ICCA5
ICCA3
ICCD
84
106
187
90
122
205
mA
mA
mA
1
Power Supply current (2:1 MUX)
- Analog
- Analog
- Digital
ICCA5
ICCA3
ICCD
84
106
160
90
122
177
mA
mA
mA
1
Power dissipation (4:1 MUX) PD 1.4 1.6 W 1
Power dissipation (2:1 DMUX) PD 1.3 1.5 W 1
DIGITAL DATA INPUTS, SYNC and IDC INPUTS
Logic compatibility LVDS
Digital input voltages:
- Differential input voltage
- Common mode
VID
VICM
100 350
1.25
500 mVp
V
1
1
Input capacitance from each single input to ground 2 pF 5
Differential Input resistance 80 100 120 1
CLOCK INPUTS
Input voltages (Differential operation swing) 0.56 1 2.24 Vpp 4
Power level (Differential operation) –4 1 8 dBm (1) 4
Common mode 2.4 2.5 2.6 V
Input capacitance from each single input to ground
(at die level) 2 pF 5
Differential Input resistance: 80 100 120 1
DSP CLOCK OUTPUT
Logic compatibility LVDS
Digital output voltages:
- Differential output voltage
- Common mode
VOD
VOCM
240 350
1.3
450 mVp
V 1
6
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Notes: 1. For use in higher Nyquist zone, it is recommended to use higher power clock within the limit.
2. See Section 3.6 on page 13 for explanation of test levels.
3. Initial gain error corresponds to the deviation of the DC gain center value from unity gain. The DC gain adjustment (GA
function) ensures that the initial gain deviation can be cancelled.
The DC gain sensitivity to power supplies is given according the rule:
GainSensVsSupply = |Gain@VccMin – Gain@VccMax| / Gain@Vccnom
4. Single-ended operation is not recommended, this line is given for better understanding of what is output by the DAC.
5. In order to modify the VOL/VOH value, potential divider could be used.
6. Sink or source.
ANALOG OUTPUT
Full-scale Differential output voltage
(100 differentially terminated) 0.92 1 1.08 Vpp 1
Full-scale output power (differential output) 0.25 1 1.64 dBm 1
Single-ended mid-scale output voltage (50 terminated) VCCA5 – 0.43 V (4)
Output capacitance 1.5 pF 5
Output internal differential resistance 90 100 110 1
Output VSWR (using e2v evaluation board)
1.5 GHz
3 GHz
4.5 GHz
1.17
1.54
1.64
4
Output bandwidth 7GHz4
FUNCTIONS
Digital functions: MODE, OCDS, PSS, MUX
- Logic 0
- Logic 1
VIL
VIH
IIN
1.6
0
VCCD
0.8
150
V
V
µA (6)
1
Gain Adjustment function GA 0
VCCA3
1
Digital output function (HTVF, STVF)
Logic 0
Logic 1
VOL
VOH
IO
–
2.3
–
–
0.8
80
V
V
µA
(5)
(6)
1
DC ACCURACY
Differential Non-Linearity DNL+ 0.5 0.95 LSB 1
Differential Non-Linearity DNL- –0.95 –0.5 LSB 1
Integral Non-Linearity INL+ 1 3 LSB 1
Integral Non-Linearity INL- –3 –0.8 LSB 1
DC gain:
- Initial gain error
- DC gain adjustment
- DC gain sensitivity to power supplies
- DC gain drift over temperature
–8 0
±11
±2
+8
+6
%
%
%
%
(3)
1
1
1
4
Table 3-3. Electrical Characteristics (Continued)
Parameter Symbol Min Typ Max Unit Note
Test
Level(2)
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EV12DS130BZP
7. Only for EV12DS130A dependency between power supplies:
Within the applicable power supplies range, the following relationship shall always be satisfied VCCA3 VCCD, taking into
account AGND and DGND planes are merged and power supplies accuracy.
8. Please refer Section 8.9 ”Power Up Sequencing” on page 70.
3.4 AC Electrical Characteristics
Values in the tables below are based on our conditions of measurement in room temperature for typical
power supply (VCCA5 = 5.0V, VCCA3 =3.3V, V
CCD = 3.3V), typical swing and in MUX4:1 otherwise
specified.
Notes: 1. See Section 3.6 on page 13 for explanation of test levels.
2. Figures in tables are derived from industrial screening; for practical reasons (necessity to cover also 2nd and 3rd Nyquist
Zones) the balun used for industrial test is not optimum for first Nyquist performances, and results when Fout or folded low
order hamonics are between DC to 400 MHz are very pessimistic. For further details please refer to Section 7.2 on page 38
for effect of the balun on performances.
Table 3-4. AC Electrical Characteristics NRZ Mode (First Nyquist Zone)
Parameter Symbol Min Typ Max Unit Note Test level(1)
Single-tone Spurious Free Dynamic Range
First Nyquist MUX 4:1
Fs = 3 Gsps @ Fout = 100 MHz 0 dBFS
Fs = 3 Gsps @ Fout = 400 MHz 0 dBFS
Fs = 3 Gsps @ Fout = 100 MHz –3 dBFS
|SFDR| 59 68
63
70
dBc 1
4
4
Highest spur level
First Nyquist MUX 4:1
Fs = 3 Gsps @ Fout = 100 MHz 0 dBFS
Fs = 3 Gsps @ Fout = 400 MHz 0 dBFS
Fs = 3 Gsps @ Fout = 100 MHz –3 dBFS
–68
–59
–72
–58
dBm
1
4
4
SFDR sensitivity & high spur level variation over temperature ±2 dB 4
SFDR sensitivity & high spur level variation over power supplies ±2 dB 4
Signal independent Spur (clock-related spur)
Fc/2 –82 dBm 4
Fc/4 –85 dBm 4
Noise Power Ratio
–14 dBFS peak to rms loading factor
Fs = 3 Gsps
20 MHz to 900 MHz broadband pattern
25 MHz notch centered on 450 MHz
NPR 46 dB (2) 4
Equivalent ENOB
Computed from NPR figure at 3 GSps ENOB 9.2 Bit 4
Signal to Noise Ratio
Computed from NPR figure at 3 GSps SNR 57 dB 4
DAC self noise density at constant code 0 or 4095 –163 dBm/Hz 4
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e2v semiconductors SAS 2014
Table 3-5. AC Electrical Characteristics NRTZ Mode (First & Second Nyquist Zone)
Parameter Symbol Min Typ Max Unit Note Test level(1)
Single-tone Spurious Free Dynamic Range
MUX4:1
Fs = 3 Gsps @ Fout = 100 MHz 0 dBFS
Fs = 3 Gsps @ Fout = 700 MHz 0 dBFS
Fs = 3 Gsps @ Fout = 1800 MHz 0 dBFS
Fs = 3 Gsps @ Fout = 700 MHz –3 dBFS
MUX2:1
Fs = 1.5 Gsps @ Fout = 700 MHz 0 dBFS
|SFDR| 54
53
68
62
61
66
65
dBc
4
4
1
4
1
Highest spur level
MUX4:1
Fs = 3 Gsps @ Fout = 100 MHz 0 dBFS
Fs = 3 Gsps @ Fout = 700 MHz 0 dBFS
Fs = 3 Gsps @ Fout = 1800 MHz 0 dBFS
Fs = 3 Gsps @ Fout = 700 MHz –3 dBFS
MUX2:1
Fs = 1.5 Gsps @ Fout = 700 MHz 0 dBFS
–70
–64
–67
–70
–68
–59
–55
dBm
4
4
1
4
1
SFDR sensitivity & high spur level variation over temperature ±2 dB 4
SFDR sensitivity & high spur level variation over power supplies ±2 dB 4
Signal independent Spur (clock-related spur)
Fc –29 dBm 4
Fc/2 –80 dBm 4
Fc/4 < –80 dBm 4
DAC self noise density at constant code 0 or 4095 –149 –144 dBm/Hz 1
Noise Power Ratio
–14 dBFS peak to rms loading factor
Fs = 3 Gsps
20 MHz to 900 MHz broadband pattern,
25 MHz notch centered on 450 MHz
NPR 46 50.2 dB (2) 1
Equivalent ENOB
Computed from NPR figure at 3 GSps ENOB 9.2 9.9 Bit (2) 1
Signal to Noise Ratio
Computed from NPR figure at 3 GSps SNR 57 61.2 dB (2) 1
Noise Power Ratio
–14 dBFS peak to rms loading factor
Fs = 1.5 Gsps
10 MHz to 450 MHz broadband pattern,
12.5 MHz notch centered on 225 MHz
NPR 55.7 dB (2) 4
Equivalent ENOB
Computed from NPR figure at 1.5 GSps ENOB 10.8 Bit (2) 4
Signal to Noise Ratio
Computed from NPR figure at 1.5 GSps SNR 66.7 dB (2) 4
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EV12DS130BZP
Notes: 1. See Section 3.6 on page 13 for explanation of test levels.
2. Figures in tables are derived from industrial screening; for practical reasons (necessity to cover also 2nd and 3rd Nyquist
Zones) the balun used for industrial test is not optimum for first Nyquist performances, and results when Fout or folded low
order hamonics are between DC to 400 MHz are very pessimistic. For further details please refer to Section 7.2 on page 38
for effect of the balun on performances.
Notes: 1. See Section 3.6 on page 13 for explanation of test levels.
2. Please refer to Section 7.2 ”AC Performances” on page 38 to have detailed characterization results.
Table 3-6. AC Electrical Characteristics RTZ Mode (Second Nyquist Zone)
Parameter Symbol Min Typ Max Unit Note Test level(1)
Single-tone Spurious Free Dynamic Range
MUX4:1
Fs = 3 Gsps @ Fout = 1600 MHz 0 dBFS
Fs = 3 Gsps @ Fout = 2900 MHz 0 dBFS
|SFDR|
50 60
57
dBc
1
4
Highest spur level
MUX4:1
Fs = 3 Gsps @ Fout = 1600 MHz 0 dBFS
Fs = 3 Gsps @ Fout = 2900 MHz 0 dBFS
–67
–66
–58 dBm 1
4
SFDR sensitivity & high spur level variation over
temperature ±2 dB 4
SFDR sensitivity & high spur level variation over power
supplies ±2 dB 4
Signal independent Spur (clock-related spur)
Fc –25 dBm 4
Fc/2 –80 dBm 4
Fc/4 < –80 dBm 4
DAC self noise density at constant code 0 or 4095 –143 dBm/Hz 4
Noise Power Ratio
–14 dBFS peak to rms loading factor
Fs = 3 Gsps
1520 MHz to 2200 MHz broadband pattern,
25 MHz notch centered on 1850 MHz
NPR 40 44.0 dB (2) 1
Equivalent ENOB
Computed from NPR figure at 3 GSps ENOB 8.2 8.8 Bit (2) 1
Signal to Noise Ratio
Computed from NPR figure at 3 GSps SNR 51 55.0 dB (2) 1
10
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e2v semiconductors SAS 2014
Table 3-7. AC Electrical Characteristics RF Mode (Second and Third Nyquist Zones)
Parameter Symbol Min Typ Max Unit Note Test level(1)
Single-tone Spurious Free Dynamic Range
2nd Nyquist
Fs = 3 Gsps @ Fout = 1600 MHz 0 dBFS
Fs = 3 Gsps @ Fout = 2900 MHz 0 dBFS
3rd Nyquist
Fs = 3 Gsps @ Fout = 3800 MHz 0 dBFS
Fs = 3 Gsps @ Fout = 4400 MHz 0 dBFS
|SFDR|
47
52
60
53
54
dBc
(2)
4
4
4
1
Highest spur level
2nd Nyquist
Fs = 3 Gsps @ Fout =1600 MHz 0 dBFS
Fs = 3 Gsps @ Fout = 2900 MHz 0 dBFS
3rd Nyquist
Fs = 3 Gsps @ Fout = 4400 MHz 0 dBFS
–58
–58
–62 –57
dBm
4
4
1
SFDR sensitivity & high spur level variation over
temperature ±2 dB 4
SFDR sensitivity & high spur level variation over power
supplies ±2 dB 4
Signal independent Spur (clock-related spur)
Fc –28 dBm 4
Fc/2 –80 dBm 4
Fc/4 < –80 dBm 4
DAC self noise density at constant code 0 or 4095 –141 dBm/Hz 4
Noise Power Ratio (2nd Nyquist)
–14 dBFS peak to rms loading factor
Fs = 3 Gsps
1520 MHz to 2200 MHz broadband pattern,
25 MHz notch centered on 1850 MHz
NPR 42 dB (2) 4
Equivalent ENOB
Computed from NPR figure at 3 GSps ENOB 8.5 Bit (2) 4
Signal to Noise Ratio
Computed from NPR figure at 3 GSps SNR 53 dB (2) 4
Noise Power Ratio
–14 dBFS peak to rms loading factor
Fs = 3 Gsps
2200 MHz to 2880 MHz broadband pattern,
25 MHz notch centered on 2550 MHz
NPR 42 dB (2) 4
Equivalent ENOB
Computed from NPR figure at 3 GSps ENOB 8.5 Bit (2) 4
Signal to Noise Ratio
Computed from NPR figure at 3 GSps SNR 53 dB (2) 4
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Notes: 1. See Section 3.6 on page 13 for explanation of test levels.
2. Figures in tables are derived from industrial screening without any correction to take in account the balun effect, but for
practical reasons (necessity to cover also 2nd and 3rd Nyquist Zones) the balun used for industrial test is not optimum for
first Nyquist performances, and results when Fout or folded low order hamonics are between DC to 400 MHz are very
pessimistic.
3.5 Timing Characteristics and Switching Performances
Noise Power Ratio
–14 dBFS peak to rms loading factor
Fs = 3 Gsps
3050 MHz to 3700 MHz broadband pattern,
25 MHz notch centered on 3375 MHz
NPR 39 40 dB (2) 1
Equivalent ENOB
Computed from NPR figure at 3 GSps ENOB 8 8.2 Bit (2) 1
Signal to Noise Ratio
Computed from NPR figure at 3 GSps SNR 50 51 dB (2) 1
Table 3-7. AC Electrical Characteristics RF Mode (Second and Third Nyquist Zones) (Continued)
Parameter Symbol Min Typ Max Unit Note Test level(1)
Table 3-8. Timing Characteristics and Switching Performances
Parameter Symbol Min Typ Max Unit Note
Test
level(1)
SWITCHING PERFORMANCE AND CHARACTERISTICS
Operating clock frequency
4:1 MUX mode
2:1 MUX mode
300
300
3000
1500
MHz 4
TIMING CHARACTERISTICS
Analog output rise/fall time TOR
TOF
60 ps (2) 4
Data Tsetup (Fc = 3 Gsps) 250 ps (3) 4
Data Thold (Fc = 3 Gsps) 100 ps (3) 4
Max Input data rate (Mux 4:1) 75 750 MSps 4
Max Input data rate (Mux 2:1) 150 750 MSps 4
Master clock input jitter 100 fs rms (4) 5
DSP clock phase tuning steps 0.5 Clock period 5
Master clock to DSP, DSPN delay TDSP 1.6 ns 4
SYNC forbidden area lower bound (Fc = 3 Gsps) T1200 ps (5)(6) 4
SYNC forbidden area upper bound (Fc = 3 Gsps) T2180 ps (5)(6) 4
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Notes: 1. See Section 3.6 on page 13 for explanation of the test level.
2. Analog output rise/fall time measured from 20% to 80% of a full scale jump, after probe de-embedding.
3. Exclusive of period (pp) jitter on Data. Setup and hold time for DATA at input relative to DSP clock at output of the
component, at PSS = 000; also applicable for IDC signal.
4. Master clock input jitter defined over 5 GHz bandwidth.
5. TC represents the master clock period. See Figure 3-3.
6. For EV12DS130A, please refer to erratasheet 1125
Figure 3-1. Timing Diagram for 4:1 MUX Principle of Operation OCDS[00]
Figure 3-2. Timing Diagram for 2:1 MUX Principle of Operation OCDS[00]
SYNC to DSP, DSPN
MUX 2:1
MUX4:1
880
1600
ps 4
Data Pipeline Delay
MUX4:1
MUX2:1
TPD 3.5
3.5
Clock period 4
Data Output Delay TOD 160 ps 4
Table 3-8. Timing Characteristics and Switching Performances (Continued)
Parameter Symbol Min Typ Max Unit Note
Test
level(1)
External CLK
Data input A
Data input B
Data input C
Data input D
Internal CLK/4 is used to clock the Data input A, B, C, D into DAC
Internal CLK/4
DSP clock is interna l CLK/4 delay by the DAC (by step of 0,5 CLK via the PSS function) to be used as DDR clo ck for th e FPGA
DSP with PSS[000]
DSP with PSS[001]
Pipeline delay 3,5 CLK + TOD Output delay TOD
OUT
NN+1xxx
Nxxx
xxx
xxx
N+1
N+2
N+3
xxx
N+12
N+5 N+9 N+13
N+4 N+8
N+10 N+14
N+7 N+11 N+14
N+6
N+2 N+3 N+4 N+5 N+10N+6 N+7 N+8 N+9
SSS
SS
SS
External CLK
Data inp ut A
Data inp ut B
Internal CLK/2 is used to clock the Data input A, B into DAC
Internal CLK /2
DSP clock is internal CLK/2 delay by the DAC (by step of 0,5 CLK via the PSS function) to be used as DDR clo ck for the FPG A
DSP with PSS[001]
DSP with PSS[000]
Pipeline delay 3,5 CLK + TOD Output delay TOD
OUT
N+10N+8N+2 N+4 N+6
N N+1 N+2 N+8N+3N+4N+5N+6
xxx XXX N+1
xxx
N+3
xxx XXX N
N+7
N+12
N+5 N+7 N+9 N+11 N+13
SS
SS
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Figure 3-3. SYNC Timing Diagram
Please refer to Section 5.8 ”Synchronization functions for multi-DAC operation” on page 26.
3.6 Explanation of Test Levels
Only MIN and MAX values are guaranteed.
Notes: 1. Unless otherwise specified.
2. If applicable, please refer to “Ordering Information”
SYNC OK OK
NOK NOK
t1
t2
SYNC OK
SYNC NOK
SYNC NOK
Master Clk
t2
t1
1 100% production tested at +25°C(1)
2 100% production tested at +25°C(1), and sample tested at specified temperatures.
3 Sample tested only at specified temperatures
4 Parameter is guaranteed by design and/or characterization testing (thermal steady-state conditions at specified temperature)
5 Parameter value is guaranteed by design
6 100% production tested over specified temperature range (for Space/Mil grade(2))
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3.7 Digital Input Coding Table
Table 3-9. Coding Table (Theorical values)
Digital output
msb………..lsb
Differential
analog output
000000000000 –500 mV
010000000000 –250 mV
011000000000 –125 mV
011111111111 –0.122 mV
100000000000 0.122 mV
101000000000 +125 mV
110000000000 +250 mV
111111111111 +500 mV
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4. Definition of Terms
Abbreviation Term Definition
(Fs max) Maximum conversion Frequency Maximum conversion frequency
(Fs min) Minimum conversion frequency Minimum conversion Frequency
(SFDR) Spurious free dynamic range
Ratio expressed in dB of the RMS signal amplitude, set at Full Scale, to the RMS value of the
highest spectral component (peak spurious spectral component). The peak spurious
component may or may not be a harmonic. It may be reported in dB (i.e., related to converter
0 dB Full Scale), or in dBc (i.e, related to input signal level).
(HSL) High Spur Level Power of highest spurious spectral component expressed in dBm.
(ENOB) Effective Number Of Bits
ENOB is determinated from NPR measurement with the formula:
ENOB = (NPR[dB] + ILF[dB]I – 3 – 1.76) / 6.02
Where LF “Loading factor” is the ratio between the Gaussian noise standard deviation versus
amplitude full scale.
(SNR) Signal to noise ratio
SNR is determinated from NPR measurement with the formula:
SNR[dB] = NPR[dB] + ILF[dB]I – 3
Where LF “Loading factor” is the ratio between the Gaussian noise standard deviation versus
amplitude full scale.
(DNL) Differential non linearity
The Differential Non Linearity for an given code i is the difference between the measured step
size of code i and the ideal LSB step size. DNL (i) is expressed in LSBs. DNL is the maximum
value of all DNL (i). DNL error specification of less than 1 LSB guarantees that there are no
missing point and that the transfer function is monotonic.
(INL) Integral non linearity
The Integral Non Linearity for a given code i is the difference between the measured voltage at
which the transition occurs and the ideal value of this transition.
INL (i) is expressed in LSBs, and is the maximum value of all |INL (i)|
(TPD/TOD) Output delay
The analog output propagation delay measured between the rising edge of the differential CLK,
CLKN clock input (zero crossing point) and the zero crossing point of a full-scale analog output
voltage step. TPD corresponds to the pipeline delay plus an internal propagation delay (TOD)
including package access propagation delay and internal (on-chip) delays such as clock input
buffers and DAC conversion time.
(NPR) Noise Power Ratio
The NPR is measured to characterize the DAC performance in response to broad bandwidth
signals. When applying a notch-filtered broadband white-noise pattern at the input to the DAC
under test, the Noise Power Ratio is defined as the ratio of the average noise measured on the
shoulder of the notch and inside the notch on the same integration bandwidth.
(VSWR) Voltage Standing Wave Ratio The VSWR corresponds to the insertion loss linked to power reflection. For example a VSWR
of 1:2 corresponds to a 20dB return loss (ie. 99% power transmitted and 1% reflected).
(IUCM) Input under clocking mode The IUCM principle is to apply a selectable division ratio between DAC section clock and the
MUX section clock.
(PSS) Phase Shift Select The Phase Shift Select function allow to tune the phase of the DSPclock.
(OCDS) Output Clock Division Selectt It allows to divide the DSPclock frequency by the OCDS coded value factor
(NRZ) Non Return to Zero mode Non Return to Zero mode on analog output
(RF) Radio Frequency mode RF mode on analog output
(RTZ) Return to zero Return to zero mode on analog output
(NRTZ) Narrow return to zero Narrow return to zero mode on analog output
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5. Functional Description
Figure 5-1. DAC Functional Diagram
Table 5-1. Functions Description
Name Function Name Function
VCCD 3.3V Digital Power Supply CLK In-phase Master clock
VCCA5 5.0V Analog Power Supply CLKN Inverted phase Master clock
VCCA3 3.3V Analog Power Supply DSP_CK In-phase Output clock
DGND Digital Ground DSP_CKN Inverted phase Output clock
AGND Analog ground (for analog supply reference) PSS[0..2] Phase shift select
A[11…0] In-phase digital input Port A GA Gain Adjust
A[11..0]N Inverted phase digital input Port A MUX Multiplexer Selection
B[11…0] In-phase digital input Port B MODE[0..1] DAC Mode: NRZ, RTZ, NRTZ, RF
B[11..0]N Inverted phase digital input Port B STVF Setup time Violation flag
C[11…0] In-phase digital input Port C HTVF Hold time Violation flag
C[11..0]N Inverted phase digital input Port C IDC_P, IDC_N Input data check
D[11…0] In-phase digital input Port D OCDS[0..1] Output Clock Division factor Selection
(by 4 or 8)
D[11..0]N Inverted phase digital input Port D Diode Diode for temperature monitoring
OUT In-phase analog output SYNC/SYNCN Synchronization signal (Active High)
OUTN Inverted phase analog output
V
CCD
AGND
DAC 12-bit
2x12
2x12
2x12
2x12
A0…A11
A0N…A11N
B0…B11
B0N…B11N
C0…C11
C0N…C11N
CLK, CLKN
SYNC
2OUT, OUTN
2DSP_CK,
DSP_CKN
MUX
MODE
V
CCA5
GA
PSS 3
D0…D11
D0N…D11N
DIODE
2
DGND
2
V
CCA3
2
OCDS 2
IDC_P
IDC_N
2
STVF
HTVF
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5.1 DSP Output Clock
The DSP output clock DSP, DSPN is an LVDS signal which is used to synchronize the FPGA generating
the digital patterns with the DAC sampling clock.
The DSP clock frequency is a fraction of the sampling clock frequency. The division factor depends on
OCDS settings. The DSP clock frequency is equal to (sampling frequency / [2N*X]) where N is the MUX
ratio and X is the output clock division factor, determined by OCDS[0..1] bits.
For example, in a 4:1 MUX ratio application with a sampling clock of 3 GHz and OCDS set to “00” (ie.
Factor of 1), the input data rate is 750 MSps and the DSP clock frequency is 375 MHz.
This DSP clock is used in the FPGA to control the digital data sequencing. Its phase can be adjusted
using the PSS[2:0] bits (refer to Section 5.4 on page 22) in order to ensure a proper synchronization
between the data coming to the DAC and the sampling clock.
The HTVF and STVF bits should be used to check whether the timing between the FPGA and the DAC
is correct. HTVF and STVF bits will indicate whether the DAC and FPGA are aligned or not. PSS bits
should then be used to shift the DSP clock and thus the input data of the DAC, so that a correct timing is
achieved between the FPGA and the DAC.
Important note: Maximum supported sampling frequency when using DSP to clock digital data is
2.1 Gsps on EV12DS130B. Please refer to application note AN1141 to use EV12DS130B at
sampling frequency beyond 2.1 GHz.
5.2 Multiplexer
Two multiplexer ratio are allowed:
• 4:1 which allows operation at full sampling rate (ie. 3 GHz)
• 2:1 which can only be used up to 1.5 GHz sampling rate
In 2:1 MUX ratio, the unused data ports (ports C and D) can be left open.
5.3 MODE Function
The MODE function allows choosing between NRZ, NRTZ, RTZ and RF functions. NRZ and narrow RTZ
should be chosen for use in 1st Nyquist zone while RTZ should be chosen for use in 2nd and RF for 3rd
Nyquist zones.
Theory of operation: see following subsections for time domain waveform of the different modes.
Label Value Description
MUX
0 4:1 mode
1 2:1 mode
Label Value Description Default Setting (Not Connected)
MODE[1:0]
00 NRZ mode
11
RF mode
01 Narrow RTZ (a.k.a. NRTZ) mode
10 RTZ Mode (50%)
11 RF mode
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Ideal equations describing max available Pout for frequency domain in the four modes are given
hereafter, with X = normalized output frequency (that is Fout/Fclock, edges of Nyquist zones are then at
X = 0 1/2 1 3/2 2 …). Due to limited bandwidth, an extra term must be added to take in account a first
order low pass filter.
NRZ mode:
where sinc(x) = sin(x)/x, and k = 1
NRTZ mode:
where T is width of reshaping pulse, T is about 75ps.
RTZ mode:
where k is the duty cycle of the clock presented at the DAC input, please note that due to phase
mismatch in balun used to convert single ended clock to differential clock the first zero may move around
the limit of the 4th and the 5th Nyquist zones. Ideally k = 1/2.
RF mode:
where k is as per in NRTZ mode.
As a consequence:
• NRZ mode offers max power for 1st Nyquist operation
• RTZ mode offers slow roll off for 2nd Nyquist or 3rd Nyquist operation
• RF mode offers maximum power over 2nd and 3rd Nyquist operation
• NRTZ mode offers optimum power over full 1st and first half of 2nd Nyquist zones. This is the most
relevant in term of performance for operation over 1st and beginning of 2nd Nyquist zone. Depending
on the sampling rate the zero of transmission moves in the 3rd Nyquist zone from begin to end when
sampling rate increases.
Note in the two following figures: Pink line is ideal equation’s result, and green line includes a first order
6 GHz cut-off low pass filter to take into account finite bandwidth effect due to die and package.
Pout(X) 20 log10
ksinckX
0.893
---------------------------------------------
=
Pout(X) 20 log10
ksinckX
0.893
---------------------------------------------
=
kTclk T–
Tclk
-----------------------=
Pout(X) 20 log10
ksinckX
0.893
---------------------------------------------
=
Pout(X) 20 log10
ksinc
kX
2
-------------------
kX
2
-------------------
sin
0.893
------------------------------------------------------------------------------------
=
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Figure 5-2. Max Available Pout[dBm] at Nominal Gain vs Fout[GHz] in the Four Output Modes at 3 Gsps, over four
Nyquist Zones, Computed for T = 75 ps.
1s
t
Nyquist 2n
d
Nyquist 3r
d
Nyquist 4
th
Nyquist 1s
t
Nyquist 2n
d
Nyquist 3r
d
Nyquist 4
th
Nyquist
1s
t
Nyquist 2n
d
Nyquist 3r
d
Nyquist 4
th
Nyquist 1s
t
Nyquist 2n
d
Nyquist 3r
d
Nyquist 4
th
Nyquist
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Figure 5-3. Max available Pout[dBm] at Nominal Gain vs Fout[GHz] in the Four Output Modes at 2 Gsps, over four
Nyquist Zones, Computed for T = 75 ps
5.3.1 NRZ Output Mode
This mode does not allow for operation in the 2nd Nyquist zone because of the Sinx/x notch.
The advantage is that it gives good results at the beginning of the 1st Nyquist zone (less attenuation than
in RTZ architecture), it removes the parasitic spur at the clock frequency (in differential).
Figure 5-4. NRZ Timing Diagram
1st Nyquist 2nd Nyquist 3rd Nyquist 4th Nyquist
1st Nyquist 2nd Nyquist 3rd Nyquist 4th Nyquist
1st Nyquist 2nd Nyquist 3rd Nyquist 4th Nyquist 1st Nyquist 2nd Nyquist 3rd Nyquist 4th Nyquist
Mux OUT
External CLK
T=TOD
T=T
clk
N N+1 N+2 N+3
Analog Output signal 0V
N+3 N+4XXX N N+1 N+2
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5.3.2 Narrow RTZ Mode (NRTZ Mode)
This mode has the following advantages:
• Optimized power in 1st Nyquist zone
• Extended dynamic through elimination of noise on transition edges
• Improved spectral purity (see Section 7.2.3 on page 45)
• Trade off between NRZ and RTZ
Figure 5-5. Narrow RTZ Timing Diagram
Note: T is independent of Fclock.
5.3.3 RTZ Mode
The advantage of the RTZ mode is to enable the operation in the 2nd zone but the drawback is clearly to
attenuate more the signal in the first Nyquist zone.
Advantages:
• Extended roll off of sinc
• Extended dynamic through elimination of hazardous transitions
Weakness:
• By construction clock spur at Fs.
Figure 5-6. RTZ Timing Diagram
Mux OUT
External CLK
T=TOD+Tτ/2
T=Tclk-Tτ
N N+1 N+2 N+3
Analog Output signal
N+4 0V
TτTτTτTτTτ
N+3 N+4XXX N N+1 N+2
Mux OUT
External CLK
T=TOD
T=0,5xTclk
N N+ 1 N+2 N+3
N+4
A
nalog Output signal 0V
N+3 N+4XXX N N+1 N+2
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5.3.4 RF Mode
RF mode is optimal for operation at high output frequency, since the decay with frequency occurs at
higher frequency than for RTZ. Unlike NRZ or RTZ modes, RF mode presents a notch at DC and 2N*Fs,
and minimum attenuation for Fout = Fs.
Advantages:
•Optimized for 2
nd and 3rd Nyquist operation
• Extended dynamic range through elimination of hazardous transitions.
• Clock spur pushed to 2.Fs
Figure 5-7. RF Timing Diagram
Note: The central transition is not hazardous but its elimination allows to push clock spur to 2.Fs
T is independent of Fclock.
5.4 PSS (Phase Shift Select Function)
It is possible to adjust the timings between the sampling clock and the DSP output clock (which
frequency is given by the following formula: Sampling clock / 2NX where N is the MUX ratio, X the output
clock division factor).
The DSP clock output phase can be tuned over a range of 3.5 input clock cycles (7 steps of half a clock
cycle) in addition to the intrinsic propagation delay between the DSP clock (DSP, DSPN) and the
sampling clock (CLK, CLKN).
Three bits are provided for the phase shift function: PSS[2:0].
By setting these 3 bits to 0 or 1, one can add a delay on the DSP clock in order to properly synchronize
the input data of the DAC and the sampling clock (the DSP clock should be applied to the FPGA and
should be used to clock the DAC digital input data).
Mux OUT
External CLK
T=TOD+Tτ
/2
T=Tclk-Tτ
N N+1 N+2 N+3
N+4
A
nalog Output signal
0V
TτTτTτTτTτ
N+3 N+4XXX N N+1 N+2
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In order to determine how much delay needs to be added on the DSP clock to ensure the
synchronization between the input data and the sampling clock within the DAC, the HTVF and STVF bits
should be monitored. Refer to Section 5.6 on page 25.
Note: In MUX 4:1 mode the 8 settings are relevant, in MUX 2:1 only the four first settings are relevant since the
four last ones will yield exactly the same results.
Figure 5-8. PSS Timing Diagram for 4:1 MUX, OCDS[00]
Figure 5-9. PSS Timing Diagram for 2:1 MUX, OCDS[00]
Table 5-2. PSS Coding Table
Label Value Description
PSS[2:0]
000 No additional delay on DSP clock
001 0.5 input clock cycle delay on DSP clock
010 1 input clock cycle delay on DSP clock
011 1.5 input clock cycle delay on DSP clock
100 2 input clock cycle delay on DSP clock
101 2.5 input clock cycle delay on DSP clock
110 3 input clock cycle delay on DSP clock
111 3.5 input clock cycle delay on DSP clock
Extern al CLK
Internal CLK/4 is used to clock the Data input A, B, C, D into DAC
Internal CLK/4
DSP with PSS[000]
T=0.5xTclk
DSP with PSS[001]
DSP with PSS[010]
DSP with PSS[011]
DSP with PSS[110]
DSP with PSS[111]
.
.
.
DSP clock is a ratio of internal clock delayed by step of 0.5 Tclk via the PSS function and outputed in DDR mode.
External CLK
Internal C LK/2 is us e d to cloc k the Data input A, B into DAC
Internal CLK/2
DSP with P SS[000]
T=0.5xTclk
DSP with P SS[001]
DSP wi th PSS[010]
DSP wi th PSS[011]
DSP wi th PSS[110]
DSP wi th PSS[111]
.
.
.
DSP clock is a ratio of internal clock delayed by step of 0.5 Tclk via the PSS function and outputed in DDR mode.
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5.5 Output Clock Division Select Function
It is possible to change the DSP clock internal division factor from 1 to 2 with respect to the sampling
clock/2N where N is the MUX ratio. This is possible via the OCDS "Output Clock Division Select" bits.
OCDS is used to obtain a synchronization clock for the FPGA slow enough to allow the FPGA to operate
with no further internal division of this clock, thus its internal phase is determined by the DSP clock
phase. This is useful in a system with multiple DACs and multiple FPGAs to guarantee deterministic
phase relationship between the FPGAs after a synchronization of all the DACs.
Figure 5-10. OCDS Timing Diagram for 4:1 MUX
Figure 5-11. OCDS Timing Diagram for 2:1 MUX
Table 5-3. OCDS[1:0] Coding Table
Label Value Description
OCDS [1:0]
00 DSP clock frequency is equal to the sampling clock divided by 2N
01 DSP clock frequency is equal to the sampling clock divided by 2N*2
10 Not allowed
11 Not allowed
External CL K
Internal CLK/4 is used to clock the Data input A, B, C, D into DAC
Internal CLK/4
DSP clock is internal CLK/4 divided by OCDS selection. This clock could be used as DDR clock for the FPGA
DSP with OCDS[00]
DSP with OCDS[01]
External CLK
Internal CLK/2 is used to clock the Data input A, B into DAC
Internal CLK/2
DSP clock is int ernal CLK/2 divided by OCDS select io n. This c lock could be used as DDR clock for the FPGA
DSP with OCDS[00]
DSP with OCDS[01]
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5.6 Synchronization FPGA-DAC: IDC_P, IDC_N, HTVF and STVF Functions
IDC_P, IDC_N: Input Data check function (LVDS signal).
HTVF: Hold Time Violation Flag. (cmos3.3V signal)
STVF: Setup Time Violation Flag. (cmos3.3V signal)
IDC signal is toggling at each cycle synchronously with other data bits. It should be considered as a DAC
input data that toggles at each cycle.
This signal should be generated by the FPGA in order for the DAC to check in real-time if the timings
between the FPGA and the DAC are correct.
Figure 5-12. IDC Timing vs Data Input
The information on the timings is then given by HTVF, STVF signals (flags).
During monitoring STVF indicates setup time of data violation (Low -> OK, High -> Violation), HTVF
indicates hold time of data violation (Low -> OK, High -> Violation).
Figure 5-13. FPGA to DAC Synoptic
Table 5-4. HTVF, STVF Coding Table
Label Value Description
HTVF 0 SYNCHRO OK
1 Data Hold time violation detected
STVF 0 SYNCHRO OK
1 Data Setup time violation detected
IDC_P,
IDC_N
Data
Xi, XiN
FPGA DAC
IDC
Port A
Port B
Port C
Port D
HTVF, STVF
OCDS
2
2
24
24
24
24
2
2
DSP
3
PSS
CLK DIV 2
τ
OUT
2
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Principle of Operation:
The Input Data Check pair (IDC_P, IDC_N) will be sampled three times with half a master clock period
shift (the second sample being synchronous with all the data sampling instant), these three samples will
be compared, and depending on the results of the comparison a violation may be signalled.
• Violation of setup time -> STVF is high level
• Violation of hold time -> HTVF is high level
In case of violation of timing (setup or hold) the user has two solutions:
• Shift phase in the FPGA PLL (if this functionality is available in FPGA) for changing the internal timing
of DATA and Data Check signal inside FPGA.
• Shift the DSP clock timing (Output clock of the DAC which can be used for FPGA synchronization –
refer to Section 5.4 on page 22), in this case this shift also shift the internal timing of FPGA clock.
Note: When used, it should be routed as the data signals (same layout rules and same length). if not used, it
should be driven to an LVDS low or high level.
For further details, refer to application note AN1087.
5.7 OCDS, MUX Combinations Summary
Note: Behaviour according to MUX, OCDS and PSS combination is independent of output mode (MODE).
5.8 Synchronization functions for multi-DAC operation
In order to synchronize the timings, a SYNC operation can be generated.
After the application of the SYNC signal the DSP clock from the DAC will stop for a period and after a
constant and known time the DSP clock will start up again.
There are two SYNC functions integrated in this DAC:
• a power up reset, which is triggered by the power supplies if the dedicated power up sequence is
applied VCCD => VCCA3 => VCCA5;
• External SYNC pulse applied on (SYNC, SYNCN).
The external SYNC is LVDS compatible (same buffer as for the digital input data). It is active high.
Table 5-5. OCDS, MUX, PSS Combinations Summary
MUX OCDS PSS Range Data Rate Comments
0
4:1
00 DSP clock division factor 8
0 to 7/(2Fs) by 1/(2Fs) steps Fs/4 Refer to
Section 5.5
0 01 DSP clock division factor 16
010 Not allowed
011 Not allowed
1
2:1
00 DSP clock division factor 4
0 to 7/(2Fs) by 1/(2Fs) steps Fs/2 Refer to
Section 5.5
1 01 DSP clock division factor 8
110 Not allowed
111 Not allowed
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Depending on the settings for OCDS, PSS and also the MUX ratio the width of the SYNC pulse must be
greater than a certain number of external clock pulses. It is also necessary that the sync pulse be
synchronized with the system clock and is an integer number of clock pulses. See application note
(ref 1087) for further details.
Figure 5-14. Reset Timing Diagram (4:1 MUX)
Figure 5-15. Reset Timing Diagram (2:1 MUX)
Important note:
For EV12DS130A:
• See erratasheet (ref 1125) for SYNC condition of use.
• SYNC, SYNCN pins have to be driven.
For EV12DS130B:
• SYNC, SYNCN pins can be left floating if unused.
• No specific timing constraints (other than T1 and T2) are required.
5.9 Gain Adjust GA Function
This function allows to adjust the internal gain of the DAC to cancel the initial gain deviation.
The gain of the DAC can be adjusted by ±11% by tuning the voltage applied on GA by varying GA
potential from 0 to VCCA3.
GA max is given for GA = 0 and GA min for GA = V CCA3
DSP,
DSPN
CLK,
CLKN
3 GHz
SYNC,
SYNCN 3 clock
cycles min Pipeline +
TDSP
DSP,
DSPN
CLK,
CLKN
1.5 GHz
SYNC,
SYNCN 3 clock
cycles min Pipeline +
TDSP
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5.10 Diode Function
A diode is available to monitor the die junction temperature of the DAC.
For the measurement of die junction temperature, you may use a temperature sensor.
Figure 5-16. Temperature DIODE Implementation
In characterization measurement a current of 1 mA is applied on the DIODE pin. The voltage across the
DIODE pin and the DGND pin gives the junction temperature using the intrinsic diode characteristics
below Figure 5-17.
Figure 5-17. Diode Characteristics for Die Junction Monitoring
Diode
DGND
DAC Temperature sensor
D+
D-
Junction Temperature Versus Diode voltage for I=1mA
y = -1.13x + 915
750
770
790
810
830
850
870
890
910
930
950
970
-35 -15 5 25 45 65 85 105 125
Junction temperature (°C)
Diode voltage (mV)
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6. PIN Description
Figure 6-1. Pinout View fpBGA196 (Top View)
Table 6-1. Pinout Table fpBGA196
Signal name Pin number Description Direction Equivalent Simplified schematics
Power Supplies
VCCA5
K7, K8, L6, L7, L8, L9, M6,
M7
5V analogue power supplies
Referenced to AGND N/A
VCCA3 J4, J5, J10, J11 3.3V analogue power supply
Referenced to AGND N/A
VCCD
D6, D7, D8, D9, E6, E7,
E8, E9, F4, F5, F10, F11
3.3V digital power supply
Referenced to DGND N/A
AGND
F6, F7, F8, F9, G6, G7,
G8, G9, H6, H7, H8, H9,
J6, J7, J8, J9, K6, K9, M8,
M9, N6, N7, N8, N9, N10,
N11, P6, P7, P8, P11
Analog Ground N/A
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DGND
A1, A14, C7, C8, D4, D5,
D10, D11, E4, E5, E10,
E11, G5, G10, H5, H10,
K4, K5, K10, K11, L4, L10,
P1, P14
Digital Ground N/A
Clock Signals
CLK, CLKN P5, N5
Master sampling clock input (differential)
with internal common mode
It should be driven in AC coupling.
Equivalent internal differential 100
input resistor.
I
DSP, DSPN P2, N2 Output clock (in-phase and inverted
phase O
Analog Output Signal
OUT, OUTN P9, P10
In phase and Inverted phase analogue
output signal (differential termination
required)
O
Table 6-1. Pinout Table fpBGA196 (Continued)
Signal name Pin number Description Direction Equivalent Simplified schematics
CLK
CLKN
50Ω
50Ω
AGND
3.75 pF
2.5V
3.3V
DGND
145Ω
DSP,
DSPN
OUT
OUTN
VCCA5
Current
Switches and
sources
50Ω
AGND
31
1077H–BDC–12/14
e2v semiconductors SAS 2014
EV12DS130AZP
EV12DS130BZP
Digital Input Signals
A0, A0N
A1, A1N
A2, A2N
A3, A3N
A4, A4N
A5, A5N
A6, A6N
A7, A7N
A8, A8N
A9, A9N
A10, A10N
A11, A11N
N1, M2
M1, L1
L2, L3
K1, J1
K2, K3
J2, J3
H1, H2
H3, H4
G1, G2
G3, G4
F1, E1
F2, F3
In-phase Digital input
Port A
Data A0, A0N is the LSB
Data A11, A11N is the LSB
I
B0, B0N
B1, B1N
B2, B2N
B3, B3N
B4, B4N
B5, B5N
B6, B6N
B7, B7N
B8, B8N
B9, B9N
B10, B10N
B11, B11N
E2, E3
D1, C1
D2, D3
B1, C2
B2, C3
A2, B3
A3, A4
B4, C4
B5, C5
A5, A6
B6, C6
A7, B7
Inverted phase Digital input
Port B
Data B0, B0N is the LSB
Data B11, B11N is the LSB
I
C0, C0N
C1, C1N
C2, C2N
C3, C3N
C4, C4N
C5, C5N
C6, C6N
C7, C7N
C8, C8N
C9, C9N
C10, C10N
C11, C11N
E13, E12
D14, C14
D13, D12
B14, C13
B13, C12
A13, B12
A12, A11
B11, C11
B10, C10
A10, A9
B9, C9
A8, B8
In-phase Digital input
Port B Data 1 I
Table 6-1. Pinout Table fpBGA196 (Continued)
Signal name Pin number Description Direction Equivalent Simplified schematics
In
InN
50Ω
50ΩDGND3.75 pF
In
InN
50Ω
50ΩDGND
3.75 pF
In
InN
50Ω
50ΩDGND
3.75 pF
32
1077H–BDC–12/14
EV12DS130AZP
EV12DS130BZP
e2v semiconductors SAS 2014
D0, D0N
D1, D1N
D2, D2N
D3, D3N
D4, D4N
D5, D5N
D6, D6N
D7, D7N
D8, D8N
D9, D9N
D10, D10N
D11, D11N
N14, M13
M14, L14
L13, L12
K14, J14
K13, K12
J13, J12
H14, H13
H12, H11
G14, G13
G12, G11
F14, E14
F13, F12
Inverted phase Digital input
Port B Data 1 I
Control Signals
HTVF M4 Setup time violation flag O
STVF M5 Hold time violation flag O
Table 6-1. Pinout Table fpBGA196 (Continued)
Signal name Pin number Description Direction Equivalent Simplified schematics
In
InN
50Ω
50ΩDGND
3.75 pF
HTVF
100Ω
400Ω
20Ω
VCCD
DGND
STVF
100Ω
400Ω
20Ω
VDD
DGND
33
1077H–BDC–12/14
e2v semiconductors SAS 2014
EV12DS130AZP
EV12DS130BZP
IDC_P,
IDC_N N3, P3 Input data check I
PSS0
PSS1
PSS2
P12
P13
M12
Phase Shift Select (PSS2 is the MSB) I
MODE0
MODE1
M10
M11 DAC Mode selection bits I
Table 6-1. Pinout Table fpBGA196 (Continued)
Signal name Pin number Description Direction Equivalent Simplified schematics
In
InN
50Ω
50ΩDGND
3.75 pF
13 kΩ
33 kΩ
200Ω
VDD
20 kΩ
DGND
PSS0,
PSS1,
PSS2
13 kΩ
33 kΩ
200Ω
VDD
20 kΩ
DGND
MODE0
MODE1
34
1077H–BDC–12/14
EV12DS130AZP
EV12DS130BZP
e2v semiconductors SAS 2014
MUX L11 MUX selection I
OCDS0
OCDS1
N13
N12
Output Clock Division Select = these bits
allow to select the clock division factor
applied on the DSP, DSPN signal.
I
Table 6-1. Pinout Table fpBGA196 (Continued)
Signal name Pin number Description Direction Equivalent Simplified schematics
13 kΩ
33 kΩ
200Ω
20 kΩ
DGND
MUX
VCCD
13 kΩ
33 kΩ
200Ω
20 kΩ
DGND
OCDS0,
OCDS1
VDD
35
1077H–BDC–12/14
e2v semiconductors SAS 2014
EV12DS130AZP
EV12DS130BZP
SYNC,
SYNCN P4, N4 In phase and Inverted phase reset signal I
GA M3 Gain adjust I
Diode L5 Diode for die junction temperature
monitoring I
Table 6-1. Pinout Table fpBGA196 (Continued)
Signal name Pin number Description Direction Equivalent Simplified schematics
In
InN
50Ω
50ΩDGND
3.75 pF
2.5 kΩ
300Ω
2.5 kΩ
1 kΩ
26.6 pF
AGND
4 pF
GA
VCCA3
SUB
Diode
DGND_DIODE
36
1077H–BDC–12/14
EV12DS130AZP
EV12DS130BZP
e2v semiconductors SAS 2014
7. Characterization Results
Unless otherwise specified results are given at room temperature (Tj ~ 60°C), nominal power supply, in
4:1 MUX mode, gain at nominal setting.
7.1 Static Performances
7.1.1 DC Gain Characterization
Figure 7-1. DAC DC Gain vs Gain Adjust (Measured in NRZ Mode)
Figure 7-2. DAC DC Gain Drift from Unity Gain vs Temperature (Measured in NRZ Mode)
Figure 7-3. DC Gain Sensitivity to Power Supply (Measured in NRZ Output Mode)
DAC 12 bit 3 Gsps : Gain DC versus Gain Adjust
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
-0.5 0 0.5 1 1.5 2 2.5 3 3.5
Gain Adjust (V)
Gain (V)
part 2
part 4
part 5
DAC 12 bit 3 Gsps : DC gain sensitivity to temperature
0.95
0.96
0.97
0.98
0.99
1.00
1.01
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140
Temperature junction(°C)
Gain (%)
part 2
part 4
part 5
Ga : 1.64V
Tamb = 66.5°C
Conditions: room temperature, supply levels:
- Min: VCCA: 4.75V // VCCA3 = VCCD = 3.15V
- Typ: VCCA: 5V // VCCA3 = VCCD = 3.3V
- Max: VCCA: 5.25V // VCCA3 = VCCD = 3.45V
DAC 12 bit 3 Gsps : DC gain sensitivity to power supplies
0.70
0.75
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
Min Typ Max
Power supplies
Gain (V)
part 2
part 4
part 5
Ga : 1.64V
Ga : 0V
Ga : 3.3V
37
1077H–BDC–12/14
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EV12DS130AZP
EV12DS130BZP
7.1.2 Static Linearity
Figure 7-4. INL/DNL Measurement at Fout = 100 kHz and 3 Gsps
INL reflects a true 12 bit DAC.
Low DNL values reflect a strictly monotonous 12 bit DAC.
38
1077H–BDC–12/14
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e2v semiconductors SAS 2014
7.2 AC Performances
7.2.1 Available Output Power vs Fout.
The following plots summarize characterization results, for a Fout sweep from 98 MHz to 4498 MHz
(step 100 MHz).
Figure 7-5. Available Pout vs Fout from 98 MHz to 4498 MHz in the 4 Output Modes at 3 Gsps
Figure 7-6. Available Pout vs Fout from 98 MHz to 4498 MHz and from 2 Gsps to 3.2 Gsps in NRZ Mode
-70
-60
-50
-40
-30
-20
-10
0
10
98
198
298
398
498
598
698
798
898
998
1098
1198
1298
1398
1498
1598
1698
1798
1898
1998
2098
2198
2298
2398
2498
2598
2698
2798
2898
2998
3098
3198
3298
3398
3498
3598
3698
3798
3898
3998
4098
4198
4298
4398
4498
Mux4:1_Mode_NRZ
Mux4:1_Mode_NRTZ
Mux4:1_Mode_RTZ
Mux4:1_Mode_RF
Pout_dBm
Output frequency (MHz)
NRZ mode offers max power for 1st Nyquist operation.
RTZ mode offer slow roll off for 2nd Nyquist operation.
RF mode offers maximum power over 2nd
and 3rd Nyquits operation.
NRTZ mode offers optimum power over full 1st and first half
of 2nd Nyquist zones.
This is the most relevant in term of performance for operation
over 1st and beginning of 2nd Nyquist zone.
1st Nyquist 2nd Nyquist 3rd Nyquist
First notch at F= Fclock,
second notch at 2xFclock
Pout_dBm
Output frequency (MHz)
-80
-70
-60
-50
-40
-30
-20
-10
0
10
98
198
298
398
498
598
698
798
898
998
1098
1198
1298
1398
1498
1598
1698
1798
1898
1998
2098
2198
2298
2398
2498
2598
2698
2798
2898
2998
3098
3198
3298
3398
3498
3598
3698
3798
3898
3998
4098
4198
4298
4398
4498
0 - 2000 - Mux4:1_Mode_NRZ
0 - 2199 - Mux4:1_Mode_NRZ
0 - 2399 - Mux4:1_Mode_NRZ
0 - 2599 - Mux4:1_Mode_NRZ
0 - 2799 - Mux4:1_Mode_NRZ
0 - 2999 - Mux4:1_Mode_NRZ
0 - 3200 - Mux4:1_Mode_NRZ
39
1077H–BDC–12/14
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EV12DS130AZP
EV12DS130BZP
Figure 7-7. Available Pout vs Fout from 98 MHz to 4498 MHz and from 2 Gsps to 3.2 Gsps in NRTZ Mode
Figure 7-8. Available Pout vs Fout from 98 MHz to 4498 MHz and from 2 Gsps to 3.2 Gsps in RTZ Mode
Figure 7-9. Available Pout vs Fout from 98 MHz to 4498 MHz and from 2 Gsps to 3.2 Gsps in RF Mode
-60
-50
-40
-30
-20
-10
0
98
198
298
398
498
598
698
798
898
998
1098
1198
1298
1398
1498
1598
1698
1798
1898
1998
2098
2198
2298
2398
2498
2598
2698
2798
2898
2998
3098
3198
3298
3398
3498
3598
3698
3798
3898
3998
4098
4198
4298
4398
4498
2000 - Mux4:1_Mode_NRTZ
2199 - Mux4:1_Mode_NRTZ
2399 - Mux4:1_Mode_NRTZ
2599 - Mux4:1_Mode_NRTZ
2799 - Mux4:1_Mode_NRTZ
2999 - Mux4:1_Mode_NRTZ
3200 - Mux4:1_Mode_NRTZ
First notch at F=1/((1/Fclock) - 75ps),
second notch at 2xF
Pout_dBm
Output frequency (MHz)
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
98
198
298
398
498
598
698
798
898
998
1098
1198
1298
1398
1498
1598
1698
1798
1898
1998
2098
2198
2298
2398
2498
2598
2698
2798
2898
2998
3098
3198
3298
3398
3498
3598
3698
3798
3898
3998
4098
4198
4298
4398
4498
2000 - Mux4:1_Mode_RTZ
2199 - Mux4:1_Mode_RTZ
2399 - Mux4:1_Mode_RTZ
2599 - Mux4:1_Mode_RTZ
2799 - Mux4:1_Mode_RTZ
2999 - Mux4:1_Mode_RTZ
3200 - Mux4:1_Mode_RTZ
First notch at F = 2 x Fclock
Pout_dBm
Output frequency (MHz)
-35
-30
-25
-20
-15
-10
-5
0
98
198
298
398
498
598
698
798
898
998
1098
1198
1298
1398
1498
1598
1698
1798
1898
1998
2098
2198
2298
2398
2498
2598
2698
2798
2898
2998
3098
3198
3298
3398
3498
3598
3698
3798
3898
3998
4098
4198
4298
4398
4498
2000 - Mux4:1_Mode_RF
2199 - Mux4:1_Mode_RF
2399 - Mux4:1_Mode_RF
2599 - Mux4:1_Mode_RF
2799 - Mux4:1_Mode_RF
2999 - Mux4:1_Mode_RF
3200 - Mux4:1_Mode_RF
First notch at DC
Pout_dBm
Output frequency (MHz)
40
1077H–BDC–12/14
EV12DS130AZP
EV12DS130BZP
e2v semiconductors SAS 2014
7.2.2 Single Tone Measurements
The following plots summarize characterization results in MUX4:1 mode, for an Fout sweep from 98 MHz
to 4498 MHz (step 100 MHz).
The left side of the plot gives SFDR expressed in dBc and the right side gives HSL (Highest Spur Level
excluding Fclock spur) expressed in dBm.
Figure 7-10. SFDR and HSL in NRZ mode at –3 dBFS for Sampling Rate from 2000 MSps to 3200 MSps
NRZ mode is only relevant for Fout below 400 MHz.
The spikes in the SFDR are caused by normalization artefacts due to the Sinc(x) null.
Figure 7-11. SFDR and HSL in NRTZ mode at –3 dBFS for Sampling Rate from 2000 MSps to 3200 MSps
NRTZ mode brings significant improvement regarding NRZ mode. This mode concentrates the benefits
of both NRZ mode (high power available) and RTZ mode (extended available dynamic range).
The spikes in the SFDR are caused by normalization artefacts due to the Sinc(x) null.
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
98
198
298
398
498
598
698
798
898
998
1098
1198
1298
1398
1498
1598
1698
1798
1898
1998
2098
2198
2298
2398
2498
2598
2698
2798
2898
2998
3098
3198
3298
3398
3498
3598
3698
3798
3898
3998
4098
4198
4298
4398
4498
98
198
298
398
498
598
698
798
898
998
1098
1198
1298
1398
1498
1598
1698
1798
1898
1998
2098
2198
2298
2398
2498
2598
2698
2798
2898
2998
3098
3198
3298
3398
3498
3598
3698
3798
3898
3998
4098
4198
4298
4398
4498
-3 - 2000 - Mux4:1_NRZ
-3 - 2199 - Mux4:1_NRZ
-3 - 2399 - Mux4:1_NRZ
-3 - 2599 - Mux4:1_NRZ
-3 - 2799 - Mux4:1_NRZ
-3 - 2999 - Mux4:1_NRZ
-3 - 3200 - Mux4:1_NRZ
Highest Spur Level (excl. Fclock)[dBm]Spurious Free Dynamic Range (excl. Fclock) [dBc]
Output frequency (MHz)
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
98
198
298
398
498
598
698
798
898
998
1098
1198
1298
1398
1498
1598
1698
1798
1898
1998
2098
2198
2298
2398
2498
2598
2698
2798
2898
2998
3098
3198
3298
3398
3498
3598
3698
3798
3898
3998
4098
4198
4298
4398
4498
98
198
298
398
498
598
698
798
898
998
1098
1198
1298
1398
1498
1598
1698
1798
1898
1998
2098
2198
2298
2398
2498
2598
2698
2798
2898
2998
3098
3198
3298
3398
3498
3598
3698
3798
3898
3998
4098
4198
4298
4398
4498
-3 - 2000 - Mux4:1_NRTZ
-3 - 2199 - Mux4:1_NRTZ
-3 - 2399 - Mux4:1_NRTZ
-3 - 2599 - Mux4:1_NRTZ
-3 - 2799 - Mux4:1_NRTZ
-3 - 2999 - Mux4:1_NRTZ
-3 - 3200 - Mux4:1_NRTZ
Highest Spur Level (excl. Fclock)[dBm]
Spurious Free Dynamic Range (excl. Fclock) [dBc]
Output frequency (MHz)
41
1077H–BDC–12/14
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EV12DS130AZP
EV12DS130BZP
Figure 7-12. SFDR and HSL in RTZ Mode at –3 dBFS for Sampling Rate from 2000 MSps to 3200 MSps
RTZ mode allows for operation over the 3 first Nyquist zones.
In first and beginning of second Nyquist zone NRTZ mode is mode relevant. The spikes in the SFDR are
caused by normalization artefacts due to the Sinc(x) null.
Figure 7-13. SFDR and HSL in RF Mode at –3 dBFS for Sampling Rate from 2000 MSps to 3200 MSps
RF mode allows for operation over 3rd Nyquist zones. Performances are not sensitive to output level.
Performance roll off occurs beyond 3000 MSps.
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
98
198
298
398
498
598
698
798
898
998
1098
1198
1298
1398
1498
1598
1698
1798
1898
1998
2098
2198
2298
2398
2498
2598
2698
2798
2898
2998
3098
3198
3298
3398
3498
3598
3698
3798
3898
3998
4098
4198
4298
4398
4498
98
198
298
398
498
598
698
798
898
998
1098
1198
1298
1398
1498
1598
1698
1798
1898
1998
2098
2198
2298
2398
2498
2598
2698
2798
2898
2998
3098
3198
3298
3398
3498
3598
3698
3798
3898
3998
4098
4198
4298
4398
4498
Somme de SFDR_dBc Somme de SFDR_dBm
-3 - 2000 - Mux4:1_RTZ
-3 - 2199 - Mux4:1_RTZ
-3 - 2399 - Mux4:1_RTZ
-3 - 2599 - Mux4:1_RTZ
-3 - 2799 - Mux4:1_RTZ
-3 - 2999 - Mux4:1_RTZ
-3 - 3200 - Mux4:1_RTZ
Spurious Free Dynamic Range (excl. Fclock) [dBc] Highest Spur Level (excl. Fclock) [dBm]
Output frequency (MHz)
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
98
198
298
398
498
598
698
798
898
998
1098
1198
1298
1398
1498
1598
1698
1798
1898
1998
2098
2198
2298
2398
2498
2598
2698
2798
2898
2998
3098
3198
3298
3398
3498
3598
3698
3798
3898
3998
4098
4198
4298
4398
4498
98
198
298
398
498
598
698
798
898
998
1098
1198
1298
1398
1498
1598
1698
1798
1898
1998
2098
2198
2298
2398
2498
2598
2698
2798
2898
2998
3098
3198
3298
3398
3498
3598
3698
3798
3898
3998
4098
4198
4298
4398
4498
-3 - 2000 - Mux4:1_RF
-3 - 2199 - Mux4:1_RF
-3 - 2399 - Mux4:1_RF
-3 - 2599 - Mux4:1_RF
-3 - 2799 - Mux4:1_RF
-3 - 2999 - Mux4:1_RF
-3 - 3200 - Mux4:1_RF
Output Frequency (MHz)
Spurious Free Dynamic Range (excl. Fclock) [dBc] Highest spur level (excl. Fclock) [dBm]
42
1077H–BDC–12/14
EV12DS130AZP
EV12DS130BZP
e2v semiconductors SAS 2014
Figure 7-14. Comparison of the 4 Output Modes at 2999 MSps and at –3 dBFS: SFDR and HSL
NRZ is interesting only at the very beginning of the first Nyquist zone.
NRTZ is relevant over 1st 2nd and 4th Nyquist zones.
RTZ is relevant over 2nd and 3rd Nyquist zones.
RF mode displays a good behavior over 2nd and 3rd Nyquist Zones.
The spikes in the SFDR are caused by normalization artefacts due to the Sinc(x) null
Figure 7-15. Comparison of the 4 Output Modes at 2000 MSps and –3 dBFS: SFDR and HSL
NRTZ is the most relevant over 1st Nyquist zone, 1st half of 2nd Nyquits zone and 4th Nyquist zone.
RF mode is the best choice for 2nd half of 2nd Nyquist Zone and 3rd Nyquist zone.
RTZ gives relevant performances over the three first Nyquist zones.
The spikes in the SFDR are caused by normalization artefacts due to the Sinc(x) null
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
98
198
298
398
498
598
698
798
898
998
1098
1198
1298
1398
1498
1598
1698
1798
1898
1998
2098
2198
2298
2398
2498
2598
2698
2798
2898
2998
3098
3198
3298
3398
3498
3598
3698
3798
3898
3998
4098
4198
4298
4398
4498
98
198
298
398
498
598
698
798
898
998
1098
1198
1298
1398
1498
1598
1698
1798
1898
1998
2098
2198
2298
2398
2498
2598
2698
2798
2898
2998
3098
3198
3298
3398
3498
3598
3698
3798
3898
3998
4098
4198
4298
4398
4498
Somme de SFDR_dBc Somme de SFDR_dBm
-3 - 2999 - Mux4:1_NRZ
-3 - 2999 - Mux4:1_RTZ
-3 - 2999 - Mux4:1_RF
-3 - 2999 - Mux4:1_NRTZ
Spurious Free Dynamic Range (excl. Fclock) [dBc] Highest Spur Level (excl. Fclock) [dBm]
1st Nyquist 2nd Nyquist 3rd Nyquist
1st Nyquist 2nd Nyquist 3rd Nyquist
Output frequency (MHz)
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
98
198
298
398
498
598
698
798
898
998
1098
1198
1298
1398
1498
1598
1698
1798
1898
1998
2098
2198
2298
2398
2498
2598
2698
2798
2898
2998
3098
3198
3298
3398
3498
3598
3698
3798
3898
3998
4098
4198
4298
4398
4498
98
198
298
398
498
598
698
798
898
998
1098
1198
1298
1398
1498
1598
1698
1798
1898
1998
2098
2198
2298
2398
2498
2598
2698
2798
2898
2998
3098
3198
3298
3398
3498
3598
3698
3798
3898
3998
4098
4198
4298
4398
4498
Somme de SFDR_dBc Somme de SFDR_dBm
-3 - 2000 - Mux4:1_NRZ
-3 - 2000 - Mux4:1_RTZ
-3 - 2000 - Mux4:1_RF
-3 - 2000 - Mux4:1_NRTZ
Spurious Free Dynamic Range (excl. Fclock) [dBc] Highest Spur Level (excl. Fclock) [dBm]
1st Nyquist 2nd Nyquist 3rd Nyquist 4th Nyquist
1st Nyquist 2nd Nyquist 3rd Nyquist 4th Nyquist
Output frequency (MHz)
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EV12DS130BZP
Figure 7-16. Comparison of NRZ and NRTZ Modes at Full Scale and –3 dBFS at 2999 MSps: SFDR and HSL (Excluding
Fclock)
NRTZ gives better performances over 1st and 2nd Nyquist zone, and is much less sensitive to output
level.
Figure 7-17. Comparison of NRTZ and RTZ Modes at Full Scale and –3 dBFS at 2999 MSps: SFDR and HSL
NRTZ is more relevant for 1st Nyquist zone and 1st half of 2nd Nyquist zone. Beyond middle of second
Nyquist zone RTZ mode is more relevant.
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
98
198
298
398
498
598
698
798
898
998
1098
1198
1298
1398
1498
1598
1698
1798
1898
1998
2098
2198
2298
2398
2498
2598
2698
2798
2898
2998
3098
3198
3298
3398
3498
3598
3698
3798
3898
3998
4098
4198
4298
4398
4498
98
198
298
398
498
598
698
798
898
998
1098
1198
1298
1398
1498
1598
1698
1798
1898
1998
2098
2198
2298
2398
2498
2598
2698
2798
2898
2998
3098
3198
3298
3398
3498
3598
3698
3798
3898
3998
4098
4198
4298
4398
4498
-3 - 2999 - Mux4:1_NRZ
-3 - 2999 - Mux4:1_NRTZ
0 - 2999 - Mux4:1_NRZ
0 - 2999 - Mux4:1_NRTZ
1st Nyquist 2nd Nyquist 3rd Nyquist
1st Nyquist 2nd Nyquist 3rd Nyquist
Output frequency (MHz)
Highest Spur Level (excl. Fclock)[dBm]Spurious Free Dynamic Range (excl. Fclock) [dBc]
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
98
198
298
398
498
598
698
798
898
998
1098
1198
1298
1398
1498
1598
1698
1798
1898
1998
2098
2198
2298
2398
2498
2598
2698
2798
2898
2998
3098
3198
3298
3398
3498
3598
3698
3798
3898
3998
4098
4198
4298
4398
4498
98
198
298
398
498
598
698
798
898
998
1098
1198
1298
1398
1498
1598
1698
1798
1898
1998
2098
2198
2298
2398
2498
2598
2698
2798
2898
2998
3098
3198
3298
3398
3498
3598
3698
3798
3898
3998
4098
4198
4298
4398
4498
-3 - 2999 - Mux4:1_RTZ
-3 - 2999 - Mux4:1_NRTZ
0 - 2999 - Mux4:1_RTZ
0 - 2999 - Mux4:1_NRTZ
1st Nyquist 2nd Nyquist 3rd Nyquist
1st Nyquist 2nd Nyquist 3rd Nyquist
Output frequency (MHz)
Highest Spur Level (excl. Fclock)[dBm]Spurious Free Dynamic Range (excl. Fclock) [dBc]
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1077H–BDC–12/14
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EV12DS130BZP
e2v semiconductors SAS 2014
Figure 7-18. Comparison of RTZ and RF Modes at Full Scale and –3 dBFS at 2999 MSps: SFDR and HSL
RF mode gives better performance over 3rd Nyquist zone.
Figure 7-19. Comparison of NRZ and NRTZ Modes at Full Scale and –3 dBFS at 2000 MSps: SFDR and HSL (Excluding
Fclock)
NRTZ linearity is slightly improved reducing the sampling rate to 2000 MSps, possibility of operation over
the 4th Nyquist zone is demonstrated.
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
98
198
298
398
498
598
698
798
898
998
1098
1198
1298
1398
1498
1598
1698
1798
1898
1998
2098
2198
2298
2398
2498
2598
2698
2798
2898
2998
3098
3198
3298
3398
3498
3598
3698
3798
3898
3998
4098
4198
4298
4398
4498
98
198
298
398
498
598
698
798
898
998
1098
1198
1298
1398
1498
1598
1698
1798
1898
1998
2098
2198
2298
2398
2498
2598
2698
2798
2898
2998
3098
3198
3298
3398
3498
3598
3698
3798
3898
3998
4098
4198
4298
4398
4498
-3 - 2999 - Mux4:1_RTZ
-3 - 2999 - Mux4:1_RF
0 - 2999 - Mux4:1_RTZ
0 - 2999 - Mux4:1_RF
1st Nyquist 2nd Nyquist 3rd Nyquist
1st Nyquist 2nd Nyquist 3rd Nyquist
Output frequency (MHz)
Highest Spur Level (excl. Fclock)[dBm]Spurious Free Dynamic Range (excl. Fclock) [dBc]
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
98
198
298
398
498
598
698
798
898
998
1098
1198
1298
1398
1498
1598
1698
1798
1898
1998
2098
2198
2298
2398
2498
2598
2698
2798
2898
2998
3098
3198
3298
3398
3498
3598
3698
3798
3898
3998
4098
4198
4298
4398
4498
98
198
298
398
498
598
698
798
898
998
1098
1198
1298
1398
1498
1598
1698
1798
1898
1998
2098
2198
2298
2398
2498
2598
2698
2798
2898
2998
3098
3198
3298
3398
3498
3598
3698
3798
3898
3998
4098
4198
4298
4398
4498
Somme de SFDR_dBc Somme de SFDR_dBm
-3 - 2000 - Mux4:1_NRZ
-3 - 2000 - Mux4:1_NRTZ
0 - 2000 - Mux4:1_NRZ
0 - 2000 - Mux4:1_NRTZ
Spurious Free Dynamic Range (excl. Fclock) [dBc] Highest Spur Level (excl. Fclock) [dBm]
1st Nyquist 2nd Nyquist 3rd Nyquist 4th Nyquist 1st Nyquist 2nd Nyquist 3rd Nyquist 4th Nyquist
Output frequency (MHz)
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1077H–BDC–12/14
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EV12DS130AZP
EV12DS130BZP
Figure 7-20. Comparison of NTRZ and RTZ Modes at Full Scale and –3 dBFS at 2000 MSps: SFDR and HSL
(Excluding Fclock)
NRTZ mode is relevant in 1st, 2nd Nyquist zones and is still usable over 4th Nyquist zone with SFDR in
excess of 50 dBc.
7.2.3 Single tone measurements: typical spectra at 3Gsps
The following figures show typical SFDR spectra obtained for the four DAC modes on an
EV12DS130A/B device.
Conditions: typical power supplies, ambient temperature, MUX4:1, Fs = 3 Gsps.
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
98
198
298
398
498
598
698
798
898
998
1098
1198
1298
1398
1498
1598
1698
1798
1898
1998
2098
2198
2298
2398
2498
2598
2698
2798
2898
2998
3098
3198
3298
3398
3498
3598
3698
3798
3898
3998
4098
4198
4298
4398
4498
98
198
298
398
498
598
698
798
898
998
1098
1198
1298
1398
1498
1598
1698
1798
1898
1998
2098
2198
2298
2398
2498
2598
2698
2798
2898
2998
3098
3198
3298
3398
3498
3598
3698
3798
3898
3998
4098
4198
4298
4398
4498
Somme de SFDR_dBc Somme de SFDR_dBm
-3 - 2000 - Mux4:1_RTZ
-3 - 2000 - Mux4:1_NRTZ
0 - 2000 - Mux4:1_RTZ
0 - 2000 - Mux4:1_NRTZ
Spurious Free Dynamic Range (excl. Fclock) [dBc] Highest Spur Level (excl. Fclock) [dBm]
1st Nyquist 2nd Nyquist 3rd Nyquist 4th Nyquist 1st Nyquist 2nd Nyquist 3rd Nyquist 4th Nyquist
Output frequency (MHz)
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1077H–BDC–12/14
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EV12DS130BZP
e2v semiconductors SAS 2014
Figure 7-21. Typical SFDR spectrum in NRZ mode. Fout = 100MHz (1st Nyquist), MUX4:1, Fs = 3Gsps. SFDR = 67dBc
Figure 7-22. Typical SFDR spectrum in NRTZ mode. Fout = 1800MHz (2nd Nyquist), MUX4:1, Fs = 3Gsps.
SFDR = 61dBc
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1077H–BDC–12/14
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EV12DS130BZP
Figure 7-23. Typical SFDR spectrum in RTZ mode. Fout = 2900MHz (2nd Nyquist), MUX4:1, Fs = 3Gsps.
SFDR = 59dBc.
Figure 7-24. Typical SFDR spectrum in RF mode. Fout = 4400MHz (3rd Nyquist), MUX4:1, Fs = 3Gsps. SFDR = 56 dBc
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e2v semiconductors SAS 2014
7.2.4 Multi Tone Measurements
A five tones pattern (400 MHz, 500 MHz, 600 MHz, 700 MHz and 800 MHz) is applied to the DAC
operating at 3 Gsps and results are observed in the 2nd, 3rd, 4th and 5th Nyquist zones.
Results are given in the most relevant mode considering the Nyquist zone observed.
Figure 7-25. Observation of the 2nd Nyquist Zone (Tones are pushed from 2.2 GHz to 2.6 GHz): NRTZ, RF and RTZ
Modes
NRTZ mode: RF mode:
RTZ mode:
Fout (MH z) Pout (dBm) SFDR (freq) SFDR (dBc)
N R TZ 2200 -23,99 1800 -51,28
RTZ 2200 -24,53 1800 -55,97
RF 2200 -21,76 2700 -57,25
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Figure 7-26. Observation of the 3rd Nyquist Zone (Tones are pushed from 3.4GHz to 3.8GHz): RF and RTZ Modes
NRTZ performances are degraded because of the sinc attenuation (first notch in the first half of the 3rd
Nyquist zone).
Figure 7-27. Observation of the 4th Nyquist Zone (Tones are pushed from 5.2 GHz to 5.6 GHz): NRTZ and RF Modes
RF mode: RTZ mode:
Fout (MHz) Pout (dBm) SFDR (freq) SFDR (dBc)
NRTZ 3400 –39.43 4000 –44.48
RTZ 3400 –28.77 3100 –55.14
RF 3400 –23.03 3100 –58.33
NRTZ mode RF mode
Fout (MHz) Pout (dBm) SFDR (freq) SFDR (dBc)
NRTZ 5200 –34.72 5000 –50.34
RTZ 5200 –40.37 4700 –45
RF 5200 –31.87 4700 –49.49
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1077H–BDC–12/14
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EV12DS130BZP
e2v semiconductors SAS 2014
RTZ mode is degraded because of the sinc attenuation (first notch at the end of the 4th Nyquist zone).
RF mode offers significantly more power than RTZ mode, this is why we still have acceptable
performances.
NRTZ operation is possible because the 4th Nyquist zone is fully included in the secondary spectral lobe.
Figure 7-28. Observation of the 5th Nyquist Zone (Tones are pushed from 6.4 GHz to 6.8 GHz): NRTZ Mode
NRTZ mode is still usable in the 5th Nyquist zone (SFDR in excess of 46 dB).
Fout (MHz) Pout (dBm ) SFDR (freq) SFDR (dBc)
N RTZ 6400 -38,64 7000 -46,92
RTZ 6800 -46,69 7000 -39,25
RF 6400 -46,89 7000 -38,01
51
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EV12DS130BZP
7.2.5 Direct Microwave Synthesis Capability Measurements: ACPR
Measurements given hereafter are performed on the DAC at 3 Gsps with a 10 MHz wide QPSK pattern
centered on 800 MHz.
Results are observed in 2nd, 3rd, 4th and 5th Nyquist zones and are given only for the most relevant
modes (that is RF and/or NRTZ modes).
Figure 7-29. NRTZ Mode, 2nd Nyquist: Center Frequency is pushed to 3 GHz – 800 MHz = 2.2 GHz
ACPR is in excess of 62 dB. DMWS capability is proven for second Nyquist in NRTZ mode.
Figure 7-30. RF Mode, 2nd Nyquist: Center Frequency is pushed to 3 GHz – 800 MHz = 2.2 GHz
ACPR is in excess of 60 dB. DMWS capability is proven for the second Nyquist zone in RF mode with
slightly reduced dynamic range regarding NRTZ mode but with increased output power.
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e2v semiconductors SAS 2014
Figure 7-31. RF Mode, 3rd Nyquist Zone: Center Frequency is pushed to 3 GHz+ 800 MHz = 3.8 GHz
ACPR is in excess of 59 dB. DMWS capability is proven for the third Nyquist zone in RF mode.
Note: due to the notch of available Pout near the middle of the third Nyquist zone, the NRTZ mode is not relevant
for DMWS in the third Nyquist zone.
Figure 7-32. NRTZ Mode, 4th Nyquist Zone: Center Frequency is pushed to 6 GHz – 800 MHz = 5.2 GHz
ACPR is in excess of 54 dB. DMWS capability is proven for the fourth Nyquist zone in NRTZ mode.
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Figure 7-33. RF Mode, 4th Nyquist Zone: Center Frequency is pushed to 6 GHz – 800 MHz = 5.2 GHz
ACPR is in excess of 53 dB. DMWS capability is proven for the fourth Nyquist zone in RF mode.
Note due to a notch of available Pout near the end of the 4th Nyquist zone in RF output mode, for DMWS
beyond middle of 4th Nyquist zone it is recommended to use the NRTZ output mode instead of the RF
output mode.
Figure 7-34. NRTZ Mode, 5th Nyquist Zone: Center Frequency is pushed to 6 GHz + 800 MHz = 6.8 GHz
ACPR is still in excess of 47 dB. DMWS capability if proven for the fifth Nyquist zone in NRTZ mode with
reduced available dynamic range.
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7.2.6 DOCSIS v3.0 Capability Measurements
Measurements hereafter have been carried out on a soldered device EV12DS130A/B, in NRTZ mode at
3 GSps.
Note: Results illustrated hereafter (spectrum and zoom on notch) come from measurement on a EV12DS130A/B
device (CI-CGA255 package). Measurements have been carried out using the ACP treatment of the
spectrum analyzer Rhode & Schwarz FSU8, in RMS detection mode.
Figure 7-35. ACPR 1 Channel Centered on 300 MHz, Output Mode NRTZ
Figure 7-36. ACPR 1 Channel Centered on 900 MHz, Output Mode NRTZ
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Figure 7-37. ACPR 1 channel centered on 300 MHz, Output Mode NRTZ
Figure 7-38. ACPR 4 Channels Centered on 300 MHz, Output Mode NRTZ
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e2v semiconductors SAS 2014
Figure 7-39. ACPR 1 Channel Centered on 900 MHz, Output Mode NRTZ
Figure 7-40. ACPR 4 Channels Centered on 900 MHz, Output Mode NRTZ
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7.2.7 NPR Performance
NPR measurements have been carried out at optimum loading factor (LF) for a 12 bit DAC, that is
–14 dBFS, with the DAC operating at 3 Gsps.
SNR can be computed from SNR measurement with the formula: SNR[dB] = NPR[dB] + ILF[dB]I – 3.
ENOB can be computed with the formula: ENOB = (SNR[dB] – 1.76) / 6.02.
Note: Results illustrated hereafter (spectrum and zoom on notch) come from measurement on a EV12DS130A/B
device (CI-CGA255 package). Measurements have been carried out using the ACP treatment of the
spectrum analyzer Rhode & Schwarz FSU8, in RMS detection mode.
Figure 7-41. NPR in First Nyquist Zone, 20 MHz to 900 MHz Noise Pattern with a 25 MHz Notch Centered on 450 MHz,
NRZ mode
Measured average NPR: 50.02 dB, therefore SNR = 61.02 dB and ENOB = 9.84 bit
Effects at low frequency are due to balun and pattern.
Figure 7-42. NPR in First Nyquist Zone, 20 MHz to 900 MHz Noise Pattern with a 25 MHz Notch Centered on 450 MHz,
NRTZ Mode
Measured average NPR: 51.36 dB, therefore SNR = 62.36 dB and ENOB = 10.07 bit.
Effects at low frequency are due to balun and pattern.
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Figure 7-43. NPR in First Nyquist Zone, 10 MHz to 450 MHz Noise Pattern with a 12.5 MHz Notch centered on 225 MHz,
NRTZ Mode at Fs = 1.5 Gsps
Measured average NPR: 55.7 dB, therefore SNR = 66.7 dB and ENOB = 10.8 bit.
Effects at low frequency are due to balun and pattern.
Figure 7-44. NPR in second Nyquist Zone, 1520 MHz to 2200 MHz Noise Pattern with a 25 MHz Notch centered on
1850 MHz, RTZ mode
Measured average NPR: 44.6 dB, therefore SNR = 55.6 dB and ENOB = 8.94 bit
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Figure 7-45. NPR in second Nyquist Zone, 1520 MHz to 2200 MHz noise pattern with a 25 MHz notch centered on
1850 MHz, RF Mode
Measured average NPR: 42.78 dB, therefore SNR = 53.78 dB and ENOB = 8.64 bit
Figure 7-46. NPR in second Nyquist Zone, 2200 MHz to 2880 MHz Noise Pattern with a 25 MHz Notch centered on
2550 MHz, RF Mode
Measured average NPR: 42.56 dB, therefore SNR = 53.56 dB and ENOB = 8.6 bit.
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Figure 7-47. NPR in Third Nyquist Zone, 3050 MHz to 3700 MHz Noise Pattern with a 25 MHz Notch Centered on
3375 MHz, RF Mode
Measured average NPR: 40.08 dB, therefore SNR = 51.08 dB and ENOB = 8.19 bit
The following figures reflect the stability of NPR in first Nyquist in NRTZ mode (and therefore SNR and
ENOB) versus temperature.
Measurements have been carried out at nominal power supply on an EV12DS130A/B, at 3 Gsps, with
the FSU8 spectrum analyzer in RMS detection mode.
Figure 7-48. Drift of NPR and Associated SNR and ENOB in First Nyquist in NRTZ Mode from Tj = –30°C to Tj = 125°C
Optimum is at Tj = 40°C, degradation over temp is within 1 dB (or 0.15 effective bit).
NPR DAC (VN15A) // Packa g e : FpBGA
N RTZ @-14dB (20MHz to 900MHz) span:25MHz notch centered : 450MHz
1st Nyquist
47.80
48.00
48.22
48.57
48.85
48.78
48.35
48.57
47.6
47.8
48.0
48.2
48.4
48.6
48.8
49.0
-40-200 20406080100120140
Tj (°C)
NPR (dB)
SNR DAC (VN15A) // Packa g e : FpBGA
N RTZ @-14dB (20MHz to 900MHz) span:25MHz notch centered : 450MHz
1st Nyquist
59.57
59.35
59.78 59.85
59.57
59.22
59.00
58.80
58.6
58.8
59.0
59.2
59.4
59.6
59.8
60.0
-40 -20 0 20 40 60 80 100 120 140
Tj (°C)
SNR (dB)
ENO B DAC (V N1 5A) // Pack ag e : FpBGA
N RTZ @-14dB (20MHz to 900MHz) span:25MHz notch centered : 450MHz
1st Nyquist
9.60
9.57
9.64 9.65
9.60
9.54
9.51
9.48
9.45
9.50
9.55
9.60
9.65
9.70
-40 -20 0 20 40 60 80 100 120 140
Tj (°C)
ENOB (Bi t)
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Measurements hereafter have been carried out on an EV12AS130AGS device at 3 Gsps, with the FSU8
spectrum analyzer in RMS detection mode.
Figure 7-49. Drift of NPR vs temperature in the 4 Output Modes at Nominal Supply
Conclusion: performances are stable in the four output modes against temperature.
Figure 7-50. NPR vs Power Supply Level in the 4 Output Modes at Room Temperature
Conditions: Typical, excepted: power supplies
Min: VCCA: 4.75V // VCCA3 = VCCD = 3.15V
Typ: VCCA: 5.0V // VCCA3 = VCCD = 3.3V
Max: VCCA: 5.25V // VCCA3 = VCCD = 3.45V.
Conclusion: performances are fairly stable against power supply.
Note: NPR performance at lower clock frequencies is affected by power up sequence. See application
note 1087 for further details.
NPR vs. temperature
38
40
42
44
46
48
50
52
54
Tj = -30˚C Tj = +44.5˚C Tj = +125˚C
Temperature (˚C)
NPR (dB)
NRZ @-14dB (20MHz to 900MHz)
span:25MHz notch centered :
450MHz
NRTZ @-14dB (20MHz to 900MHz)
span:25MHz notch centered :
450MHz
RTZ @-14dB (1520MHz to 2200MHz)
span:25MHz notch centered :
1850MHz
RF @-14dB (1520MHz to 2200MHz)
span:25MHz notch centered :
1850MHz
RF @-14dB (2200MHz to 2880MHz)
span:25MHz notch centered :
2550MHz
RF @-14dB (3050MHz to 3700MHz)
span:25MHz notch centered :
3375MHz
NPR vs. power supplies
38
40
42
44
46
48
50
52
54
Min Typ Max
Power supplies
NPR (dB)
NRZ @-14dB (20MHz to 900MHz)
span:25MHz notch centered :
450MHz
NRTZ @-14dB (20MHz to 900MHz)
span:25MHz notch centered :
450MHz
RTZ @-14dB (1520MHz to 2200MHz)
span:25MHz notch centered :
1850MHz
RF @-14dB (1520MHz to 2200MHz)
span:25MHz notch centered :
1850MHz
RF @-14dB (2200MHz to 2880MHz)
span:25MHz notch centered :
2550MHz
RF @-14dB (3050MHz to 3700MHz)
span:25MHz notch centered :
3375MHz
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7.2.8 Spectrum over 4 Nyquist Zones in the Four Output Modes
Observation of a 1GHz broadband pattern with a 25 MHz notch centered on 500 MHz spectrum over
4 Nyquist zones at 3 Gsps (that is from DC to 6 GHz), measurements performed on an EV12DS130A/B
device (CI-CGA 255 package, with an overall 6 GHz bandwidth limitation).
By periodisation of a sampled system each tone Fi of the pattern in the 1st Nyquist zone is duplicated as
follows:
•2
nd Nyquist Zone: tone at Fclock - Fi
•3
rd Nyquist Zone: tone at Fclock + Fi
•4
th Nyquist Zone: tone at 2*Fclock - Fi
Figure 7-51. Spectrum over 4 Nyquist Zones at 3 Gsps in NRZ Output Mode
First Zero of the sinc() function is at Fclock.
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Figure 7-52. Spectrum over 4 Nyquist Zones at 3 Gsps in NRTZ Output Mode
Figure 7-53. Spectrum over 4 Nyquist Zones at 3 Gsps in RTZ Output Mode
First Zero of the sinc() function is slightly before 2*Fclock which indicates that the duty cycle of RTZ
function is a little bit more than 50%, this is due to the balun which introduced some phase error beyond
the 180 degrees between CLK and CLKN thus creating a duty cycle on the clock actually seen by the
DAC.
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Figure 7-54. Spectrum over 4 Nyquist Zones at 3 Gsps in RF Output Mode
Measurements are showing a pretty good fit with theory, see Section 5.3 on page 17.
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8. Application Information
For further details, please refer to application note 1087.
8.1 Analog Output (OUT/OUTN)
The analog output should be used in differential way as described in the figures below.
If the application requires a single-ended analog output, then a balun is necessary to generate a single-
ended signal from the differential output of the DAC.
Figure 8-1. Analog Output Differential Termination
Figure 8-2. Analog Output Using a 1/ 2 Balun
Note: The AC coupling capacitors should be chosen as broadband capacitors with a value depending on the
application.
MUXDAC
VCCA5
100nF
100nF
OUT
OUTN
Current
Switches and
sources
AGND
50Ω
50Ω
50Ω lines
OUT
OUTN
AGND
MUXDAC
AGND
50Ω termination
50Ω line OUT
50Ω line
1/sqrt2
50Ω line
100nF
100nF
OUT
OUTN
VCCA5
Current
Switches and
sources
50Ω
AGND
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8.2 Clock Input (CLK/CLKN)
The DAC input clock (sampling clock) should be entered in differential mode as described in Figure 5-9.
Figure 8-3. Clock Input Differential Termination
Note: The buffer is internally pre-polarized to 2.5V (buffer between VCC5 and AGND).
Figure 8-4. Clock Input Differential with Balun
Note: The AC coupling capacitors should be chosen as broadband capacitors with a value depending on the
application.
Differential
sinewave 50Ω
Source
CLK
CLKN
DAC Clock Input Buffer
50Ω
50Ω
AGND
3.75 pF
C = 100pF
C = 100pF
2.5 V
50Ω line
50Ω line
50Ω line
50Ω line
Single
sinewave 50Ω
Source
CLK
CLKN
DAC Clock Input Buffer
50Ω
50Ω
AGND
C = 100pF
C = 100pF
2.5 V
50Ω line
50Ω line
50Ω line
1/sqrt2
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8.3 Digital Data, SYNC and IDC Inputs
LVDS buffers are used for the digital input data, the reset signal (active high) and IDC signal.
They are all internally terminated by 2 × 50 to ground via a 3.75 pF capacitor.
Figure 8-5. Digital Data, Reset and IDC Input Differential Termination
Notes: 1. In the case when only two ports are used (2:1 MUX ratio), then the unused data should be left open
(no connect).
2. Data and IDC signals should be routed on board with the same layout rules and the same length than
the data.
3. In case SYNC is not used, it is necessary to bias the SYNC to 1.1V and SYNCN to 1.4V on
EV12DS130A.
8.4 DSP Clock
The DSP, DSPN output clock signals are LVDS compatible.
They have to be terminated via a differential 100 termination as described in Figure 5-11.
Figure 8-6. DSP Output Differential Termination
LVDS Output
Buffer
In
InN
DAC Data and Sync Input Buffer
50Ω
50Ω
DGND
3.75 pF
50Ω line
50Ω line
DAC Output DSP
Differential Output
buffers
Z0 = 50Ω
Z0 = 50Ω
100ΩTermination
DSP
DSPN
To Load
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8.5 Control Signal Settings
The MUX, MODE, PSS and OCDS control signals use the same static input buffer.
Logic “1” = 200 K to Ground, or tied to VCCD = 3.3V or left open
Logic “0” = 10 to Ground or Grounded
Figure 8-7. Control Signal Settings
The control signal can be driven by FPGA.
Figure 8-8. Control Signal Settings with FPGA
Logic “1” > VIH or VCCD = 3.3V
Logic “0” < VIL or 0V
8.6 HTVF and STVF Control Signal
The HTVF and STVF control signals is a 3.3V CMOS output buffer.
These signals could be acquired by FPGA.
Figure 8-9. Control Signal Settings with FPGA
In order to modify the VOL/VOH value, pull up and pull down resistances could be used, or a potential
divider.
8.7 GA Function Signal
This function allows adjustment of the internal gain of the DAC.
The gain of the DAC can be tuned with applied analog voltage from 0 to VCCA3
This analog input signal could be generated by a DAC controlled by FPGA or microcontroller.
Figure 8-10. Control Signal Settings with GA
10Ω
200 KΩ
GND GND
Control
Signal Pin
Control
Signal Pin
Control
Signal Pin
Not
Connected
Active Low Level (‘0’)
Inactive High Level (‘1’)
Control
Signal Pin
FPGA
HTVF STVF Control
Signal
FPGA
GA
DAC16b
FPGA n
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8.8 Power Supplies Decoupling and Bypassing
The DAC requires 3 distinct power supplies:
VCCA5 = 5.0V (for the analog core)
VCCA3 = 3.3V (for the analog part)
VCCD = 3.3V (for the digital part)
It is recommended to decouple all power supplies to ground as close as possible to the device balls with
100 pF in parallel to 10nF capacitors. The minimum number of decoupling pairs of capacitors can be
calculated as the minimum number of groups of neighboring pins.
4 pairs of 100pF in parallel to 10 nF capacitors are required for the decoupling of VCCA5. 4 pairs for the
VCCA3 is the minimum required and finally, 10 pairs are necessary for VCCD.
Figure 8-11. Power Supplies Decoupling Scheme
Each power supply has to be bypassed as close as possible to its source or access by 100 nF in parallel
to 22 µF capacitors (value depending of DC/DC regulators).
Analog and digital ground plane should be merged.
DAC 10-bit
AGND
AGND
DGND
100 pF
10 nF
100 pF
10 nF
100 pF
10 nF
X 4 (min)
X 4 (min)
X 10 (min)
VCCA5
VCCA3
VCCD
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8.9 Power Up Sequencing
For EV12DS130B there is no forbidden power-up sequence, nor power supplies dependency
requirement.
For EV12DS130A the following instructions must be implemented:
Power-up sequence:
It is necessary to raise VCCA5 power supply within the range 5.20V up to a recommended maximum of
5.60V during at least 1ms at power up. Then the supply voltage has to settle within 500 ms to a steady
nominal supply voltage within a range of 4.75V up to 5.25V.
A power-up sequence on VCCA5 that does not comply with the above recommendation will not
compromise the functional operation of the device. Only the noise floor will be affected.
Figure 8-12. Power-up Sequence
The rise time for any of the power supplies (VCCA5, VCCA3 and VCCD) shall be 10 ms.
At power-up a SYNC pulse is internally and automatically generated when the following sequence is
satisfied: VCCD, VCCA3 and VCCA5. To cancel the SYNC pulse at power-up, it is necessary to apply the
sequence: VCCA5, VCCA3, VCCD. (VCCA3 can not reach 0.5V until VCCA5 is greater than 4.5V. VCCD can not
reach 0.5V until VCCA3 is greater than 3.0V). Any other sequence may not have a deterministic SYNC
behaviour. See erratasheet (ref 1125) for specific condition of use relative to the SYNC operation.
Relationship between power supplies:
Within the applicable power supplies range, the following relationship shall always be satisfied
VCCA3 VCCD, taking into account AGND and DGND planes are merged and power supplies accuracy.
1 ms min
10 ms max
5.6V max 5.2V min
5.25V max 4.75V min
500 ms max
Time
VCCA5
3.45V max 3.15V min
VCCA3 > VCCD
VCCA3
VCCD
3V
4.5V
0.5V
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8.10 Balun Influence
It is important to know that balun characteristic may influence significantly DAC output spectral
response. Especially harmonic distortion can dramatically be degraded when part of the band of interest
lies out of the specified domain of the balun.
As depicted in the following figure an inappropriate balun choice can result in a strong increase in
harmonic peaks amplitude, thus degrading performances. The balun used in this measurement covers
only the 500MHz to 7GHz band so that the DC to 500MHz region of the first nyquist zone is distorted.
Figure 8-13. Observation of the 1st and 2nd nyquist zones in output mode RTZ with 0.5 GHz-7 GHz Balun
On the opposite, when appropriate balun is used the real device response is measured
Figure 8-14. Spectrum of the 1st Nyquist Zone, Output Mode RTZ with a 2 MHz to 2GHz Bandwidth Balun
As a consequence, one must be aware that optimum performances can only be reached when using a
balun optimal for the band of interest of the application. We specifically recommend selecting a balun
which frequency domain covers the whole band of interest (for instance one whole Nyquist zone).
H4 degradati on due
to Balun out of band
H3
Folded H1: 1518MHz
0 1.5 GHz 3 GHz
H1 : 1482MHz
Folded H3
Folded H2
H2 degradation due
to Balun out of band
Folded H4
H2 = - 82 dBm
residual impact of balun H3= -89 dbm
Balun :
2M – 2G
Fundamental :
1482MHz , - 3dFS
Images:
Fcloc k/16 +/- Fout
Images:
Fcloc k/8 +/- F out
Start 0 Hz 150 MHz Stop 1.5 GHz
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9. Package Information
9.1 fpBGA 196 Outline
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9.2 Land Pattern Recommendation
Figure 9-1. Land Pattern Recommendation
10. Thermal Characteristics fpBGA196
10.1 Thermal Resistance
Assumptions:
Still air
Pure conduction
No radiation
Heating zone = 5% of die surface
Rth Junction – bottom of Balls = 13.3°C/W
Rth Junction – board (JEDEC JESD-51-8) = 17.8°C/W
Rth Junction – top of case = 14.5°C/W
Assumptions:
Heating zone = 5% of die surface
Still air, JEDEC condition
Rth Junction – ambient (JEDEC) = 32°C/W
11. Differences between EV12DS130A and EV12DS130B
EV12DS130A and EV12DS130B exhibit the same dynamic performances.
EV12DS130B requires no specific dependency between power supplies nor power up sequences while
the EV12DS130A does require specific power up sequences as described in Section 8.9 on page 70.
Maximum supported sampling frequency with DSP clock feature for EV12DS130B is 2.1GHz due to
internal jitter. It is however possible to benefit from the EV12DS130B DAC performances up to 3GHz if
specific system architecture is implemented. Please refer to application AN1141 for further information.
No SYNC timing constraints (other than T1 T2) are required on EV12DS130B.
14 12 10 8 6 4 2
13 11 9 7 5 3 1
A
C
E
G
J
L
N
B
D
F
H
K
M
P
D
e
A
E
BE
e
b
D
BOTTOM VIEWTOP VIEW LAND PATTERN
RECOMMENDATIONS
C
ABCDEe b
15.00 15.00 1.21 13.00 13.00 1.00 0.45
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As a summary
When using EV12DS130A, please ensure your system fulfills those specific recommendations
• Power Up Sequence (See Section 8.9 on page 70)
• Power supplies dependency (see Section 8.9 on page 70)
• SYNC pin have to be driven in any case
• Please refer to errata sheet 1125
When using EV12DS130B, please ensure your system fulfills those specific recommendations
• In case sampling frequency is above 2.1 Gsps, please read the AN1141 “Using EV1xDS130B at
sampling rate higher than 2.1GSps”
Please refer to application note AN1140 "Replacing EV1xDS130A with EV1xDS130B” for further details
12. Ordering Information
Please refer to datasheet details and application notes before ordering.
Table 12-1. Ordering Information
Part Number Package Lead Finish Temperature Range Screening Level Comments
EV12DS130A
EVX12DS130AZPY fpBGA196
RoHS SAC 305 Ambient Prototype
EV12DS130ACZPY fpBGA196
RoHS SAC 305 0°C < Tc, Tj < 90°C Commercial « C »
Grade
EV12DS130AVZPY fpBGA196
RoHS SAC 305 –40°C < Tc, Tj < 110°C Industrial « V » Grade
EV12DS130AZPY-EB fpBGA196
RoHS NA Ambient Prototype Evaluation board
EVX12DS130AZP fpBGA196 SnPb 63/37 Ambient Prototype Contact sales for
availability
EV12DS130AVZP fpBGA196 SnPb 63/37 –40°C < Tc, Tj < 110°C Industrial « V » Grade Contact sales for
availability
EV12DS130B
EVX12DS130BZPY fpBGA196
RoHS SAC 305 Ambient Prototype
EV12DS130BCZPY fpBGA196
RoHS SAC 305 0°C < Tc, Tj < 90°C Commercial « C »
Grade
EV12DS130BVZPY fpBGA196
RoHS SAC 305 –40°C < Tc, Tj < 110°C Industrial « V » Grade
EV12DS130BZPY-EB fpBGA196
RoHS NA Ambient Prototype Evaluation board
EV12DS130BVZP fpBGA196 SnPb 63/37 –40°C < Tc, Tj < 110°C Industrial « V » Grade Contact sales for
availability
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13. Revision History
This table provides revision history for this document.
Table 13-1. Revision History
Rev. No Date Substantive Change(s)
1077H December 2014 Table 6-1 on page 28: VCCD pin F10 added
Section 5.5 on page 24: OCDS [10] not allowed
1077G November 2014 Figure 1-1 on page 2: Typo error
1077F October 2014
Introduction and description of EV12DS130B
New Section 11. ”Differences between EV12DS130A and EV12DS130B” on page 73
Table 3-9, “Coding Table (Theorical values),” on page 14: typo error on lines (RTZ) and
(NRTZ)
Section 5.1 ”DSP Output Clock” on page 17 updated
Section 5.3 ”MODE Function” on page 17: equations updated
Section 5.4 ”PSS (Phase Shift Select Function)” on page 22 updated
Section 5.8 ”Synchronization functions for multi-DAC operation” on page 26 updated
Figure 7-5 on page 38 updated
Figure 7-13 on page 41 updated
New Section 7.2.3 ”Single tone measurements: typical spectra at 3Gsps” on page 45
New Section 8.10 ”Balun Influence” on page 71
Table 12-1, “Ordering Information,” on page 74 added column Lead Finish and added part
number EV12DS130AVZP and all EV12DS130B part numbers
1077E December 2013 Table 3-3, “Electrical Characteristics,” on page 5: typo error on note 7: VCCA3 VCCD
1077D December 2013 Table 3-2, “Recommended Conditions of Use,” on page 4: typo error on note 2:
VCCA3 VCCD
1077C November 2013
Typo errors corrections
OCDS restrictions to OCDS1 & 2
HTVF STVF flag application clarifications
Power sequencing modification, relative to SYNC operation
1077B July 2012
Typo errors corrections
Absolute max rating clarifications
Addition of pin equivalent schematic description
Power up sequencing recommendation
1077A February 2012 Initial revision
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Table of Contents
Main Features............................................................................................ 1
Performances............................................................................................ 1
Applications .............................................................................................. 2
1 Block Diagram .......................................................................................... 2
2 Description ............................................................................................... 2
3 Electrical Characteristics ........................................................................ 3
3.1 Absolute Maximum Ratings .................................................................................. 3
3.2 Recommended Conditions of Use ........................................................................4
3.3 Electrical Characteristics ......................................................................................5
3.4 AC Electrical Characteristics ................................................................................7
3.5 Timing Characteristics and Switching Performances .........................................11
3.6 Explanation of Test Levels .................................................................................13
3.7 Digital Input Coding Table ..................................................................................14
4 Definition of Terms ................................................................................ 15
5 Functional Description .......................................................................... 16
5.1 DSP Output Clock ..............................................................................................17
5.2 Multiplexer ..........................................................................................................17
5.3 MODE Function ..................................................................................................17
5.4 PSS (Phase Shift Select Function) .....................................................................22
5.5 Output Clock Division Select Function ...............................................................24
5.6 Synchronization FPGA-DAC: IDC_P, IDC_N, HTVF and STVF Functions ........25
5.7 OCDS, MUX Combinations Summary ................................................................26
5.8 Synchronization functions for multi-DAC operation ............................................26
5.9 Gain Adjust GA Function ....................................................................................27
5.10 Diode Function ...................................................................................................28
6 PIN Description ...................................................................................... 29
7 Characterization Results ....................................................................... 36
7.1 Static Performances ...........................................................................................36
7.2 AC Performances ............................................................................................... 38
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8 Application Information ........................................................................ 65
8.1 Analog Output (OUT/OUTN) ..............................................................................65
8.2 Clock Input (CLK/CLKN) ....................................................................................66
8.3 Digital Data, SYNC and IDC Inputs ....................................................................67
8.4 DSP Clock ..........................................................................................................67
8.5 Control Signal Settings ....................................................................................... 68
8.6 HTVF and STVF Control Signal ......................................................................... 68
8.7 GA Function Signal ............................................................................................68
8.8 Power Supplies Decoupling and Bypassing ....................................................... 69
8.9 Power Up Sequencing ........................................................................................70
8.10 Balun Influence ................................................................................................... 71
9 Package Information ............................................................................. 72
9.1 fpBGA 196 Outline .............................................................................................72
9.2 Land Pattern Recommendation ..........................................................................73
10 Thermal Characteristics fpBGA196 ..................................................... 73
10.1 Thermal Resistance .........................................................................................73
11 Differences between EV12DS130A and EV12DS130B ........................ 73
12 Ordering Information ............................................................................. 74
13 Revision History .................................................................................... 75
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use thereof and also reserves the right to change the specification of goods without prior notice. e2v accepts no liability beyond that set out in its
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support and assistance. e2v technologies reserves the right to modify, make corrections, improvements and other changes to its products and
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