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Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA
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© 2005 Fairchild Semiconductor Corporation DS500202 www.fairchildsemi.com
January 1999
Revised June 2005
74LVX161284 Low Voltage IEEE 161284 Translating Transceiver
74LVX161284
Low Voltage IEEE 161284 Translating Transceiver
General Descript ion
The LVX161284 contains eight bidirectional data buffers
and eleven control/status buffers to implement a full
IEEE 1284 compliant interface. The device supports the
IEEE 1284 standard and is intended to be used in an
Extended Capabilities Port mode ( ECP). The pinout allows
for easy connection from the Peripheral (A-side) to the
Host (cable side).
Outputs on the cable side can be configured to be either
open drai n or h igh dri ve (
r
14 mA) a nd are connect ed t o a
separate pow er supply pin (V CC-cable) to allow these out-
puts to be driven by a higher supply voltage than the A-
side. The pull-up and pull-down series termination resis-
tance of these outputs on the cable side is optimized to
drive an ext ern al ca bl e . In add it ion , all inpu ts (exce pt HLH)
and outputs on the cable side contain internal pull-up resis-
tors connected to the VCC-cable supply to provide proper
termination and pull-ups for open drain mode.
Outputs on the Peripheral side are standard low-drive
CMOS outputs designed to interface with 3V logic. The DIR
input controls data flow on the A1–A8/B1–B8 transceiver
pins.
Features
■Supports I EEE 1284 Level 1 and Level 2 signaling
standards for bidirectional parallel communications
between personal computers and printing peripherals
■Translation capability allows outputs on the cable side to
interface with 5V signals
■All inputs have hysteresis to provide noise margin
■B and Y output resistance optimized to drive external
cable
■B and Y outpu ts in high impedan ce mode duri ng power
down
■Inputs and outputs on cable side have internal pull-up
resistors
■Flow-through pin configuration allows easy interface
between the “Peripheral and Host”
■Replaces the function of two (2) 74ACT1284 devices
Ordering Code
Device a l s o av ailable in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram Pin Descripti ons
Order Num b er Packag e Num b er Packa ge Des cri pt io n
74LVX161284MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74L VX161284MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
HD High Drive Enable Input (Active HIGH)
DIR Direction Control Input
A1–A8Inputs or Outputs
B1–B8Inputs or Outputs
A9–A13 Inputs
Y9–Y13 Outputs
A14–A17 Outputs
C14–C17 Inputs
PLHIN Peripheral Logic HIGH Input
PLH Peripheral Logic HIGH Output
HLHIN Host Logic HIGH Input
HLH Host Logic HIGH Output
www.fairchildsemi.com 2
74LVX161284
Logic Symbol
Truth Table
Note 1: Y9–Y13 Open Drain Outputs
Note 2: B1–B8 Open Drain Outputs
Logic Diagram
Inputs Outputs
DIR HD
LLB
1–B8 Data to A1–A8, and
A9–A13 Data to Y9–Y13 (Note 1)
C14–C17 Data to A14–A17
PLH Open Drain Mode
LHB
1–B8 Data to A1–A8, and
A9–A13 Data to Y9–Y13
C14–C17 Data to A14–A17
HLA
1–A8 Data to B1–B8 (Note 2)
A9–A13 Data to Y9–Y13 (Note 1)
C14–C17 Data to A14–A17
PLH Open Drain Mode
HHA
1–A8 Data to B1–B8
A9–A13 Data to Y9–Y13
C14–C17 Data to A14–A17
3 www.fairchildsemi.com
74LVX161284
Absolute Maxim um Ratings(Note 3) Recommended Operating
Conditions
Note 3: Absolute maximum ratings are values beyond which the device
may be damage d or have its us eful life im paired. Fairc hild does not recom-
mend o peration ou tside the databook specificat ions.
Note 4: Eith er v oltage limit or cu rrent limit is su ffici ent t o protect inp uts.
DC Electrical Characteristics
Supply Voltage
VCC
0.5V to
4.6V
VCC—Cable
0.5V to
7.0V
VCC—Cable Must Be
t
VCC
Input Vo l tage (VI)—(Note 4)
A1–A13, PLHIN, DIR, HD
0.5V to VCC
0.5V
B1–B8, C14–C17, HLHIN
0.5V to
5.5V (DC)
B1–B8, C14–C17, HLHIN
2.0V to
7.0V*
*40 ns Transient
Output Voltage (VO)
A1–A8, A14–A17, HLH
0.5V to VCC
0.5V
B1–B8, Y9–Y13, PLH
0.5V to
5.5V (DC)
B1–B8, Y9–Y13, PLH
2.0V to
7.0V*
*40 ns Transient
DC Output Current (IO)
A1–A8, HLH
r
25 mA
B1–B8, Y9–Y13
r
50 mA
PLH (Output LOW) 84 mA
PLH (Output HIGH)
50 mA
Input Diode Current (IIK)—(Note 4)
DIR, HD, A9–A13, PLH, HLH, C14–C17
20 mA
Output Diode Current (IOK)
A1–A8, A14–A17, HLH
r
50 mA
B1–B8, Y9–Y13, PLH
50 mA
DC Continuous VCC or Ground
Current
r
200 mA
Storage Temperature
65
q
C to
150
q
C
ESD (HBM) Last Passing Voltage 2000V
Supply Voltage
VCC 3.0V to 3.6V
VCC—Cable 3.0V to 5.5V
DC Input Voltage (VI)0V to V
CC
Open Drain Voltage (VO) 0V to 5.5V
Operating Temperature (TA)
40
q
C to
85
q
C
Symbol Parameter VCC
(V) VCC—Cable
(V)
TA
0
q
CT
A
40
q
C
Units Conditions
to
70
q
Cto
85
q
C
Guaranteed Limits
VIK Input Clamp 3.0 3.0
1.2
1.2 V Ii
18 m A
Diode Voltage
VIH Minimum An, Bn, PLHIN, DIR, HD 3.0–3.6 3.0–5.5 2.0 2.0 VHIGH Level Cn3.0–3.6 3.0–5.5 2.3 2.3
Input Voltage HLHIN 3.0–3.6 3.0–5.5 2.6 2.6
VIL Maximum An, Bn, PLHIN, DIR, HD 3.0–3.6 3.0–5.5 0.8 0.8 VLOW Level Cn3.0–3.6 3.0–5.5 0.8 0.8
Input Voltage HLHIN 3.0–3.6 3.0–5.5 1.6 1.6
'
VTMinimum Input An, Bn, PLHIN, DIR, HD 3.3 5.0 0.4 0.4 VVT
–VT
Hysteresis Cn3.3 5.0 0.8 0.8 VT
–VT
HLHIN 3.3 5.0 0.2 0.2 VT
–VT
VOH Minimum HIGH An, HLH 3.0 3.0 2.8 2.8
V
IOH
50
P
A
Level Output 3.0 3.0 2.4 2.4 IOH
4 mA
Voltage Bn, Yn3.0 3.0 2.0 2.0 IOH
14 mA
Bn, Yn3.0 4.5 2.23 2.23 IOH
14 mA
PLH 3.15 3.15 3.1 3.1 IOH
500
P
A
www.fairchildsemi.com 4
74LVX161284
DC Electrical Characteristics (Continued)
Note 5: Output im pedance is m easured wit h the output ac t iv e LOW and act iv e HIGH (HD
HIGH).
Note 6: Power-down leakage to VCC or VCC—Cable is tested by s im ultaneously forcing a ll pins on t he cable- si de (B1–B8, Y9–Y13, PLH, C14–C17 and HLHIN)
to 5.5V and measuring the resulting ICC or ICC—Cable.
Note 7: This param et er is guarante ed but not test ed, characte riz ed only.
Symbol Parameter VCC
(V) VCC—Cable
(V)
TA
0
q
CT
A
40
q
C
Units Conditions
to
70
q
Cto
85
q
C
Guarant eed Lim its
VOL Maximum LOW An, HLH 3.0 3.0 0.2 0.2
V
IOL
50
P
A
Level Output 3.0 3.0 0.4 0.4 IOL
4 mA
Voltage Bn, Yn3.0 3.0 0.8 0.8 IOL
14 mA
Bn, Yn3.0 4.5 0.77 0.77 IOL
14 mA
PLH 3.0 3.0 0.85 0.95 IOL
84 mA
PLH 3.0 4.5 0.8 0.9 IOL
84 mA
RDMaximum Output B1–B8, Y9–Y13 3.3 3.3 60 60
:
(Note 5)(Note 7)
Impedance 3.3 5.0 55 55
Minimum Output B1–B8, Y9–Y13 3.3 3.3 30 30 (Note 5)(Note 7)
Impedance 3.3 5.0 35 35
RPMaximum Pull-Up B1–B8, Y9–Y13, 3.3 3.3 1650 1650
:
Resistance C14–C17 3.3 5.0 1650 1650
Minimum Pull-Up B1–B8, Y9–Y13 3.3 3.3 1150 1150
:
Resistance C14–C17 3.3 5.0 1150 1150
IIH Maximum Input A9–A13, PLHIN, 3.6 3.6 1.0 1.0
P
A
VI
3.6V
Current in HD, DIR, HLHIN
HIGH State C14–C17 3.6 3.6 50.0 50.0 VI
3.6V
C14–C17 3.6 5.5 100 100 VI
5.5V
IIL Maximum Input A9–A13, PLHIN,3.63.6
1.0
1.0
P
AV
I
0.0V
Current in HD, DIR, HLHIN
LOW State C14–C17 3.6 3.6
3.5
3.5 mA VI
0.0V
C14–C17 3.6 5.5
5.0
5.0 mA VI
0.0V
IOZH Maximum Output A1–A83.6 3.6 20 20
P
AV
O
3.6V
Disable Current B1–B83.6 3.6 50 50
P
AV
O
3.6V
(HIGH) B1–B83.6 5.5 100 100
P
AV
O
5.5V
IOZL Maximum A1–A83.6 3.6
20
20
P
AV
O
0.0V
Output Disable B1–B83.6 3.6
3.5
3.5 mA
Current (LOW) B1–B83.6 5.5
5.0
5.0 mA
IOFF Power Down B1–B8, Y9–Y13,0.0 0.0 100 100
P
AV
O
5.5V
Output Leakage PLH
IOFF Power Down C14–C17, HLHIN 0.0 0.0 100 100
P
AV
I
5.5V
Input Leakage
IOFF—ICC Power Down 0.0 0.0 250 250
P
A (Note 6)
Leakage to VCC
IOFF—ICC2 Power Down Leakage 0.0 0.0 250 250
P
A (Note 6)
to VCC—Cable
ICC Maximum Supply 3.6 3.6 45 45 mA VI
VCC or GND
Current 3.6 5.5 70 70 mA VI
VCC or GND
5 www.fairchildsemi.com
74LVX161284
AC Electrical Characteristics
Note 8: Open Drain
Note 9: tSKEW is measured for common edge output transitions and compares the measured propagation delay for a given path type:
(i) A1–A8 to B1–B8, A9–A13 to Y9–Y13
(ii) B1–B8 to A1–A8
(iii) C14–C17 to A14–A17
Note 10: This parameter is guaranteed but not tested, characterized only.
Capacitance
Note 11: CI/O is meas ured at frequency
1 MHz, per MIL-STD-883B, Met hod 3012
Symbol Parameter
TA
0
q
C to
70
q
CT
A
40
q
C to
85
q
C
Units Figure
Number
VCC
3.0V–3.6V VCC
3.0V–3.6V
VCC—Cable
3.0V–5.5V VCC—Cable
3.0V–5.5V
Min Max Min Max
tPHL A1–A8 to B1–B82.0 40.0 2.0 44.0 ns Figure 1
tPLH A1–A8 to B1–B82.0 40.0 2.0 44.0 ns Figure 2
tPHL B1–B8 to A1–A82.0 40.0 2.0 44.0 ns Figure 3
tPLH B1–B8 to A1–A82.0 40.0 2.0 44.0 ns Figure 3
tPHL A9–A13 to Y9–Y13 2.0 40.0 2.0 44.0 ns Figure 1
tPLH A9–A13 to Y9–Y13 2.0 40.0 2.0 44.0 ns Figure 2
tPHL C14–C17 to A14–A17 2.0 40.0 2.0 44.0 ns Figure 3
tPLH C14–C17 to A14–A17 2.0 40.0 2.0 44.0 ns Figure 3
tSKEW LH-LH or HL-HL 10.0 12.0 ns (Note 9)
tPHL PLHIN to PLH 2.0 40.0 2.0 44.0 ns Figure 1
tPLH PLHIN to PLH 2.0 40.0 2.0 44.0 ns Figure 2
tPHL HLHIN to HLH 2.0 40.0 2.0 44.0 ns Figure 3
tPLH HLHIN to HLH 2.0 40.0 2.0 44.0 ns Figure 3
tPHZ Output Disable Time 2.0 15.0 2.0 18.0 ns Figure 7
tPLZ DIR to A1–A82.0 15.0 2.0 18.0
tPZH Output Enable Time 2.0 50.0 2.0 50.0 ns Figure 8
tPZL D IR to A1–A82.0 50.0 2.0 50.0
tPHZ Output Disable Time 2.0 50.0 2.0 50.0 ns Figure 9
tPLZ DIR to B1–B82.0 50.0 2.0 50.0
tpEN Output Enable Time 2.0 25.0 2.0 28.0 ns Figure 2
HD to B1–B8, Y9–Y13 2.0 25.0 2.0 28.0
tpDIS Output Disable Time 2.0 25.0 2.0 28.0 ns Figure 2
HD to B1–B8, Y9–Y13 2.0 25.0 2.0 28.0
tpEN–tpDIS Output Enable- 10.0 12.0 ns
Output Disable
tSLEW Output Slew Rate
tPLH B1–B8, Y9–Y13 0.05 0.40 0.05 0.40 V/ns Figure 5
tPHL 0.05 0.40 0.05 0.40 Figure 4
tr, tftRISE and tFALL 120 120 ns Figure 6
B1–B8 (Note 8), 120 12 0 (Note 10)
Y9–Y13 (Note 8)
Symbol Parameter Typ Units Conditions
CIN Input Capacitance 3 pF VCC
0.0V (HD, DIR, A9–A13, C14–C17, PLHIN and HLHIN)
CI/O (Note 11) I/O Pin Capacitance 5 pF VCC
3.3V
www.fairchildsemi.com 6
74LVX161284
AC Loading and Waveforms
Pulse Generator for all pulses: Rate
d
1.0 MHz; ZO
d
50
:
; tf
d
2.5 ns, tr
d
2.5 ns.
FIGURE 1. Port A to B and A to Y Propagation Delay Waveforms
FIGURE 2. Port A to B and A to Y Output Waveforms
FIGURE 3. Port B to A, C to A and HLHin to HLH Propagation Delay Waveforms
7 www.fairchildsemi.com
74LVX161284
AC Loading and Waveforms (Continued)
FIGURE 4. Port A to B and A to Y HL Slew Test Load and Waveforms
FIGURE 5. Port A to B and A to Y LH Slew Test Load and Waveforms
www.fairchildsemi.com 8
74LVX161284
AC Loading and Waveforms (Continu ed)
tr
Output Rise Time, Open Drain
tf
Output Fall Time, Open Drain
FIGURE 6. Ports A to B and A to Y Rise and Fall Test Load and Waveforms for Open Drain Outputs
FIGURE 7. tPHZ and tPLZ Test Load and Waveforms, DIR to A1–A8
9 www.fairchildsemi.com
74LVX161284
AC Loading and Waveforms (Continued)
FIGURE 8. tPZH and tPZL Test Load and Waveforms, DIR to A1–A8
FIGURE 9. tPHZ an d tPLZ Test Load and Waveforms
DIR to B1–B8
www.fairchildsemi.com 10
74LVX161284
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS48A
11 www.fairchildsemi.com
74LVX161284 Low Voltage IEEE 161284 Translating Transceiver
Physical Dim ensions inches (millimeters) unless otherwise noted (Continued)
48-Lea d Th in S hri nk Sm all Ou tlin e Pack age (TSSOP), JED EC MO-1 53, 6.1mm Wide
Package Number MTD48
Fairchild does not assum e any responsibility for use of any circuitry described, no circuit patent lice nses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r syst ems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instruct ions fo r use provided in the labe li ng, can be re a-
sonably expected to result in a significant injury to the
user.
2. A crit ical com ponen t in any com ponen t of a life s uppor t
device or system whose failure to perform can be rea-
sonabl y e xpec ted to cause the fa i lure of the life supp or t
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
www.onsemi.com
1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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