TOSHIBA {LOGIC/MEMORY} WHE D mm 9097248 OO1e41 2 TOSHIBA MOS MEMORY PRODUCTS ~<y225- DESCRIPTION T551001 PL-70/PL-85/PL-10 TC551001FL-70/FL-85/FL-10 The TCSSIOO1PL/FL is 1,948,576 bits static random access memory organized as 131,072 words by 8 bits using CMOS technology, and operated a single 5V power supply. Advanced circuit techniques provide both high speed and low power features with a maxi- mum operating current of 5mA/NH2(Typ.) and minimum cycle time of 70/85/100ns. When GEI is a logical high, or CE2 is low, the device is placed in low power standby mode in which standby current is 2A typically. The TC551001PL/FL has three control inputs. Chip enable inputs (CEL, CE2) allow for device selection and data retention control, and an output enable input (0E) provides fast memory access. Thus the TC551001PL/FL is suitable for use in various microprocessor application system where high speed, low power, and battery back up are required. The TCSS1001PL/FL is offered in both a dual-in-Line 32 pin standard plastic package and small-out line plastic flat package. FEATURES * Low Power Dissipation 27.5mW/MHz(Typ.) . * Standby Current: 1lOOWA(Max.) 5V Single Power Supply * Power Down Feature: CE], CE2 PIN CONNECTION] (TOP VIEW) N.C G1 321 Yn Al6 | 2 3169 Als Al4 3 300 cE2 Al2 a4 290 R-W A? 5 280 ara AS O 6 27100 As AS 7 260 a At a 8 25D All A3 G9 24 OF A2 Gio 23 9 Alo Al (tt 220 Cri AQ 12 210 1 ur 1/ol 013 200 Lar 102 Oig 19D 1-06 1/03 (15 180 1-05 GND 416 Wow [PIN NAMES] AO Al6 Address Inputs R/W Read/Write Control Input OE Output Enable Input CEL, CE2 {Chip Enable Inputs 1/01 ~ I/08|Data Inputs/Outputs VDD Power (+5V) GND Ground N.C, No Connection * Data Retention Supply Voltage: 2.9%5.5V * Access Time TC551001 TC551 001 TCSS1O01 : PL/FL-70 PL/FL-85 PL FL-0 Access Time (Max.) 70ns 85ns 100ns CE1 Access Time (Max.) 7Ons 85ns 100ns CE2 Access Time (Max.) 70ns 85ns 100ns OE Access Time (Max.) 40ns 45ns 50ns * Directly TTL Compatible: All Inputs and Outputs * Plsatic DIP and Plastic Flat Packace BLOCK DIAGRAM CE Ad a a a 9 pn AS a ne no MOY oC AG os ta Be MEMORY CRLL ~<O (ND A BE) 2a] [8 ARRAY A 43| [gl |= 512664432 4 = 21 2 (1018576) SENSE AMP. COLUMN. ADDRESS DECODER COLUMN ADD DECODER GENERATOR CLOCK COLUAN ADDRESS BUFFER CE AO AL A2 A3 AB ASAIOAIL i -~c: = SH = 4 7m Qn D-87 TOSHIBA {LOGIC/MEMORY? TCS51001PL-70/PL-85/PL-10 3 TCSSIOO1FL-70/FL-85/FL-10 Ss . DHE D M@ FO8?e4a Goede 4 mm OPERATION MODE CEI CE2 OE R/W 1/01 1/08 POWER Read L L H Dour - Ippo Write L * L DIN- Ippo Output Deselect * * _#H x High~Z Ippo H * * * High-Z Ipps Standby * L * High-Z Ipps *: H or L SYMBOL ITEM RATING UNIT Vpp Power Supply Voltage -0.3%7.0 Vv VIN Input Voltage -~0.3* 7,0 Vv Vt/o Input and Output Voltage. -0.5 % Vpp+0.5 Vv Pp Power Dissipation 1,0/0.6%* Ww Tsolder Soldering Temperature 260 - 10 C* sec Tstrg. Storage Temperature -55% 150 C Topr. Operating Temperature 0~70 c *: -3.0V at pulse width 50ns MAX. *k: SOP [D.C. RECOMMENDED OPERATING CONDITIONS] SYMBOL PARAMETER MIN. TYP. MAX, UNIT Von Power Supply Voltage 4.5 5.0 Vin Input High Voltage 2.2 - Vppt0.3 Vin Input Low Voltage -0.3 */ - v Von Data Retention Supply Voltage 2.0 - *: =3.0V at pulse width 50ns MAX. 0-88 fo ooo To46-23-14TOSHIBA CLOGIC/MEMORY}F AYE D Mm. 9097248 BOL9e43 6 mm 1551001PL-70/PL-85/PL-10 _ 76551001 FL-70/FL-85/FL-10 (D.C. and OPERATING CHARACTERISTICS] (Ta=0~70C, vpp=5V#10%) SYMBOL PARAMETER TEST CONDITION MIN.{| TYP. | MAX. | UNIT Tin Input Leakage Current Vrn=0 ~ Vpp - ~ $1.0 | pA Tou Output High Current Von=2-4V 1,0 ] - - mA Ton Output Low Current Voi=0.4V 4.0} - - mA I Output Leakage Current CEIViH or CEN IL r - - 1.0 pA 40 . OE=Vin Vour=0~ Vpp CEI=Vy;, and CE2=Vyy_ and R/W=Vzy, Ipy_=OmA Tppo1 Other Input=Vyp/Vr7, - - 80 | mA Ceycle=Min. cycle Operating Current CE1=0,2V and CE2=Vpp-0.2V ipo? R/W=Vpp-0.2V, Ipyr=OmA _ _ 70 | mA Other Input=Vpp-0.2V/0.2V teycle=Min. cycle Ippsi CEL=Vzq or CE2=Vzy, - |- | 3 | m CEI=Vpp-0.2V or CE2=0.2 Ipps? Standby Current Vpp=2-0Vv 5.5V, - - 100 | yA Ta=0 v 70C (Ta=25C, =1MHz) SYMBOL PARAMETER TEST CONDITION MAX. | UNIT Crrx Input Capacitance Viy=GND 10 Cour Output Capacitance Vour=GND 10 Pr Note: This parameter periodically sampled is not 100% tested. D-89 fw ap . T-46-23-14be RF es HS a ARTSY, Ne ELAS NT Uo idl TOSHIBA {LOGIC/MEMORY} TC551001PL-70/PL-85/PL-10 TOSSIOOIFL-7O/FL-B5/FL-10 f A.C. CHARACTERISTICS] (Ta=0% 70C, Vpp=5V+10%) Read Cycle TC551001PL~70 | TC551001 PL-85 | TC551001 PL-10 SYMBOL PARAMETER TC551001FL-70 | TC551001 FL-85 | TC551001FL-10 UNIT MIN. | MAX. MIN. MAX.} MIN, MAX. tre Read Cycle Time 70 - 85 - 100 - tacc | Address Access Time - 70 - 85 - 100 col | CEI Access Time - 70 - 85 - 100 fco2 |CE2 Access Time - 70 - 85 - 100 tor Output Enable to Output in Valid - 40 - 45 - 50 tCOE Chip Enable (CEI, CE2) to Output 5 _ 10 _ 10 . ns CORE | Output Enable to Output in Low-Z 0 - 0 - 0 - top in utenog (CE1, CE2) to Output _ 30 _ 30 _ 35 ODO |Output Enable to Output in High-z - 30 - 30 - 35 tox Output Data Hold Time 10 ~ 10 ~- 10 ~ Write Cycle TCS51001PL~70 | TC551001 PL-85 | 10551001 PL-10 SYMBOL PARAMETER TC551001FL70 | TC551001 FL-85 | TC551001 FL-10 | UNIT MIN. MAX.| MIN. MAX.| MIN. MAX. twe Write Cycle Time 70 - 85 - 100 - twe |Write Pulse Width 50 - 60 - 60 - tcqy Chip Selection to End of Write 65 - 75 - 80 - tas Address Set up Time ~ - 0 - twR Write Recovery Time - - - ns Copw |R/W to Output in High-Z - 30 - 30 ~ 35 SOEW |R/W to Output in Low-Z 0 - 0 - 0 - tps Data Set up Time 35 - 35 - 40 - tpy Data Hold Time 0 - 0 - 0 - A.C. TEST CONDITION * Output Load + 100pF + 1 TTL Gate * Input Pulse Level : 0.6V, 2.4V * Timing Measurement Vin 0.8V, 2.2V Reference Levels Vout: 0.8V, 2.2V * ty, te : S5ns D-90 | ae T-46-23-14TOSHIBA {fLOGIC/MEMORY} AME D = Toes OOnAeNS | T mm a 70551 001 PL-70/ PL-85/ PL-1 o Tg - Te5sI 001 FL-70/1 FL: 85/ FL o oe TIMING WAVEFORMS READ CYCLE (1) ADDRESSES x tacc tou | cre YUM tco2 Ww NIN \ top | | = (UH TL ANN ses MMMM Dour __ "lg, ouTPUT DATA VALID WRITE CYCLE 1 (4) (R/W Controlled Write) twe ADDRES SES R/W CE2 Dour tps DIN DATA IN STABLE D-91 SUNy Me ROSSA TS, jarani ork aed SO RATA RE 76551001 FL-70/FL-85/FL-10 =* TOSHIBA {LOGIC/MEMORY} LHE D M@ 109?%c4Ss OOLIC4E Lm - 76551001 PL-70/PL-85/PL-10 WRITE CYCLE 2 (4) (CEI Controlled Write) twe ADDRESSES R/W t DIN DATA IN STABLE WRITE CYCLE 3 (4) (CE2 Controlled Write) t ADDRESSES R/W gq tH wal Dout tps t DIN DATA IN STABLE D-92 fo T-46-23~14 *TOSHIBA {LOGIC/MEMORY? UNE D mm 9097248 OOL9e4? 3 mm } po aa 76551001 PL-70/PL-85/PL-19 ee 16551001 FL-70/FL-85/FL-10 T-46~23-14 NOTE: (1) R/W is High for Read Cycle. (2) Assuming that CEL Low transition or CE2 High transition occurs coincident with or after R/W Low transition, Outputs remain in a high impedance state. (3) Assuming that CEI High transition or CE2 Low transition occurs coincident with or prior to R/W High transition, outputs remain in a high impedance state, (4) Assuming that OE is High for Write Cycle, Outputs are in high impedance state during this period. DATA RETENTION CHARACTERISTICS (Ta=0~ 70C) SYMBOL PARAMETER MIN. TYP. MAX. UNIT Vou Data Retention Supply Voltage 2.0 - 5.5 Vv Vpp=3 OV - - 50 Ipps2 Standby Current | wa Vpp=5-5V - - 100 tCDR Chip Deselection to Data Retention Mode 0 - - ns tR Recovery Time 5 - - mS CEL Controlled Data Retention Mode (1) v Ypp DD AN DATA RETENTION NODE. i... I 4.5 -----~-f-- (2) Vin --- rr CEI tcprR Vpp 0.2V tr \ GND D-93 PAE, IR SCR Ey AE WGI RRS TEI ATOSHIBA {LOGIC/MEMORY} LHE D M@@ 4097244 0019848 5S mm T551001PL-70/PL-85/PL-10 ] oe, | aa 10551001 FL-70/FL-85/FL-10 OB Fan 23- CE2 Controlled Data Retention Mode (3) Ypp a DATA RETENTION MODE {_ 48V ~-~---\)--~~.-------h~ ~~. + 1 NI, o2y MMA NOTE: (1) In CE controlled data retention mode, minimum standby current mode is achieved under the condition of CE20.2V or CE22 Vpp-0.2V. (2) If the Vyzq of CEL is 2.2V in operation, during the period that the Vpp voltage is going down from 4.5V to 2.4V, Ipps ] current flows. (3) In CE2 controlled data retention mode, minimum standby current mode is achieved under the condition of CE20.2V. D-94 Weeeen 1 GsTOSHIBA {LOGIC/MEMORY? LYE D mm 9097248 0019249 7 me an oe 70551001 PL-70/PL-85/PL-10 - . _ 76551001 FL-70/FL-85/FL-10 DIP 32 PIN OUTLINE DRAWING (DIP32-P-600) Unit in mm 32 17 Onno mommopr 7 o~15 5 / 140+0.2 [1524] +01 0,25-0.05 OOOO OTIOE oa oa 1 16 | 420402 \ I na poe 1.96 TYP 4 1440.1 losto.r Note) Package width and length do not include mold protrusion. Allowable mold protrusion is 0.15mm. 3.50.3 MFP 32 PIN OUTLINE DRAWING (SOP32-P-450) Uagggngaggagnnng tT S i 11.43 (450mil) 88 +0.2 2.23403 TO OHEBRHBRDHH EOE KL o77sTyP | j} | 035401 1 | 0.775 TYP [1.27 | {@- [0.12 @& J rra 20.6402 z 2.85 MAX. +01 0.150.05 0.19:0.15 \ a] Note) Package width and length do not include mold protrusion. Allowable mold protrusion is 0.15mm. D-95