74LCX374MTCX - Fairchild - Datasheet.Live

74LCX374 — Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs

74LCX374 Rev. 1.6.0

February 2008

74LCX374

Low Voltage Octal D-Type Flip-Flop

with 5V Tolerant Inputs and Outputs

Features

■

5V tolerant inputs and outputs

■

2.3V–3.6V V

CC

specifications provided

■

8.5ns t

PD

max (V

CC

=

3.3V), 10µA I

CC

max

■

Power-down high impedance inputs and outputs

■

Supports live insertion/withdrawal

(1)

■

±24mA output drive (V

CC

=

3.0V)

■

Latch-up performance exceeds JEDEC 78 conditions

■

ESD performance

– Human Body Model

>

2000V

– Machine Model

>

200V

■

Leadless DQFN package

Note:

1. To ensure the high impedance state during power up

or down, OE should be tied to V

CC

through a pull-up

resistor: the minimum value of the resistor is

determined by the current-sourcing capability of the

driver.

General Description

The LCX374 consists of eight D-type flip-flops featuring

separate D-type inputs for each flip-flop and 3-STATE

outputs for bus-oriented applications. A buffered clock

(CP) and Output Enable (OE) are common to all flip-

flops. The LCX374 is designed for low voltage appli-

cations with capability of interfacing to a 5V signal

environment.

The LCX374 is fabricated with an advanced CMOS

technology to achieve high speed operation while main-

taining CMOS low power dissipation.

Ordering Information

Note:

2. DQFN package available in Tape and Reel only.

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

Order Number

Package

Number Package Description

74LCX374WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300"

Wide

74LCX374SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LCX374BQX

(2)

MLP20B 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN),

JEDEC MO-241, 2.5 x 4.5mm

74LCX374MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm

Wide

74LCX374MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm Wide

Implements proprietary noise/EMI reduction circuitry

74LCX374 Rev. 1.6.0 2

74LCX374 — Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs

Connection Diagrams

Pin Assignments for

SOIC, SOP, SSOP, TSSOP

Pad Assignments for DQFN

(Top View)

Pin Description

Logic Symbol

Truth Table

H

=

HIGH Voltage Level

L

=

LOW Voltage Level

X

=

Immaterial

Z

=

High Impedance

=

LOW-to-HIGH Transition

O

0

=

Previous O

0

before HIGH-to-LOW of CP

Functional Description

The LCX374 consists of eight edge-triggered flip-flops

with individual D-type inputs and 3-STATE true outputs.

The buffered clock and buffered Output Enable are com-

mon to all flip-flops. The eight flip-flops will store the

state of their individual D inputs that meet the setup and

hold time requirements on the LOW-to-HIGH Clock (CP)

transition. With the Output Enable (OE) LOW, the con-

tents of the eight flip-flops are available at the outputs.

When the OE is HIGH, the outputs go to the high imped-

ance state. Operation of the OE input does not affect the

state of the flip-flops.

Please note that this diagram is provided only for the

understanding of logic operations and should not be

used to estimate propagation delays.

Pin Names Description

D

0

–D

7

Data Inputs

CP Clock Pulse Input

OE Output Enable Input

O

0

–O

7

3-STATE Outputs

D

0

D

1

O

1

O

2

D

2

D

3

O

3

GND

O

0

D

7

D

6

O

6

O

5

D

5

D

4

O

4

CP

O

7

V

CC

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

OE

D0

D1

O1

O2

D2

D3

O3

GND

O0

D7

D6

O6

O5

D5

D4

O4

CP

O7

VCC

120

2

3

4

5

6

7

8

9

10 11

19

18

17

16

15

14

13

12

OE

Inputs Outputs

D

n

CP OE O

n

HLH

LLL

XLLO

0

XXHZ

D0D1D2D3D4D5D6D7

O0

OE

CP

O1O2O3O4O5O6O7

74LCX374 Rev. 1.6.0 3

74LCX374 — Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to

estimate propagation delays.

CP

O

0

CP

OE

O

1

O

2

O

3

O

4

O

5

O

6

O

7

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

D

O

CP D

O

CP D

O

CP D

O

CP D

O

CP D

O

CP D

O

CP D

O

74LCX374 Rev. 1.6.0 4

74LCX374 — Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Recommended Operating Conditions

(4)

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to absolute maximum ratings.

Notes:

3. I

O

Absolute Maximum Rating must be observed.

4. Unused inputs must be held HIGH or LOW. They may not float.

Symbol Parameter Conditions Value Units

V

CC

Supply Voltage –0.5 to +7.0 V

V

I

DC Input Voltage –0.5 to +7.0 V

V

O

DC Output Voltage Output in 3-STATE –0.5 to +7.0 V

Output in HIGH or LOW State

(3)

–0.5 to V

CC

+ 0.5

I

IK

DC Input Diode Current V

I

<

GND –50 mA

I

OK

DC Output Diode Current V

O

<

GND –50 mA

V

O

>

V

CC

+50

I

O

DC Output Source/Sink Current ±50 mA

I

CC

DC Supply Current per Supply Pin ±100 mA

I

GND

DC Ground Current per Ground Pin ±100 mA

T

STG

Storage Temperature –65 to +150 °C

Symbol Parameter Conditions Min. Max. Units

V

CC

Supply Voltage Operating 2.0 3.6 V

Data Retention 1.5 3.6

V

I

Input Voltage 0 5.5 V

V

O

Output Voltage HIGH or LOW State 0 V

CC

V

3-STATE 0 5.5

I

OH

/

I

OL

Output Current V

CC

= 3.0V–3.6V ±24 mA

V

CC

= 2.7V–3.0V ±12

V

CC

= 2.3V–2.7V ±8

T

A

Free-Air Operating Temperature –40 85 °C

∆

t

/

∆

V Input Edge Rate V

IN

= 0.8V–2.0V, V

CC

= 3.0V 0 10 ns

/V

74LCX374 Rev. 1.6.0 5

74LCX374 — Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs

DC Electrical Characteristics

AC Electrical Characteristics

Notes:

5. Outputs disabled or 3-STATE only.

6. Skew is defined as the absolute value of the difference between the actual propagation delay for any two

separate outputs of the same device. The specification applies to any outputs switching in the same direction,

either HIGH-to-LOW (t

OSHL

) or LOW-to-HIGH (t

OSLH

).

Symbol Parameter V

CC

(V) Conditions

T

A

=

–40°C to +85°C

UnitsMin. Max.

V

IH

HIGH Level Input Voltage 2.3–2.7 1.7 V

2.7–3.6 2.0

V

IL

LOW Level Input Voltage 2.3–2.7 0.7 V

2.7–3.6 0.8

V

OH

HIGH Level Output

Voltage

2.3–3.6 I

OH

=

–100µA V

CC

– 0.2 V

2.3 I

OH

=

–8mA 1.8

2.7 I

OH

=

–12mA 2.2

3.0 I

OH

=

–18mA 2.4

I

OH

=

–24mA 2.2

V

OL

LOW Level Output

Voltage

2.3–3.6 I

OL

=

100µA 0.2 V

2.3 I

OL

=

8mA 0.6

2.7 I

OL

=

12mA 0.4

3.0 I

OL

=

16mA 0.4

I

OL

=

24mA 0.55

I

Input Leakage Current 2.3–3.6 0

≤

V

I

≤

5.5V ±5.0 µA

I

OZ

3-STATE Output Leakage 2.3–3.6 0 ≤ VO ≤ 5.5V,

VI = VIH or VIL

±5.0 µA

IOFF Power-Off Leakage Current 0 VI or VO = 5.5V 10 µA

ICC Quiescent Supply Current 2.3–3.6 VI = VCC or GND 10 µA

3.6V ≤ VI, VO ≤ 5.5V(5) ±10

∆ICC Increase in ICC per Input 2.3–3.6 VIH = VCC – 0.6V 500 µA

Symbol Parameter

TA = –40°C to +85°C, RL = 500Ω

Units

VCC = 3.3V ± 0.3V,

CL = 50pF

VCC = 2.7V,

CL = 50pF

VCC = 2.5V ± 0.2V,

CL = 30pF

Min. Max. Min. Max. Min. Max.

fMAX Maximum Clock Frequency 150 150 150 MHz

tPHL, tPLH Propagation Delay CP to On1.5 8.5 1.5 9.5 1.5 10.5 ns

tPZL, tPZH Output Enable Time 1.5 8.5 1.5 9.5 1.5 10.5 ns

tPLZ, tPHZ Output Disable Time 1.5 7.5 1.5 8.5 1.5 9.0 ns

tSSetup Time 2.5 2.5 4.0 ns

tHHold Time 1.5 1.5 2.0 ns

tWPulse Width 3.3 3.3 4.0 ns

tOSHL, tOSLH Output to Output Skew(6) 1.0 ns

74LCX374 Rev. 1.6.0 6

74LCX374 — Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs

Dynamic Switching Characteristics

Capacitance

Symbol Parameter VCC (V) Conditions

TA = 25°C

UnitsTypical

VOLP Quiet Output Dynamic Peak VOL 3.3 CL = 50pF, VIH = 3.3V, VIL = 0V 0.8 V

2.5 CL = 30pF, VIH = 2.5V, VIL = 0V 0.6

VOLV Quiet Output Dynamic Valley VOL 3.3 CL = 50pF, VIH = 3.3V, VIL = 0V –0.8 V

2.5 CL = 30pF, VIH = 2.5V, VIL = 0V –0.6

Symbol Parameter Conditions Typical Units

CIN Input Capacitance VCC = Open, VI = 0V or VCC 7pF

COUT Output Capacitance VCC = 3.3V, VI = 0V or VCC 8pF

CPD Power Dissipation Capacitance VCC = 3.3V, VI = 0V or VCC, f = 10 MHz 25 pF

74LCX374 Rev. 1.6.0 7

74LCX374 — Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs

AC Loading and Waveforms (Generic for LCX Family)

Figure 1. AC Test Circuit (CL includes probe and jig capacitance)

Waveform for Inverting and

Non-Inverting Functions

Propagation Delay. Pulse Width and

trec Waveforms

3-STATE Output Low Enable and

Disable Times for Logic

3-STATE Output High Enable and

Disable Times for Logic

Setup Time, Hold Time and

Recovery Time for Logic

trise and tfall

Figure 2. Waveforms (Input Characteristics; f =1MHz, tr = tf = 3ns)

V

CC

DUT

C

L

500Ω

500ΩOPEN t

PLH

, t

PHL

t

PZH

, t

PHZ

t

PZL

, t

PLZ

GND

V

I

TEST

SIGNAL

Test Switch

tPLH, tPHL Open

tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V

VCC x 2 at VCC = 2.5 ± 0.2V

tPZH, tPHZ GND

VCC

GND

DATA

IN

DATA

OUT

tpxx tpxx

Vmi

Vmo

VCC

GND

CONTROL

IN

CLOCK

OUTPUT

tPHL tPLH

trec

tW

Vmi

Vmo

VCC

VX

VOL

GND

DATA

OUT

OUTPUT

CONTROL

tPZL tPLZ

Vmi

Vmo

DATA

OUT

OUTPUT

CONTROL

tPZH tPHZ

VCC

GND

Vmi

VOH

VY

Vmo

DATA

IN

CONTROL

INPUT

MR

OR

CLEAR

tS

tH

trec

VCC

GND

VCC

GND

Vmi

ANY

OUTPUT

trtf

VOH

VOL

10% 10%

90% 90%

Symbol

VCC

3.3V ± 0.3V 2.7V 2.5V ± 0.2V

Vmi 1.5V 1.5V VCC / 2

Vmo 1.5V 1.5V VCC / 2

VxVOL + 0.3V VOL + 0.3V VOL + 0.15V

VyVOH – 0.3V VOH – 0.3V VOH – 0.15V

74LCX374 Rev. 1.6.0 8

74LCX374 — Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs

Schematic Diagram (Generic for LCX Family)

ESD

Input Stage

Output

Input Stage

P1

P2

P5 X1

GTO™

VCC

VDD

N1

N+/P–D2

P3

P4

N4

N5

N3

N+/P–D4

N+/P–

D6

Data

Enable

N2

74LCX374 Rev. 1.6.0 9

74LCX374 — Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs

Tape and Reel Specification

Tape Format for DQFN

Tape Dimensions inches (millimeters)

Reel Dimensions inches (millimeters)

Package

Designator

Tape

Section

Number

Cavities

Cavity

Status

Cover Tape

Status

BQX Leader (Start End) 125 (typ) Empty Sealed

Carrier 3000 Filled Sealed

Trailer (Hub End) 75 (typ) Empty Sealed

Tape Size A B C D N W1 W2

12mm 13.0 (330.0) 0.059 (1.50) 0.512 (13.00) 0.795 (20.20) 2.165 (55.00) 0.488 (12.4) 0.724 (18.4)

74LCX374 Rev. 1.6.0 10

74LCX374 — Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs

Physical Dimensions

Figure 3. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

0.10 C

C

A

SEE DETAIL A

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC

MS-013, VARIATION AC, ISSUE E

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

E) LANDPATTERN STANDARD: SOIC127P1030X265-20L

PIN ONE

INDICATOR

0.25

110

BC A

M

20 11

B

X 45°

8°

0°

SEATING PLANE

GAGE PLANE

DETAIL A

SCALE: 2:1

SEATING PLANE

LAND PATTERN RECOMMENDATION

F) DRAWING FILENAME: MKT-M20BREV3

0.65

1.27

2.25

9.50

13.00

12.60

11.43

7.60

7.40

10.65

10.00

0.51

0.35 1.27

2.65 MAX

0.30

0.10

0.33

0.20

0.75

0.25

(R0.10)

1.27

0.40

(1.40)

0.25

D) CONFORMS TO ASME Y14.5M-1994

74LCX374 Rev. 1.6.0 11

74LCX374 — Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs

Physical Dimensions (Continued)

Figure 4. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

74LCX374 Rev. 1.6.0 12

74LCX374 — Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs

Physical Dimensions (Continued)

Figure 5. 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

74LCX374 Rev. 1.6.0 13

74LCX374 — Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs

Physical Dimensions (Continued)

Figure 6. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

74LCX374 Rev. 1.6.0 14

74LCX374 — Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs

Physical Dimensions (Continued)

Figure 7. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

74LCX374 Rev. 1.6.0 15

TRADEMARKS

Thefollowing includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global

subsidiaries, and is not intended to be an exhaustive list of all such trademarks.

ACEx®

Build it Now™

CorePLUS™

CROSSVOLT™

CTL™

Current Transfer Logic™

EcoSPARK®

EZSWITCH™ *

™

®

Fairchild®

Fairchild Semiconductor®

FACT Quiet Series™

FACT®

FAST®

FastvCore™

FlashWriter®*

FPS™

FRFET®

Global Power ResourceSM

Green FPS™

Green FPS™e-Series™

GTO™

i-Lo™

IntelliMAX™

ISOPLANAR™

MegaBuck™

MICROCOUPLER™

MicroFET™

MicroPak™

MillerDrive™

Motion-SPM™

OPTOLOGIC®

OPTOPLANAR®

®

PDP-SPM™

Power220®

POWEREDGE®

Power-SPM™

PowerTrench®

Programmable Active Droop™

QFET®

QS™

QT Optoelectronics™

Quiet Series™

RapidConfigure™

SMART START™

SPM®

STEALTH™

SuperFET™

SuperSOT™-3

SuperSOT™-6

SuperSOT™-8

SupreMOS™

SyncFET™®

The Power Franchise®

TinyBoost™

TinyBuck™

TinyLogic®

TINYOPTO™

TinyPower™

TinyPWM™

TinyWire™

µSerDes™

UHC®

Ultra FRFET™

UniFET™

VCX™

*EZSWITCH™ and FlashWriter®are trademarks of System General Corporation, used under license by Fairchild Semiconductor.

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS

HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE

APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS

PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S

WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR

SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body or

(b) support or sustain life, and (c) whose failure to perform

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to

result in a significant injury of the user.

2. A critical component in any component of a life support,

device, or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or In Design This datasheet contains the design specifications for product

development. Specifications may change in any manner without notice.

Preliminary First Production

This datasheet contains preliminary data; supplementary data will be

published at a later date. Fairchild Semiconductor reserves the right to

make changes at any time without notice to improve design.

No Identification Needed Full Production

This datasheet contains final specifications. Fairchild Semiconductor

reserves the right to make changes at any time without notice to improve

the design.

Obsolete Not In Production

This datasheet contains specifications on a product that has been

discontinued by Fairchild Semiconductor. The datasheet is printed for

reference information only.

Rev. I33

74LCX374 — Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs