16K x 4 Static RAM
with Separate I/O
CY7C161
CY7C162
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Ma
y
1986 – Revised March 1995
Features
• High speed
—15-ns
• Transparent write (7C161)
• CMOS for optimum speed/power
• Low active power
—633 mW
• Low standby pow er
—220 mW
• TTL compatible inputs and outputs
• A utomatic power-down when deselected
Functional Description
The CY7C161 and CY7C162 are high-performance CMOS
static RAMs organized as 16,384 by 4 bits with separate I/O.
Easy memory expansion is provided by active LOW chip en-
ables (CE1, CE2) and three-state drivers. They have an auto-
matic power-down feature, reducing the power consumption
by 65% when deselected.
Writing to the device is accomplished when the chip enable
(CE1, C E2) and write enable (WE) inputs are both LOW. Data
on the f our inpu t pins (I0 throug h I3) is writt en into the memory
location specifi ed on the address pi ns (A0 through A13).
Reading the device is accomplished by taking the chip enables
(CE1, C E 2) LOW while write enab le (WE) rema i ns H IG H . U n-
der these conditions the contents of the memory location
specif ied on the address pins will appear on the four data out-
put pins.
The output pins stay in a high-impedance state when write
enable (WE) is LOW (7C162 only), or one of the chip enables
(CE1, C E2) are HIGH.
A die coat is used to i nsure alpha immunity.
Logic Block Diagram Pin Configurations
C162-1
7C161
7C162
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
256 x 256
ARRAY
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A11
A10
A12
A13
COLUMN DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
POWER
DOWN
O0
O1
O2
O3
I0
I1
I2
I3
CE1
CE2
WE
OE
7C162 ONLY
7C161 ONLY
Top Vie w
DIP
C162-2
A5
A6
A7
A12
A10
A9
A11
A13
A8
I0
I1
I2
CE
OE
GND WE
I3
VCC
A4
A3
A2
A1
A0
O2
O1
O3
O0
CE2
Selectio n Guide[1]
7C161−12
7C162−12 7C161−15
7C162−15 7C161−20
7C162−20 7C161−25
7C162−25 7C161−35
7C162−35
Maximum Access Time (ns) 12 15 20 25 35
Maxim um Operating Current (mA) 160 115 80 70 70
Maximum Standby Current (mA) 40/20 40/20 40/ 20 20/20 20/20
Shaded areas indicate preliminary information.
Note:
1. For military specifications, see the CY7C161A/CY7C162A datasheet.
CY7C161
CY7C162
2
Maximum Ratings
(Above which the usefu l l ife may be impa ired. F or user guide-
li nes, not tes ted.)
Storage Temperature .....................................−65°C to +150°C
Ambient Temperature wit h
Power Applied..................................................−55°C to +125°C
Supply Voltage to Ground Potenti al
(Pin 24 to Pin 12)..................................................−0.5V to+7.0V
DC Voltage Applied to Output s
in High Z State[2] ..................................................−0.5V to+7.0V
DC Input Vol tage[2]..............................................−0.5V to +7 . 0V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ........... .. ....... .. ...... .. ....... .. ....>2001V
(per MIL- STD-883, Method 3015 )
Latch-Up Current......... ............................................>200 mA
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +70°C 5V ± 10%
Electrical Characte ristics Over the Operating Range 7C161−12
7C162−12 7C161−15
7C162−15
Parameter Description Test Conditi ons Min. Max. Min. Max. Unit
VOH Output HIGH Voltage VCC = Min.,I OH = −4.0 mA 2.4 2.4 V
VOL Output LOW Voltage VCC = Min.,I OL = 8.0 mA 0.4 0.4 V
VIH Input HIGH Voltage 2.2 VCC 2.2 VCC V
VIL Input LOW Voltage[2] −0.5 0.8 −0.5 0.8 V
IIX Input Load Current GND < VI < VCC −5+5 −5+5 µA
IOZ Output Leaka ge
Current GND < VI < VCC,
Output Disabled −5+5 −5+5 µA
IOS Output Short
Circuit Curren t [3] VCC = Max.,
VOUT = GND −350 −350 mA
ICC VCC Operating
Supply Current VCC = Max.,
IOUT = 0 mA 160 115 mA
ISB1 Automatic CE1
Power-Down Curr ent Max. VCC, CE1 > VIH
Min. Duty Cycle = 100% 40 40 mA
ISB2 Automatic CE1
P ower-Down Current Max. VCC, CE1 > VCC − 0. 3V,
VIN > VCC − 0.3V or VIN < 0. 3V 20 20 mA
Shaded areas indicate preliminary information.
Notes:
2. Minimum voltage is equal to -3.0V for pulse durations less than 30 ns.
3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
CY7C161
CY7C162
3
Electrical Characte ristics Ov er the Operating Range (continued) 7C161−20
7C162−20 7C161−25, 35
7C162−25, 35
Parameter Description Test Conditions Min. Max. Min. Max. Unit
VOH Output HIGH Voltage VCC = Min ., I OH = −4.0 mA 2.4 2.4 V
VOL Output LOW Voltage VCC = Min ., I OL = 8.0 mA 0.4 0.4 V
VIH Input HIGH Voltage 2.2 VCC 2.2 VCC V
VIL Input LOW Voltage[2] −0.5 0.8 −0.5 0.8 V
IIX Input Load Current GND < VI < VCC −5+5 −5+5 µA
IOZ Output Leaka ge Current GND < VI < VCC,Output Disabled −5+5 −5+5 µA
IOS Output Short
Circuit Curren t [3] VCC = Max.,
VOUT = GND −350 −350 mA
ICC VCC Operating
Supply Current VCC = Max.,
IOUT = 0 mA 80 70 mA
ISB1 Automatic CE1
P ower-Down Current Max. VCC, CE1 > VIH
Min. Duty Cycle = 100% 40 20 mA
ISB2 Automatic CE1
P ower-Down Current Max. VCC, CE1 > VCC − 0.3V,
VIN > VCC − 0.3V or VIN < 0.3V 20 20 mA
Capacitance[4]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 5.0V 10 pF
COUT Outpu t Capacitance 10 pF
Notes:
4. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
3.0V
5V
OUTPUT
R1 481
Ω
R2
255Ω
30pF GND
90% 90%
10%
≤5ns ≤5ns
5V
OUTPUT
R2
255Ω
5pF
(a) (b)
OUTPUT 1.73V
Equivalent to: THÉ VENIN EQUIVALENT
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
R1 481Ω
10%
C162-3 C162-4
ALL INPUT PULSES
167Ω
CY7C161
CY7C162
4
Switching Charac teris t ics Ov er the Operating Range[5, 6]
7C161−12
7C162−12 7C161−15
7C162−15 7C161−20
7C162−20 7C161−25
7C162−25 7C161−35
7C162−35
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Time 12 15 20 25 35 ns
tAA Addr e ss to Da t a Va lid 12 15 20 25 35 ns
tOHA Out put Hol d from Ad dre ss Change 3 3 5 5 5 ns
tACE CE LOW to Data Valid 12 15 20 25 35 ns
tDOE OE LOW to Data Valid 12 10 10 12 15 ns
tLZOE OE LOW to Low Z 0 3 3 3 3 ns
tHZOE OE HIGH to High Z 78810 12 ns
tLZCE CE LOW to Low Z[7] 3 3 5 5 5 ns
tHZCE CE HIGH to High Z[7, 8 ] 78810 15 ns
tPU CE LOW to Powe r- Up 0 0 0 0 0 ns
tPD CE HIGH to P ower-Do wn 12 15 20 20 20 ns
WRITE CY CLE[9]
tWC Write Cycle Time 12 15 20 20 25 ns
tSCE CE LOW to Write End 812 15 20 25 ns
tAW Address Set-Up to W rite End 812 15 20 25 ns
tHA Add ress Hold from Write End 0 0 0 0 0 ns
tSA Address Set-Up to W rite Start 0 0 0 0 0 ns
tPWE WE Pulse Width 812 15 15 20 ns
tSD Data Set-Up to Write End 610 10 10 15 ns
tHD Data Hold from Write End 0 0 0 0 0 ns
tLZWE WE HIGH to Low Z[7] (7C162) 3 5 5 5 5 ns
tHZWE WE LOW to High Z[7, 8] (7C162) 677710 ns
tAWE WE LOW to Data Valid (7C161) 12 15 20 25 30 ns
tADV Dat a Valid to Outp ut V a lid (7C161) 12 15 20 20 30 ns
tDCE CE LOW to Data Valid 12 15 20 25 35 ns
Shaded areas indicate preliminary information.
Notes:
5. Test conditions assume signal transition time of 5 ns or less, timing reference lev els of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load c apacitanc e .
6. Both CE1 and CE2 are repres ented by C E in the Swi tching Cha ract eristics an d W a vef orms s ections .
7. At any given temperature and voltage condition, tHZ is l ess than tLZ for any given de vice .
8. tHZCE and tHZWE a re specifi ed wi th CL = 5 pF as in part (b) of A C Test Loads . Trans ition is measur ed ±500 mV f rom steady-stat e vol t age.
9. The internal write time of the memory is defined by the overlap of CE1 LO W , CE2 L OW, and W E LO W. Both s ignals must b e LO W to i nitiate a writ e and e ither s ignal
can terminat e a write b y goi ng H IGH. The dat a input se t-up and ho ld ti ming shoul d be r ef erenc ed to the rising ed ge of the si gnal t hat terminates the write.
CY7C161
CY7C162
5
Switching Wavef orms[8]
Notes:
10. WE is HIGH for read cycle.
11. Device is continuously selected, CE1, CE2 = VIL.
12. Address valid prior to or coincident with CE1, CE2 t ra nsition LOW.
Read Cycle No.1
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
C162-5
[10,11]
Read Cycle No. 2
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
DATA OUT HIGH IMPEDANCE IMPEDANCE
ICC
ISB
tHZOE
tHZCE
tPD
OE
CE
HIGH
VCC
SUPPLY
CURRENT
C162-6
[10,12]
Write Cycle No.1(WE Controlled)
tWC
DATA UNDEFINED HIGH IMPEDANCE
tSCE
tAW
tSA tPWE tHA
tHD
tHZWE tLZWE
tSD
DATA UNDEFINED
tADV
DATA VALID
CE
WE
DATA IN
DATA OUT
ADDRESS
DATA OUT
(7C161)
(7C162)
C162-7
tDWE
DATAINVALID
[9]
CY7C161
CY7C162
6
Note:
13. If CE goes HIGH simu ltaneousl y with WE HIG H, the outp ut r emains i n a high-impe dance state (7C 162 only) .
Switching Wavef orms[8] (Con ti nued)
WriteCycleNo.2(CEControlled) tWC
HIGH IMPEDANCE
tSCE
tAW
tSA
tPWE tHA
tHD
tSD
CE
WE
ADDRESS
DATA IN
DATA OUT
DATA OUT DATA VALID
(7C162)
(7C161) C162-8
tHZLE
tHZLE
tDCE
DATAIN VALID
[9,13]
Typical DC and AC Characteristi cs
1.2
1.4
1.0
0.6
0.4
0.2
4.0 4.5 5.0 5.5 6.0
1.6
1.4
1.2
1.0
0.8
−55 25 125
−55 25 125
1.2
1.0
0.8
NORMALIZED tAA
120
100
80
60
40
20
0.0 1.0 2.0 3.0 4.0
OUTPUT SOURCE CURRENT (mA)
SUPPLY VOL TAGE (V)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (°C)
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (°C) OUTPUT VOLTAGE (V)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
0.0
0.8
1.4
1.3
1.2
1.1
1.0
0.9
4.0 4.5 5.0 5.5 6.0
NORMALIZED tAA
SUPPLY VOL TAGE (V)
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
120
140
100
60
40
20
0.0 1.0 2.0 3.0 4.0
OUTPUT SINK CURRENT (mA)
0
80
OUTPUT VOLT AGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
0.6
0.4
0.2
0.0
NORMALIZED I , I
CC SB
NORMALIZED I , I
CC SB
ISB
VCC =5.0V
VIN =5.0V
ICC
ICC
VCC =5.0V
VCC =5.0V
TA=25°C
VCC =5.0V
TA=25°C
ISB
TA=25
°C
0.6
0.8
0
CY7C161
CY7C162
7
Typical DC and AC Characteristi cs
3.0
2.5
2.0
1.5
1.0
0.5
0.0 1.0 2.0 3.0 4.0
NORMALIZED IPO
SUPPLY VOLTAGE (V)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE 30.0
25.0
20.0
15.0
10.0
5.0
0 200 400 600 800
NORMALIZED t (ns)
AA
CAPACITANCE (pF)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING 1.25
1.00
0.75
10 20 30 40
NORMALIZED ICC
CYCLE FREQUENCY (MHz)
NORMALIZED ICC vs.CYCLETIME
0.0 5.0 0.0 1000 0.50
VCC =4.5V
TA=25°C
VCC =5.0V
TA=25
°C
VCC =0.5V
Address Designators
Address
Name Address
Function Pin
Number
A5 X3 1
A6 X4 2
A7 X5 3
A8 X6 4
A9 X7 5
A10 Y0 6
A11 Y1 7
A12 Y5 8
A13 Y4 9
A0 Y3 23
A1 Y2 24
A2 X0 25
A3 X1 26
A4 X2 27
CY7C161
CY7C162
8
Document #: 38−00029−I
Ordering Information
Speed
(ns) Ordering Code Package
Name Package Typ e Operating
Range
12 CY7C161−12PC P21 28-Lead (300-Mil) Molded DIP Commercial
CY7C161−12VC V21 28-Lead Molded SOJ
15 CY7C161−15PC P21 28-Lead (300-Mil) Molded DIP Commercial
CY7C161−15VC V21 28-Lead Molded SOJ
20 CY7C161−20PC P21 28-Lead (300-Mil) Molded DIP Commercial
CY7C161−20VC V21 28-Lead Molded SOJ
25 CY7C161−25PC P21 28-Lead (300-Mil) Molded DIP Commercial
CY7C161−25VC V21 28-Lead Molded SOJ
35 CY7C161−35PC P21 28-Lead (300-Mil) Molded DIP Commercial
CY7C161−35VC V21 28-Lead Molded SOJ
Speed
(ns) Ordering Code Package
Name Package Typ e Operating
Range
12 CY7C162−12PC P21 28-Lead (300-Mil) Molded DIP Commercial
CY7C162−12VC V21 28-Lead Molded SOJ
15 CY7C162−15PC P21 28-Lead (300-Mil) Molded DIP Commercial
CY7C162−15VC V21 28-Lead Molded SOJ
20 CY7C162−20PC P21 28-Lead (300-Mil) Molded DIP Commercial
CY7C162−20VC V21 28-Lead Molded SOJ
25 CY7C162−25PC P21 28-Lead (300-Mil) Molded DIP Commercial
CY7C162−25VC V21 28-Lead Molded SOJ
35 CY7C162−35PC P21 28-Lead (300-Mil) Molded DIP Commercial
CY7C162−35VC V21 28-Lead Molded SOJ
Shaded areas indicate preliminary information.
CY7C161
CY7C162
© Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuit ry other than circuitry embodied in a Cypress Semiconduc tor product. Nor does it con vey or imply any lice nse under patent or other rights . Cypress Semiconductor does not authoriz e
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cy press Semiconductor against all charges.
Package Di ag r ams
28-Lead (300-Mil) Molded DIP P21
28-Lead Molded SOJ V21
