CY7C161 CY7C162 16K x 4 Static RAM with Separate I/O Features Easy memory expansion is provided by active LOW chip enables (CE1, CE2) and three-state drivers. They have an automatic power-down feature, reducing the power consumption by 65% when deselected. * High speed -- 15-ns * Transparent write (7C161) * CMOS for optimum speed/power * Low active power -- 633 mW * Low standby power -- 220 mW * TTL compatible inputs and outputs * Automatic power-down when deselected Writing to the device is accomplished when the chip enable (CE1, CE2) and write enable (WE) inputs are both LOW. Data on the four input pins (I0 through I3) is written into the memory location specified on the address pins (A 0 through A13). Reading the device is accomplished by taking the chip enables (CE1, CE2) LOW while write enable (WE) remains HIGH. Under these conditions the contents of the memory location specified on the address pins will appear on the four data output pins. Functional Description The CY7C161 and CY7C162 are high-performance CMOS static RAMs organized as 16,384 by 4 bits with separate I/O. The output pins stay in a high-impedance state when write enable (WE) is LOW (7C162 only), or one of the chip enables (CE1, CE2) are HIGH. A die coat is used to insure alpha immunity. Logic Block Diagram Pin Configurations I0 I1 DIP Top View I2 A5 A6 A7 A8 A9 A 10 A 11 A 12 A 13 I0 I1 CE OE GND I3 INPUT BUFFER SENSE AMPS O0 ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 256 x 256 ARRAY O1 O2 O3 28 2 27 3 26 4 25 5 24 6 23 7 7C161 7C162 8 22 21 9 20 10 19 11 18 12 17 13 16 14 15 CE1 CE2 VCC A4 A3 A2 A1 A0 I3 I2 O3 O2 O1 O0 WE CE2 C162-2 7C162 ONLY A 13 A 12 A 11 A9 A 10 A8 COLUMN DECODER POWER DOWN 1 WE OE 7C161 ONLY C162-1 Selection Guide[1] 7C161-12 7C162-12 12 160 40/20 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA) 7C161-15 7C162-15 15 115 40/20 7C161-20 7C162-20 20 80 40/20 7C161-25 7C162-25 25 70 20/20 7C161-35 7C162-35 35 70 20/20 Shaded areas indicate preliminary information. Note: 1. For military specifications, see the CY7C161A/CY7C162A datasheet. Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 May 1986 - Revised March 1995 CY7C161 CY7C162 DC Input Voltage[2].............................................. -0.5V to +7.0V Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Storage Temperature .....................................-65C to +150C Latch-Up Current..................................................... >200 mA Ambient Temperature with Power Applied ..................................................-55C to +125C Operating Range Range Ambient Temperature VCC Commercial 0C to +70C 5V 10% Supply Voltage to Ground Potential (Pin 24 to Pin 12)..................................................-0.5V to+7.0V DC Voltage Applied to Outputs in High Z State[2] ..................................................-0.5V to+7.0V Electrical Characteristics Over the Operating Range 7C161-12 7C162-12 Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min.,IOH = -4.0 mA VOL Output LOW Voltage VCC = Min.,IOL = 8.0 mA VIH Input HIGH Voltage [2] Min. Max. 2.4 7C161-15 7C162-15 Min. Max. 2.4 0.4 Unit V 0.4 V 2.2 VCC 2.2 VCC V -0.5 0.8 -0.5 0.8 V VIL Input LOW Voltage IIX Input Load Current GND < V I < V CC -5 +5 -5 +5 A IOZ Output Leakage Current GND < V I < V CC, Output Disabled -5 +5 -5 +5 A IOS Output Short Circuit Current[3] VCC = Max., VOUT = GND -350 -350 mA ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA 160 115 mA ISB1 Automatic CE1 Power-Down Current Max. VCC, CE1 > V IH Min. Duty Cycle = 100% 40 40 mA ISB2 Automatic CE1 Power-Down Current Max. VCC, CE1 > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V 20 20 mA Shaded areas indicate preliminary information. Notes: 2. Minimum voltage is equal to -3.0V for pulse durations less than 30 ns. 3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 2 CY7C161 CY7C162 Electrical Characteristics Over the Operating Range (continued) 7C161-20 7C162-20 Test Conditions Min. VOH Parameter Output HIGH Voltage Description VCC = Min., IOH = -4.0 mA 2.4 VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage 7C161-25, 35 7C162-25, 35 Max. Min. 0.4 [2] Max. Unit 2.4 V 0.4 V 2.2 VCC 2.2 VCC V -0.5 0.8 -0.5 0.8 V -5 +5 -5 +5 A +5 -5 VIL Input LOW Voltage IIX Input Load Current IOZ Output Leakage Current GND < VI < VCC GND < VI < VCC,Output Disabled +5 A IOS Output Short Circuit Current[3] VCC = Max., VOUT = GND -350 -350 mA ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA 80 70 mA ISB1 Automatic CE1 Power-Down Current Max. V CC, CE1 > VIH Min. Duty Cycle = 100% 40 20 mA ISB2 Automatic CE1 Power-Down Current Max. V CC, CE1 > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V 20 20 mA -5 Capacitance[4] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. Unit 10 pF 10 pF TA = 25C, f = 1 MHz, VCC = 5.0V Notes: 4. Tested initially and after any design or process changes that may affect these parameters. AC Test Loads and Waveforms R1 481 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE Equivalent to: R1 481 5V OUTPUT R2 255 (a) ALL INPUT PULSES 3.0V 5 pF INCLUDING JIG AND SCOPE R2 255 5 ns (b) C162-3 THEVENIN EQUIVALENT OUTPUT 167 GND 10% 1.73V 3 90% 90% 10% 5 ns C162-4 CY7C161 CY7C162 Switching Characteristics Over the Operating Range[5, 6] Parameter Description 7C161-12 7C162-12 7C161-15 7C162-15 7C161-20 7C162-20 7C161-25 7C162-25 7C161-35 7C162-35 Min. Min. Min. Min. Max. Min. Max. Max. Max. Max. Unit READ CYCLE tRC Read Cycle Time 12 tAA Address to Data Valid tOHA Output Hold from Address Change tACE CE LOW to Data Valid 12 15 20 25 35 ns tDOE OE LOW to Data Valid 12 10 10 12 15 ns tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z tLZCE CE LOW to Low Z[7] 12 3 7 CE HIGH to High Z tPU CE LOW to Power-Up tPD CE HIGH to Power-Down 20 8 7 8 8 12 25 10 8 15 35 12 10 20 ns 5 0 ns ns 15 0 20 ns ns 3 5 0 ns 5 3 5 0 35 5 3 3 0 25 5 3 3 [7, 8] 20 15 3 0 tHZCE WRITE CYCLE 15 ns ns 20 ns [9] tWC Write Cycle Time 12 15 20 20 25 ns tSCE CE LOW to Write End 8 12 15 20 25 ns tAW Address Set-Up to Write End 8 12 15 20 25 ns tHA Address Hold from Write End 0 0 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 0 0 ns tPWE WE Pulse Width 8 12 15 15 20 ns tSD Data Set-Up to Write End 6 10 10 10 15 ns tHD Data Hold from Write End 0 0 0 0 0 ns tLZWE WE HIGH to Low Z[7] (7C162) 3 5 5 5 5 ns [7, 8] tHZWE WE LOW to High Z (7C162) 6 7 7 7 10 ns tAWE WE LOW to Data Valid (7C161) 12 15 20 25 30 ns tADV Data Valid to Output Valid (7C161) 12 15 20 20 30 ns tDCE CE LOW to Data Valid 12 15 20 25 35 ns Shaded areas indicate preliminary information. Notes: 5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I OL/IOH and 30-pF load capacitance. 6. Both CE1 and CE2 are represented by CE in the Switching Characteristics and Waveforms sections. 7. At any given temperature and voltage condition, tHZ is less than tLZ for any given device. 8. t HZCE and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 9. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 LOW, and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 4 CY7C161 CY7C162 Switching Waveforms[8] Read Cycle No. 1 [10,11] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID C162-5 Read Cycle No. 2 [10,12] t RC CE tACE OE t HZOE tDOE DATA OUT tHZCE t LZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT t PD t PU ICC 50% 50% ISB C162-6 Write Cycle No. 1 (WE Controlled) [9] tWC ADDRESS t SCE CE t SA tAW tHA tPWE WE t SD DATAIN VALID DATA IN tHZWE DATA OUT (7C162) t HD t DWE DATA UNDEFINED tLZWE HIGH IMPEDANCE tADV DATA OUT (7C161) DATA UNDEFINED DATA VALID C162-7 Notes: 10. WE is HIGH for read cycle. 11. Device is continuously selected, CE1, CE2 = VIL. 12. Address valid prior to or coincident with CE1, CE2 transition LOW. 5 CY7C161 CY7C162 Switching Waveforms[8] (Continued) Write Cycle No. 2 (CE Controlled) [9,13] t WC ADDRESS t SA tSCE CE tAW tHA t PWE t HZLE WE t HD tSD DATA IN VALID DATA IN t HZLE HIGH IMPEDANCE DATA OUT (7C162) t DCE DATA OUT (7C161) DATA VALID C162-8 Note: 13. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state (7C162 only). NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.2 NORMALIZED I CC, ISB 1.2 ICC 1.0 0.8 0.6 0.4 0.0 4.0 4.5 5.0 ICC 0.8 0.6 0.4 VCC = 5.0V VIN = 5.0V ISB 0.2 ISB 0.2 1.0 5.5 0.0 -55 6.0 NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE 1.4 1.6 1.3 1.4 NORMALIZED tAA NORMALIZED tAA NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.2 TA = 25C 1.0 1.2 1.0 VCC = 5.0V 0.8 0.9 0.8 4.0 125 4.5 5.0 5.5 SUPPLY VOLTAGE (V) OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 VCC = 5.0V TA = 25C 60 40 20 0 0.0 AMBIENT TEMPERATURE (C) SUPPLY VOLTAGE (V) 1.1 25 6.0 0.6 -55 25 125 AMBIENT TEMPERATURE (C) 6 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT (mA) NORMALIZED ICC , ISB 1.4 OUTPUT SOURCE CURRENT (mA) Typical DC and AC Characteristics OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 VCC = 5.0V TA = 25C 80 60 40 20 0 0.0 1.0 2.0 3.0 OUTPUT VOLTAGE (V) 4.0 CY7C161 CY7C162 Typical DC and AC Characteristics TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 2.5 2.0 1.5 1.0 0.5 0.0 0.0 NORMALIZED I CC vs.CYCLE TIME 30.0 1.25 25.0 20.0 15.0 10.0 VCC = 4.5V TA = 25C NORMALIZED ICC NORMALIZED tAA (ns) NORMALIZED IPO 3.0 TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING VCC = 5.0V TA = 25C VCC = 0.5V 1.00 0.75 5.0 1.0 2.0 3.0 5.0 4.0 SUPPLY VOLTAGE (V) 0.0 0 200 400 600 800 1000 CAPACITANCE (pF) Address Designators Address Name Address Function Pin Number A5 X3 1 A6 X4 2 A7 X5 3 A8 X6 4 A9 X7 5 A10 Y0 6 A11 Y1 7 A12 Y5 8 A13 Y4 9 A0 Y3 23 A1 Y2 24 A2 X0 25 A3 X1 26 A4 X2 27 7 0.50 10 20 30 CYCLE FREQUENCY (MHz) 40 CY7C161 CY7C162 Ordering Information Speed (ns) 12 15 20 25 35 Speed (ns) 12 15 20 25 35 Package Name Package Type Operating Range CY7C161-12PC P21 28-Lead (300-Mil) Molded DIP Commercial CY7C161-12VC V21 28-Lead Molded SOJ CY7C161-15PC P21 28-Lead (300-Mil) Molded DIP CY7C161-15VC V21 28-Lead Molded SOJ CY7C161-20PC P21 28-Lead (300-Mil) Molded DIP CY7C161-20VC V21 28-Lead Molded SOJ CY7C161-25PC P21 28-Lead (300-Mil) Molded DIP CY7C161-25VC V21 28-Lead Molded SOJ CY7C161-35PC P21 28-Lead (300-Mil) Molded DIP CY7C161-35VC V21 28-Lead Molded SOJ Ordering Code Commercial Commercial Commercial Commercial Package Name Package Type Operating Range CY7C162-12PC P21 28-Lead (300-Mil) Molded DIP Commercial CY7C162-12VC V21 28-Lead Molded SOJ CY7C162-15PC P21 28-Lead (300-Mil) Molded DIP CY7C162-15VC V21 28-Lead Molded SOJ CY7C162-20PC P21 28-Lead (300-Mil) Molded DIP CY7C162-20VC V21 28-Lead Molded SOJ CY7C162-25PC P21 28-Lead (300-Mil) Molded DIP CY7C162-25VC V21 28-Lead Molded SOJ CY7C162-35PC P21 28-Lead (300-Mil) Molded DIP CY7C162-35VC V21 28-Lead Molded SOJ Ordering Code Shaded areas indicate preliminary information. Document #: 38-00029-I 8 Commercial Commercial Commercial Commercial CY7C161 CY7C162 Package Diagrams 28-Lead (300-Mil) Molded DIP P21 28-Lead Molded SOJ V21 (c) Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.