DDC264 DD C2 64 SBAS368C - MAY 2006 - REVISED JULY 2011 www.ti.com 64-Channel, Current-Input Analog-to-Digital Converter Check for Samples: DDC264 FEATURES 1 * 2 * * * * * * * * * Single-Chip Solution to Directly Measure 64 Low-Level Currents Proven High-Precision, True Integrating Architecture with 100% Charge Collection Easy Upgrade for Existing DDC Family Applications Very Low Power: 3mW/channel Extremely Linear: INL = 0.025% of Reading 1.0ppm of FSR Low Noise: 6.3ppm of FSR Adjustable Full-Scale Range Adjustable Speed - Data Rates up to 6kSPS with 20-bit Performance - Integration Times as low as 160s Daisy-Chainable Serial Interface In-Package Bypass Capacitors Simplify PCB Design APPLICATIONS * * * CT Scanner DAS Photodiode Sensors X-Ray Detection Systems DESCRIPTION The DDC264 is a 20-bit, 64-channel, current-input analog-to-digital (A/D) converter. It combines both current-to-voltage and A/D conversion so that 64 separate low-level current output devices, such as photodiodes, can be directly connected to its inputs and digitized. For each of the 64 inputs, the DDC264 uses the proven dual switched integrator front-end. This configuration allows for continuous current integration: while one integrator is being digitized by the onboard A/D converter, the other is integrating the input current. This architecture provides both a very stable offset and a loss-less collection of the input current. Adjustable integration times range from 160s to 1s, allowing currents from fAs to As to be continuously measured with outstanding precision. The DDC264 has a serial interface designed for daisy-chaining in multi-device systems. Simply connect the output of one device to the input of the next to create the chain. Common clocking feeds all the devices in the chain so that the digital overhead in a multi-DDC264 system is minimal. The DDC264 uses a +5V analog supply and a +2.7V to +3.6V digital supply. Bypass capacitors within the DDC264 package help minimize the external component requirements. Operating over the temperature range of 0C to +70C, the DDC264 BGA-100 package is offered in two versions: the DDC264C for low-power applications, and the DDC264CK when higher speeds are required. AVDD VREF DVDD 0.2mF 0.3mF IN1 0.1mF Dual Switched Integrator CLK DS ADC IN2 Dual Switched Integrator CONV Configuration and Control DIN_CFG CLK_CFG RESET IN3 Dual Switched Integrator DS ADC IN4 Dual Switched Integrator IN61 Dual Switched Integrator DVALID DCLK Serial Interface DS ADC IN62 Dual Switched Integrator IN63 Dual Switched Integrator DOUT DIN DS ADC IN64 Dual Switched Integrator AGND DGND Protected by US Patent #5841310 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2006-2011, Texas Instruments Incorporated DDC264 SBAS368C - MAY 2006 - REVISED JULY 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DDC FAMILY OVERVIEW PRODUCT NO. OF CHANNELS FULL-SCALE MAXIMUM DATA RATE POWER/CHANNEL PACKAGELEAD DDC112 2 1000pC 20kSPS 40mW SO-28 DDC112K 2 1000pC 3.3kSPS 40mW TQFP-32 DDC114 4 350pC 3.3kSPS 13mW QFN-48 DDC118 8 350pC 3.3kSPS 13mW QFN-48 DDC316 16 12pC 100kSPS 28mW BGA-64 DDC232C 32 350pC 3.1kSPS 7mW BGA-64 DDC232CK 32 350pC 6.2kSPS 10mW BGA-64 DDC264C 64 150pC 3.1kSPS 3mW BGA-100 DDC264CK 64 150pC 6.2kSPS 5.5mW BGA-100 ORDERING INFORMATION For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) AVDD to AGND -0.3V to +6V DVDD to DGND -0.3V to +3.6V AGND to DGND VREF Input to AGND Analog Input to AGND 0.2V 2.0V to AVDD + 0.3V -0.3V to +0.7V Digital Input Voltage to DGND -0.3V to DVDD + 0.3V Digital Output Voltage to DGND -0.3V to DVDD + 0.3V Operating Temperature Storage Temperature Junction Temperature (TJ) ESD Ratings: (1) 2 0C to +70C -60C to +150C +150C Human Body Model (HBM) JEDEC standard 22, test method A114-C.01, all pins 4kV Charged Device Model (CDM) JEDEC standard 22, test method A114-C.01, all pins 1kV Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Copyright (c) 2006-2011, Texas Instruments Incorporated DDC264 SBAS368C - MAY 2006 - REVISED JULY 2011 www.ti.com ELECTRICAL CHARACTERISTICS At TA = +25C, AVDD = +5V, DVDD = +3.0V, VREF = +4.096V, tINT = 333s for DDC264C or 166s for DDC264CK, and Range = 3 (150pC), unless otherwise noted. DDC264C PARAMETER TEST CONDITIONS DDC264CK MIN TYP MAX MIN TYP MAX UNIT Range 0 10.5 12.5 14.5 10.5 12.5 14.5 pC Range 1 47.5 50 52.5 47.5 50 52.5 pC Range 2 95 100 105 95 100 105 pC Range 3 142.5 150 157.5 142.5 150 157.5 pC ANALOG INPUT RANGE -0.4% of Positive Full-Scale Range Negative Full-Scale Range -0.4% of Positive Full-Scale Range pC 6 6.25 kSPS 166 1,000,000 s DYNAMIC CHARACTERISTICS Data Rate Integration Time, tINT System Clock (CLK) 320 3 3.125 333 1,000,000 160 Clkdiv = 0 1 5 1 10 MHz Clkdiv = 1 4 20 4 40 MHz Data Clock (DCLK) 32 32 MHz Configuration Clock (CLK_CFG) 20 20 MHz ACCURACY Noise, Low-Level Input (1) Range = 3, CSENSOR (2) = 35pF Integral Linearity Error (4) Resolution Input Bias Current 0.05% Reading 1.5ppm FSR, max 0.05% Reading 1.5ppm FSR, max 20 20 No Missing Codes, Format = 0 16 16 Range Error Match (5) Range Sensitivity to VREF 6.3 0.025% Reading 1.0ppm FSR, typ No Missing Codes, Format = 1 TA = +25C to +45C VREF = 4.096 0.1V 0.5 5 pA 0.1 0.5 0.1 0.5 % of FSR 1000 500 1000 ppm of FSR 1:1 Offset Error Match (5) 150 (1) (2) (3) (4) (5) (6) Bits 5 500 Power-Supply Rejection Ratio Bits 0.5 Offset Error DC Bias Voltage (6) ppm of FSR (3), rms 6.3 0.025% Reading 1.0ppm FSR, typ 1:1 150 ppm of FSR Low-Level Input (< 1% FSR) 0.1 1 0.1 1 mV At dc 100 300 100 300 ppm of FSR/V Input is less than 1% of full-scale. CSENSOR is the capacitance seen at the DDC264 inputs from wiring, photodiode, etc. FSR is full-scale range. A best-fit line is used in measuring nonlinearity. Matching between side A and side B of the same input. Voltage produced by the DDC264 at its input that is applied to the sensor. Copyright (c) 2006-2011, Texas Instruments Incorporated 3 DDC264 SBAS368C - MAY 2006 - REVISED JULY 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) At TA = +25C, AVDD = +5V, DVDD = +3.0V, VREF = +4.096V, tINT = 333s for DDC264C or 166s for DDC264CK, and Range = 3 (150pC), unless otherwise noted. DDC264C PARAMETER TEST CONDITIONS MIN DDC264CK TYP MAX 0.5 0.2 MIN TYP MAX UNIT 5 (7) 0.5 5 (7) ppm of FSR/C (7) 0.2 2 (7) ppm of FSR/minute 0.01 1 (7) 0.01 1 (7) pA/C Range Drift (9) 25 50 25 50 ppm/C Range Drift Match (10) 5 PERFORMANCE OVER TEMPERATURE Offset Drift Offset Drift Stability DC Bias Voltage Drift (8) 2 3 Input Bias Current Drift TA = +25C to +45C 3 V/C 5 ppm/C REFERENCE Voltage 4.000 Input Current (11) 4.096 Average Value with tINT = 333s 4.200 4.000 4.096 4.200 V A 825 Average Value with tINT = 166s A 1650 DIGITAL INPUT/OUTPUT Logic Levels VIH 0.8 DVDD DVDD + 0.1 0.8 DVDD DVDD + 0.1 V VIL -0.1 0.2 DVDD -0.1 0.2 DVDD V VOH IOH = -500A VOL IOL = 500A 0.4 0.4 V 0 < VIN < DVDD 10 10 A Input Current (IIN) DVDD - 0.4 Data Format (12) DVDD - 0.4 Straight Binary V Straight Binary POWER-SUPPLY REQUIREMENTS Analog Power-Supply Voltage (AVDD) 4.75 5.0 5.25 4.9 5.0 5.1 V Digital Power-Supply Voltage (DVDD) 2.7 3.3 3.6 2.7 3.3 3.6 V Supply Current Analog Current 34 60 Digital Current 7.5 15 mA Total Power Dissipation Per Channel Power Dissipation (7) (8) (9) (10) (11) (12) mA 192 256 350 mW 3 4 5.5 mW/Channel Ensured by design; not production tested. Voltage produced by the DDC264 at its input that is applied to the sensor. Range drift does not include external reference drift. Matching between side A and side B of the same input. Input reference current decreases with increasing tINT (see the Voltage Reference section). Data format is Straight Binary with a small offset. The number of bits in the output word is controlled by the Format bit. THERMAL INFORMATION THERMAL METRIC (1) DDC264C, DDC264CK ZAW Package UNITS 100 Balls JA Junction-to-ambient thermal resistance 25.7 JCtop Junction-to-case (top) thermal resistance 9.8 JB Junction-to-board thermal resistance 7.1 JT Junction-to-top characterization parameter 0.1 JB Junction-to-board characterization parameter 7.0 JCbot Junction-to-case (bottom) thermal resistance N/A (1) 4 C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Copyright (c) 2006-2011, Texas Instruments Incorporated DDC264 SBAS368C - MAY 2006 - REVISED JULY 2011 www.ti.com PIN CONFIGURATION ZAW PACKAGE 9mm x 9mm BGA (TOP VIEW) Columns K J H G F E D C B A IN39 IN40 IN8 IN45 IN16 IN49 IN51 IN55 IN57 IN58 1 IN38 IN7 IN41 IN12 IN48 IN19 IN20 IN23 IN25 IN26 2 IN37 IN6 IN9 IN44 IN15 IN50 IN53 IN56 IN60 IN59 3 IN3 IN5 IN42 IN11 IN47 IN18 IN21 IN28 IN27 IN32 4 IN34 IN35 IN10 IN43 IN14 IN52 IN54 IN61 IN62 IN63 IN33 IN4 IN36 IN13 IN46 IN17 IN22 IN29 IN30 IN31 Rows 5 6 IN1 IN2 QGND QGND AGND AGND AGND AGND IN24 IN64 7 AGND AGND AGND AVDD AGND VREF VREF AGND AGND AGND 8 AVDD AVDD AVDD AVDD AVDD DGND DGND RST DIN_CFG CLK_CFG 9 CONV DGND DGND DVALID CLK DVDD DVDD DCLK DIN DOUT 10 PIN DESCRIPTIONS PIN LOCATION FUNCTION DESCRIPTION IN1-IN64 Rows 1-6, A7, B7, J7, K7 Analog input Analog inputs for channels 1 to 64 QGND G7, H7 Analog Quiet analog ground; see the guidelines described in the Layout section AGND A8, B8, C7, C8, D7, E7, F7, F8, H8, J8. K8 Analog Analog ground DGND D9, E9, H10, J10 Digital Digital ground AVDD F9, G8, G9, H9, J9, K9 Analog Analog power supply, +5V nominal VREF D8, E8 Analog input External voltage reference input, +4.096V nominal DVALID G10 Digital output Data valid output, active low DIN_CFG B9 Digital input Configuration register data input CLK_CFG A9 Digital input Configuration register clock input RESET C9 Digital input Digital reset, active low DVDD D10, E10 Digital CONV K10 Digital input Conversion control input: 0 = integrate on side B; 1 = integrate on side A DIN B10 Digital input Serial data input DOUT A10 Digital output Serial data output CLK F10 Digital input Master clock input DCLK C10 Digital input Serial data clock input Copyright (c) 2006-2011, Texas Instruments Incorporated Digital power supply, +3.3V nominal 5 DDC264 SBAS368C - MAY 2006 - REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS At TA = +25C, unless otherwise indicated. DDC264C, 3kSPS 60 Range 0 50 40 Range 3 30 20 10 0 Range 2 Range 1 -10 -20 -30 0 INTEGRAL NONLINEARITY Integral Nonlinearity (ppm of Full-Scale) Integral Nonlinearity (ppm of Full-Scale) INTEGRAL NONLINEARITY 70 125 100 75 Range 3 50 25 0 -25 Range 2 -50 Range 1 -75 -100 -125 0 100k 200k 300k 400k 500k 600k 700k 800k 900k 1M Figure 1. Figure 2. INTEGRAL NONLINEARITY ENVELOPE OF ALL 64 CHANNELS INTEGRAL NONLINEARITY ENVELOPE OF ALL 64 CHANNELS DDC264C, 3kSPS Range 3, +25C 40 30 Average 20 10 0 -10 -20 -30 -40 -50 0 100k 200k 300k 400k 500k 600k 700k 800k 900k 1M Input (ppm of Full-Scale) Integral Nonlinearity (ppm of Full-Scale) Integral Nonlinearity (ppm of Full-Scale) Input (ppm of Full-Scale) 50 125 DDC264CK, 6kSPS Range 3, +25C 100 75 50 25 Average 0 -25 -50 -75 -100 -125 0 100k 200k 300k 400k 500k 600k 700k 800k 900k 1M Input (ppm of Full-Scale) 100k 200k 300k 400k 500k 600k 700k 800k 900k 1M Input (ppm of Full-Scale) Figure 3. Figure 4. DDC264C, 3kSPS Range 3 40 +75C +60C 30 20 10 0 +45C -10 +25C -20 -5C -30 -40 -50 0 100k 200k 300k 400k 500k 600k 700k 800k 900k 1M Input (ppm of Full-Scale) Figure 5. 6 INTEGRAL NONLINEARITY vs TEMPERATURE Integral Nonlinearity (ppm of Full-Scale) Integral Nonlinearity (ppm of Full-Scale) INTEGRAL NONLINEARITY vs TEMPERATURE 50 Range 0 DDC264CK, 6kSPS 125 DDC264CK, 6kSPS Range 3 100 +75C 75 +60C 50 +45C 25 0 -25 -50 -75 +25C -100 -5C -125 0 100k 200k 300k 400k 500k 600k 700k 800k 900k 1M Input (ppm of Full-Scale) Figure 6. Copyright (c) 2006-2011, Texas Instruments Incorporated DDC264 SBAS368C - MAY 2006 - REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25C, unless otherwise indicated. NOISE vs INTEGRATION TIME DDC264C, 3kSPS DDC264CK, 6kSPS CSENSOR = 35pF Range 3 9 8 7 Range 1 Noise (ppm of Full-Scale, RMS) Noise (ppm of Full-Scale, RMS) NOISE vs INPUT LEVEL 12 10 6 5 4 3 2 1 0 10 Range 2 8 6 Range 3 4 DDC264C, 3kSPS DDC264CK, 6kSPS CSENSOR = 35pF 2 0 0.1 1 10 100 0 20 80 Figure 7. Figure 8. 100 INPUT BIAS CURRENT vs TEMPERATURE 10 CSENSOR = 35pF DDC264C, 3kSPS DDC264CK, 6kSPS Ranges 1, 2, 3 35 30 Range 0 Bias Current (pA) Noise (ppm of Full-Scale, RMS) 60 Percentage of Input (%) NOISE vs TEMPERATURE 40 40 Integration Time (ms) 25 20 Range 1 15 1 0.1 Range 2 10 5 Range 3 0 0.01 0 10 20 30 40 50 60 70 0 10 20 Temperature (C) Figure 9. 150 50 60 70 OFFSET DRIFT STABILITY OVER TIME HISTOGRAM 12 DDC264C, 3kSPS DC264CK, 6kSPS Ranges 1, 2, 3 Repeated measurement of offset drift taken over a 1-min interval 10 100 % of Occurrences Offset Drift (ppm of FSR) 200 40 Figure 10. OFFSET DRIFT vs TEMPERATURE 250 30 Temperature (C) 50 0 -50 -100 -150 DDC264C, 3kSPS DC264CK, 6kSPS Range 3 8 6 4 2 -200 -250 Temperature (C) 65 70 0 0.6 60 0.45 55 0.3 50 0.15 45 -0.15 40 -0.3 35 -0.45 30 -0.6 0 25 Offset Drift (ppm of FSR/min) Figure 11. Copyright (c) 2006-2011, Texas Instruments Incorporated Figure 12. 7 DDC264 SBAS368C - MAY 2006 - REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25C, unless otherwise indicated. ANALOG SUPPLY CURRENT vs TEMPERATURE DIGITAL SUPPLY CURRENT vs TEMPERATURE 70 20 65 DDC264CK 6kSPS 55 50 45 DDC264C 3kSPS 40 DDC264CK 6kSPS 15 Current (mA) Current (mA) 60 10 DDC264C 3kSPS 5 35 30 0 0 10 20 30 40 50 60 70 0 20 30 40 50 Temperature (C) Figure 13. Figure 14. DC BIAS VOLTAGE vs INPUT PERCENTAGE 60 70 DC BIAS VOLTAGE vs INPUT PERCENTAGE 2.5 3.5 Range 3 DDC264C 3kSPS 2 Range 2 1.5 Range 1 1 Range 0 Range 3 DDC264CK 6kSPS 3 DC Bias Voltage (mV) DC Bias Voltage (mV) 10 Temperature (C) Range 2 2.5 2 1.5 Range 1 1 Range 0 0.5 0.5 0 0 0 8 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 Percentage of Input (%) Percentage of Input (%) Figure 15. Figure 16. 80 90 100 Copyright (c) 2006-2011, Texas Instruments Incorporated DDC264 SBAS368C - MAY 2006 - REVISED JULY 2011 www.ti.com Noise (ppm of FSR, rms) Figure 17. NOISE vs CSENSOR 600 DDC264C, 3kSPS 550 DDC264CK, 6kSPS Range 0 500 450 400 350 300 250 Range 3 200 Range 2 150 Range 1 100 50 0 0 100 200 300 400 500 600 700 800 900 1000 CSENSOR (pF) Figure 18. Table 1. NOISE vs CSENSOR (1) CSENSOR RANGE 0pF 10pF 30pF 43pF 57pF 100pF 270pF 470pF 1000pF 44 71 160 270 510 ppm of FSR, rms Range 0: 12.5pC 16 20 30 37 Range 1: 50pC 6.4 7.4 10 12 14 21 45 74 130 Range 2: 100pC 5.1 5.5 7.1 8 9.1 12 25 39 71 Range 3: 150pC 4.8 5 6 6.5 7.2 9.6 17 27 49 Range 0: 12.5pC 0.20 0.25 0.38 0.46 0.55 0.89 2.0 3.38 6.38 Range 1: 50pC 0.32 0.37 0.53 0.62 0.73 1.09 2.29 3.73 6.88 Range 2: 100pC 0.51 0.55 0.71 0.80 0.91 1.28 2.50 3.97 7.16 Range 3: 150pC 0.72 0.75 0.90 0.98 1.08 1.45 2.67 4.14 7.36 fC, rms Electrons, rms (1) Range 0: 12.5pC 1250 1560 2340 2890 3430 5540 12480 21070 39790 Range 1: 50pC 2010 2310 3340 3910 4570 6800 14200 23300 42900 Range 2: 100pC 3220 3440 4450 5000 5680 7990 15600 24800 44700 Range 3: 150pC 4530 4730 5610 6120 6770 9050 16700 25800 45900 Noise in Table 1 is expressed in three different units for reader convenience. The first section lists noise in units of parts per million of full-scale range; the second section shows noise as an equivalent input charge (in fC); and the third section converts noise to electrons. Copyright (c) 2006-2011, Texas Instruments Incorporated 9 DDC264 SBAS368C - MAY 2006 - REVISED JULY 2011 www.ti.com THEORY OF OPERATION General Description A dual switched integrator input channel for the DDC264 is shown in Figure 19. The DDC264 contains 64 identical input channels that perform the function of current-to-voltage integration followed by a multiplexed A/D conversion. Each input has two integrators so that the current-to-voltage integration can be continuous in time. The DDC264 continuously integrates the input signal by switching integrations between side A and side B. Input Current For example, while side A integrates the input signal, the side B outputs are digitized by the onboard ADC. This integration and A/D conversion process is controlled by the convert pin, CONV. The results from side A and side B of each signal input are stored in a serial output shift register. The DVALID output goes low when the shift register data are ready to be retrieved. Side A Integrator IN1 QGND To ADC Photodiode Side B Integrator QGND Figure 19. Dual Switched Integrator Architecture 10 Copyright (c) 2006-2011, Texas Instruments Incorporated DDC264 SBAS368C - MAY 2006 - REVISED JULY 2011 www.ti.com Basic Integration Cycle At the completion of an A/D conversion, the charge on the integration capacitor (CF) is reset with SREF1 and SRESET (see Figure 21 and Figure 22a). This process is done during reset. In this manner, the selected capacitor is charged to the reference voltage, VREF. Once the integration capacitor is charged, SREF1 and SRESET are switched so that VREF is no longer connected to the amplifier circuit while it waits to begin integrating (see Figure 22b). With the rising edge of CONV, SINTA closes, which begins the integration of side A. This process puts the integrator stage into its integrate mode (see Figure 22c). The topology of the front end of the DDC264 is an analog integrator as shown in Figure 20. In this diagram, only input IN1 is shown. The input stage consists of an operational amplifier, a selectable feedback capacitor network (CF), and several switches that implement the integration cycle. The timing relationships of all of the switches shown in Figure 20 are illustrated in Figure 21. Figure 21 conceptualizes the operation of the integrator input stage of the DDC264 and should not be used as an exact timing tool for design. See Figure 22 for the block diagrams of the reset, integrate, wait, and convert states of the integrator section of the DDC264. This internal switching network is controlled externally with the convert pin (CONV) and the system clock (CLK). For the best noise performance, CONV must be synchronized with the falling edge of CLK. It is recommended that CONV toggle within 10ns of the falling edge of CLK. Charge from the input signal is collected on the integration capacitor, causing the voltage output of the amplifier to decrease. The falling edge of CONV stops the integration by switching the input signal from side A to side B (SINTA and SINTB). Prior to the falling edge of CONV, the signal on side B was converted by the A/D converter and reset during the time that side A was integrating. With the falling edge of CONV, side B starts integrating the input signal. At this point, the output voltage of the side A operational amplifier is presented to the input of the A/D converter (see Figure 22d). The noninverting inputs of the integrators are connected to the QGND pin. Consequently, the DDC264 analog ground, QGND, should be as clean as possible. In Figure 20, the feedback capacitors (CF) are shown in parallel between the inverting input and output of the operational amplifier. At the beginning of a conversion, the switches SA/D, SINTA, SINTB, SREF1, SREF2, and SRESET are set (see Figure 21). A special elecrostatic discharge (ESD) structure protects the inputs but does not increase current leakage on the input pins. Range Selection Capacitors (CF) SREF1 VREF 3pF 12.5pF Range[0] Bit 25pF Range[1] Bit Input Current SINTA SREF2 IN1 SRESET Photodiode ESD Protection Diodes SADC1A To Converter Integrator A SINTB QGND Integrator B Figure 20. Basic Integration Configuration Copyright (c) 2006-2011, Texas Instruments Incorporated 11 DDC264 SBAS368C - MAY 2006 - REVISED JULY 2011 www.ti.com CONV CLK SINTA SINTB SREF1 SREF2 SRESET Convert Wait Wait Integrate Reset Wait Convert Wait Configuration of Integrator A Reset SA/D1A VREF Integrator A Voltage Output Figure 21. Integration Timing (see Figure 20) SREF1 CF VREF SINT SREF2 CF IN SREF1 VREF To Converter SRESET SA/D SINT SREF2 IN To Converter SRESET SA/D a) Reset/Auto Zero Configuration CF SREF1 b) Wait Configuration VREF SINT SREF2 CF IN SREF1 VREF To Converter SRESET SA/D SINT SREF2 IN To Converter SRESET SA/D c) Integrate Configuration d) Convert Configuration Figure 22. Four Configurations of the Front-End Integrators 12 Copyright (c) 2006-2011, Texas Instruments Incorporated DDC264 SBAS368C - MAY 2006 - REVISED JULY 2011 www.ti.com Integration Capacitors amount of charge needed by the A/D converter is independent of the integration time; therefore, increasing the integration time lowers the average current. For example, an integration time of 800s lowers the average VREF current to 340A. There are four different capacitor configurations available on-chip for both sides of every channel in the DDC264. These internal capacitors are trimmed in production to achieve the specified performance for range error of the DDC264. The range control bits (Range[1:0]) set the capacitor value for all integrators. Consequently, all inputs and both sides of each input always have the same full-scale range. Table 2 shows the capacitor value selected for each range selection. It is critical that VREF be stable during the different modes of operation (see Figure 22). The A/D converter measures the voltage on the integrator with respect to VREF. Because the integrator capacitors are initially reset to VREF, any drop in VREF from the time the capacitors are reset to the time when the converter measures the integrator output introduces an offset. It is also important that VREF be stable over longer periods of time because changes in VREF correspond directly to changes in the full-scale range. Finally, VREF should introduce as little additional noise as possible. Table 2. Range Selection RANGE CONTROL BITS CF INPUT RANGE 0 3pF -0.04 to 12.5pC 0 1 12.5pF -0.2 to 50.0pC 2 1 0 25pF -0.4 to 100pC 3 1 1 37.5pF -0.6 to 150pC RANGE Range[1] Range[0] 0 0 1 For these reasons, it is strongly recommended that the external reference source be buffered with an operational amplifier, as shown in Figure 23. In this circuit, the voltage reference is generated by a +4.096V reference. A low-pass filter to reduce noise connects the reference to an operational amplifier configured as a buffer. This amplifier should have low noise and input/output common-mode ranges that support VREF. Even though the circuit in Figure 23 might appear to be unstable because of the large output capacitors, it works well for the OPA350. It is not recommended that series resistance be placed in the output lead to improve stability because this can cause a drop in VREF, which produces large offsets. Voltage Reference The external voltage reference is used to reset the integration capacitors before an integration cycle begins. It is also used by the A/D converter while the converter is measuring the voltage stored on the integrators after an integration cycle ends. During this sampling, the external reference must supply the charge needed by the A/D converter. For an integration time of 333s, this charge translates to an average VREF current of approximately 825A. The +5V +5V 0.10mF 0.47mF 7 2 1 REF3040 6 2 1kW 3 + To VREF Pin on the DDC264 OPA350 0.7W 0.7W 47mF 3 0.10mF 4 (1) 100mF (1) 10mF Near Each DDC (1) Ceramic X5R capacitors are recommended. Figure 23. Recommended External Voltage Reference Circuit for Best Low-Noise Operation Copyright (c) 2006-2011, Texas Instruments Incorporated 13 DDC264 SBAS368C - MAY 2006 - REVISED JULY 2011 www.ti.com Frequency Response System and Data Clocks (CLK and DCLK) The frequency response of the DDC264 is set by the front-end integrators and is that of a traditional continuous time integrator, as shown in Figure 24. By adjusting the integration time, tINT, the user can change the 3dB bandwidth and the location of the notches in the response. The frequency response of the A/D converter that follows the front-end integrator is of no consequence because the converter samples a held signal from the integrators. That is, the input to the A/D converter is always a dc signal. The output of the front-end integrators are sampled; therefore, aliasing can occur. Whenever the frequency of the input signal exceeds one-half of the sampling rate, the signal folds back down to lower frequencies. The system clock is supplied to CLK and the data clock is supplied to DCLK. It is recommended that the CLK pin be driven by a free-running clock source (that is, do not start and stop CLK between conversions). Make sure the clock signals are clean--avoid overshoot or ringing. For best performance, generate both clocks from the same clock source. Disable DCLK by taking it low after the data have been shifted out and while CONV is transitioning. 0 When using multiple DDC264s, pay close attention to the DCLK distribution on the printed circuit board (PCB). In particular, make sure to minimize skew in the DCLK signal because this can lead to timing violations in the serial interface specifications. See the Cascading Multiple Converters section for more details. -10 Gain (dB) Data Valid (DVALID) -20 -30 -40 -50 0.1 tINT 1 tINT 10 tINT 100 tINT Frequency Figure 24. Frequency Response DIGITAL INTERFACE The digital interface of the DDC264 sends the digital results via a synchronous serial interface that consists of a data clock (DCLK), a valid data pin (DVALID), a serial data output pin (DOUT), and a serial data input pin (DIN). The integration and conversion process is fundamentally independent of the data retrieval process. Consequently, the CLK and DCLK frequencies need not be the same, though for best performance, it is highly recommended that they be derived from the same clocking source to keep the phase relationship constant. DIN is only used when multiple converters are cascaded and should be tied to DGND otherwise. Depending on tINT, CLK, and DCLK, it is possible to daisy-chain multiple converters. This option greatly simplifies the interconnection and routing of the digital outputs in those applications where a large number of converters are needed. Configuration of the DDC264 is set by a dedicated register addressed using the DIN_CFG and CLK_CFG pins. 14 The DVALID signal indicates that data are ready. Data retrieval may begin after DVALID goes low. This signal is generated using an internal clock divided down from the system clock, CLK. The phase relationship between this internal clock and CLK is set when power is first applied and is random. Because the user must synchronize CONV with CLK, the DVALID signal has a random phase relationship with CONV. This uncertainty is 1/fCLK. Polling DVALID eliminates any concern about this relationship. If the data readback is timed from CONV, make sure to wait for the required amount of time. Reset (RESET) The DDC264 is reset asynchronously by taking the RESET input low, as shown in Figure 25. Make sure the release pulse is a minimum of tRST wide. It is very important that RESET is glitch-free to avoid unintentional resets. The Configuration Register must be programmed immediately afterwards. After programming the DDC264, wait at least four conversions before using the data. RESET tRST Figure 25. Reset Timing Copyright (c) 2006-2011, Texas Instruments Incorporated DDC264 SBAS368C - MAY 2006 - REVISED JULY 2011 www.ti.com TIMING EXAMPLES Integration Time Figure 26 shows a few integration cycles beginning after the device has been powered up, reset, and the Configuration Register has been programmed. The top signal is CONV and is supplied by the user. The integration status trace indicates which side is integrating. As described in the data sheet, DVALID goes active low when data are ready to be retrieved from the DDC264. It stays low until DCLK is taken high and then back low by the user. The text below the DVALID pulse indicates the side of the data available to be read. The arrow is used to match the data to the corresponding integration. Table 3 shows the timing specifications for Figure 26. The minimum tINT depends on which device is being used. The minimum time scales directly with the internal clock frequency. For the DDC264C, with an internal clock frequency of 5MHz, the minimum time is 320s. For the DDC264CK, with an internal clock frequency of 10MHz, the minimum time is 166s. If the minimum integration time is violated, the DDC264 stops continuously integrating the input signal. To return to normal operation (that is, continuous integration) after a violation of the minimum tINT specification, perform three integrations that each last for a minimum of 5000 internal clock periods. In other words, integrate three times with each integration lasting for at least 1ms when using an internal clock frequency of 5MHz. During this time, ignore the DVALID pin. Once the three integrations complete, normal continuous operation resumes, and data can be retrieved. tINT CONV Integration Status Integrate B Integrate A Integrate B Integrate A tDR DVALID Side B Data Side A Data Side B Data Figure 26. Integration Sequence Timing Table 3. Timing Specifications for Figure 26 SYMBOL DESCRIPTION tINT Integration time tDR Time until data ready Copyright (c) 2006-2011, Texas Instruments Incorporated DDC264C Internal Clock Frequency = 5MHz DDC264CK Internal Clock Frequency = 10MHz MIN MAX MIN 1,000,000 160 TYP 320 276.4 0.4 TYP MAX UNITS s 138.2 0.2 s 15 DDC264 SBAS368C - MAY 2006 - REVISED JULY 2011 www.ti.com DATA FORMAT Make sure not to retrieve data around changes in CONV because this change can introduce noise. Stop activity on DCLK at least 2s before or after a CONV transition. The serial output data are provided in an offset binary code as shown in Table 4. The Format bit in the Configuration Register selects how many bits are used in the output word. When Format = 1, 20 bits are used. When Format = 0, the lower four bits are truncated so that only 16 bits are used. Note that the LSB size is 16 times bigger when Format = 0. An offset is included in the output to allow slightly negative inputs (for example, from board leakages) from clipping the reading. This offset is approximately 0.4% of the positive full-scale. Setting the Format bit = 0 (16-bit output word) reduces the time needed to retrieve data by 20% because there are fewer bits to shift out. This technique can be useful in multichannel systems requiring only 16 bits of resolution. Table 4. Ideal Output Code(1) vs Input Signal DATA RETRIEVAL The data from the last conversion are available for retrieval on the falling edge of DVALID (see Figure 27 and Table 5). Data are shifted out on the falling edge of the data clock, DCLK. INPUT SIGNAL IDEAL OUTPUT CODE FORMAT = 1 IDEAL OUTPUT CODE FORMAT = 0 100% FS 1111 1111 1111 1111 1111 1111 1111 1111 1111 0.001531% FS 0000 0001 0000 0001 0000 0000 0001 0000 0001 0.001436% FS 0000 0001 0000 0000 1111 0000 0001 0000 0000 0.000191% FS 0000 0001 0000 0000 0010 0000 0001 0000 0000 0.000096% FS 0000 0001 0000 0000 0001 0000 0001 0000 0000 0% FS 0000 0001 0000 0000 0000 0000 0001 0000 0000 -0.3955% FS 0000 0000 0000 0000 0000 0000 0000 0000 0000 (1) Excludes the effects of noise, INL, offset, and gain errors. CLK tPDCDV DVALID tPDDCDV tHDDODV DCLK tHDDODC Input 64 MSB DOUT Input 64 Input 63 LSB LSB Input 5 LSB Input 4 MSB Input 2 LSB Input 1 MSB Input 1 LSB Input 64 MSB tPDDCDO Figure 27. Digital Interface Timing Diagram for Data Retrieval From a Single DDC264 Table 5. Timing for DDC264 Data Retrieval SYMBOL 16 MIN TYP MAX UNITS Propagation delay from falling edge of CLK to DVALID Low 10 ns tPDDCDV Propagation delay from falling edge of DCLK to DVALID High 5 ns tHDDODV Hold time that DOUT is valid before the falling edge of DVALID tHDDODC Hold time that DOUT is valid after falling edge of DCLK tPDDCDO (1) DESCRIPTION tPDCDV (1) Propagation delay from falling edge of DCLK to valid DOUT 400 ns 4 ns 25 ns With a maximum load of one DDC264 (4pF typical) with an additional load of 5pF. Copyright (c) 2006-2011, Texas Instruments Incorporated DDC264 SBAS368C - MAY 2006 - REVISED JULY 2011 www.ti.com Cascading Multiple Converters Figure 29 shows the timing diagram when the DIN input is used to daisy-chain several devices. Table 6 gives the timing specification for data retrieval using DIN. Multiple DDC264 devices can be connected in a serial configuration; see Figure 28. DOUT can be used with DIN to daisy-chain multiple DDC264 devices together to minimize wiring. In this mode of operation, the serial data output is shifted through multiple DDC264s; see Figure 28. DCLK DVALID IN3 IN2 IN1 3 2 1 IN61 IN4 61 DIN 4 IN63 IN62 62 IN64 IN1 65 64 IN2 66 DDC264 DOUT 63 IN3 DIN 67 IN61 IN4 125 68 IN63 IN64 128 IN62 IN1 129 126 IN2 130 127 IN3 131 DCLK DVALID DCLK DVALID IN61 DDC264 DOUT IN4 189 IN1 193 DIN 132 IN2 194 IN63 IN3 195 IN62 IN4 190 IN61 196 IN64 IN62 253 192 IN63 254 DDC264 DOUT 191 IN64 DIN 255 Sensor DDC264 DOUT 256 Data Retrieval Output DCLK DVALID Data Clock Figure 28. Daisy-Chained DDC264s DVALID DCLK tSTDIDC tHDDIDC DIN DOUT Input 256 MSB Input 256 LSB Input 255 MSB Input 3 LSB Input 2 MSB Input 2 LSB Input 1 MSB Input 1 LSB Input 256 MSB Figure 29. Timing Diagram When Using DDC264 DIN Function; See Figure 28 Table 6. Timing for DDC264 Data Retrieval Using DIN SYMBOL DESCRIPTION MIN TYP MAX UNITS tSTDIDC Set-up time from DIN to falling edge of DCLK 10 ns tHDDIDC Hold time for DIN after falling edge of DCLK 10 ns Copyright (c) 2006-2011, Texas Instruments Incorporated 17 DDC264 SBAS368C - MAY 2006 - REVISED JULY 2011 www.ti.com Retrieval Before CONV Toggles Data retrieval should occur before CONV toggles. Data retrieval begins soon after DVALID goes low and finishes before CONV toggles, as shown in Figure 30. For best performance, data retrieval must stop tSDCV before CONV toggles. This method is most appropriate for longer integration times. The maximum time available for readback is (tINT - tCMDR - tSDCV). The maximum number of DDC264s that can be daisy-chained together (Format = 1) is calculated by Equation 1: tINT - (tDR + tSDCV) (20 64)tDCLK (or 14 DDC264s for Format = 0) (1) tINT CONV DVALID NOTE: (16 x 64)DCLK is used for Format = 0, where DCLK is the period of the data clock. For example, if tINT = 1000s and DCLK = 20MHz, the maximum number of DDC264s with Format = 1 is shown in Equation 2: 1000ms - 278.4ms = 11.5 (R) 11 DDC264s (1280)(50ns) (2) tINT tDR tSDCV DCLK 1/4 1/4 DOUT 1/4 1/4 Side B Data Side A Data Figure 30. Readback Before CONV Toggles Table 7. Timing for Readback SYMBOL tSDCV 18 DESCRIPTION Data retrieval shutdown before or after edge of CONV MIN 2 TYP MAX UNITS s Copyright (c) 2006-2011, Texas Instruments Incorporated DDC264 SBAS368C - MAY 2006 - REVISED JULY 2011 www.ti.com Retrieval After CONV Toggles Retrieval Before and After CONV Toggles For shorter integration times, more time is available if data retrieval begins after CONV toggles and ends before the new data are ready. Data retrieval must wait tSDCV after CONV toggles before beginning. See Figure 31 for an example of this timing sequence. The maximum time available for retrieval is tDR - (tSDCV + tHDDODV), regardless of tINT. The maximum number of DDC264s that can be daisy-chained together with Format = 1 is calculated by Equation 3: 274ms For the absolute maximum time for data retrieval, data can be retrieved before and after CONV toggles. Nearly all of tINT is available for data retrieval. Figure 32 illustrates how this process is done by combining the two previous methods. Pause the retrieval during CONV toggling to prevent digital noise, as discussed previously, and finish before the next data are ready. The maximum number of DDC264s that can be daisy-chained together with Format = 1 is: tINT - (tSDCV + tSDCV + tHDDODV) (20 64)tDCLK (3) (20 64)tDCLK NOTE: (16 x 64)DCLK is for Format = 0. NOTE: (16 x 64)DCLK is used for Format = 0. For DCLK = 20MHz, the maximum number of DDC264s is four (or five for Format = 0). For tINT = 400s and DCLK = 20MHz, the maximum number of DDC264s is six (or seven for Format = 0). tINT CONV (4) tINT tINT DVALID tDR tSDCV tHDDODV DCLK 1/4 1/4 1/4 DOUT 1/4 1/4 1/4 Side A Data Side B Data Side A Data Figure 31. Readback After CONV Toggles tINT CONV tINT DVALID tINT tSDCV tHDDODV tSDCV DCLK 1/4 1/4 1/4 1/4 1/4 1/4 DOUT 1/4 1/4 1/4 1/4 1/4 1/4 Side B Data Side A Data Figure 32. Readback Before and After CONV Toggles Copyright (c) 2006-2011, Texas Instruments Incorporated 19 DDC264 SBAS368C - MAY 2006 - REVISED JULY 2011 www.ti.com CONFIGURATION REGISTER Read and Write Operations NOTE: With Format = 1, the check pattern is 300 bits, with only the last 72 bits non-zero. This sequence of outputs is repeated twice for each DDC264 and daisy-chaining is supported in configuration readback. Table 8 shows the check pattern configuration during readback. Table 9 shows the timing for the Configuration Register read and write operations. Strobe CONV to begin normal operation. The Configuration Register must be programmed after power-up or a device reset. The DIN_CFG, CLK_CFG, and RESET pins are used to write to this register. When beginning a write operation, hold CONV low and strobe RESET; see Figure 33. Then begin shifting in the configuration data on DIN_CFG. Data are written to the Configuration Register most significant bit first. The data are internally latched on the falling edge of CLK_CFG. Partial writes to the Configuration Register are not allowed--make sure to send all 16 bits when updating the register. Table 8. Check Pattern During Readback Check Pattern (Hex) Total Readback Bits 0 180 0s, 30F066012480F6h 1024 1 228 0s, 30F066012480F69055h 1280 Format Bit Optional readback of the Configuration Register is available immediately after the write sequence. During readback, 320 '0's, then the 16-bit configuration data followed by a 4-bit revision ID and the check pattern are shifted out on the DOUT pin on the rising edge of DCLK. The check pattern can be used to check or verify the DOUT functionality. tRST RESET Configuration Register Operations tWTRST (1) Normal Operation tWTWR CLK_CFG tSTCF DIN_CFG tHDCF MSB LSB Read Configuration Register and Check Pattern Write Configuration Register Data 1 320 (2) DCLK DOUT MSB 320 0s (2) LSB Configuration Register Data Check Pattern CONV (1) CLK must be running during Configuration Register write and read operations. (2) In 16-bit mode (FORMAT = 0), only 256 0s are read before the Configuration Register write and read operations. Figure 33. Configuration Register Write and Read Operations Table 9. Timing for the Configuration Register Read/Write 20 SYMBOL DESCRIPTION MIN tWTRST Wait Required from Reset High to First Rising Edge of CLK_CFG 2 TYP MAX UNITS s tWTWR Wait Required from Last CLK_CFG of Write Operation to First DCLK of Read Operation 2 s ns tSTCF Set-Up Time from DIN_CFG to Falling Edge of CLK_CFG 10 tHDCF Hold Time for DIN_CFG After Falling Edge of CLK_CFG 10 ns tRST Pulse Width for RESET Active 1 s Copyright (c) 2006-2011, Texas Instruments Incorporated DDC264 SBAS368C - MAY 2006 - REVISED JULY 2011 www.ti.com Configuration Register Bit Assignments Bit 15 0 Bit 7 Version Bit 14 0 Bit 6 0 Bit 13 Clkdiv Bit 5 0 Bit 12 0 Bit 4 Reserved Bits 15:14 These bits must always be set to '0'. Bit 13 Clkdiv Bit 11 0 Bit 3 0 Bit 10 Range[1] Bit 2 0 Bit 9 Range[0] Bit 1 0 Bit 8 Format Bit 0 Test The Clkdiv input enables an internal divider on the system clock as shown in Table 10. When Clkdiv = 1, the system clock is divided by 4. This configuration allows a system clock that is faster by a factor of four, which in turn provides a finer quantization of the integration time, because the CONV signal must be synchronized with the system clock for the best performance. 0 = Internal clock divider set to 1 1 = Internal clock divider set to 4 Table 10. Clkdiv Operation Clkdiv Bit CLK Divider Value CLK Frequency Internal Clock Frequency 0 1 5MHz 5MHz 1 4 20MHz 5MHz Bits 12:11 These bits must always be set to '0'. Bits 10:9 Range[1:0] These bits set the full-scale range. 00 = Range 0 = 12.5pC 01 = Range 1 = 50.0pC Bit 8 10 = Range 2 = 100.0pC 11 = Range 3 = 150.0pC Format Format selects how many bits are used in the data output word. 0 = 16-bit output 1 = 20-bit output Bit 7 Version This bit must be set to match the device being used. Must be set to '0' for DDC264C. Must be set to '1' for DDC264CK. Bits 6:5 These bits must always be set to '0'. Bit 4 Reserved This bit is reserved and must be set to '0'. Bits 3:1 These bits must always be set to '0'. Bit 0 Test When Test Mode is used, the inputs (IN1 through IN64) are disconnected from the DDC264 integrators to enable the user to measure a zero input signal regardless of the current supplied to the inputs. 0 = TEST mode off 1 = TEST mode on Copyright (c) 2006-2011, Texas Instruments Incorporated 21 DDC264 SBAS368C - MAY 2006 - REVISED JULY 2011 www.ti.com LAYOUT POWER-UP SEQUENCING Power Supplies and Grounding Before device power-up, all digital and analog inputs must be low. At the time of power-up, all of these signals should remain low until the power supplies have stabilized, as shown in Figure 35. The analog supply must come up before or at the same time as the digital supply. At this time, begin supplying the master clock signal to the CLK pin. Wait for time tPOR, then give a RESET pulse. After releasing RESET, the Configuration Register must be written to. Table 11 shows the timing for the power-up sequence. Both AVDD and DVDD should be as quiet as possible. It is particularly important to eliminate noise from AVDD that is non-synchronous with the DDC264 operation. Figure 34 illustrates how to supply power to the DDC264. Each DDC264 has internal bypass capacitors on AVDD and DVDD; therefore, the only external bypass capacitors typically needed are 10F ceramic capacitors, one per PCB. It is recommended that both the analog and digital grounds (AGND and DGND) be connected to a single ground plane on the PCB. tPOR Power Supplies Analog Supply tRST 0.3mF AVDD AGND RESET 10mF DDC264 Digital Supply CLK 0.1mF DVDD DGND Write to the Configuration Register Configuration Serial Interface 10mF Figure 35. DDC264 Timing Diagram at Power-Up Figure 34. Power-Supply Connections Shielding Analog Signal Paths As with any precision circuit, careful PCB layout ensures the best performance. It is essential to make short, direct interconnections and avoid stray wiring capacitance--particularly at the analog input pins and QGND. The analog input pins are high-impedance and extremely sensitive to extraneous noise. The QGND pin should be treated as a sensitive analog signal and connected directly to the supply ground with proper shielding. Leakage currents between the PCB traces can exceed the input bias current of the DDC264 if shielding is not implemented. Digital signals should be kept as far as possible from the analog input signals on the PCB. 22 Table 11. Timing for DDC264 Power-Up Sequence SYMBOL tPOR DESCRIPTION Wait after power-up until reset MIN 250 TYP MAX UNITS ms Copyright (c) 2006-2011, Texas Instruments Incorporated DDC264 SBAS368C - MAY 2006 - REVISED JULY 2011 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (January, 2011) to Revision C * Updated Table 1; revised values for Range 0 performance in fC and Electrons ................................................................. 9 Changes from Revision A (January, 2011) to Revision B * Page Page Changed second paragraph of Basic Integration Cycle section to correct CONV timing description error ....................... 11 Copyright (c) 2006-2011, Texas Instruments Incorporated 23 PACKAGE OPTION ADDENDUM www.ti.com 1-Jul-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) DDC264CKZAW ACTIVE NFBGA ZAW 100 168 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR DDC264CKZAWR ACTIVE NFBGA ZAW 100 1000 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR DDC264CZAW ACTIVE NFBGA ZAW 100 168 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR DDC264CZAWR ACTIVE NFBGA ZAW 100 1000 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. 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