DDC264
Serial
Interface
DVALID
DCLK
DOUT
DIN
Configuration
and
Control
IN2
IN1
DGNDAGND
IN4
IN3
IN62
IN61
DS
ADC
IN64
IN63
CLK
CONV
DIN_CFG
CLK_CFG
RESET
Dual
Switched
Integrator
Dual
Switched
Integrator
Dual
Switched
Integrator
Dual
Switched
Integrator
Dual
Switched
Integrator
Dual
Switched
Integrator
Dual
Switched
Integrator
Dual
Switched
Integrator
VREF DVDDAVDD
0.2 Fm
0.1 Fm
0.3 Fm
DS
ADC
DS
ADC
DS
ADC
DDC264
www.ti.com
SBAS368C –MAY 2006–REVISED JULY 2011
64-Channel, Current-Input
Analog-to-Digital Converter
Check for Samples: DDC264
The DDC264 has a serial interface designed for
1FEATURES daisy-chaining in multi-device systems. Simply
2•Single-Chip Solution to Directly Measure 64 connect the output of one device to the input of the
Low-Level Currents next to create the chain. Common clocking feeds all
•Proven High-Precision, True Integrating the devices in the chain so that the digital overhead
Architecture with 100% Charge Collection in a multi-DDC264 system is minimal.
•Easy Upgrade for Existing DDC Family The DDC264 uses a +5V analog supply and a +2.7V
Applications to +3.6V digital supply. Bypass capacitors within the
•Very Low Power: 3mW/channel DDC264 package help minimize the external
•Extremely Linear: component requirements. Operating over the
INL = ±0.025% of Reading ±1.0ppm of FSR temperature range of 0°C to +70°C, the DDC264
BGA-100 package is offered in two versions: the
•Low Noise: 6.3ppm of FSR DDC264C for low-power applications, and the
•Adjustable Full-Scale Range DDC264CK when higher speeds are required.
•Adjustable Speed
–Data Rates up to 6kSPS with 20-bit
Performance
–Integration Times as low as 160μs
•Daisy-Chainable Serial Interface
•In-Package Bypass Capacitors Simplify PCB
Design
APPLICATIONS
•CT Scanner DAS
•Photodiode Sensors
•X-Ray Detection Systems
DESCRIPTION
The DDC264 is a 20-bit, 64-channel, current-input
analog-to-digital (A/D) converter. It combines both
current-to-voltage and A/D conversion so that 64
separate low-level current output devices, such as
photodiodes, can be directly connected to its inputs
and digitized.
For each of the 64 inputs, the DDC264 uses the
proven dual switched integrator front-end. This
configuration allows for continuous current
integration: while one integrator is being digitized by
the onboard A/D converter, the other is integrating
the input current. This architecture provides both a
very stable offset and a loss-less collection of the
input current. Adjustable integration times range from
160μs to 1s, allowing currents from fAs to μAs to be
continuously measured with outstanding precision. Protected by US Patent #5841310
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright ©2006–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DDC264
SBAS368C –MAY 2006–REVISED JULY 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DDC FAMILY OVERVIEW
MAXIMUM PACKAGE-
PRODUCT NO. OF CHANNELS FULL-SCALE DATA RATE POWER/CHANNEL LEAD
DDC112 2 1000pC 20kSPS 40mW SO-28
DDC112K 2 1000pC 3.3kSPS 40mW TQFP-32
DDC114 4 350pC 3.3kSPS 13mW QFN-48
DDC118 8 350pC 3.3kSPS 13mW QFN-48
DDC316 16 12pC 100kSPS 28mW BGA-64
DDC232C 32 350pC 3.1kSPS 7mW BGA-64
DDC232CK 32 350pC 6.2kSPS 10mW BGA-64
DDC264C 64 150pC 3.1kSPS 3mW BGA-100
DDC264CK 64 150pC 6.2kSPS 5.5mW BGA-100
ORDERING INFORMATION
For the most current package and ordering information see the Package Option Addendum at the end of this
document, or visit the device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
AVDD to AGND –0.3V to +6V
DVDD to DGND –0.3V to +3.6V
AGND to DGND ±0.2V
VREF Input to AGND 2.0V to AVDD + 0.3V
Analog Input to AGND –0.3V to +0.7V
Digital Input Voltage to DGND –0.3V to DVDD + 0.3V
Digital Output Voltage to DGND –0.3V to DVDD + 0.3V
Operating Temperature 0°C to +70°C
Storage Temperature –60°C to +150°C
Junction Temperature (TJ) +150°C
Human Body Model (HBM) 4kV
JEDEC standard 22, test method A114-C.01, all pins
ESD
Ratings: Charged Device Model (CDM) 1kV
JEDEC standard 22, test method A114-C.01, all pins
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
2Copyright ©2006–2011, Texas Instruments Incorporated
DDC264
www.ti.com
SBAS368C –MAY 2006–REVISED JULY 2011
ELECTRICAL CHARACTERISTICS
At TA= +25°C, AVDD = +5V, DVDD = +3.0V, VREF = +4.096V, tINT = 333μs for DDC264C or 166μs for DDC264CK,
and Range = 3 (150pC), unless otherwise noted. DDC264C DDC264CK
PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT
ANALOG INPUT RANGE
Range 0 10.5 12.5 14.5 10.5 12.5 14.5 pC
Range 1 47.5 50 52.5 47.5 50 52.5 pC
Range 2 95 100 105 95 100 105 pC
Range 3 142.5 150 157.5 142.5 150 157.5 pC
Negative Full-Scale Range –0.4% of Positive Full-Scale Range –0.4% of Positive Full-Scale Range pC
DYNAMIC CHARACTERISTICS
Data Rate 3 3.125 6 6.25 kSPS
Integration Time, tINT 320 333 1,000,000 160 166 1,000,000 μs
System Clock (CLK) Clkdiv = 0 1 5 1 10 MHz
Clkdiv = 1 4 20 4 40 MHz
Data Clock (DCLK) 32 32 MHz
Configuration Clock (CLK_CFG) 20 20 MHz
ACCURACY
Noise, Low-Level Input(1) Range = 3, CSENSOR(2) = 35pF 6.3 6.3 ppm of FSR(3), rms
Integral Linearity Error(4) ±0.025% Reading ±1.0ppm FSR, typ ±0.025% Reading ±1.0ppm FSR, typ
±0.05% Reading ±1.5ppm FSR, max ±0.05% Reading ±1.5ppm FSR, max
Resolution No Missing Codes, Format = 1 20 20 Bits
No Missing Codes, Format = 0 16 16 Bits
Input Bias Current TA= +25°C to +45°C±0.5 ±5±0.5 ±5 pA
Range Error Match(5) 0.1 0.5 0.1 0.5 % of FSR
Range Sensitivity to VREF VREF = 4.096 ±0.1V 1:1 1:1
Offset Error ±500 ±1000 ±500 ±1000 ppm of FSR
Offset Error Match(5) ±150 ±150 ppm of FSR
DC Bias Voltage(6) Low-Level Input (<1% FSR) ±0.1 ±1±0.1 ±1 mV
Power-Supply Rejection Ratio At dc 100 ±300 100 ±300 ppm of FSR/V
(1) Input is less than 1% of full-scale.
(2) CSENSOR is the capacitance seen at the DDC264 inputs from wiring, photodiode, etc.
(3) FSR is full-scale range.
(4) A best-fit line is used in measuring nonlinearity.
(5) Matching between side A and side B of the same input.
(6) Voltage produced by the DDC264 at its input that is applied to the sensor.
Copyright ©2006–2011, Texas Instruments Incorporated 3
DDC264
SBAS368C –MAY 2006–REVISED JULY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
At TA= +25°C, AVDD = +5V, DVDD = +3.0V, VREF = +4.096V, tINT = 333μs for DDC264C or 166μs for DDC264CK,
and Range = 3 (150pC), unless otherwise noted. DDC264C DDC264CK
PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT
PERFORMANCE OVER TEMPERATURE
Offset Drift ±0.5 5(7) ±0.5 5(7) ppm of FSR/°C
Offset Drift Stability ±0.2 2(7) ±0.2 2(7) ppm of FSR/minute
DC Bias Voltage Drift(8) ±3±3μV/°C
Input Bias Current Drift TA= +25°C to +45°C 0.01 1(7) 0.01 1(7) pA/°C
Range Drift(9) 25 50 25 50 ppm/°C
Range Drift Match(10) ±5±5 ppm/°C
REFERENCE
Voltage 4.000 4.096 4.200 4.000 4.096 4.200 V
Input Current(11) Average Value with tINT = 333μs 825 μA
Average Value with tINT = 166μs 1650 μA
DIGITAL INPUT/OUTPUT
Logic Levels
VIH 0.8 DVDD DVDD + 0.1 0.8 DVDD DVDD + 0.1 V
VIL –0.1 0.2 DVDD –0.1 0.2 DVDD V
VOH IOH =–500μA DVDD –0.4 DVDD –0.4 V
VOL IOL = 500μA 0.4 0.4 V
Input Current (IIN) 0 <VIN <DVDD ±10 ±10 μA
Data Format(12) Straight Binary Straight Binary
POWER-SUPPLY REQUIREMENTS
Analog Power-Supply Voltage (AVDD) 4.75 5.0 5.25 4.9 5.0 5.1 V
Digital Power-Supply Voltage (DVDD) 2.7 3.3 3.6 2.7 3.3 3.6 V
Supply Current
Analog Current 34 60 mA
Digital Current 7.5 15 mA
Total Power Dissipation 192 256 350 mW
Per Channel Power Dissipation 3 4 5.5 mW/Channel
(7) Ensured by design; not production tested.
(8) Voltage produced by the DDC264 at its input that is applied to the sensor.
(9) Range drift does not include external reference drift.
(10) Matching between side A and side B of the same input.
(11) Input reference current decreases with increasing tINT (see the Voltage Reference section).
(12) Data format is Straight Binary with a small offset. The number of bits in the output word is controlled by the Format bit.
THERMAL INFORMATION DDC264C,
DDC264CK
THERMAL METRIC(1) UNITS
ZAW Package
100 Balls
θJA Junction-to-ambient thermal resistance 25.7
θJCtop Junction-to-case (top) thermal resistance 9.8
θJB Junction-to-board thermal resistance 7.1 °C/W
ψJT Junction-to-top characterization parameter 0.1
ψJB Junction-to-board characterization parameter 7.0
θJCbot Junction-to-case (bottom) thermal resistance N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4Copyright ©2006–2011, Texas Instruments Incorporated
Columns
F D BGH E C A
IN48 IN20 IN25IN12IN41 IN19 IN23 IN26
2
IN15 IN53 IN60IN44IN9 IN50 IN56 IN59
3
IN47 IN21 IN27IN11IN42 IN18 IN28 IN32
4
IN14 IN54 IN62IN43IN10 IN52 IN61 IN63
5
IN46 IN22 IN30IN13IN36 IN17 IN29 IN31
6
AGND VREF AGNDAVDDAGND VREF AGND AGND
8
IN16 IN51 IN57IN45IN8 IN49 IN55 IN58
1
Rows
AGND AGND IN24QGNDQGND
JK
IN7
IN38
IN6IN37
IN5IN3
IN35IN34
IN4IN33
AGNDAGND
IN40IN39
IN2IN1 AGND AGND IN64
7
CLK DVDD DINDVALIDDGND DVDD DCLK DOUT
10
AVDD DGND DIN_CFG
AVDDAVDD
DGNDCONV
AVDDAVDD DGND RST CLK_CFG
9
DDC264
www.ti.com
SBAS368C –MAY 2006–REVISED JULY 2011
PIN CONFIGURATION
ZAW PACKAGE
9mm ×9mm BGA
(TOP VIEW)
PIN DESCRIPTIONS
PIN LOCATION FUNCTION DESCRIPTION
IN1-IN64 Rows 1-6, A7, B7, J7, K7 Analog input Analog inputs for channels 1 to 64
QGND G7, H7 Analog Quiet analog ground; see the guidelines described in the Layout section
A8, B8, C7, C8, D7, E7, F7, F8, H8, J8.
AGND Analog Analog ground
K8
DGND D9, E9, H10, J10 Digital Digital ground
AVDD F9, G8, G9, H9, J9, K9 Analog Analog power supply, +5V nominal
VREF D8, E8 Analog input External voltage reference input, +4.096V nominal
DVALID G10 Digital output Data valid output, active low
DIN_CFG B9 Digital input Configuration register data input
CLK_CFG A9 Digital input Configuration register clock input
RESET C9 Digital input Digital reset, active low
DVDD D10, E10 Digital Digital power supply, +3.3V nominal
CONV K10 Digital input Conversion control input: 0 = integrate on side B; 1 = integrate on side A
DIN B10 Digital input Serial data input
DOUT A10 Digital output Serial data output
CLK F10 Digital input Master clock input
DCLK C10 Digital input Serial data clock input
Copyright ©2006–2011, Texas Instruments Incorporated 5
70
60
50
40
30
20
10
0
10
20
30
-
-
-
Integral Nonlinearity (ppm of Full-Scale)
0100k 200k 300k 400k 500k 600k 700k 800k 900k 1M
Input (ppm of Full-Scale)
Range 0
DDC264C, 3kSPS
Range 3
Range 2
Range 1
125
100
75
50
25
0
25
50
75
100
125
-
-
-
-
-
Integral Nonlinearity (ppm of Full-Scale)
0100k 200k 300k 400k 500k 600k 700k 800k 900k 1M
Input (ppm of Full-Scale)
Range 0
DDC264CK, 6kSPS
Range 3
Range 2
Range 1
50
40
30
20
10
0
10
20
30
40
50
-
-
-
-
-
Integral Nonlinearity (ppm of Full-Scale)
0100k 200k 300k 400k 500k 600k 700k 800k 900k 1M
Input (ppm of Full-Scale)
DDC264C, 3kSPS
Range 3, +25 C°
Average
125
100
75
50
25
0
25
50
75
100
125
-
-
-
-
-
Integral Nonlinearity (ppm of Full-Scale)
0100k 200k 300k 400k 500k 600k 700k 800k 900k 1M
Input (ppm of Full-Scale)
DDC264CK, 6kSPS
Range 3, +25 C°
Average
50
40
30
20
10
0
10
20
30
40
50
-
-
-
-
-
Integral Nonlinearity (ppm of Full-Scale)
0100k 200k 300k 400k 500k 600k 700k 800k 900k 1M
Input (ppm of Full-Scale)
DDC264C, 3kSPS
Range 3
+45 C°
+25 C°
-5 C°
+60 C°
+75 C°
125
100
75
50
25
0
25
50
75
100
125
-
-
-
-
-
Integral Nonlinearity (ppm of Full-Scale)
0100k 200k 300k 400k 500k 600k 700k 800k 900k 1M
Input (ppm of Full-Scale)
+45 C°
+25 C° -5 C°
+75 C°
+60 C°
DDC264CK, 6kSPS
Range 3
DDC264
SBAS368C –MAY 2006–REVISED JULY 2011
www.ti.com
TYPICAL CHARACTERISTICS
At TA= +25°C, unless otherwise indicated.
INTEGRAL NONLINEARITY INTEGRAL NONLINEARITY
Figure 1. Figure 2.
INTEGRAL NONLINEARITY INTEGRAL NONLINEARITY
ENVELOPE OF ALL 64 CHANNELS ENVELOPE OF ALL 64 CHANNELS
Figure 3. Figure 4.
INTEGRAL NONLINEARITY vs TEMPERATURE INTEGRAL NONLINEARITY vs TEMPERATURE
Figure 5. Figure 6.
6Copyright ©2006–2011, Texas Instruments Incorporated
10
9
8
7
6
5
4
3
2
1
0
Noise (ppm of Full-Scale, RMS)
Integration Time (ms)
0.1 1001 10
DDC264C, 3kSPS
DDC264CK, 6kSPS
C = 35pF
Range 3
SENSOR
12
10
8
6
4
2
0
Noise (ppm of Full-Scale, RMS)
Percentage of Input (%)
DDC264C, 3kSPS
DDC264CK, 6kSPS
C = 35pF
SENSOR
0 20 40 60 80 100
Range 1
Range 2
Range 3
40
35
30
25
20
15
10
5
0
Noise (ppm of Full-Scale, RMS)
0 10 20 30 40 50 60 70
Temperature ( C)°
C = 35pF
SENSOR
Range 0
Range 3
Range 2
Range 1
10
1
0.1
0.01
Bias Current (pA)
0 10 20 30 40 50 60 70
Temperature ( C)°
DDC264C, 3kSPS
DDC264CK, 6kSPS
Ranges 1, 2, 3
250
200
150
100
50
0
50
100
150
200
250
-
-
-
-
-
Offset Drift (ppm of FSR)
25 30 35 40 45 50 55 60 65 70
Temperature ( C)°
DDC264C, 3kSPS
DC264CK, 6kSPS
Ranges 1, 2, 3
DDC264
www.ti.com
SBAS368C –MAY 2006–REVISED JULY 2011
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, unless otherwise indicated.
NOISE vs INTEGRATION TIME NOISE vs INPUT LEVEL
Figure 7. Figure 8.
NOISE vs TEMPERATURE INPUT BIAS CURRENT vs TEMPERATURE
Figure 9. Figure 10.
OFFSET DRIFT vs TEMPERATURE OFFSET DRIFT STABILITY OVER TIME HISTOGRAM
Figure 11. Figure 12.
Copyright ©2006–2011, Texas Instruments Incorporated 7
70
65
60
55
50
45
40
35
30
Current (mA)
0 10 20 30 40 50 60 70
Temperature ( C)°
DDC264CK
6kSPS
DDC264C
3kSPS
20
15
10
5
0
Current (mA)
0 10 20 30 40 50 60 70
Temperature ( C)°
DDC264CK
6kSPS
DDC264C
3kSPS
2.5
2
1.5
1
0.5
0
DC Bias Voltage (mV)
0 10 20 30 40 50 60 70 80 90 100
Percentage of Input (%)
Range 0
Range 3
Range 2
Range 1
DDC264C
3kSPS
3.5
3
2.5
2
1.5
1
0.5
0
DC Bias Voltage (mV)
0 10 20 30 40 50 60 70 80 90 100
Percentage of Input (%)
Range 0
Range 3
Range 2
Range 1
DDC264CK
6kSPS
DDC264
SBAS368C –MAY 2006–REVISED JULY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, unless otherwise indicated.
ANALOG SUPPLY CURRENT DIGITAL SUPPLY CURRENT
vs TEMPERATURE vs TEMPERATURE
Figure 13. Figure 14.
DC BIAS VOLTAGE vs INPUT PERCENTAGE DC BIAS VOLTAGE vs INPUT PERCENTAGE
Figure 15. Figure 16.
8Copyright ©2006–2011, Texas Instruments Incorporated
600
550
500
450
400
350
300
250
200
150
100
50
0
Noise (ppm of FSR, rms)
0 100 200 300 400 500 600 700 800 900 1000
C (pF)
SENSOR
Range 0
Range 1
Range 2
Range 3
DDC264C, 3kSPS
DDC264CK, 6kSPS
DDC264
www.ti.com
SBAS368C –MAY 2006–REVISED JULY 2011
Figure 17. NOISE vs CSENSOR
Figure 18.
Table 1. NOISE vs CSENSOR(1)
CSENSOR
RANGE 0pF 10pF 30pF 43pF 57pF 100pF 270pF 470pF 1000pF
ppm of FSR, rms
Range 0: 12.5pC 16 20 30 37 44 71 160 270 510
Range 1: 50pC 6.4 7.4 10 12 14 21 45 74 130
Range 2: 100pC 5.1 5.5 7.1 8 9.1 12 25 39 71
Range 3: 150pC 4.8 5 6 6.5 7.2 9.6 17 27 49
fC, rms
Range 0: 12.5pC 0.20 0.25 0.38 0.46 0.55 0.89 2.0 3.38 6.38
Range 1: 50pC 0.32 0.37 0.53 0.62 0.73 1.09 2.29 3.73 6.88
Range 2: 100pC 0.51 0.55 0.71 0.80 0.91 1.28 2.50 3.97 7.16
Range 3: 150pC 0.72 0.75 0.90 0.98 1.08 1.45 2.67 4.14 7.36
Electrons, rms
Range 0: 12.5pC 1250 1560 2340 2890 3430 5540 12480 21070 39790
Range 1: 50pC 2010 2310 3340 3910 4570 6800 14200 23300 42900
Range 2: 100pC 3220 3440 4450 5000 5680 7990 15600 24800 44700
Range 3: 150pC 4530 4730 5610 6120 6770 9050 16700 25800 45900
(1) Noise in Table 1 is expressed in three different units for reader convenience. The first section lists noise in units of parts per million of
full-scale range; the second section shows noise as an equivalent input charge (in fC); and the third section converts noise to electrons.
Copyright ©2006–2011, Texas Instruments Incorporated 9
To ADC
IN1
Input
Current
Side A Integrator
Photodiode
Side B Integrator
QGND
QGND
DDC264
SBAS368C –MAY 2006–REVISED JULY 2011
www.ti.com
THEORY OF OPERATION
General Description For example, while side A integrates the input signal,
A dual switched integrator input channel for the the side B outputs are digitized by the onboard ADC.
DDC264 is shown in Figure 19. The DDC264 This integration and A/D conversion process is
contains 64 identical input channels that perform the controlled by the convert pin, CONV. The results from
function of current-to-voltage integration followed by a side A and side B of each signal input are stored in a
multiplexed A/D conversion. Each input has two serial output shift register. The DVALID output goes
integrators so that the current-to-voltage integration low when the shift register data are ready to be
can be continuous in time. The DDC264 continuously retrieved.
integrates the input signal by switching integrations
between side A and side B.
Figure 19. Dual Switched Integrator Architecture
10 Copyright ©2006–2011, Texas Instruments Incorporated
12.5pF
25pF
VREF
Range[0] Bit
Range[1] Bit
SRESET
SREF2 SADC1A
SINTA
SREF1
IN1
ESD
Protection
Diodes
Input
Current
Integrator A
Integrator B
Photodiode
3pF
To Converter
SINTB QGND
Range Selection Capacitors (C )
F
DDC264
www.ti.com
SBAS368C –MAY 2006–REVISED JULY 2011
Basic Integration Cycle At the completion of an A/D conversion, the charge
on the integration capacitor (CF) is reset with SREF1
The topology of the front end of the DDC264 is an and SRESET (see Figure 21 and Figure 22a). This
analog integrator as shown in Figure 20. In this process is done during reset. In this manner, the
diagram, only input IN1 is shown. The input stage selected capacitor is charged to the reference
consists of an operational amplifier, a selectable voltage, VREF. Once the integration capacitor is
feedback capacitor network (CF), and several charged, SREF1 and SRESET are switched so that
switches that implement the integration cycle. The VREF is no longer connected to the amplifier circuit
timing relationships of all of the switches shown in while it waits to begin integrating (see Figure 22b).
Figure 20 are illustrated in Figure 21.Figure 21 With the rising edge of CONV, SINTA closes, which
conceptualizes the operation of the integrator input begins the integration of side A. This process puts the
stage of the DDC264 and should not be used as an integrator stage into its integrate mode (see
exact timing tool for design. Figure 22c).
See Figure 22 for the block diagrams of the reset, Charge from the input signal is collected on the
integrate, wait, and convert states of the integrator integration capacitor, causing the voltage output of
section of the DDC264. This internal switching the amplifier to decrease. The falling edge of CONV
network is controlled externally with the convert pin stops the integration by switching the input signal
(CONV) and the system clock (CLK). For the best from side A to side B (SINTA and SINTB). Prior to the
noise performance, CONV must be synchronized with falling edge of CONV, the signal on side B was
the falling edge of CLK. It is recommended that converted by the A/D converter and reset during the
CONV toggle within ±10ns of the falling edge of CLK. time that side A was integrating. With the falling edge
of CONV, side B starts integrating the input signal. At
The noninverting inputs of the integrators are this point, the output voltage of the side A operational
connected to the QGND pin. Consequently, the amplifier is presented to the input of the A/D
DDC264 analog ground, QGND, should be as clean converter (see Figure 22d).
as possible. In Figure 20, the feedback capacitors
(CF) are shown in parallel between the inverting input A special elecrostatic discharge (ESD) structure
and output of the operational amplifier. At the protects the inputs but does not increase current
beginning of a conversion, the switches SA/D, SINTA,leakage on the input pins.
SINTB, SREF1, SREF2, and SRESET are set (see
Figure 21).
Figure 20. Basic Integration Configuration
Copyright ©2006–2011, Texas Instruments Incorporated 11
CONV
CLK
SINTA
SINTB
SREF1
SREF2
SRESET
SA/D1A
Configuration of
Integrator A
VREF
Integrator A
Voltage Output
Convert Convert
Wait Wait
Integrate
Reset
Reset
Wait
Wait
To Converter
SRESET
SREF2
SA/D
VREF
SREF1
SINT
IN
CF
To Converter
SRESET
SREF2
SA/D
VREF
SREF1
SINT
IN
CF
To Converter
SRESET
SREF2
SA/D
VREF
SREF1
SINT
IN
CF
To Converter
SRESET
SREF2
SA/D
VREF
SREF1
SINT
IN
CF
a) Reset/Auto Zero Configuration
c) Integrate Configuration
d) Convert Configuration
b) Wait Configuration
DDC264
SBAS368C –MAY 2006–REVISED JULY 2011
www.ti.com
Figure 21. Integration Timing (see Figure 20)
Figure 22. Four Configurations of the Front-End Integrators
12 Copyright ©2006–2011, Texas Instruments Incorporated
4
3
2
3
1
2
7
6
+
OPA350 To VREF Pin on
the DDC264
+5V
+5V
0.10 Fm
0.10 Fm
0.47 Fm
REF3040
1kW
0.7W
47 Fm
100mF(1)
0.7W
10 Fm(1)
Near Each DDC
DDC264
www.ti.com
SBAS368C –MAY 2006–REVISED JULY 2011
Integration Capacitors amount of charge needed by the A/D converter is
independent of the integration time; therefore,
There are four different capacitor configurations increasing the integration time lowers the average
available on-chip for both sides of every channel in current. For example, an integration time of 800μs
the DDC264. These internal capacitors are trimmed lowers the average VREF current to 340μA.
in production to achieve the specified performance for
range error of the DDC264. The range control bits It is critical that VREF be stable during the different
(Range[1:0]) set the capacitor value for all integrators. modes of operation (see Figure 22). The A/D
Consequently, all inputs and both sides of each input converter measures the voltage on the integrator with
always have the same full-scale range. Table 2 respect to VREF. Because the integrator capacitors
shows the capacitor value selected for each range are initially reset to VREF, any drop in VREF from the
selection. time the capacitors are reset to the time when the
converter measures the integrator output introduces
Table 2. Range Selection an offset. It is also important that VREF be stable
over longer periods of time because changes in
RANGE CONTROL BITS INPUT
RANGE CFVREF correspond directly to changes in the full-scale
RANGE
Range[1] Range[0] range. Finally, VREF should introduce as little
–0.04 to additional noise as possible.
0 0 0 3pF 12.5pC
–0.2 to For these reasons, it is strongly recommended that
1 0 1 12.5pF 50.0pC the external reference source be buffered with an
–0.4 to operational amplifier, as shown in Figure 23. In this
2 1 0 25pF 100pC circuit, the voltage reference is generated by a
–0.6 to
3 1 1 37.5pF +4.096V reference. A low-pass filter to reduce noise
150pC connects the reference to an operational amplifier
configured as a buffer. This amplifier should have low
Voltage Reference noise and input/output common-mode ranges that
support VREF. Even though the circuit in Figure 23
The external voltage reference is used to reset the might appear to be unstable because of the large
integration capacitors before an integration cycle output capacitors, it works well for the OPA350. It is
begins. It is also used by the A/D converter while the not recommended that series resistance be placed in
converter is measuring the voltage stored on the the output lead to improve stability because this can
integrators after an integration cycle ends. During this cause a drop in VREF, which produces large offsets.
sampling, the external reference must supply the
charge needed by the A/D converter. For an
integration time of 333μs, this charge translates to an
average VREF current of approximately 825μA. The
(1) Ceramic X5R capacitors are recommended.
Figure 23. Recommended External Voltage Reference Circuit for Best Low-Noise Operation
Copyright ©2006–2011, Texas Instruments Incorporated 13
0
−
10
−
20
−
30
−
40
−
50
0.1
tINT
100
1
tINT
10
Frequency
Gain (dB)
tINT tINT
RESET tRST
DDC264
SBAS368C –MAY 2006–REVISED JULY 2011
www.ti.com
System and Data Clocks (CLK and DCLK)
Frequency Response The system clock is supplied to CLK and the data
The frequency response of the DDC264 is set by the clock is supplied to DCLK. It is recommended that the
front-end integrators and is that of a traditional CLK pin be driven by a free-running clock source
continuous time integrator, as shown in Figure 24. By (that is, do not start and stop CLK between
adjusting the integration time, tINT, the user can conversions). Make sure the clock signals are
change the 3dB bandwidth and the location of the clean—avoid overshoot or ringing. For best
notches in the response. The frequency response of performance, generate both clocks from the same
the A/D converter that follows the front-end integrator clock source. Disable DCLK by taking it low after the
is of no consequence because the converter samples data have been shifted out and while CONV is
a held signal from the integrators. That is, the input to transitioning.
the A/D converter is always a dc signal. The output of
the front-end integrators are sampled; therefore, When using multiple DDC264s, pay close attention to
aliasing can occur. Whenever the frequency of the the DCLK distribution on the printed circuit board
input signal exceeds one-half of the sampling rate, (PCB). In particular, make sure to minimize skew in
the signal folds back down to lower frequencies. the DCLK signal because this can lead to timing
violations in the serial interface specifications. See
the Cascading Multiple Converters section for more
details.
Data Valid (DVALID)
The DVALID signal indicates that data are ready.
Data retrieval may begin after DVALID goes low. This
signal is generated using an internal clock divided
down from the system clock, CLK. The phase
relationship between this internal clock and CLK is
set when power is first applied and is random.
Because the user must synchronize CONV with CLK,
the DVALID signal has a random phase relationship
with CONV. This uncertainty is ±1/fCLK. Polling
DVALID eliminates any concern about this
relationship. If the data readback is timed from
CONV, make sure to wait for the required amount of
Figure 24. Frequency Response time.
Reset (RESET)
DIGITAL INTERFACE The DDC264 is reset asynchronously by taking the
The digital interface of the DDC264 sends the digital RESET input low, as shown in Figure 25. Make sure
results via a synchronous serial interface that the release pulse is a minimum of tRST wide. It is very
consists of a data clock (DCLK), a valid data pin important that RESET is glitch-free to avoid
(DVALID), a serial data output pin (DOUT), and a unintentional resets. The Configuration Register must
serial data input pin (DIN). The integration and be programmed immediately afterwards. After
conversion process is fundamentally independent of programming the DDC264, wait at least four
the data retrieval process. Consequently, the CLK conversions before using the data.
and DCLK frequencies need not be the same, though
for best performance, it is highly recommended that
they be derived from the same clocking source to
keep the phase relationship constant. DIN is only
used when multiple converters are cascaded and
should be tied to DGND otherwise. Depending on Figure 25. Reset Timing
tINT, CLK, and DCLK, it is possible to daisy-chain
multiple converters. This option greatly simplifies the
interconnection and routing of the digital outputs in
those applications where a large number of
converters are needed. Configuration of the DDC264
is set by a dedicated register addressed using the
DIN_CFG and CLK_CFG pins.
14 Copyright ©2006–2011, Texas Instruments Incorporated
Integrate AIntegrate B Integrate B Integrate A
CONV
Integration
Status
DVALID
Side B
Data
Side A
Data
Side B
Data
tINT
tDR
DDC264
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SBAS368C –MAY 2006–REVISED JULY 2011
Integration Time
TIMING EXAMPLES The minimum tINT depends on which device is being
Figure 26 shows a few integration cycles beginning used. The minimum time scales directly with the
after the device has been powered up, reset, and the internal clock frequency. For the DDC264C, with an
Configuration Register has been programmed. The internal clock frequency of 5MHz, the minimum time
top signal is CONV and is supplied by the user. The is 320μs. For the DDC264CK, with an internal clock
integration status trace indicates which side is frequency of 10MHz, the minimum time is 166μs. If
integrating. As described in the data sheet, DVALID the minimum integration time is violated, the DDC264
goes active low when data are ready to be retrieved stops continuously integrating the input signal. To
from the DDC264. It stays low until DCLK is taken return to normal operation (that is, continuous
high and then back low by the user. The text below integration) after a violation of the minimum tINT
the DVALID pulse indicates the side of the data specification, perform three integrations that each last
available to be read. The arrow is used to match the for a minimum of 5000 internal clock periods. In other
data to the corresponding integration. Table 3 shows words, integrate three times with each integration
the timing specifications for Figure 26.lasting for at least 1ms when using an internal clock
frequency of 5MHz. During this time, ignore the
DVALID pin. Once the three integrations complete,
normal continuous operation resumes, and data can
be retrieved.
Figure 26. Integration Sequence Timing
Table 3. Timing Specifications for Figure 26
DDC264C DDC264CK
Internal Clock Frequency = 5MHz Internal Clock Frequency = 10MHz
SYMBOL DESCRIPTION MIN TYP MAX MIN TYP MAX UNITS
tINT Integration time 320 1,000,000 160 μs
tDR Time until data ready 276.4 ±0.4 138.2 ±0.2 μs
Copyright ©2006–2011, Texas Instruments Incorporated 15
CLK
DVALID
tPDCDV
tPDDCDV
tHDDODC
tHDDODV
tPDDCDO
DCLK
DOUT Input 64
MSB
Input 64
MSB
Input 64
LSB
Input 63
LSB
Input 5
LSB
Input 4
MSB
Input 2
LSB
Input 1
MSB
Input 1
LSB
DDC264
SBAS368C –MAY 2006–REVISED JULY 2011
www.ti.com
DATA FORMAT Make sure not to retrieve data around changes in
CONV because this change can introduce noise.
The serial output data are provided in an offset binary Stop activity on DCLK at least 2μs before or after a
code as shown in Table 4. The Format bit in the CONV transition.
Configuration Register selects how many bits are
used in the output word. When Format = 1, 20 bits Setting the Format bit = 0 (16-bit output word)
are used. When Format = 0, the lower four bits are reduces the time needed to retrieve data by 20%
truncated so that only 16 bits are used. Note that the because there are fewer bits to shift out. This
LSB size is 16 times bigger when Format = 0. An technique can be useful in multichannel systems
offset is included in the output to allow slightly requiring only 16 bits of resolution.
negative inputs (for example, from board leakages)
from clipping the reading. This offset is approximately Table 4. Ideal Output Code(1) vs Input Signal
0.4% of the positive full-scale. INPUT IDEAL OUTPUT CODE IDEAL OUTPUT CODE
SIGNAL FORMAT = 1 FORMAT = 0
DATA RETRIEVAL ≥100% FS 1111 1111 1111 1111 1111 1111 1111 1111 1111
0.001531% FS 0000 0001 0000 0001 0000 0000 0001 0000 0001
The data from the last conversion are available for 0.001436% FS 0000 0001 0000 0000 1111 0000 0001 0000 0000
retrieval on the falling edge of DVALID (see Figure 27 0.000191% FS 0000 0001 0000 0000 0010 0000 0001 0000 0000
and Table 5). Data are shifted out on the falling edge
of the data clock, DCLK. 0.000096% FS 0000 0001 0000 0000 0001 0000 0001 0000 0000
0% FS 0000 0001 0000 0000 0000 0000 0001 0000 0000
–0.3955% FS 0000 0000 0000 0000 0000 0000 0000 0000 0000
(1) Excludes the effects of noise, INL, offset, and gain errors.
Figure 27. Digital Interface Timing Diagram for Data Retrieval From a Single DDC264
Table 5. Timing for DDC264 Data Retrieval
SYMBOL DESCRIPTION MIN TYP MAX UNITS
tPDCDV Propagation delay from falling edge of CLK to DVALID Low 10 ns
tPDDCDV Propagation delay from falling edge of DCLK to DVALID High 5 ns
tHDDODV Hold time that DOUT is valid before the falling edge of DVALID 400 ns
tHDDODC Hold time that DOUT is valid after falling edge of DCLK 4 ns
tPDDCDO (1) Propagation delay from falling edge of DCLK to valid DOUT 25 ns
(1) With a maximum load of one DDC264 (4pF typical) with an additional load of 5pF.
16 Copyright ©2006–2011, Texas Instruments Incorporated
IN64
IN64
IN64
IN64
256
192
128
64
Sensor
DIN
DOUT DDC264
Data
Retrieval
Output
DataClock
DIN
DOUT DDC264 DIN
DOUT DDC264 DIN
DOUT DDC264
DVALID
DCLK
DVALID
DCLK
DVALID
DCLK
DVALID
DCLK
IN63
255
IN62
254
IN61
253
IN4
196
IN3
195
IN2
194
IN1
193
IN1
129
IN1
65
IN1
1
IN2
130
IN2
66
IN2
2
IN3
131
IN3
67
IN3
3
IN4
132
IN4
68
IN4
4
IN61
189
IN61
125
IN61
61
IN62
190
IN62
126
IN62
62
IN63
191
IN63
127
IN63
63
DVALID
DCLK
DIN
tSTDIDC tHDDIDC
DOUT
Input
256
MSB
Input
256
MSB
Input
256
LSB
Input
255
MSB
Input 3
LSB
Input 2
MSB
Input 2
LSB
Input 1
MSB
Input 1
LSB
DDC264
www.ti.com
SBAS368C –MAY 2006–REVISED JULY 2011
Cascading Multiple Converters Figure 29 shows the timing diagram when the DIN
input is used to daisy-chain several devices. Table 6
Multiple DDC264 devices can be connected in a gives the timing specification for data retrieval using
serial configuration; see Figure 28.DIN.
DOUT can be used with DIN to daisy-chain multiple
DDC264 devices together to minimize wiring. In this
mode of operation, the serial data output is shifted
through multiple DDC264s; see Figure 28.
Figure 28. Daisy-Chained DDC264s
Figure 29. Timing Diagram When Using DDC264 DIN Function; See Figure 28
Table 6. Timing for DDC264 Data Retrieval Using DIN
SYMBOL DESCRIPTION MIN TYP MAX UNITS
tSTDIDC Set-up time from DIN to falling edge of DCLK 10 ns
tHDDIDC Hold time for DIN after falling edge of DCLK 10 ns
Copyright ©2006–2011, Texas Instruments Incorporated 17
1000 s 278.4 s- mm
(1280)(50ns) = 11.5 11 DDC264s®
t (t + t )
INT DR
-SDCV
(20 64)´ tDCLK
¼¼
¼¼
Side B
Data
Side A
Data
tINT tINT
tDR
tSDCV
CONV
DVALID
DCLK
DOUT
DDC264
SBAS368C –MAY 2006–REVISED JULY 2011
www.ti.com
Retrieval Before CONV Toggles
Data retrieval should occur before CONV toggles. NOTE: (16 ×64)τDCLK is used for Format = 0, where
Data retrieval begins soon after DVALID goes low τDCLK is the period of the data clock. For example, if
and finishes before CONV toggles, as shown in tINT = 1000μs and DCLK = 20MHz, the maximum
Figure 30. For best performance, data retrieval must number of DDC264s with Format = 1 is shown in
stop tSDCV before CONV toggles. This method is most Equation 2:
appropriate for longer integration times. The
maximum time available for readback is (tINT –(2)
tCMDR –tSDCV). The maximum number of DDC264s
that can be daisy-chained together (Format = 1) is (or 14 DDC264s for Format = 0)
calculated by Equation 1:
(1)
Figure 30. Readback Before CONV Toggles
Table 7. Timing for Readback
SYMBOL DESCRIPTION MIN TYP MAX UNITS
tSDCV Data retrieval shutdown before or after edge of CONV 2 μs
18 Copyright ©2006–2011, Texas Instruments Incorporated
274 sm
(20 64)´ tDCLK
t (t +t +t )-
INT SDCV SDCV HDDODV
(20 64)´ tDCLK
tINT
tDR
tSDCV
tINT tINT
¼ ¼ ¼
¼ ¼ ¼
Side A
Data
Side B
Data
Side A
Data
CONV
DVALID
DCLK
DOUT
tHDDODV
¼ ¼ ¼ ¼ ¼ ¼
¼ ¼ ¼ ¼ ¼ ¼
DCLK
DVALID
CONV
DOUT
Side B
Data
Side A
Data
tINT
tSDCV
tSDCV tHDDODV
tINT tINT
DDC264
www.ti.com
SBAS368C –MAY 2006–REVISED JULY 2011
Retrieval After CONV Toggles Retrieval Before and After CONV Toggles
For shorter integration times, more time is available if For the absolute maximum time for data retrieval,
data retrieval begins after CONV toggles and ends data can be retrieved before and after CONV toggles.
before the new data are ready. Data retrieval must Nearly all of tINT is available for data retrieval.
wait tSDCV after CONV toggles before beginning. See Figure 32 illustrates how this process is done by
Figure 31 for an example of this timing sequence. combining the two previous methods. Pause the
The maximum time available for retrieval is tDR –retrieval during CONV toggling to prevent digital
(tSDCV + tHDDODV), regardless of tINT. The maximum noise, as discussed previously, and finish before the
number of DDC264s that can be daisy-chained next data are ready. The maximum number of
together with Format = 1 is calculated by Equation 3: DDC264s that can be daisy-chained together with
Format = 1 is:
(3) (4)
NOTE: (16 ×64)τDCLK is for Format = 0. NOTE: (16 ×64)τDCLK is used for Format = 0.
For DCLK = 20MHz, the maximum number of
DDC264s is four (or five for Format = 0). For tINT = 400μs and DCLK = 20MHz, the maximum
number of DDC264s is six (or seven for Format = 0).
Figure 31. Readback After CONV Toggles
Figure 32. Readback Before and After CONV Toggles
Copyright ©2006–2011, Texas Instruments Incorporated 19
Configuration
Register
Data
Write Configuration Register Data
Configuration Register Operations(1)
Check Pattern
Read Configuration Register
and Check Pattern
RESET
CLK_CFG
DIN_CFG
DCLK
DOUT
CONV
Normal Operation
tWTWR
tWTRST
MSB LSB
MSB LSB
tSTCF
tRST
tHDCF
1 320(2)
320 0s(2)
DDC264
SBAS368C –MAY 2006–REVISED JULY 2011
www.ti.com
CONFIGURATION REGISTER NOTE: With Format = 1, the check pattern is 300
Read and Write Operations bits, with only the last 72 bits non-zero. This
sequence of outputs is repeated twice for each
The Configuration Register must be programmed DDC264 and daisy-chaining is supported in
after power-up or a device reset. The DIN_CFG, configuration readback. Table 8 shows the check
CLK_CFG, and RESET pins are used to write to this pattern configuration during readback. Table 9 shows
register. When beginning a write operation, hold the timing for the Configuration Register read and
CONV low and strobe RESET; see Figure 33. Then write operations. Strobe CONV to begin normal
begin shifting in the configuration data on DIN_CFG. operation.
Data are written to the Configuration Register most
significant bit first. The data are internally latched on Table 8. Check Pattern During Readback
the falling edge of CLK_CFG. Partial writes to the Check Pattern Total Readback
Configuration Register are not allowed—make sure to Format Bit (Hex) Bits
send all 16 bits when updating the register. 0 180 0s, 1024
Optional readback of the Configuration Register is 30F066012480F6h
available immediately after the write sequence. 1 228 0s, 1280
During readback, 320 '0's, then the 16-bit 30F066012480F69055h
configuration data followed by a 4-bit revision ID and
the check pattern are shifted out on the DOUT pin on
the rising edge of DCLK. The check pattern can be
used to check or verify the DOUT functionality.
(1) CLK must be running during Configuration Register write and read operations.
(2) In 16-bit mode (FORMAT = 0), only 256 0s are read before the Configuration Register write and read operations.
Figure 33. Configuration Register Write and Read Operations
Table 9. Timing for the Configuration Register Read/Write
SYMBOL DESCRIPTION MIN TYP MAX UNITS
tWTRST Wait Required from Reset High to First Rising Edge of CLK_CFG 2 μs
Wait Required from Last CLK_CFG of Write Operation to
tWTWR 2μs
First DCLK of Read Operation
tSTCF Set-Up Time from DIN_CFG to Falling Edge of CLK_CFG 10 ns
tHDCF Hold Time for DIN_CFG After Falling Edge of CLK_CFG 10 ns
tRST Pulse Width for RESET Active 1 μs
20 Copyright ©2006–2011, Texas Instruments Incorporated
DDC264
www.ti.com
SBAS368C –MAY 2006–REVISED JULY 2011
Configuration Register Bit Assignments
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
0 0 Clkdiv 0 0 Range[1] Range[0] Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Version 0 0 Reserved 0 0 0 Test
Bits 15:14 These bits must always be set to '0'.
Bit 13 Clkdiv
The Clkdiv input enables an internal divider on the system clock as shown in Table 10. When
Clkdiv = 1, the system clock is divided by 4. This configuration allows a system clock that is
faster by a factor of four, which in turn provides a finer quantization of the integration time,
because the CONV signal must be synchronized with the system clock for the best performance.
0 = Internal clock divider set to 1
1 = Internal clock divider set to 4
Table 10. Clkdiv Operation
Clkdiv Bit CLK Divider Value CLK Frequency Internal Clock Frequency
0 1 5MHz 5MHz
1 4 20MHz 5MHz
Bits 12:11 These bits must always be set to '0'.
Bits 10:9 Range[1:0]
These bits set the full-scale range.
00 = Range 0 = 12.5pC 10 = Range 2 = 100.0pC
01 = Range 1 = 50.0pC 11 = Range 3 = 150.0pC
Bit 8 Format
Format selects how many bits are used in the data output word.
0 = 16-bit output
1 = 20-bit output
Bit 7 Version
This bit must be set to match the device being used.
Must be set to '0' for DDC264C.
Must be set to '1' for DDC264CK.
Bits 6:5 These bits must always be set to '0'.
Bit 4 Reserved
This bit is reserved and must be set to '0'.
Bits 3:1 These bits must always be set to '0'.
Bit 0 Test
When Test Mode is used, the inputs (IN1 through IN64) are disconnected from the DDC264
integrators to enable the user to measure a zero input signal regardless of the current supplied
to the inputs.
0 = TEST mode off
1 = TEST mode on
Copyright ©2006–2011, Texas Instruments Incorporated 21
Power Supplies
RESET
tRST
tPOR
Write to the
Configuration Register
Configuration
Serial Interface
CLK
AVDD
DVDD
AGND
DGND
DDC264
10 Fm
0.3 Fm
0.1 Fm
10 Fm
Analog
Supply
Digital
Supply
DDC264
SBAS368C –MAY 2006–REVISED JULY 2011
www.ti.com
LAYOUT POWER-UP SEQUENCING
Before device power-up, all digital and analog inputs
Power Supplies and Grounding must be low. At the time of power-up, all of these
Both AVDD and DVDD should be as quiet as signals should remain low until the power supplies
possible. It is particularly important to eliminate noise have stabilized, as shown in Figure 35. The analog
from AVDD that is non-synchronous with the DDC264 supply must come up before or at the same time as
operation. Figure 34 illustrates how to supply power the digital supply. At this time, begin supplying the
to the DDC264. Each DDC264 has internal bypass master clock signal to the CLK pin. Wait for time tPOR,
capacitors on AVDD and DVDD; therefore, the only then give a RESET pulse. After releasing RESET, the
external bypass capacitors typically needed are 10μF Configuration Register must be written to. Table 11
ceramic capacitors, one per PCB. It is recommended shows the timing for the power-up sequence.
that both the analog and digital grounds (AGND and
DGND) be connected to a single ground plane on the
PCB.
Figure 35. DDC264 Timing Diagram at Power-Up
Figure 34. Power-Supply Connections
Table 11. Timing for DDC264 Power-Up Sequence
Shielding Analog Signal Paths SYMBOL DESCRIPTION MIN TYP MAX UNITS
As with any precision circuit, careful PCB layout Wait after power-up
tPOR 250 ms
ensures the best performance. It is essential to make until reset
short, direct interconnections and avoid stray wiring
capacitance—particularly at the analog input pins and
QGND. The analog input pins are high-impedance
and extremely sensitive to extraneous noise. The
QGND pin should be treated as a sensitive analog
signal and connected directly to the supply ground
with proper shielding. Leakage currents between the
PCB traces can exceed the input bias current of the
DDC264 if shielding is not implemented. Digital
signals should be kept as far as possible from the
analog input signals on the PCB.
22 Copyright ©2006–2011, Texas Instruments Incorporated
DDC264
www.ti.com
SBAS368C –MAY 2006–REVISED JULY 2011
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (January, 2011) to Revision C Page
•Updated Table 1; revised values for Range 0 performance in fC and Electrons ................................................................. 9
Changes from Revision A (January, 2011) to Revision B Page
•Changed second paragraph of Basic Integration Cycle section to correct CONV timing description error ....................... 11
Copyright ©2006–2011, Texas Instruments Incorporated 23
PACKAGE OPTION ADDENDUM
www.ti.com 1-Jul-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
DDC264CKZAW ACTIVE NFBGA ZAW 100 168 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
DDC264CKZAWR ACTIVE NFBGA ZAW 100 1000 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
DDC264CZAW ACTIVE NFBGA ZAW 100 168 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
DDC264CZAWR ACTIVE NFBGA ZAW 100 1000 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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