®
Altera Corporation 1
MAX 3000A
Programmable Logic
Device Famil y
March 2001, ver. 2.0 Data Sheet
A-DS-M3000A-02.0
Features... ■High–performance, low–cost CMOS EEPROM–based programmable
logic devices (PLDs) built on a MAX® architecture (see Table 1)
■3.3-V in-system programmability (ISP) through the built–in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with
advanced pin-locking capabi lit y
–ISP circuitry compatible with IEEE Std. 1532
■Built–in boundary-scan test (BST) circuitry compliant with
IEEE Std. 1149 .1 -19 90
■Enhanced ISP featur es:
–Enhanc ed ISP alg orit hm for fast er prog ra mming
–ISP_Done bit to ensure complete programming
–Pull-up resistor on I/O pins during in–system programming
■High–density PLDs ranging from 600 to 5,000 usable gates
■4.5–ns p in–to–pin logic delays with counter frequencies of up to
227.3 MHz
■MultiVoltTM I/O interfa ce enabling the de vice core to run at 3. 3 V,
while I/O pins are co mpatible with 5.0–V, 3.3–V, and 2.5–V logic
levels
■Pin counts ranging from 44 to 208 in a variety of thin quad flat pack
(TQFP), plastic quad flat pack (PQFP), and plastic J–lead chip carr ier
(PLCC) packages
■Hot–socketing support
■Programmable interconnect array (PIA) continuous routing structure
for fast, predictable performan ce
■PCI compatible
■Bus–friendly architect ure includin g progra mmable slew –rate control
■Open–drain output option
Table 1. MAX 3000A De vice Fea tures
Feature EPM3032A EPM3064A EPM3128A EPM3256A
Usable gates 600 1,250 2,500 5,000
Macrocells 32 64 128 256
Logic array blocks 2 4 8 16
Maximum user I/O
pins 34 66 96 158
tPD (ns) 4.5 4.5 5.0 5.5
tSU (ns) 2.9 2.8 3.3 3.9
2Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
...and More
Features
■Programmable macrocell flipflops with individual clear, preset,
clock, and clock enab le con tr o ls
■Programmable power–savin g mode for a power reduction of ove r
50% in each macrocell
■Configurable expander product–term distribution, allowing up to
32 prod uc t te r m s per mac r o ce l l
■Programmable security bit for protection of proprietary designs
■Enhanc ed ar ch ite ctu ra l feat ures, inc lu di ng:
–Six pin– or logic–driven output enable signals
–Two global clock signals with optional inversion
–Enhanced interconnect resources for improved routability
–Programmable output slew–rate control
■Software design support and automatic place–and–route provided
by Altera’s development systems for Windows–ba sed PCs an d Sun
SPARCs tations , and HP 9000 Series 700/8 00 workstatio ns
■Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other inter faces to popular EDA t ools from
third–party manufacturers such as Cadence, Exemplar Logic, Mentor
Graphics, OrCAD, Synopsys, Synplicity, and VeriBest
■Programming support wit h the Alte ra mas ter p rogra mmi ng unit
(MPU), MasterBlasterTM communications cable, ByteBlasterMVTM
parallel port downlo ad cab le, BitB lasterTM seri al down loa d ca ble as
well as pr ogramming hard ware from thir d–party manufacturers and
any in–circuit tester that supports J am TM Standard Test and
Programming Language (STAPL) Files (.jam), Jam STAPL Byte-Code
Files (.jbc), or Serial Vector Format Files (.svf)
General
Description
MAX 3000A devices are low–cost, high–performance devices based on the
Altera MAX architecture. Fabricated with advanced CMOS technology,
the EEPROM–based MAX 3000A de vices operate with a 3.3-V supply
voltage and provide 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast
as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 3000A devices in
the –4, –5, –6, –7, and –10 speed grades are compatible with the timing
requirements of the PCI Special Interest Group (PCI SIG) PCI Local Bus
Specification, Revision 2.2. See Table 2.
tCO1 (ns) 3.0 3.1 3.4 3.5
fCNT (MHz) 227.3 222.2 192.3 172.4
Table 1. MAX 3000A Device Features
Feature EPM3032A EPM3064A EPM3128A EPM3256A
Altera Corporation 3
MAX 3000A Pr ogrammable Logic Device Famil y Data Sheet
Note:
(1) Contact Al te r a for up -t o- date inf o r mation on the availab ility of this speed grade.
The MAX 3000A architecture supports 100% transist or-to-tra nsisto r logic
(TTL) emulation and high–density small-scale integrat ion (S S I),
medium-scale integration (MSI), and large-scale integration (LSI) logic
functions. The MAX 3000A ar chitecture easily integra tes multiple devices
ranging from PALs, GALs, and 22V10s to MACH and pLSI devices.
MAX 3000A dev ic es ar e av ai lab le in a wide ra ng e of pac kages, including
PLCC, PQFP, and TQFP packages. See Table 3.
Notes:
(1) Con tact Alte r a for up–to–date infor m at ion on available devic e pac kage opt ions.
(2) When the IEEE Std. 1149.1 (JTAG) interface is used for in–system programming or
boundary–scan testing, four I/O pins become JTAG pins.
MAX 3000A devices use CMOS EEPROM cells to implement logic
functions. The user–configurable MAX 3000A architecture accommodates
a variety of independent combinatorial and sequential logic functions.
The devices can be reprogrammed for quick and efficient iterations
during design development and debugging cycles, and can be
programmed and erased up to 100 times.
Table 2. MAX 3000A Speed G rades
Device Speed Grade
–4 –5 –6 –7 –10
EPM3032A vvv
EPM3064A vvv
EPM3128A vvv
EPM3256A v (1) vv
Table 3. MAX 3000A Maximum U s er I/O Pi ns Notes (1), (2)
Device 44–Pin
PLCC 44–Pin
TQFP 100–Pin
TQFP 144–Pin
TQFP 208–Pin
PQFP
EPM3032A 34 34
EPM3064A 34 34 66
EPM3128A 80 96
EPM3256A 116 158
4Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
MAX 3000A devices contain 32 to 256 macrocells , combined into groups
of 16 macrocells called logic array blocks (LABs). Each macrocell has a
programmable–AND/fixed–OR array and a co nfigurable regist er with
independently programmable clock, clock enable, clear, and preset
functions. To build complex logic functions, each macrocell can be
supplemented with shareable expander and high–speed parallel
expander product terms to provide up to 32 product terms per macrocell.
MAX 3000A devices provide programmable speed/power optimization.
Speed–critical portions of a design can run at high speed/full power,
while the remaining portions run at reduced speed/low power. This
speed/power optimization feature enables the designer to configure one
or more macrocells to operate a t 50% or low er power wh ile adding only a
nominal timing delay. MAX 3000A devices also provide an option that
reduces the slew rate of the output buffers, minimizing noise transients
when n on–speed–critical signals are switching. The output drivers of all
MAX 3000A devi ces can be set for 2.5 V or 3.3 V, and all inpu t p ins are
2.5–V, 3.3–V, and 5. 0-V tolerant , allow ing MAX 3000 A devices to be used
in mixed–voltage systems.
MAX 3000A devices are supported by Altera development systems,
which are integrated packages that offer schematic, text—including
VHDL, Verilog HDL, and the Altera Hardware Description Language
(AHDL)—and waveform design entry, compilation and logic synthesis,
simulation and timing analysis, and device prog ramming. The software
provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other
interfaces for additional design entry and simulation support from other
industry–standard PC – and UNIX–workstation–based EDA tools. The
software runs on Windows–based PCs, as well as S un SPARCst ation, and
HP 9000 Series 700/800 workst ations.
fFor more information on development tools, see the MAX+PLUS II
Programmable Logic Development System & Software Data She et andthe
Quartus Programmable Logic Development System & Software Data Sheet.
Functional
Description
The MAX 3000A architecture includes the following elements:
■Logic array blocks (LABs)
■Macrocells
■Expander product terms (shareable and parallel)
■Programmable interconnect array (PIA)
■I/O control blocks
The MAX 3000A architecture includes four dedicated inputs that can be
used as general–purpose inputs or as high–speed, global control signals
(clock, clear, an d two ou tput enable signals) for each macrocell and I/O
pin. Figure 1 shows the architecture of MAX 3000A devices.
Altera Corporation 5
MAX 3000A Pr ogrammable Logic Device Famil y Data Sheet
Figure 1. MAX 3000A Device Block Diagram
Logic Array Blocks
The MAX 3000A device architecture is based on the linking of
high–performance LABs. LABs consist of 16–macrocell arrays, as shown
in Figure 1. Multiple LABs are linked together via the PIA, a global bus
that is fed by all dedicated input pins, I/O pins, and macrocells.
Each LAB is fed by the following signals:
■36 signals from the PIA that are used for general logic inputs
■Global controls that are used for secondary register functions
Macrocells
MAX 3000A macrocells can be individually configured for either
sequential or combinatorial logic operation. Macrocells consist of three
functional blocks: logic array, product–term select matrix, and
programmable register. Figure 2 shows a MA X 3000A macrocell .
6
6
INPUT/GCLRn 6 Output Enables 6 Output Enables
16
36 36
16
I/O
Control
Block
LAB C LAB D
I/O
Control
Block
6
16
36 36
16
I/O
Control
Block
LAB A
Macrocells
1 to 16
LAB B
I/O
Control
Block
6
PIA
INPUT/GCLK1
INPUT/OE2/GCLK2
INPUT/OE1
6 to 16 I/O
6 to 16 I/O
6 to 16 I/O
6 to 16 I/O
6 to 16
6 to 16
6 to 16
6 to 16
6 to 16
6 to 16
6 to 16
6 to 16
Macrocells
17 to 32
Macrocells
33 to 48 Macrocells
49 to 64
6Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Figure 2. MAX 3000A Macrocell
Combinatorial logic is implemented in the logic array, which provides
five product terms per macrocell. The product–term select matrix
allocates these pr oduct terms for use a s either primary logic input s (to the
OR and XOR gates) to implement combinatorial functions, or as secondary
inpu ts to the macrocell’s register preset, clock, and clock enable control
functions.
Two kinds of expander product terms (“expanders”) are av ailable to
supplement macrocell lo gic resources:
■Shareable expanders, which are inverted product terms that are fed
back into the logic array
■Parallel expanders, w hich are product terms borr owed from adjacent
macrocells
The Altera development system automatically optimizes product–term
allocation according to the logic requirements of the design.
Product
-
T
erm
Select
Matri
x
36 Signals
f
rom PIA 16 Expander
Product Terms
LAB Local Arra
y
Parallel Logic
Expanders
(
from other
macrocells
)
Shared Lo
g
ic
Expanders
Clear
Select
Global
Clear Global
Clocks
Clock/
Enable
Select
2
PRN
C
LR
N
Q
ENA
Register
B
y
pass
T
o I/O
C
ontrol
Bloc
k
T
o PIA
Pro
g
rammable
Re
g
iste
r
VCC
D/T
Altera Corporation 7
MAX 3000A Pr ogrammable Logic Device Famil y Data Sheet
For registered functions, each macrocell flipflop can be individually
programmed to implement D, T, JK, or S R operation with prog rammable
clock control. The flipflop ca n be by pass ed for combi natorial operation.
During design entry, the designer specifies the desired flipflop type; the
Altera development system software then selects the most efficient
flipflop operation for each registered function to optimize resource
utilization.
Each programmable register can be clocked in three different modes:
■Global clock sig nal mode, which achieves the fa stest clock–to–output
performance.
■Globa l cl ock signal enabled by an activ e–high clock en ab l e . A clock
enable i s generat ed by a product te rm. This mode provides an enab le
on each flipflop while still achieving the fast clock–to–output
performance of the global clock.
■Array clock im plemented with a pr od uct term . In this mod e, the
flipflop can b e clocked by sign als from buried macrocells or I/O pin s.
Two global clo c k signal s are availabl e in MAX 3000A devices. As shown
in Figure 1, these global clock signals can be the true or the complement of
either of the two global clock pins, GCLK1 or GCLK2.
Each register also supports asynchronous preset and clear functions. As
shown in Figure 2, the product–term select matrix allocates product terms
to control these operations. Although the product–term–driven preset
and clear from the register are active high, active–low cont rol ca n be
obtained by inverting the signal within the logic array. In addition, each
register clear function can be individually driven by the active–low
dedicated global clear pin (GCLRn).
Expander Product Terms
Altho ugh most lo gic f uncti ons c an be impl eme nted w ith the f ive p roduc t
terms ava ilable in each macrocell, highly compl ex logic fu nctio ns require
addition al produc t terms. An oth er m acroc ell can be used to supply the
required logic resources. However, the MAX 3000A architecture also
offers both shareable a nd parallel expande r product terms (“expanders”)
that provide additional product terms directly to any macrocell in the
same LAB. Th ese expanders help ens ure that logi c is synthesized wi th the
fewest possible logic resources to obtain the fastest possible speed.
8Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Shareable Expan ders
Each LAB has 16 shareable expanders that can be viewed as a pool of
uncommitted single product terms (one fro m e ach macrocell) with
inverted outputs that feed back into the logic array. Each shareable
expander can be used and shared by any or all macrocells in the LAB to
build complex logic functions. Shareable expanders incur a small delay
(tSEXP). Figure 3 shows how shareable expanders can feed multiple
macrocells.
Figur e 3. MAX 3000A Shareable Expanders
Shareable exp anders can be sh ared by any or al l macrocel ls in an LAB.
Parallel Expanders
Parallel expanders are unused product terms that can be allocated to a
neighboring macrocell to implement fast, complex logic functions.
Parallel expanders allow up to 20 product terms to directly feed the
macrocell OR logic, with five product terms provided by the macrocell and
15 parallel expanders provided by neighboring macrocells in the LAB.
Macrocell
Product-Ter
m
Logic
Pr
oduc
t-
T
erm Select Matrix
Macrocell
Product-Ter
m
Logic
36 Si
g
nals
f
rom PIA 16 Share
d
Expanders
Altera Corporation 9
MAX 3000A Pr ogrammable Logic Device Famil y Data Sheet
The Altera development system compiler can automatically allocate up to
three sets of up to five parallel expanders to the macrocells that require
additional product terms. Each set of five parallel expanders incurs a
small, incre me nt al timin g dela y (tPEXP). For example, if a macrocell
requires 14 product terms, the compiler uses the five dedicated product
terms within the macrocell and allocates two sets of parallel expanders;
the first set includes five product terms, and the second set includes four
product terms, increasing the to tal delay by 2 × tPEXP.
Two groups of eight macrocells within each LAB (e.g., macrocells 1
through 8 and 9 through 16) form two chains to lend or borrow parallel
expanders. A macrocell borrows parallel expanders from lower–
numbered macrocells. For example, macrocell 8 can borrow parallel
expanders from macrocell 7, from macrocells 7 and 6, or from macrocells
7, 6, and 5. Within each group of eight, the lowes t –numbered macrocell
can only lend parallel expanders and the highest–numbered macrocell can
only borrow them. Figure 4 shows how parallel expanders can be
borrowed from a neighboring macrocell.
Figure 4. MA X 3000A Parallel Exp anders
Unused product te rms in a mac rocell can be allocated to a nei ghboring macrocel l .
Preset
Clock
Clear
Product
-
er
Selec
t
M
atri
x
Preset
Clock
Clear
Product
-
T
er
T
er
T
m
Selec
t
Matri
x
Macrocell
Product-
Term Logic
From
Previous
M
acrocel
l
To Next
Macrocell
Macrocell
Product-
Term Logic
36 Signals
from PIA 16 Shared
Expanders
10 Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Programmable Interconnect Array
Logic is routed between LABs on the PIA. This global bus is a
programmable path that connects any signal source to any destination on
the device. All MAX 3000A dedicated inputs, I/O pins, and macrocell
outputs feed the PIA, which makes the signals available throughout the
entire device. Only the signals required by each LAB are actually routed
from the P IA into the LA B. Figure 5 s hows how the P IA signals are routed
into the LAB. An EEPROM cell controls one input to a two-input AND gate,
which selects a PIA signal to drive into the LAB.
Figure 5. M AX 3000A PIA Routing
While the rou ting delays of channe l–base d routi ng sc heme s in ma ske d or
FPGAs are cumulative, variable , a nd path–depend en t, the MA X 3000A
PIA has a predictable delay. The PIA makes a design’s timing
performance easy to predict.
I/O Contr ol Blocks
The I/O control block allows each I/O pin to be individually configured
for input, ou tp ut, o r b idir ec tion al opera ti on. A ll I/O pin s h av e a tr i–state
buffer that is individually controlled by one of the global output enable
signals or directly connected to ground or VCC. Figure 6 shows the I/O
control block for MAX 3000A devices. The I/O control block has
six gl obal outpu t enable s ignals that are drive n by the tr ue or comp lement
of two output enable signals, a subset of the I/O pins, or a subset of the
I/O macrocells.
To LAB
PIA Signals
Altera Corporation 11
MAX 3000A Pr ogrammable Logic Device Famil y Data Sheet
Figure 6. I/O Control Block of MAX 3000A Devices
When the tri–state buffer control is connected to ground, the output is
tri-stated (high impedance), and the I/O pin can be used as a dedicated
input. When th e tri–state buffer contro l is connected to VCC, t he ou tput is
enabled.
The MAX 3000A architecture provides dual I/O feedback, in which
macrocell and pin feedbacks are independent. When an I/O pin is
configured as an input, the associated macrocell can be used for buried
logic.
In–System
Programma-
bility
MAX 3000A devices can be programmed in–system via an industry–
standa rd four–pin IEEE Std. 1149.1-1990 (JTAG) interface. In-system
programmability (ISP) offers quick, efficient iterations during design
development and debugging cycles. The MAX 3000A architecture
interna lly generates t he high program ming voltages r equired to prog ram
its EEPROM cells, allowing in–system programming with only a single
3.3–V power supply. During in–system programming, the I/O pins are
tri–stated an d weakly pulled –up to eliminate board conflicts. The pull–up
value is nominally 50 k¾.
From
Macrocell
Slew-Rate Contro
l
To PIA
To Other I/O Pins
6 Global
Output Enable Signals
PIA
VCC
Open-Drain Outpu
t
OE Select Multiplexer
GND
12 Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
MAX 3000A device s have an enhanc ed ISP alg orithm for faster
programming . These devices also offer an ISP_Done b it th at ensu res safe
operation when in–system programming is interrupted. This ISP_Done
bit, which is the last bit programmed, prevents all I/O pins from driving
until the bit is progr amm ed.
ISP simplifies the manufacturing flow by allowing devices to be mounted
on a printed circuit board (PCB) with standard pick–and–place equipment
before they are programmed. MAX 3000A devices can be programmed by
downloading the information via in–circuit testers, embedded processors,
the MasterBlaster communications cable, the ByteBlasterMV parallel port
download cable, and the BitBlaster serial download cable. Programming
the devices after t hey are placed on t he board elimin at es l ead dama ge on
high–pin–count packages (e.g., QFP packages) due to device handling.
MAX 3000A devices can be reprogrammed after a system has already
shipped to the field . F or example , product upgrad es can b e performed in
the field via software or modem.
The Jam STAPL programming and test language can be used to program
MAX 3000A de vices with in–c ircuit test ers, PCs, or emb edded processo rs.
fFor more information on using the Jam STAPL programming and test
language , see Appl ication Note 88 (Using the Jam Language for ISP & ICR via
an Embedded Processor), Application Note 122 (Using Jam STAPL for ISP &
ICR via an Embedded Processor) and AN 111 ( Embedded Programming Using
the 8051 and Jam Byte-Code).
The ISP circuitry in MAX 3000A devices is compliant with the IEEE Std.
1532 specification. The IEEE Std. 1532 is a standard developed to allow
concurrent ISP between multiple PLD vendors.
Programming
with External
Hardware
MAX 3000A devices can be prog rammed on Windows–based PCs with an
Altera Logic Programmer card, MPU, and the appropriate device adapter.
The MPU performs continuity checking to ensure adequate electrical
contact between the adapter and the devi ce.
fFor more information, see the Altera Programming Hardware Data Sheet.
The Altera software can use text– or waveform–format test vectors created
with the Altera Text Editor or Waveform Editor to te st the programmed
device. For added design verification, designers can perform functional
testing to compa re the fu nctional device behavior with the results of
simulation.
Data I/O, BP Microsystems, and other programming hardware
manufacturers als o provid e programming support for Altera devices.
fFor more information, see Programming Hardware Manufa cturers.
Altera Corporation 13
MAX 3000A Pr ogrammable Logic Device Famil y Data Sheet
IEEE Std.
1149.1 (JTAG)
Boundary–Scan
Support
MAX 3000A devices include the JTAG BST circuitry defined by IEEE
Std. 1149.1–1990. Table 4 describes the JTAG instructions supported by
MAX 3000A devices. The pin-out tables found on the Altera web site
(http://www.altera.com) or the Altera Digi tal Library show the location of
the JTAG control pins for each device. If the JTAG interface is not
required, the JTAG pins are available as user I/O pins.
The instruction register length of MAX 3000A devices is 10 bits. The
IDCODE and USERCODE register length is 32 bits. Tables 5 and 6 show
the boundary –scan register length and device IDCODE information for
MAX 3000A devices.
Table 4. MAX 3000A JTAG Instructions
JTAG Instruction Description
SAMPLE/PRELOAD Allows a snapshot of signals at the device pins to be captured and examined during
normal device operation, and permits an initial data pattern output at the device pins
EXTEST Allows the external circuitry and board–level interconnections to be tested by forcing a
test pattern at the output pins and capturing test results at the input pins
BYPAS S Places the 1–bit bypass register between the TDI and TDO pins, which allows the BST
data to pass synchronously through a selected device to adjacent devices during normal
device operation
IDCODE Selects the IDCODE register and places it between the TDI and TDO pins, allowing the
IDCODE to be serially shifted out of TDO
USERCODE Selects the 32–bit USERCODE regist er and places it between the TDI and TDO pins,
allowing the USERCODE value to be shifted out of TDO
ISP Instructions These instructions are used when programming MAX 3000A devices via the JTAG ports
with the MasterBlaster, ByteBlasterMV, or BitBlaster cable, or when using a Jam STAPL
file, JBC file, or SVF file via an embedded processor or test equipment
14 Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Notes:
(1) The most significant bit (MS B) is on the left.
(2) The least significant bit (LSB) for all JTAG IDCODEs is 1.
fSee Application Note 39 (IEEE 1149.1 (JTAG) Boundary–Scan Testing in Altera
Devices) for more information on JTAG BST.
Table 5. MAX 3000A Boundary–Sc an Regi ster Length
Device Boundary–Scan Register Length
EPM3032A 96
EPM3064A 192
EPM3128A 288
EPM3256A 480
Tabl e 6. 32–Bit MAX 3000A Device IDCODE Value Note (1)
Device IDCODE (32 bits)
Version
(4 Bits) Part Number (16 Bits) Manufacturer’s
Identity (11 Bits) 1 (1 Bit)
(2)
EPM3032A 0001 0111 0000 0011 0010 00001101110 1
EPM3064A 0001 0111 0000 0110 0100 00001101110 1
EPM3128A 0001 0111 0001 0010 1000 00001101110 1
EPM3256A 0001 0111 0010 0101 0110 00001101110 1
Altera Corporation 15
MAX 3000A Pr ogrammable Logic Device Famil y Data Sheet
Figure 7 shows the timing infor mation for th e JTAG signals.
Figur e 7. MAX 3000A JTAG Wave forms
Table 7 shows the JT A G timing parameters and values for MAX 3000A
devices.
Table 7. JTAG Timing Parameters & Values for MAX 3000A Devices
Symbol Parameter Min Max Unit
tJCP TCK cloc k period 100 ns
tJCH TCK cloc k high time 50 ns
tJCL TCK clock low time 50 ns
tJPSU JTAG port setup time 20 ns
tJPH JTAG port hold time 45 ns
tJPCO JTAG port clock to output 25 ns
tJPZX JTAG port high impedance to valid output 25 ns
tJPXZ JTAG port valid output to high impedance 25 ns
tJSSU Capt ure register setup time 20 ns
tJSH Capture register hold time 45 ns
tJSCO Update register clock to output 25 ns
tJSZX Update register high impedance to valid output 25 ns
tJSXZ Update register valid output to high impedance 25 ns
TDO
TCK
tJPZX tJPCO
tJPH
tJPXZ
tJCP tJPSU
tJCL
tJCH
TDI
TMS
Signal
to Be
Captured
Signal
to Be
Driven
tJSZX
tJSSU tJSH
tJSCO tJSXZ
16 Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Programma ble
Speed/Power
Control
MAX 3000A devices offer a power–saving mode that supports low-power
operation across user–defined signal paths or the entire device. This
feature allows total power dissipation to be reduced by 50% or more
because most logic applications require only a small fractio n of all gates to
operate at maximum frequency.
The designer can program each individual macrocell in a MAX 3000A
device for either high–speed or low–power operatio n. As a result,
speed-critical paths in the design can run at high speed, while the
remaining paths can operate at reduced power. Macrocells that run at low
power incur a nominal timing delay adder (tLPA) for the tLAD, tLAC, tIC,
tACL, tEN, tCPPW and tSEXP parameters.
Output
Configuration
MAX 3000A device outputs can be programmed to meet a variety of
system–lev el requir em ent s.
Mult iVolt I/O Interface
The MAX 3000A device ar chitecture support s the MultiVolt I/O interf ace
feat ure, which allows MAX 3000A de vices to connec t to sy stems with
differing supply voltages. MAX 3000A devices in all packages can be set
for 2.5–V, 3.3–V, or 5 .0–V I/O pin operation . These devices have one set of
VCC pin s for internal operation and inpu t buffers (VCCINT), and another
set for I/O output drivers (VCCIO).
The VCCIO pins can be connected to eit her a 3.3–V or 2.5–V power supply,
depending on the output requirements. When the VCCIO pins are
conn ected to a 2 .5–V power supply, the output levels are compatible with
2.5–V systems. When the VCCIO pins are connected to a 3.3–V power
supply, the output high is at 3.3 V and is therefore compatible with 3.3-V
or 5.0–V system s. Devices opera ting wit h VCCIO levels lowe r than 3.0 V
incur a nomi nally greate r timing delay of tOD2 instead of tOD1. Input s can
always be driven by 2.5–V, 3.3–V, or 5.0–V signals.
Table 8 summarizes the MAX 3000A MultiVolt I/O support.
Note:
(1) When VCCIO is 3.3 V, a MAX 3000A device can drive a 2.5–V device that has 3.3–V
tolerant inp ut s.
Table 8. MAX 3000A MultiVolt I/O Support
VCCIO Voltage Input Signal (V) Output Signal (V)
2.5 3.3 5.0 2.5 3.3 5.0
2.5 vvvv
3.3 vvvvvv
Altera Corporation 17
MAX 3000A Pr ogrammable Logic Device Famil y Data Sheet
Open–Drain Output Option
MAX 3000A devices provide an optional open–drain (equivalent to
open-collector) output for each I/O pin. This open–drain output enables
the device to provide system–level control signals (e.g., interrupt and
write e na ble sig na ls) that can be asser ted b y any o f se ver al dev ic es. I t c an
also provide an additional wired–OR plane.
Open-drain output pins on MAX 3000A devices (with a pull-up resistor to
the 5.0-V supply) can drive 5.0-V CMOS input pins that require a high VIH.
When the open-drain pin is active, it will drive low. When the pin is
inactive, the resistor will pull up the trace to 5.0 V, thereby meeting CMOS
requirements. The open-drain pin will only drive low or tri-state; it will
never drive high. The rise time is dependent on the value of the pull-up
resistor and load impedance. The IOL current specification should be
considered when selecting a pull-up resistor
Slew–Rate C ontrol
The output buffer for each MAX 3000A I/O pin has an adjustable output
slew rate th at can be configu red for low–noise or high–speed
performance. A faster slew rate provides high–speed transitions for
high-performance systems. However, these fast transitions may introduce
noise transients into the system. A slow slew rate reduces system noise,
but adds a nomin al delay of 4 to 5 ns. When the conf igur at ion ce ll is
turned off, the slew rate is set for low–noise performance. Each I/O pin
has an indiv idu al EEPROM bit that con tr ols th e slew rat e , all owing
designers to specify the slew rate on a pin–by–pin basis. The slew rate
control affects both the rising and falling edges of the output signal.
Design Security All MAX 3000A devices cont ain a programmable se curity bit that controls
acces s to the data progra mmed into th e device. When this bit is
programmed, a design implemented in the device cannot be copied or
retrieved. This feature provides a high level of design security because
program med da t a wi thin EEP ROM c el ls is inv is ible. The securit y bit t ha t
control s th is fu nc ti on, a s well as all other programmed dat a, is reset only
when the device is reprogrammed.
Generic Testing MAX 3000A devices ar e fully tested . Complete te sting of each
program mable EEPROM b it and all int erna l logic elemen ts ensures 100%
programming yield. AC test meas urements are taken under conditions
equivalent to those show n in Figure 8. Test pat terns can be used and then
erased during early stages of the production flow.
18 Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Figur e 8. MAX 3000A AC Test Conditions
Operating
Conditions
Tables 9 through 12 provide information on absolute maximum ratings,
recommen ded opera ti ng condit ion s, DC operating condit ion s, and
capacitan ce for MAX 3000A devices.
V
CC
To Test
System
C1 (includes jig
capacitance)
Device input
rise and fall
times < 2 ns
Device
Output
703 Ω
620 Ω
[521 Ω]
[481 Ω]
Power suppl y t r ansients can af fect AC
measurements. Simultaneous transitions
of multi pl e outputs sh oul d be avoided fo r
accurate measurement. Threshold tests
must not be performed under AC
conditions. Large–amplitude, fast–
ground–current transients normally occur
as the device outputs discharge the load
capacitances. When these transients flow
through the para si t i c i nductan ce between
the device ground pin and the test system
ground, significant reductions in
observa bl e noise immunity can result.
Numb ers in br ackets are for 2 .5 – V
output s. Nu mbers w ithou t brac kets are for
3.3–V devices or outputs.
Table 9. MAX 3000A Device Absolute Maximum Ratings No te (1)
Symbol Parameter Conditions Min Max Unit
VCC Supply voltage With respect to ground (2) –0.5 4.6 V
VIDC input voltage –2.0 5.75 V
IOUT DC output current, per pin –25 25 mA
TSTG Storage temperature No bias –65 150 ° C
TAAmbient temperature Under bias –65 135 ° C
TJJunction temperature PQFP and TQFP packages, under bias 135 ° C
Altera Corporation 19
MAX 3000A Pr ogrammable Logic Device Famil y Data Sheet
Table 10. MAX 3000A Device Recommended Operating Conditi ons
Symbol Parameter Conditions Min Max Unit
VCCINT Supply voltage for internal logic and
input buffers (9) 3.0 3.6 V
VCCIO Supply voltage for out put driv ers,
3.3–V operation 3.0 3.6 V
Supply vol ta ge for out put driv ers,
2.5–V operation 2.3 2.7 V
VCCISP Supply voltage duri ng ISP 3.0 3.6 V
VIInput voltage (3) –0.5 5.75 V
VOOutput voltage 0 VCCIO V
TAAmbient temperature For commercial use 0 70 ° C
TJJunction temperature For commercial use 0 90 ° C
tRInput rise time 40 ns
tFInput fall time 40 ns
Tab le 11. M AX 3000A Device DC Operating Conditions Note (4)
Symbol Parameter Conditions Min Max Unit
VIH High–level input voltage 1.7 5.75 V
VIL Low–level input voltage –0.5 0.8 V
VOH 3.3–V high–level TTL output
voltage IOH = –8 mA DC, VCCIO = 3.00 V (5) 2.4 V
3.3–V high–level CMOS output
voltage IOH = –0.1 mA DC, VCCIO = 3.00 V (5) VCCIO – 0.2 V
2.5–V high–level output voltage IOH = –100 µA DC, VCCIO = 2.30 V (5) 2.1 V
IOH = –1 mA DC, VCCIO = 2.30 V (5) 2.0 V
IOH = –2 mA DC, VCCIO = 2.30 V (5) 1.7 V
VOL 3.3–V low–level TTL output voltage IOL = 8 mA DC, VCCIO = 3.00 V (6) 0.4 V
3.3–V low–level CMOS output
voltage IOL = 0.1 mA DC, VCCIO = 3.00 V (6) 0.2 V
2.5–V low–level output voltage IOL = 100 µA DC, VCCIO = 2.30 V (6) 0.2 V
IOL = 1 mA DC, VCCIO = 2.30 V (6) 0.4 V
IOL = 2 mA DC, VCCIO = 2.30 V (6) 0.7 V
IIInput leakage current VI = VCCINT or ground –10 10 µA
IOZ Tri–state output off–state current VO = VCCINT or ground –10 10 µA
RISP Value of I/O pin pull–up resistor
when programming in–system or
during power–up
VCCIO = 2.3 to 3.6 V (7) 20 74 k¾
20 Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Notes to tables:
(1) S ee the Operating Requirements for Altera Devices Data Sheet.
(2) Minimum DC input voltage is –0.5 V. Dur ing transitions, the inputs may unders hoo t to –2.0 V or overshoot to
5.75 V for input currents less than 100 mA and per iods s hor ter than 20 ns .
(3) All pins, including dedic ated inputs, I/O pins, and JTAG pins, may be driven before VCCINT and VCCIO are
powered.
(4) These values are specified under the recommended operating conditions, as shown in Table 10 on page 19 .
(5) The parameter is measured with 50% of the outputs each sourcing the specified current. The IOH parameter refers
to high –level TTL or CMOS output current.
(6) The parameter is measured with 50 % of the outputs each sinking the specified current. The IOL parameter refers to
low–level TTL, PCI, or CMOS output cur rent .
(7) This pull–up exists while devices are programmed in–system and in unprogrammed devices during power–up.
(8) Capacitance is measured at 25° C and is sample–tested only. The OE1 pin (high –voltage pin during programming)
has a maximum capacitance of 20 pF.
(9) The POR time for MAX3000A devices does not exceed 100 ms.
Figure 9 shows the typical output drive characteristics of MAX 3000A
devices.
Table 12. MAX 3 000A De vice Capacitance Note (8)
Symbol Parameter Conditions Min Max Unit
CIN Input pin capacitance VIN = 0 V, f = 1.0 MHz 8 pF
CI/O I/O pin capacitance VOUT = 0 V, f = 1 .0 MHz 8 pF
Altera Corporation 21
MAX 3000A Pr ogrammable Logic Device Famil y Data Sheet
Figur e 9. Output Drive Characteristics o f MAX 3000A Devices
Power
Sequencing &
Hot–Socketing
Because MAX 3000A devices can be used in a mixed–voltage
environment, they have been designed specifically to tolerate any possible
power–up sequence. The VCCIO and V CCINT power planes can be
powered in any order.
Signals can be driven into MAX 3000A devices before and during
power-up w ithout damaging the device. I n addition, MAX 3000A devices
do not drive out during power-up. Once operating conditions are
reached, MAX 3000A devices operate as specified by the user.
VO Output Voltage (V)
1234
0
0
50
IOL
IOH
VCCINT = 3.3
= 25 C
V
VCCIO = 3.3 V
Temperature
100
150
Typical I
Output
Current (mA)
O
VO Output Voltage (V)
1234
VCCINT = 3.3 V
VCCIO = 2.5 V
IOH
2.5 V
3.3 V
Typical I
Output
Current (mA)
O
00
50
IOL
100
150
O
= 25 C
Temperature O
22 Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Timing Model MAX 3000A de vice timi ng can b e analyz ed with th e Altera software, with
a variety of popular industry–standard EDA simulators and timing
analyzers, or with the timing model shown in Figure 10. MAX 3000A
devices have predictable internal delays that enable the designer to
deter mine th e wo rst –case timing of any design. The software provides
timing s imulation, point–to–point delay prediction, and detailed timing
analysis for device–wide performance evaluation.
Figure 10. M AX 3000A Timi ng Model
The timi ng character is tics of any si gnal path can be d erived from the
timing model and parameters of a particular device. External timing
parameters, which represent pin–to–pin timing delays, can be calculated
as the sum of internal parameters. Figure 11 shows the timing relationship
between internal and external delay parameters.
Logic Array
Delay
t
LAD
Output
Delay
t
OD3
t
OD2
t
OD1
t
XZ
Z
t
X1
t
ZX2
t
ZX3
Input
Delay
t
IN
Register
Delay
t
SU
t
H
t
PRE
t
CLR
t
RD
t
COMB
PIA
Delay
t
PIA
Shared
Expander Delay
t
SEXP
Register
Control Delay
t
LAC
t
IC
t
EN
I/O
Delay
t
IO
Global Control
Delay
t
GLOB
Internal Output
Enable Delay
t
IOE
Parallel
Expander Delay
t
PEXP
Altera Corporation 23
MAX 3000A Pr ogrammable Logic Device Famil y Data Sheet
Figure 11. MAX 3000A Switching Wavefor m s
Combinatorial Mode
Input Pin
I/O Pin
PIA Delay
Shared Expander
Delay
Logic Array
Input
Parallel Expander
Delay
Logic Array
Output
Output Pin
t
IN
t
LAC
, t
LAD
t
PIA
t
OD
t
PEXP
t
IO
t
SEXP
t
COMB
Global Clock Mode
Global
Clock Pin
Global Clock
at Register
Data or Enable
(Logic Array Output)
t
F
t
CH
t
CL
t
R
t
IN
t
GLOB
t
SU
t
H
Array Clock Mode
Input or I/O Pin
Clock into PIA
Clock into
Logic Array
Clock at
Register
Data from
Logic Array
Register to PIA
to Logic Array
Register Output
to Pin
t
F
t
R
t
ACH
t
ACL
t
SU
t
IN
t
IO
t
RD
t
PIA
t
CLR
, t
PRE
t
H
t
PIA
t
IC
t
PIA
t
OD
t
OD
tR & tF < 2 ns. Inputs are
driven at 3 V for a logic
high and 0 V for a logic
low. All timing
characteristics are
measured at 1.5 V.
24 Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Tables 13 th rou gh 20 show EPM3032A, EPM3064A, EPM3128A, and
EPM3256A timing information.
Table 13. EPM303 2A External Tim ing Parameters Note (1)
Symbo l Par a meter Conditions Speed Gra de Unit
–4–7–10
Min Max Min Max Min Max
tPD1 Input to non–
registered output C1 = 35 pF
(2) 4.5 7.5 10 ns
tPD2 I/O input to non–
registered output C1 = 35 pF
(2) 4.5 7.5 10 ns
tSU Global clock setup
time (2) 2.9 4.7 6.3 ns
tHGlobal clock hold time (2) 0.0 0.0 0.0 ns
tCO1 Global clock to output
delay C1 = 35 pF 1.0 3. 0 1.0 5.0 1.0 6.7 ns
tCH Global clock high time 2.0 3.0 4.0 ns
tCL Global clock low time 2.0 3.0 4.0 ns
tASU Array clock setup time (2) 1.6 2.5 3.6 ns
tAH Array clock hold time (2) 0.3 0.5 0.5 ns
tACO1 Array clock to output
delay C1 = 35 pF
(2) 1.0 4.3 1.0 7.2 1.0 9.4 ns
tACH Array clock high time 2.0 3.0 4.0 ns
tACL Array clock low time 2.0 3.0 4.0 ns
tCPPW Minimum pulse width
for clear and preset (3) 2.0 3.0 4.0 ns
tCNT Minimum global clock
period (2) 4.4 7.2 9.7 ns
fCNT Maximum internal
global clock frequency (2), (4) 227.3 138.9 103.1 MHz
tACNT Minimum array clock
period (2) 4.4 7.2 9.7 ns
fACNT Maximum internal
array clock frequency (2), (4) 227.3 138.9 103.1 MHz
Altera Corporation 25
MAX 3000A Pr ogrammable Logic Device Famil y Data Sheet
Table 14. EPM3032A Internal Timing Parameters (Part 1 of 2) Note (1)
Symbol Parameter Conditions Speed Grade Unit
–4–7–10
Min Max Min Max Min Max
tIN Input pad and buffer delay 0.7 1.2 1.5 ns
tIO I/O input pad and buffer
delay 0.7 1.2 1.5 ns
tSEXP Shared expander delay 1.9 3.1 4.0 ns
tPEXP Parallel expander delay 0.5 0.8 1.0 ns
tLAD Logic array delay 1.5 2.5 3.3 ns
tLAC Logic control array delay 0. 6 1.0 1.2 ns
tIOE Internal output enable delay 0.0 0.0 0.0 ns
tOD1 Output buffer and pad
delay, slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF 0.8 1.3 1.8 ns
tOD2 Output buffer and pad
delay, slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF 1.3 1.8 2.3 ns
tOD3 Output buffer and pad
delay, slow slew rate = on
VCCIO = 2.5 V or 3.3 V
C1 = 35 pF 5.8 6.3 6.8 ns
tZX1 Output buffer enable delay,
slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF 4.0 4.0 5.0 ns
tZX2 Output buffer enable delay,
slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF 4.5 4.5 5.5 ns
tZX3 Output buffer enable delay,
slow slew rate = on
VCCIO = 2.5 V or 3.3 V
C1 = 35 pF 9.0 9.0 10.0 ns
tXZ Output buffer disable delay C1 = 5 pF 4.0 4.0 5.0 ns
tSU Register setup time 1.3 2.0 2.8 ns
tHRegister hold time 0.6 1.0 1.3 ns
tRD Register delay 0.7 1.2 1.5 ns
tCOMB Combinatorial delay 0.6 1.0 1.3 ns
tIC Array clock delay 1.2 2.0 2.5 ns
tEN Register enable time 0.6 1.0 1.2 ns
tGLOB Global control delay 0.8 1.3 1.9 ns
tPRE Register preset time 1.2 1.9 2.6 ns
26 Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
tCLR Register clear time 1.2 1.9 2.6 ns
tPIA PIA delay (2) 0.9 1.5 2.1 ns
tLPA Low–power adder (5) 2.5 4.0 5.0 ns
Table 15. EPM306 4A External Tim ing Parameters Note (1)
Symb ol Para me te r Conditions Speed Gr a de Unit
–4–7–10
MinMaxMinMaxMinMax
tPD1 Input to non–registered
output C1 = 35 pF (2) 4.5 7.5 10.0 ns
tPD2 I/O input to non–registered
output C1 = 35 pF (2) 4.5 7.5 10.0 ns
tSU Global clock setup time (2) 2.8 4.7 6.2 ns
tHGlobal clock hold time (2) 0.0 0.0 0.0 ns
tCO1 Global clock to output delay C1 = 35 pF 1.0 3.1 1.0 5.1 1.0 7.0 ns
tCH Global clock high time 2.0 3 .0 4.0 ns
tCL Global clock low time 2.0 3 .0 4.0 ns
tASU Array clock setup time (2) 1.6 2.6 3.6 ns
tAH Array clock hold time (2) 0.3 0.4 0.6 ns
tACO1 Array clock to output delay C1 = 35 pF (2) 1.0 4.3 1.0 7.2 1.0 9.6 ns
tACH Array clock high time 2.0 3. 0 4.0 ns
tACL Array clock low time 2.0 3.0 4.0 ns
tCPPW Minimum pulse width for
clear and preset (3) 2.0 3.0 4.0 ns
tCNT Minimum global clock
period (2) 4.5 7.4 10.0 ns
fCNT Maximum internal global
clock frequency (2), (4) 222.2 135.1 100.0 MHz
tACNT Minimum array clock period (2) 4.5 7.4 10.0 ns
fACNT Maximum internal array
clock frequency (2), (4) 222.2 135.1 100.0 MHz
Table 14. EPM3032A Internal Timing Parameters (Part 2 of 2) Note (1)
Symbol Parameter Conditions Speed Grade Unit
–4–7–10
Min Max Min Max Min Max
Altera Corporation 27
MAX 3000A Pr ogrammable Logic Device Famil y Data Sheet
Table 16. EPM3064A Internal Timing Parameters (Part 1 of 2) Note (1)
Symbol Parameter Conditions Speed Grade Unit
–4–7–10
Min Max Min Max Min Max
tIN Input pad and buffer delay 0.6 1.1 1.4 ns
tIO I/O input pad and buffer
delay 0.6 1.1 1.4 ns
tSEXP Shared expander delay 1.8 3.0 3.9 ns
tPEXP Parallel expander delay 0.4 0.7 0.9 ns
tLAD Logic array delay 1.5 2.5 3.2 ns
tLAC Logic control array delay 0. 6 1.0 1.2 ns
tIOE Internal output enable delay 0.0 0.0 0.0 ns
tOD1 Output buffer and pad
delay, slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF 0.8 1.3 1.8 ns
tOD2 Output buffer and pad
delay, slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF 1.3 1.8 2.3 ns
tOD3 Output buffer and pad
delay, slow slew rate = on
VCCIO = 2.5 V or 3.3 V
C1 = 35 pF 5.8 6.3 6.8 ns
tZX1 Output buffer enable delay,
slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF 4.0 4.0 5.0 ns
tZX2 Output buffer enable delay,
slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF 4.5 4.5 5.5 ns
tZX3 Output buffer enable delay,
slow slew rate = on
VCCIO = 2.5 V or 3.3 V
C1 = 35 pF 9.0 9.0 10.0 ns
tXZ Output buffer disable delay C1 = 5 pF 4.0 4.0 5.0 ns
tSU Register setup time 1.3 2.0 2.9 ns
tHRegister hold time 0.6 1.0 1.3 ns
tRD Register delay 0.7 1.2 1.6 ns
tCOMB Combinatorial delay 0.6 0.9 1.3 ns
tIC Array clock delay 1.2 1.9 2.5 ns
tEN Register enable time 0.6 1.0 1.2 ns
tGLOB Global control delay 1.0 1.5 2.2 ns
tPRE Register preset time 1.3 2.1 2.9 ns
tCLR Register clear time 1.3 2.1 2.9 ns
tPIA PIA delay (2) 1.0 1.7 2.3 ns
28 Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
tLPA Low–power adder (5) 3.5 4.0 5.0 ns
Table 17. EPM312 8A External Tim ing Parameters Note (1)
Symbo l Par a meter Conditions Speed Gra de Unit
–5–7–10
Min Max Min Max Min Max
tPD1 Input to non–
registered output C1 = 35 pF
(2) 5.0 7.5 10 ns
tPD2 I/O input to non–
registered output C1 = 35 pF
(2) 5.0 7.5 10 ns
tSU Global clock setup
time (2) 3.3 4.9 6.6 ns
tHGlobal clock hold time (2) 0.0 0.0 0.0 ns
tCO1 Global clock to output
delay C1 = 35 pF 1.0 3. 4 1.0 5.0 1.0 6.6 ns
tCH Global clock high time 2.0 3.0 4.0 ns
tCL Global clock low time 2.0 3.0 4.0 ns
tASU Array clock setup time (2) 1.8 2.8 3.8 ns
tAH Array clock hold time (2) 0.2 0.3 0.4 ns
tACO1 Array clock to output
delay C1 = 35 pF
(2) 1.0 4.9 1.0 7.1 1.0 9.4 ns
tACH Array clock high time 2.0 3.0 4.0 ns
tACL Array clock low time 2.0 3.0 4.0 ns
tCPPW Minimum pulse width
for clear and preset (3) 2.0 3.0 4.0 ns
tCNT Minimum global clock
period (2) 5.2 7.7 10.2 ns
fCNT Maximum internal
global clock frequency (2), (4) 192.3 129.9 98.0 MHz
tACNT Minimum array clock
period (2) 5.2 7.7 10.2 ns
fACNT Maximum internal
array clock frequency (2), (4) 192.3 129.9 98.0 MHz
Table 16. EPM3064A Internal Timing Parameters (Part 2 of 2) Note (1)
Symbol Parameter Conditions Speed Grade Unit
–4–7–10
Min Max Min Max Min Max
Altera Corporation 29
MAX 3000A Pr ogrammable Logic Device Famil y Data Sheet
Table 18. EPM3128A Internal Timing Parameters (Part 1 of 2) Note (1)
Symbol Par a m ete r Conditions Speed Gr ad e Unit
–5–7–10
Min Max Min Max Min Max
tIN Input pad and buffer delay 0.7 1.0 1.4 ns
tIO I/O input pad and buffer
delay 0.7 1.0 1.4 ns
tSEXP Shared expander delay 2.0 2.9 3.8 ns
tPEXP Parallel expander delay 0.4 0.7 0.9 ns
tLAD Logic array delay 1.6 2.4 3.1 ns
tLAC Logic control array delay 0.7 1.0 1.3 ns
tIOE Internal output enable delay 0.0 0.0 0.0 ns
tOD1 Output buffer and pad
delay, slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF 0.8 1.2 1.6 ns
tOD2 Output buffer and pad
delay, slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF 1.3 1.7 2.1 ns
tOD3 Output buffer and pad
delay, slow slew rate = on
VCCIO = 2.5 V or 3.3 V
C1 = 35 pF 5.8 6.2 6.6 ns
tZX1 Output buffer enable delay,
slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF 4.0 4.0 5.0 ns
tZX2 Output buffer enable delay,
slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF 4.5 4.5 5.5 ns
tZX3 Output buffer enable delay,
slow slew rate = on
VCCIO = 2.5 V or 3.3 V
C1 = 35 pF 9.0 9.0 10.0 ns
tXZ Output buffer disable delay C1 = 5 pF 4.0 4.0 5.0 ns
tSU Register setup time 1.4 2.1 2.9 ns
tHRegister hold time 0.6 1.0 1.3 ns
tRD Register delay 0.8 1.2 1.6 ns
tCOMB Combinat orial delay 0.5 0.9 1.3 ns
tIC Array clock delay 1.2 1.7 2.2 ns
tEN Register enable time 0.7 1.0 1.3 ns
tGLOB Global control delay 1.1 1.6 2.0 ns
tPRE Register preset time 1.4 2.0 2.7 ns
tCLR Register clear time 1.4 2.0 2.7 ns
30 Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
tPIA PIA delay (2) 1.4 2.0 2.6 ns
tLPA Low–power adder (5) 4.0 4.0 5.0 ns
Table 19. EPM325 6A External Tim ing Parameters Note (1)
Symbo l Par a meter Conditions Speed Gra de Unit
–5–7–10
Min Max Min Max Min Max
tPD1 Input to non–
registered output C1 = 35 pF
(2) 5.5 7.5 10 ns
tPD2 I/O input to non–
registered output C1 = 35 pF
(2) 5.5 7.5 10 ns
tSU Global clock setup
time (2) 3.9 5.2 6.9 ns
tHGlobal clock hold time (2) 0.0 0.0 0.0 ns
tCO1 Global clock to output
delay C1 = 35 pF 1.0 3. 5 1.0 4.8 1.0 6.4 ns
tCH Global clock high time 2.0 3.0 4.0 ns
tCL Global clock low time 2.0 3.0 4.0 ns
tASU Array clock setup time (2) 2.0 2.7 3.6 ns
tAH Array clock hold time (2) 0.2 0.3 0.5 ns
tACO1 Array clock to output
delay C1 = 35 pF
(2) 1.0 5.4 1.0 7.3 1.0 9.7 ns
tACH Array clock high time 2.0 3.0 4.0 ns
tACL Array clock low time 2.0 3.0 4.0 ns
tCPPW Minimum pulse width
for clear and preset (3) 2.0 3.0 4.0 ns
tCNT Minimum global clock
period (2) 5.8 7.9 10.5 ns
fCNT Maximum internal
global clock frequency (2), (4) 172.4 126.6 95.2 MHz
tACNT Minimum array clock
period (2) 5.8 7.9 10.5 ns
fACNT Maximum internal
array clock frequency (2), (4) 172.4 126.6 95.2 MHz
Table 18. EPM3128A Internal Timing Parameters (Part 2 of 2) Note (1)
Symbol Parameter Conditions Speed Grade Unit
–5–7–10
Min Max Min Max Min Max
Altera Corporation 31
MAX 3000A Pr ogrammable Logic Device Famil y Data Sheet
Table 20. EPM3256A Internal Timing Parameters (Part 1 of 2) Note (1)
Symbol Parameter Conditions Speed Grade Unit
–5–7–10
Min Max Min Max Min Max
tIN Input pad and buffer delay 0.7 0.9 1.2 ns
tIO I/O input pad and buffer
delay 0.7 0.9 1.2 ns
tSEXP Shared expander delay 2.1 2.8 3.7 ns
tPEXP Parallel expander delay 0.3 0.5 0.6 ns
tLAD Logic array delay 1.7 2.2 2.8 ns
tLAC Logic control array delay 0. 8 1.0 1.3 ns
tIOE Internal output enable delay 0.0 0.0 0.0 ns
tOD1 Output buffer and pad
delay, slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF 0.9 1.2 1.6 ns
tOD2 Output buffer and pad
delay, slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF 1.4 1.7 2.1 ns
tOD3 Output buffer and pad
delay, slow slew rate = on
VCCIO = 2.5 V or 3.3 V
C1 = 35 pF 5.9 6.2 6.6 ns
tZX1 Output buffer enable delay,
slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF 4.0 4.0 5.0 ns
tZX2 Output buffer enable delay,
slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF 4.5 4.5 5.5 ns
tZX3 Output buffer enable delay,
slow slew rate = on
VCCIO = 2.5 V or 3.3 V
C1 = 35 pF 9.0 9.0 10.0 ns
tXZ Output buffer disable delay C1 = 5 pF 4.0 4.0 5.0 ns
tSU Register setup time 1.5 2.1 2.9 ns
tHRegister hold time 0.7 0.9 1.2 ns
tRD Register delay 0.9 1.2 1.6 ns
tCOMB Combinatorial delay 0.5 0.8 1.2 ns
tIC Array clock delay 1.2 1.6 2.1 ns
tEN Register enable time 0.8 1.0 1.3 ns
tGLOB Global control delay 1.0 1.5 2.0 ns
tPRE Register preset time 1.6 2.3 3.0 ns
32 Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Notes to tables:
(1) These values are specified under the recommended operating conditions, as shown in Table 10 on page 19 .
(2) These values are specified for a PIA fan–out of one LAB (16 macrocells). For each additional LAB fan–out in the se
devices, add an additional 0.1 ns to the PIA timing value.
(3) This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA paramete r
must be adde d to th is minimum width if the cl ear or reset signal incorporates the tLAD parameter into the sign al
path.
(4) These parameters are meas ured with a 16–bit loadab le, enabled, up/down co un ter programmed int o each LAB.
(5) T he tLPA paramete r m ust be adde d to the tLAD, tLAC, tIC, tEN, tSEXP, tACL, a nd tCPPW pa rame te rs for m a c rocel ls
running in low–pow er m o d e .
Power
Consumption
Supply power (P) versus frequency (fMAX, in MHz) for MAX 3000A
devices is calcul ated wit h th e following equation:
P = PINT + PIO = ICCINT × VCC + PIO
The PIO value, which depends on the device output load characteristics
and switching frequency, can be calculated using the guidelines given in
Appli ca t io n No te 74 (E va lu at i ng Po w e r fo r A lt er a De v ice s ).
The ICCINT value depen ds on the switchi ng frequency and the appli cation
logic. The ICCINT value is calculated with the following equation:
ICCINT =
(A × MCTON) + [B × (MCDEV – MCTON)] + (C × MCUSED × fMAX × togLC)
The parameters in the ICCINT equation are:
tCLR Register clear time 1.6 2.3 3.0 ns
tPIA PIA delay (2) 1.7 2.4 3.2 ns
tLPA Low–power adder (5) 4.0 4.0 5.0 ns
Table 20. EPM3256A Internal Timing Parameters (Part 2 of 2) Note (1)
Symbol Parameter Conditions Speed Grade Unit
–5–7–10
Min Max Min Max Min Max
Altera Corporation 33
MAX 3000A Pr ogrammable Logic Device Famil y Data Sheet
MCTON = Number of macrocells with the Turbo BitTM option turned
on, as reported in the MAX+PLUS II Report File (.rpt)
MCDEV = Number of macrocells in the device
MCUSED = Total number of macrocells in the design, as reported in
the RPT File
fMAX = Highest clock frequency to the device
togLC = Average percentage of logic cells toggling at each clock
(typically 12 .5%)
A, B, C = Constants (shown in Table 21)
The ICCINT calculation provides an ICC estimate based on typical
conditions using a patte rn of a 16–bit, loadable, ena bl e d, up/down
counter in each LAB with no output load. Actual ICC should be verified
during operation because this measurement is sensitive to the actual
pattern in the device and the environmental operating conditions.
Tab le 21. MAX 3000A ICC Equati on Constants
Device A B C
EPM3032A 0.85 0.36 0.017
EPM3064A 0.85 0.36 0.017
EPM3128A 0.85 0.36 0.017
EPM3256A 0.85 0.36 0.017
34 Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Figures 12 and 13 show the typical supply current versus frequency for
MAX 3000A devices.
Figure 12. ICC vs. Frequency for MAX 3000A Devi ces
EPM3032A
VCC = 3.3 V
Room Temperature
Frequency (MHz)
60
80
120
140
VCC = 3.3 V
Room Temperature
0
Frequency (MHz)
High Speed
Non-Turbo
50 100 150200
222.2 MHz
125.0 MHz
250˚
050 100 150200 250
EPM3064A
20
100
40
30
40
60
70
High Speed
Non-Turbo
227.3 MHz
144.9 MHz
10
50
20
Typical I
Active (mA)
CC
Typical I
Active (mA)
CC
Altera Corporation 35
MAX 3000A Pr ogrammable Logic Device Famil y Data Sheet
Figure 13. ICC vs. Frequency for MAX 3000A Devices
EPM3128A
VCC = 3.3 V
Room Temperature
Frequency (MHz)
150
200
300
350
VCC = 3.3 V
Room Temperature
0
Frequency (MHz)
High Speed
Non-Turbo
50 100 150200
172.4 MHz
102.0 MHz
050 100 150200 250
EPM3256A
50
250
100
90
120
180
210
High Speed
Non-Turbo
192.3 MHz
108.7 MHz
30
150
60
Typical I
Active (mA)
CC
Typical I
Active (mA)
CC
36 Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Device
Pin–Outs
See the Altera web site (http://www.altera.com) or the Altera Digital
Library for pin–out information.
Figures 14 through 17 show the package pin–out diagrams for
MAX 3000A devices.
Figure 14. 44–Pin PLCC/TQF P Pack ag e Pin–Out Diagram
Package outlines not drawn to scale .
Figure 15. 100–Pin TQ FP Packa ge Pin–Out Diagram
Package outline not drawn to scale.
44-Pin PLCC
I/O
I/O
I/O
VCC
INPUT/OE2/GCLK2
INPUT/GCLRn
INPUT/OE1
INPUT/GCLK1
GND
I/O
I/O
I/O
I/O/TDO
I/O
GND
VCC
I/O
I/O
I/O/TCK
I/O
GND
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
6 5 4 3 2 1 44 43 42 41 40
18 19 20 21 22 23 24 25 26 27 28
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
EPM3032A
EPM3064A
I/O/TDI
I/O
I/O
GND
I/O
I/O
I/O/TMS
I/O
VCC
I/O
GND
44-Pin TQFP
Pin 12 Pin 23
Pin 34
Pin 1
I/O
I/O
I/O
VCC
INPUT/OE2/GCLK2
INPUT/GCLRn
INPUT/OE1
INPUT/GCLK1
GND
I/O
I/O
I/O
I/O/TDO
I/O
GND
VCC
I/O
I/O
I/O/TCK
I/O
GND
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O/TDI
I/O
I/O
GND
I/O
I/O
I/O/TMS
I/O
VCC
I/O
GND
EPM3032A
EPM3064A
Pin 1
Pin 26
Pin 76
Pin 51
EPM3064A
EPM3128A
Altera Corporation 37
MAX 3000A Pr ogrammable Logic Device Famil y Data Sheet
Figure 16. 144–Pin TQ FP Packa ge Pin–Out Diagram
Package outline not drawn to scale.
Figure 17. 208–Pin PQ FP Package Pin–Out Diagram
Package outline not drawn to scale.
Indicates location
of Pin 1
Pin 1 Pin 109
Pin 73
Pin 37
EPM3128A
EPM3256A
Pin 1 Pin 157
Pin 105Pin 53
EPM3256A
38 Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Altera Corporation 39
MAX 3000A Pr ogrammable Logic Device Famil y Data Sheet
Altera, BitBlaster, B yteBlasterMV, Jam, MasterBl aster, MAX, MAX+PLUS II, MultiVolt, Quartus, Tur bo Bit,
and spe cific device d esignations are trad emarks a nd/or service marks o f Altera Co rporation in the United
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applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to
current specifications in ac cordance w i th Altera’s standard warranty, but reserves the right to make changes
to any pr oduc ts and ser vices at a ny ti me wi thout not ice. A lter a assu mes no respons ibilit y or liabi lity a ris ing
out of the application or use of any information, product, or service described herein except as expressly
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®
MAX 3000A Pr ogrammable Logic Device Famil y Data Sheet
40 Alte ra Corporation
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