DataSheeT - enpirion(R) power solutions EP5388QI 800mA PowerSoC Step-Down DC-DC Switching Converter with Integrated Inductor DESCRIPTION FEATURES The EP5388QI is a synchronous buck converter with integrated Inductor, PWM controller, MOSFETS, and Compensation providing the smallest possible solution size. The EP5388QI requires only two small MLCC capacitors to make a complete solution. Integration of the inductor greatly simplifies design, contains noise, reduces part count, and reduces solution footprint. Low output ripple ensures compatibility with RF systems. The EP5388QI operates at a switching frequency of 4 MHz, enabling this unprecedented level of integration and small external components. Type III voltage mode control is used to provide high noise immunity and wide control loop bandwidth. The small footprint makes this part ideal for space constrained portable applications. Shutdown current of <1uA extends battery life Output voltage level is programmed via a 3-pin VID selector providing seven pre-programmed output voltages along with an option for external resistor divider. All Enpirion products are RoHS compliant and leadfree manufacturing environment compatible. * 3mm x 3mm x 1.1mm QFN package * Only two low cost MLCC caps required * 4 MHz switching frequency * High efficiency, up to 94% * Up to 800mA continuous output current * Wide 2.4V to 5.5V input range * VOUT Range: 0.6V to VIN - 0.5V * 3-Pin VID output voltage programming * 100% duty cycle capable * Less than 1 A standby current * Low VOUT ripple for RF compatibility * Short circuit and over current protection * UVLO and thermal protection * RoHS compliant; MSL 3 260C reflow APPLICATIONS * * * * * * Noise sensitive RF applications Area constrained applications Wireless data applications Portable gaming devices Personal Media Players Advanced Mobile Processors, DSP, IO, Memory, Video, Multimedia Engines VSense ENABLE VIN Vin EP5388QI 4.7F 0603 Voltage Select VFB VS0 VS1 VS2 VOUT Vout 47F 1206 GND Figure 2. Typical Application Schematic Figure 1. Integrated Inductor Technology Page 1 02377 January,18, 2019 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP5388QI ORDERING INFORMATION Part Number Package Markings TJ Rating Package Description EP5388QI ABXX -40C to +125C 16-pin (3mm x 3mm x 1.1mm) QFN EP5388QI-E QFN Evaluation Board Packing and Marking Information: www.intel.com/support/reliability/packing/rel-packing-and-marking.html NC(SW) 1 PGND NC(SW) NC(SW) PIN FUNCTIONS 2 13 ENABLE PGND 3 12 VS0 VFB 4 11 VS1 VSENSE 5 10 VS2 AGND 6 9 NC 7 8 VOUT VOUT 15 VIN 16 14 Figure 3. EP5388QI Pin Out Diagram (Top View) NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground or voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage. NOTE B: White `dot' on top left is pin 1 indicator on top of the device package. Page 2 02377 January,18, 2019 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP5388QI PIN DESCRIPTIONS PIN NAME TYPE FUNCTION 1, 15, 16 NC(SW) - NO CONNECT - These pins are internally connected to the common drain output of the internal MOSFETs. NC(SW) pins are not to be electrically connected to any external signal, ground, or voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage. 2, 3 PGND Ground Power Ground 4 VFB Analog Feedback pin for external divider option. When using the external divider option (VS0=VS1=VS2= high) connect this pin to the center of the external divider. Set the divider such that VFB = 0.6V. The "ground" side of the external divider should be connected to AGND. This pin may be left unconnected when using Voltage Select pins (VS0-VS2) to set the output voltage. 5 VSENSE Analog Sense pin for output voltage regulation. Refer to application section for proper configuration. 6 AGND Ground Analog ground. This is the quiet ground for the internal control circuitry 7, 8 VOUT Power Regulated Output Voltage. Refer to application section for proper layout and decoupling. 9 NC Analog NO CONNECT - This pin should not be electrically connected to any external signal, voltage, or ground. This pin may be connected internally. However, this pin must be soldered to the PCB. 10, 11, 12 VS0,VS1,VS2 Analog Output voltage select. VS2=pin10 VS1=pin11, VS0=pin12. Selects one of seven preset output voltages or choose external divider by connecting pins to logic high or low. Refer to section on output voltage select for more detail. 13 ENABLE Analog Output enable. Enable = logic high, disable = logic low. 14 VIN Power Input voltage pin. Refer to application section for proper layout and decoupling. Page 3 02377 January,18, 2019 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP5388QI ABSOLUTE MAXIMUM RATINGS CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating conditions is not implied. Stress beyond the absolute maximum ratings may impair device life. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Absolute Maximum Pin Ratings PARAMETER SYMBOL MIN MAX UNITS VIN -0.3 7.0 V ENABLE, VSENSE, VSO - VS2 -0.3 VIN+0.3 V VFB -0.3 2.7 V MIN MAX UNITS -65 +150 C +260 C MAX UNITS Input Supply Voltage Absolute Maximum Thermal Ratings PARAMETER CONDITION Storage Temperature Range Reflow Peak Body Temperature (10 Sec) MSL3 JEDEC J-STD-020A Absolute Maximum ESD Ratings PARAMETER CONDITION MIN HBM (Human Body Model) 2000 V RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL MIN MAX UNITS VIN 2.4 5.5 V VOUT 0.603 VIN- 0.5 V Operating Ambient Temperature Range TA -40 +85 C Operating Junction Temperature TJ -40 +125 C Input Voltage Range Output Voltage Range THERMAL CHARACTERISTICS PARAMETER Thermal Resistance: Junction to Ambient -0 LFM (1) Thermal Overload Trip Point Thermal Overload Trip Point Hysteresis SYMBOL TYPICAL UNITS JA 100 C/W TJ-TP +150 C 15 C (1) Based on 2oz. external copper layers and proper thermal design in line with EIJ/JEDEC JESD51-7 standard for high thermal conductivity boards. Page 4 02377 January,18, 2019 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP5388QI ELECTRICAL CHARACTERISTICS NOTE: TA = -40C to +85C unless otherwise noted. Typical values are at TA = 25C, VIN = 3.6V CIN = 4.7F 0603 MLCC, COUT = 47F 0805 MLCC PARAMETER SYMBOL TEST CONDITIONS MIN VOUT Initial Accuracy (VID Preset Mode) VOUT_initl TA = 25C, 2.4V VIN 5.5V -2% Line Regulation VOUT_linel 2.4V VIN 5.5V 0.0566 %/V Load Regulation VOUT_load 0A ILOAD 800mA 0.0003 %/mA Temperature Variation VOUT_templ -40C TA +85C 0.0078 %/C Overall VOUT Accuracy TYP MAX UNITS +2% 2.4V VIN 5.5V (Line, Load, and Temperature combined) VOUT_All Dropout Resistance RDROPOUT -40C TA +85C -3% +3% 0A ILOAD 800mA Dynamic Voltage Slew Rate Vslew Continuous Output Current IOUT Shut-Down Current ISD PFET OCP Threshold 0.975 -20C TA +85C 800 -40C TA +85C 750 400 500 m 1.5 2.025 V/ms mA 0.75 A ILIM 1000 mA Feedback Pin Voltage VFB 0.603 V Feedback Pin Input Current IFB VS0-VS1, Enable Voltage Threshold VTH VS0-VS2 Pin Input Current IVSX 1 nA Operating Frequency FOSC 4 MHz PFET On Resistance RDS(ON) 340 m NFET On Resistance RDS(ON) 270 m Soft-Start Slew Rate VSS VID programming mode 0.975 1.5 2.025 V/ms VOUT Rise Time TSS VFB programming mode 0.784 1.2 1.628 ms Enable = Low 100 Pin = Low 0.0 0.4 Pin = High 1.4 VIN nA (2) VDO = IOUT x RDO Page 5 02377 January,18, 2019 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP5388QI 95 95 90 90 85 85 80 80 Efficiency (%) Efficiency (%) TYPICAL PERFORMANCE CURVES 75 70 75 70 65 65 60 60 55 55 50 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 50 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 Load Current (A) Load Current (A) Efficiency Versus Load; VIN = 3.3V, VOUT (from top to bottom) 2.5V, 1.8V, 1.5V, 1.2V Efficiency Versus Load; VIN = 3.7V, VOUT (from top to bottom) 2.5V, 1.8V, 1.5V, 1.2V 95 90 85 Efficiency (%) 80 75 70 65 60 55 50 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 Load Current (A) Efficiency Versus Load; VIN = 5V, VOUT (from top to bottom) 3.3V, 2.5V, 1.8V, 1.5V, 1.2V Page 6 02377 January,18, 2019 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP5388QI TYPICAL PERFORMANCE CHARACTERISTICS Output Ripple, VIN = 5.0V, VOUT = 2.5V, Load = 500mA Output Ripple, VIN = 5.0V, VOUT = 1.8V, Load = 500mA Output Ripple, VIN = 5.0V, VOUT = 3.3V, Load = 500mA Output Ripple, VIN = 3.3V, VOUT = 1.2V, Load = 500mA Output Ripple, VIN = 3.3V, VOUT = 1.8V, Load = 500mA Output Ripple, VIN = 3.3V, VOUT = 2.5V, Load = 500mA Page 7 02377 January,18, 2019 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP5388QI TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED) Transient, VIN = 5.0V, VOUT = 1.2V, Load = 0-800mA Transient, VIN = 5.0V, VOUT = 3.3V, Load = 0-800mA Transient, VIN = 3.3V, VOUT = 1.2V, Load = 0-800mA Transient, VIN = 3.3V, VOUT = 1.8V, Load = 0-800mA Startup, VIN = 3.6V, VOUT = 1.5V, Load = 500mA. Shutdown, VIN = 3.6V, VOUT = 1.5V, Load = 500mA. Enable in light blue; Vout in Dark blue. Enable in light blue; Vout in Dark blue. Page 8 02377 January,18, 2019 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP5388QI FUNCTIONAL BLOCK DIAGRAM VIN UVLO Thermal Limit Current Limit ENABLE NC(SW) Soft Start P-Drive (-) Logic VOUT PWM Comp (+) N-Drive GND VSENSE Sawtooth Generator Compensation Network (-) Switch Error Amp VFB (+) DAC VREF Voltage Select Package Boundry VS0 VS1 VS2 Figure 4: Functional Block Diagram Page 9 02377 January,18, 2019 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP5388QI FUNCTIONAL DESCRIPTION Synchronous DC-DC Step-Down PowerSoC The EP5388QI is a complete DC-DC converter solution requiring only two low cost MLCC capacitors. MOSFET switches, PWM controller, Gate-drive, compensation, and inductor are integrated into the tiny 3mm x 3mm x 1.1mm package to provide the smallest footprint possible while maintaining high efficiency, low ripple, and high performance. The converter uses voltage mode control to provide the simplest implementation and high noise immunity. The device operates at a 4MHz switching frequency. The high switching frequency allows for a wide control loop bandwidth providing excellent transient performance. The high switching frequency further enables the use of very small components making possible this unprecedented level of integration. Intel Enprion's proprietary power MOSFET technology provides very low switching loss at frequencies of 4 MHz and higher, allowing for the use of very small internal components, and high performance. Integration of the magnetics virtually eliminates the design/layout issues normally associated with switch-mode DC-DC converters. All of this enables much easier and faster incorporation into various applications to meet demanding EMI requirements. Output voltage is chosen from seven preset values via a three pin VID voltage select scheme. An external divider option enables the selection of any voltage in VIN to 0.6V range. This reduces the number of components that must be qualified and reduces inventory burden. The VID pins can be toggled on the fly to implement glitch free dynamic voltage scaling. Protection features include under-voltage lock-out (UVLO), over-current protection (OCP), short circuit protection, and thermal overload protection. Integrated Inductor Intel Enpirion has introduced the world's first product family featuring integrated inductors. The EP5388QI utilizes a proprietary low loss integrated inductor. The use of an internal inductor localizes the noises associated with the output loop currents. The inherent shielding and compact construction of the integrated inductor reduces the radiated noise that couples into the traces of the circuit board. Further, the package layout is optimized to reduce the electrical path length for the AC ripple currents that are a major source of radiated emissions from DC-DC converters. The integrated inductor significantly reduces parasitic effects that can harm loop stability, and makes layout very simple. Stable Over Wide Range of Operating Conditions The EP5388QI utilizes an internal type III compensation network and is designed to provide a high degree of stability over a wide range of operating conditions. The device operates over the entire input and output voltage range with no external modifications required. The very high switching frequency allows for a very wide control loop bandwidth. Soft Start Internal soft start circuits limit in-rush current when the device starts up from a power down condition or when the "ENABLE" pin is asserted "high". Digital control circuitry limits the VOUT ramp rate to levels that are safe for the Power MOSFETS and the integrated inductor. The EP5388QI has two soft start operating modes. When VOUT is programmed using a preset voltage in VID mode, the device has a constant slew rate. When the EP5388QI is configured in external resistor divider mode, the device has a constant VOUT ramp time. Output voltage slew rate and ramp time is given in the Electrical Characteristics Table. Page 10 02377 January,18, 2019 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP5388QI Excess bulk capacitance on the output of the device can cause an over-current condition at startup. Maximum allowable output capacitance depends on the device's minimum current limit, the output current at startup, the minimum soft-start time and the output voltage (all are listed in the Electrical Characteristics Table). The total maximum capacitance on the output rail is estimated by the equation below: COUT_MAX = 0.7 * (ILIMIT - IOUT) * tSS / VOUT COUT_MAX = maximum allowable output capacitance ILIMIT = minimum current limit = 0.8A IOUT = output current at startup VOUT = output voltage 0.7 = margin factor tSS(VFB) = min soft-start time = 0.784ms External feedback setting tSS(VID) = VOUT [V] / 2.025 [V/ms] VID setting The soft-start time in VID setting is different than External Feedback (VFB) setting, so be sure to use the correct value when calculating the maximum allowable output capacitance. NOTE: Do not use excessive output capacitance since it may affect device stability. The EP5388QI has high loop bandwidth and 80F is all that is needed for transient response optimization. Over Current/Short Circuit Protection The current limit function is achieved by sensing the current flowing through a sense P-MOSFET which is compared to a reference current. When this level is exceeded the P-FET is turned off and the N-FET is turned on, pulling VOUT low. This condition is maintained for a period of 1ms and then a normal soft start is initiated. If the over current condition still persists, this cycle will repeat in a "hiccup" mode. Under Voltage Lockout During initial power up an under voltage lockout circuit will hold-off the switching circuitry until the input voltage reaches a sufficient level to insure proper operation. If the voltage drops below the UVLO threshold the lockout circuitry will again disable the switching. Hysteresis is included to prevent chattering between states. Enable The ENABLE pin provides a means to shut down the converter or enable normal operation. A logic low will disable the converter and cause it to shut down. A logic high will enable the converter into normal operation. In shutdown mode, the device quiescent current will be less than 1A. At extremely cold conditions below 30C, the controller may not be properly powered if ENABLE is tied directly to AVIN during startup. It is recommended to use an external RC circuit to delay the ENABLE voltage rise so that the internal controller has time to startup into regulation (see circuit below). The RC circuit may be adjusted so that AVIN and PVIN are above UVLO before ENABLE is high. The startup time will be delayed by the extra time it takes for the capacitor voltage to reach the ENABLE threshold. Page 11 02377 January,18, 2019 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP5388QI Figure 5. ENABLE Delay Circuit NOTE: This pin must not be left floating Thermal Shutdown When excessive power is dissipated in the chip, the junction temperature rises. Once the junction temperature exceeds the thermal shutdown temperature the thermal shutdown circuit turns off the converter output voltage thus allowing the device to cool. When the junction temperature decreases to a safe operating level, the device will go through the normal startup process. The specific thermal shutdown junction temperature and hysteresis values can be found in the thermal characteristics table. Page 12 02377 January,18, 2019 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP5388QI APPLICATION INFORMATION Output Voltage Programming To provide the highest degree of flexibility in choosing output voltage, the EP5388QI uses a 3 pin VID, or Voltage ID, output voltage select arrangement. This allows the designer to choose one of seven preset voltages, or to use an external voltage divider. Internally, the output of the VID multiplexer sets the value for the voltage reference DAC, which in turn is connected to the non-inverting input of the error amplifier. This allows the use of a single feedback divider with constant loop gain and optimum compensation, independent of the output voltage selected. shows the various VS0-VS2 pin logic states and the associated output voltage levels. A logic "1" indicates a connection to VIN or to a "high" logic voltage level. A logic "0" indicates a connection to ground or to a "low" logic voltage level. These pins can be either hardwired to VIN or GND or alternatively can be driven by standard logic levels. Logic low is defined as VLOW 0.4V. Logic high is defined as VHIGH 1.4V. Any level between these two values is indeterminate. These pins must not be left floating. Table 1: VID Voltage Select Settings VS2 VS1 VS0 VOUT 0 0 0 3.3V 0 0 1 2.5V 0 1 0 1.8V 0 1 1 1.5V 1 0 0 1.25V 1 0 1 1.2V 1 1 0 0.8V 1 1 1 User Selectable External Voltage Divider As described above, the external voltage divider option is chosen by connecting the VS0, VS1, and VS2 pins to VIN or logic "high". The EP5388QI uses a separate feedback pin, VFB, when using the external divider. VSENSE must be connected to VOUT as indicated in Figure 6. VIN VSense ENABLE Vin 4.7F 0603 EP5388QI VS0 VS1 VS2 VOUT Vout Ra VFB 47F 1206 Rb GND Figure 6. External Divider Application Circuit Page 13 02377 January,18, 2019 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP5388QI The output voltage is selected by the following formula: VOUT = 0.603V (1 + Ra Rb ) Ra must be chosen as 200k to maintain loop gain. Then Rb is given as: Rb = 1.206 x10 5 VOUT - 0.603 VOUT can be programmed over the range of 0.6V to VIN-0.5V. Dynamically Adjustable Output The EP5388QI is designed to allow for dynamic switching between the predefined VID voltage levels. The inter-voltage slew rate is optimized to prevent excess undershoot or overshoot as the output voltage levels transition. The slew rate is identical to the soft-start slew rate of 1.5V/mS. Dynamic transitioning between internal VID settings and the external divider is not allowed. Input and Output Capacitors The input capacitance requirement is 4.7F 0603 MLCC. Intel Enpirion recommends that a low ESR MLCC capacitor be used. The input capacitor must use a X5R or X7R or equivalent dielectric formulation. Y5V or equivalent dielectric formulations lose capacitance with frequency, bias, and with temperature, and are not suitable for switch-mode DC-DC converter input filter applications. A variety of output capacitor configurations are possible depending on footprint and ripple requirements. For applications where VIN range is up to 5.5V, it is recommended to use a single 47F 1206 MLCC capacitor. Ripple performance can be improved by using 2 x 22F 0805 MLCC capacitors. A single 10F 0805 MLCC can be used if VOUT programming is accomplished using an external divider, with the addition of a 10pF phase lead capacitor as shown in Figure 7. Note that in this configuration, VSENSE should NOT be connected to VOUT. This modification is necessary to ensure proper operation of the compensation network over the range of operating conditions. As described in the Soft Start section, there is a limitation on the maximum bulk capacitance that can be placed on the output of this device. Please refer to the section on Soft Start for more details. The output capacitor must use a X5R or X7R or equivalent dielectric formulation. Y5V or equivalent dielectric formulations lose capacitance with frequency, bias, and temperature and are not suitable for switch-mode DCDC converter output filter applications. VIN VSense ENABLE Vin 4.7F 0603 EP5388QI VS0 VS1 VS2 X VOUT Vout 10F 0805 Ra VFB Rb 10pF GND Figure 7. Applications circuit for COUT = 1 x 10F 0805 Page 14 02377 January,18, 2019 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP5388QI Power-Up/Down Sequencing During power-up, ENABLE should not be asserted before VIN. During power down, the VIN should not be powered down before the ENABLE. Tying PVIN and ENABLE together during power-up or power-down meets this requirement. Pre-Bias Start-up The EP5388QI does not support startup into a pre-biased condition. Be sure the output capacitors are not charged or the output of the EP5388QI is not pre-biased when the EP5388QI is first enabled. Page 15 02377 January,18, 2019 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP5388QI LAYOUT RECOMMENDATIONS Figure 8 shows critical components and layer 1 traces of a recommended minimum footprint EP5388QI layout. ENABLE configurations and other small signal pins need to be connected and routed according to specific customer application. Please see the Gerber files on the Intel website www.Intel.com/enpirion for exact dimensions and other layers. Please refer to Figure 8 while reading the layout recommendations in this section. Figure 8: PCB Layer Critical Components and Copper for Minimum Footprint Recommendation 1: The input and output filter capacitors should be placed as close to the EP5388QI as possible to reduce EMI from input and output loop AC currents. This reduces the physical area of these AC current loops. Recommendation 2: The system ground plane should be the first layer immediately below the surface layer (PCB layer 2). If it is not possible to make PCB layer 2 the system ground plane, a local ground island should be created on PCB layer 2 under the Altera Enpirion device and including the area under the input and output filter capacitors. This ground plane, or ground island, should be continuous and uninterrupted underneath the Altera Enpirion device and the input and output filter capacitors. Recommendation 3: The surface layer ground pour should include a "slit" as shown in Figure 8 to separate the input and output AC loop currents. This will help reduce noise coupling from the input current loop to the output current loop. Recommendation 4: Multiple small vias (approximately 0.25mm finished diameter) should be used to connect the ground terminals of the input and output capacitors, and the surface ground pour under the device, to the system ground plane. If a local ground island is used on PCB layer 2, the vias should connect to the ground island and continue down to the PCB system ground plane. Recommendation 5: The AGND pin should be connected to the system ground plane using a via as described in recommendation 4. AGND must NOT be connected to the surface layer ground pour. Recommendation 6: As with any switch-mode DC-DC converter, do not run any sensitive signal or control lines under the converter package. Page 16 02377 January,18, 2019 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP5388QI RECOMMENDED PCB FOOTPRIN Figure 9: EP5388QI PCB Footprint (Top View) Page 17 02377 January,18, 2019 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP5388QI PACKAGE DIMENSIONS Figure 10: EP5388QI Package Dimensions Packing and Marking Information: https://www.intel.com/support/quality-and-reliability/packing.html Page 18 02377 January,18, 2019 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP5388QI REVISION HISTORY Rev Date Change(s) F June, 2017 Max Bulk Cap (COUT_MAX) equation updated to reflect loading and startup time (with margin added) G Dec, 2017 Revision History added H Dec, 2018 Changed datasheet into Intel format. WHERE TO GET MORE INFORMATION For more information about Intel(R) and Enpirion(R) PowerSoCs, visit: www.intel.com/enpirion (c) 2017 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS, and STRATIX words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Other marks and brands may be claimed as the property of others. Intel reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. * Other marks and brands may be claimed as the property of others. Page 19 02377 January,18, 2019 Rev H