IDT74ALVCH162373PAG8 - Integrated Device Technology

November 2001

Revised November 2001

74ALVCH162373 Low Voltage 16-Bit Transparent Latch with Bushold and 26

Ω

Series Resistors in Outputs

74ALVCH162373

Low Voltage 16-Bit Transparent Latch with Bushold

and 26Ω Series Resistors in Outputs

General Description

The ALVCH162373 contains sixteen non-inverting latches

with 3-STATE outputs and is intended for bus oriented

applications. The device is byte controlled. The flip-flops

appear to be transparent to the data when the Latch enable

(LE) is HIGH. When LE is LOW, the data that meets the

setup time is latched. Data appears on the bus when the

Output Enable (OE) is LOW. When OE is HIGH, the out-

puts are in a high impedance state.

The ALVCH1623 73 data in puts include act ive bushold c ir-

cuitry, eliminating the need for external pull-up resistors to

hold unused or floating data inputs at a valid logic level.

The ALVCH162373 is a lso d esi gn ed w it h 26 Ω series re sis-

tors in the outputs. This d esign reduces line noise in ap pli-

cations such as memory address driver, clock drivers and

bus transceivers /tra nsm itter s.

The 74ALVCH162373 is designed for low voltage (1.65V to

3.6V) VCC applications with output compatibility up to 3.6V.

The 74ALVCH162373 is fabricated with an advanced

CMOS technology to achieve high speed operation while

maintaining low CMOS power dissipation.

Features

■1.65V to 3.6V VCC supply operation

■3.6V tolerant control inputs and outputs

■Bushold on data inputs eliminates the need for external

pull-up/pull-down resistors

■26Ω series resistors in outputs

■tPD (In to On)

3.8 ns max for 3.0V to 3.6V VCC

5.0 ns max for 2.3V to 2.7V VCC

9.0 ns max for 1.65V to 1.95V VCC

■Uses patente d noise /E MI reducti o n circuitr y

■Latchup conforms to JEDEC JED78

■ESD performa nce :

Human body model > 2000V

Machine model > 200V

Ordering Code:

Devices also available in Tape and Reel. Speci fy by appe nding the s uffix let t er “X” to the o rdering code.

Logic Symbol Pin Descriptions

Ordering Number Package Number Package Description

74ALVCH162373T MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Pin Names Description

OEnOutput Enable Input (Active LOW)

LEnLatc h Enab le Input

I0–I15 Bushold Inputs

O0–O15 Outputs

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74ALVCH162373

Connection Diagram Truth Tables

H = HIGH Voltage Level

L = LO W Voltage Level

X = Immaterial (HIGH or LOW, control inputs may not float)

Z = High Impedance

O0 = Previous O0 before HIGH-t o-LOW of Lat c h Enable

Functional Description

The 74ALVCH162373 contains sixteen edge D-type

latches with 3-ST ATE outputs. The device is byte controlled

with each byte functioning identically, but independent of

the other . Control pins can be shorted together to obtain full

16-bit operation. The following description applies to each

byte. W hen the Lat ch Enable (LE n) input is HIGH, data o n

the In enters the latches. In this condition the latches are

transpa rent, i.e ., a latc h output will chang e state ea ch tim e

its I input changes. When LEn is LOW, the latches store

information that was present on the I inputs a setup time

preceding the HIGH-to-LOW transition on LEn. The 3-

STATE outputs are controlled by the Output Enable (OEn)

input. When OEn is LOW the standard outputs are in the 2-

state mode . When OEn is HIGH, the standard outp uts are

in the high impedance mode but this does not interfere with

entering new data into the latches.

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Inputs Outputs

LE1OE1I0–I7O0–O7

XHXZ

HLLL

HLHH

LLXO

Inputs Outputs

LE2OE2I8–I15 O8–O15

XHXZ

HLLL

HLHH

LLXO

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74ALVCH162373

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions (Note 3)

Note 1: The Absolute Maximum Ratings are those values beyond which

the saf ety of the device cannot be gu aranteed. Th e device shou ld not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the Absolute Maximum Rat-

ings. The “Recommended Operating Conditions” table will define the condi-

tio ns f or actu al dev ice operation.

Note 2: IO Absolute Maximum Rating must be observed, limited to 4.6V.

Note 3: Floating or unused control inputs must be held HIGH or LOW.

DC Electrical Characteristics

Supply Voltage (VCC)−0.5V to +4.6V

DC Input Voltage (VI)−0.5V to 4.6V

Output Voltage (VO) (Note 2) −0.5V to VCC +0.5V

DC Input Diode Current (IIK)

VI < 0V −50 mA

DC Output Diode Current (IOK)

VO < 0V −50 mA

DC Output Source/Sink Current

(IOH/IOL)±50 mA

DC VCC or GND Current per

Supply Pin (ICC or GND) ±100 mA

Stora ge Temperatu re R ang e (TSTG)−65°C to +150°C

Power Supply

Operating 1.65V to 3.6V

Input Voltage (VI)0V to V

Output Voltage (VO)0V to V

Free Air Operating Temperature (TA)−40°C to +85°C

Minimum Input Edge Rate (∆t/∆V)

VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V

Symbol Parameter Conditions VCC Min Max Units

(V)

VIH HIGH Level Input Voltage 1.65 - 1.95 0.65 x VCC V2.3 - 2.7 1.7

2.7 - 3.6 2.0

VIL LOW Level Input Voltage 1.65 - 1.95 0.35 x VCC V2.3 - 2.7 0.7

2.7 - 3.6 0 .8

VOH HIGH Level Output Voltage IOH = −100 µA 1.65 - 3.6 VCC - 0.2

IOH = −2 mA 1.65 1.2

IOH = −4 mA 2.3 1.9

IOH = −6 mA 2.3 1.7

3.0 2.4

IOH = −8 mA 2.7 2

IOH = −12 mA 3.0 2

VOL LOW Level Output Voltage IOL = 100 µA 1.65 - 3.6 0.2

IOL = 2 mA 1.65 0.45

IOL = 4 mA 2.3 0.4

IOL = 6 mA 2.3 0.55

3.0 0.55

IOL = 8 mA 2.7 0.6

IOL = 12 mA 3 0.8

IIInput Leakage Current 0 ≤ VI ≤ 3.6V 3.6 ±5.0 µA

II(HOLD) Bushold Input Minimum VIN = 0.58V 1.65 25

µA

Drive Hold Current VIN = 1.07V 1.65 −25

VIN = 0.7V 2.3 45

VIN = 1.7V 2.3 −45

VIN = 0.8V 3.0 75

VIN = 2.0V 3.0 −75

0 < VO ≤ 3.6V 3 .6 ±500

IOZ 3-STATE Output Leakage 0 ≤ VO ≤ 3.6V 3.6 ±10 µA

ICC Quiescent Supply Current VI = VCC or GND, IO = 0 3.6 40 µA

∆ICC Increase in ICC per Input VIH = VCC − 0.6V 3 - 3.6 750 µA

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74ALVCH162373

AC Electrical Characteristics

Capacitance

Symbol Parameter

TA = −40°C to +85°C, RL = 500Ω

Units

CL = 50 pF CL = 30 pF

VCC = 3.3V ± 0.3V VCC = 2.7V VCC = 2.5V ± 0.2V VCC = 1.8V ± 0.15V

Min Max Min Max Min Max Min Max

tPHL, tPLH Propagation Delay 1.3 3.8 1.5 5.0 1.0 4.5 1.5 9.0 ns

Bus to Bus

tPHL, tPLH Propagation Delay 1.3 4.1 1.5 5.4 1.0 4.9 1.5 9.8 ns

LE to Bus

tPZL, tPZH Output Enable Time 1.3 4.4 1.5 5.9 1.0 5.4 1.5 9.8 ns

tPLZ, tPHZ Output Disable Time 1.3 4.5 1.5 4.9 1.0 4.4 1.5 7.9 ns

tWPulse Width 1.5 1.5 1.5 4.0 ns

tSSetup Time 1.5 1.5 1.5 2.5 ns

tHHold Time 1.0 1.0 1.0 1.0 ns

Symbol Parameter Conditions TA = +25°CUnits

VCC Typical

CIN Input Capacitance VI = 0V or VCC 3.3 6 pF

COUT Output Capacitance VI = 0V or VCC 3.3 7 pF

CPD Power Dissipation Capacitance Outputs Enabled f = 10 MHz, CL = 50 pF 3.3 20 pF

2.5 20

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74ALVCH162373

AC Loading and Waveforms

FIGURE 1. AC Test Circuit

TABLE 1. Values for Figure 1

TABLE 2. Variable Matrix

(Input Characteristics: f = 1MHz; tr = tf = 2ns; Z0 = 50Ω)

FIGURE 2. Waveform for Inverting and

Non-Inverting Functions FIGURE 3. 3-STATE Output HIGH Enable and

Disable Times for Low Voltage Logic

FIGURE 4. 3-STATE Output LOW Enable and Disable Times for Low Voltage Logic

FIGURE 5. Propagation Delay, Pulse Width and

tREC Waveforms FIGURE 6. Setup Time, Hold Time and

Recovery Time for Low Voltage Logic

TEST SWITCH

tPLH, tPHL Open

tPZL, tPLZ VL

tPZH, tPHZ GND

Symbol VCC

3.3V ± 0.3V 2.7V 2.5V ± 0.2V 1.8 V ± 0.15V

Vmi 1.5V 1.5V VCC/2 VCC/2

Vmo 1.5V 1.5V VCC/2 VCC/2

VXVOL + 0.3V VOL + 0.3V VOL + 0.15V VOL + 0.1 5V

VYVOH − 0.3V VOH − 0.3 V VOH − 0.15V VOH − 0.15V

VL6V 6V VCC*2 VCC*2

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74ALVCH162373 Low Voltage 16-Bit Transparent Latch with Bushold and 26

Ω

Series Resistors in O utputs

Physical Dimensions inches (millimeters) unless otherwise noted

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Package Number MTD48

Fairchild does not assu me any responsibility for use of any circuitry de scribed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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