© 2001 Fairchild Semiconductor Corporation DS500708 www.fairchildsemi.com
November 2001
Revised November 2001
74ALVCH162373 Low Voltage 16-Bit Transparent Latch with Bushold and 26
Ω
Series Resistors in Outputs
74ALVCH162373
Low Voltage 16-Bit Transparent Latch with Bushold
and 26Ω Series Resistors in Outputs
General Description
The ALVCH162373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear to be transparent to the data when the Latch enable
(LE) is HIGH. When LE is LOW, the data that meets the
setup time is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the out-
puts are in a high impedance state.
The ALVCH1623 73 data in puts include act ive bushold c ir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
The ALVCH162373 is a lso d esi gn ed w it h 26 Ω series re sis-
tors in the outputs. This d esign reduces line noise in ap pli-
cations such as memory address driver, clock drivers and
bus transceivers /tra nsm itter s.
The 74ALVCH162373 is designed for low voltage (1.65V to
3.6V) VCC applications with output compatibility up to 3.6V.
The 74ALVCH162373 is fabricated with an advanced
CMOS technology to achieve high speed operation while
maintaining low CMOS power dissipation.
Features
■1.65V to 3.6V VCC supply operation
■3.6V tolerant control inputs and outputs
■Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
■26Ω series resistors in outputs
■tPD (In to On)
3.8 ns max for 3.0V to 3.6V VCC
5.0 ns max for 2.3V to 2.7V VCC
9.0 ns max for 1.65V to 1.95V VCC
■Uses patente d noise /E MI reducti o n circuitr y
■Latchup conforms to JEDEC JED78
■ESD performa nce :
Human body model > 2000V
Machine model > 200V
Ordering Code:
Devices also available in Tape and Reel. Speci fy by appe nding the s uffix let t er “X” to the o rdering code.
Logic Symbol Pin Descriptions
Ordering Number Package Number Package Description
74ALVCH162373T MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
OEnOutput Enable Input (Active LOW)
LEnLatc h Enab le Input
I0–I15 Bushold Inputs
O0–O15 Outputs