© Semiconductor Components Industries, LLC, 2011
May, 2011 Rev. 15
1Publication Order Number:
CAT24C01/D
CAT24C01, CAT24C02,
CAT24C04, CAT24C08,
CAT24C16
1-Kb, 2-Kb, 4-Kb, 8-Kb and
16-Kb I2C CMOS Serial
EEPROM
Description
The CAT24C01/02/04/08/16 are 1Kb, 2Kb, 4Kb, 8Kb and
16Kb respectively CMOS Serial EEPROM devices organized
internally as 8/16/32/64 and 128 pages respectively of 16 bytes each.
All devices support both the Standard (100 kHz) as well as Fast
(400 kHz) I2C protocol.
Data is written by providing a starting address, then loading 1 to 16
contiguous bytes into a Page Write Buffer, and then writing all data to
nonvolatile memory in one internal write cycle. Data is read by
providing a starting address and then shifting out data serially while
automatically incrementing the internal address count.
External address pins make it possible to address up to eight
CAT24C01 or CAT24C02, four CAT24C04, two CAT24C08 and one
CAT24C16 device on the same bus.
Features
Supports Standard and Fast I2C Protocol
1.7 V to 5.5 V Supply Voltage Range
16Byte Page Write Buffer
Hardware Write Protection for Entire Memory
Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs
(SCL and SDA)
Low power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Extended Temperature Range
These Devices are PbFree, Halogen Free/BFR Free and are RoHS
Compliant
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.
ORDERING INFORMATION
SOIC8
W SUFFIX
CASE 751BD
TSOT23
TD SUFFIX
CASE 419AE
PDIP8
L SUFFIX
CASE 646AA
TSSOP8
Y SUFFIX
CASE 948AL
MSOP8
Z SUFFIX
CASE 846AD
TDFN8
VP2 SUFFIX
CASE 511AK
VCC
WP
SDA
VSS
SCL 1
2
3
5
4
TSOT23 (TD) (Top View)
PIN CONFIGURATIONS
SDA
SCL
WP
VCC
VSS
1
2
3
4
8
7
6
5
PDIP (L), SOIC (W), TSSOP (Y), MSOP (Z),
TDFN, (VP2), UDFNEP (HU4) (Top View)
CAT24C__
16 / 08 / 04 / 02 / 01
NC ////
NC NC
NC NC
NC
A0A0
A1A1A1
A2A2A2
A2
////
////
UDFN8EP
HU4 SUFFIX
CASE 517AZ
WLCSP4*
C4A SUFFIX
CASE 567DC
WLCSP5*
C5A SUFFIX
CASE 567DD
WLCSP4*
(Bottom View)
WLCSP5*
(Bottom View)
A = WP
B = SCL
C = SDA
D = VCC
E = VSS
B
A
C
DE
BC
DE
* WLCSP are available upon request for the
CAT24C04, CAT24C08 and CAT24C16 only. For
availability, please contact factory.
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
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2
SCL
WP
CAT24Cxx
Figure 1. Functional Symbol
VSS
SDA
VCC
A2, A1, A0
Table 1. PIN FUNCTION
Pin Name Function
A0, A1, A2 Device Address Input
SDA Serial Data Input/Output
SCL Serial Clock Input
WP Write Protect Input
VCC Power Supply
VSS Ground
NC No Connect
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters Ratings Units
Storage Temperature 65 to +150 °C
Voltage on any pin with respect to Ground (Note 1) 0.5 to +6.5 V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. During input transitions, voltage undershoot on any pin should not exceed 1 V for more than 20 ns. Voltage overshoot on pins A0, A1, A2
and WP should not exceed VCC + 1 V for more than 20 ns, while voltage on the I2C bus pins, SCL and SDA, should not exceed the absolute
maximum ratings, irrespective of VCC.
Table 3. RELIABILITY CHARACTERISTICS (Note 2)
Symbol Parameter Min Units
NEND (Note 3) Endurance 1,000,000 Program / Erase Cycles
TDR Data Retention 100 Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECQ100
and JEDEC test methods.
3. Page Mode, VCC = 5 V, 25°C.
Table 4. D.C. OPERATING CHARACTERISTICS
(VCC = 1.8 V to 5.5 V, TA = 40°C to +125°C and VCC = 1.7 V to 5.5 V, TA = 40°C to +85°C, unless otherwise specified.)
Symbol Parameter Test Conditions Min Max Units
ICCR Read Current Read, fSCL = 400 kHz 1 mA
ICCW Write Current Write, fSCL = 400 kHz 2 mA
ISB Standby Current All I/O Pins at GND or VCC TA = 40°C to +85°C
VCC 3.3 V
1mA
TA = 40°C to +85°C
VCC > 3.3 V
3
TA = 40°C to +125°C 5
ILI/O Pin Leakage Pin at GND or VCC 2mA
VIL Input Low Voltage 0.5 0.3 x VCC V
VIH Input High Voltage A0, A1, A2 and WP 0.7 x VCC VCC + 0.5 V
SCL and SDA 0.7 x VCC 5.5
VOL Output Low
Voltage
VCC > 2.5 V, IOL = 3 mA 0.4
VCC < 2.5 V, IOL = 1 mA 0.2
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
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3
Table 5. PIN IMPEDANCE CHARACTERISTICS
(VCC = 1.8 V to 5.5 V, TA = 40°C to +125°C and VCC = 1.7 V to 5.5 V, TA = 40°C to +85°C, unless otherwise specified.)
Symbol Parameter Conditions Max Units
CIN (Note 4) SDA Pin Capacitance VIN = 0 V, f = 1.0 MHz, VCC = 5.0 V 8 pF
Other Pins 6 pF
IWP (Note 5) WP Input Current VIN < VIH, VCC = 5.5 V 130 mA
VIN < VIH, VCC = 3.3 V 120
VIN < VIH, VCC = 1.7 V 80
VIN > VIH 2
IA (Note 5) Address Input Current
(A0, A1, A2)
Product Rev H
VIN < VIH, VCC = 5.5 V 50 mA
VIN < VIH, VCC = 3.3 V 35
VIN < VIH, VCC = 1.7 V 25
VIN > VIH 2
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECQ100
and JEDEC test methods.
5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pulldown is
relatively strong; therefore the external driver must be able to supply the pulldown current when attempting to drive the input HIGH. To
conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pulldown reverts to a weak
current source.
Table 6. A.C. CHARACTERISTICS
(Note 6) (VCC = 1.8 V to 5.5 V, TA = 40°C to +125°C and VCC = 1.7 V to 5.5 V, TA = 40°C to +85°C, unless otherwise specified.)
Symbol Parameter
Standard Fast
Units
Min Max Min Max
FSCL Clock Frequency 100 400 kHz
tHD:STA START Condition Hold Time 4 0.6 ms
tLOW Low Period of SCL Clock 4.7 1.3 ms
tHIGH High Period of SCL Clock 4 0.6 ms
tSU:STA START Condition Setup Time 4.7 0.6 ms
tHD:DAT Data In Hold Time 0 0 ms
tSU:DAT Data In Setup Time 250 100 ns
tRSDA and SCL Rise Time 1000 300 ns
tF (Note 6) SDA and SCL Fall Time 300 300 ns
tSU:STO STOP Condition Setup Time 4 0.6 ms
tBUF Bus Free Time Between STOP and START 4.7 1.3 ms
tAA SCL Low to Data Out Valid 3.5 0.9 ms
tDH Data Out Hold Time 100 100 ns
Ti (Note 6) Noise Pulse Filtered at SCL and SDA Inputs 100 100 ns
tSU:WP WP Setup Time 0 0 ms
tHD:WP WP Hold Time 2.5 2.5 ms
tWR Write Cycle Time 5 5 ms
tPU (Notes 7, 8) Powerup to Ready Mode 1 1 ms
6. Test conditions according to “AC Test Conditions” table.
7. Tested initially and after a design or process change that affects this parameter.
8. tPU is the delay between the time VCC is stable and the device is ready to accept commands.
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
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4
Table 7. A.C. TEST CONDITIONS
Input Drive Levels 0.2 x VCC to 0.8 x VCC
Input Rise and Fall Time v 50 ns
Input Reference Levels 0.3 x VCC, 0.7 x VCC
Output Reference Level 0.5 x VCC
Output Test Load Current Source IOL = 3 mA (VCC w 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF
PowerOn Reset (POR)
Each CAT24Cxx* incorporates PowerOn Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state.
A CAT24Cxx device will power up into Standby mode
after VCC exceeds the POR trigger level and will power
down into Reset mode when VCC drops below the POR
trigger level. This bidirectional POR feature protects the
device against ‘brownout’ failure following a temporary
loss of power.
*For common features, the CAT24C01/02/04/08/16 will be
referred to as CAT24Cxx.
Pin Description
SCL: The Serial Clock input pin accepts the Serial Clock
generated by the Master.
SDA: The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this pin
is open drain. Data is acquired on the positive edge, and is
delivered on the negative edge of SCL.
A0, A1 and A2: The Address inputs set the device address
when cascading multiple devices. When not driven, these
pins are pulled LOW internally.
WP: The Write Protect input pin inhibits all write
operations, when pulled HIGH. When not driven, this pin is
pulled LOW internally.
Functional Description
The CAT24Cxx supports the InterIntegrated Circuit
(I2C) Bus data transmission protocol, which defines a device
that sends data to the bus as a transmitter and a device
receiving data as a receiver. Data flow is controlled by a
Master device, which generates the serial clock and all
START and STOP conditions. The CAT24Cxx acts as a
Slave device. Master and Slave alternate as either
transmitter or receiver.
I2C Bus Protocol
The I2C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the VCC supply via pullup
resistors. Master and Slave devices connect to the 2wire
bus via their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to ‘transmit’ a ‘0’ and
releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see AC Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is high. An SDA transition while SCL is
high will be interpreted as a START or STOP condition
(Figure 2). The START condition precedes all commands. It
consists of a HIGH to LOW transition on SDA while SCL
is HIGH. The START acts as a ‘wakeup’ call to all
receivers. Absent a START, a Slave will not respond to
commands. The STOP condition completes all commands.
It consists of a LOW to HIGH transition on SDA while SCL
is HIGH.
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an 8bit
serial Slave address. For normal Read/Write operations, the
first 4 bits of the Slave address are fixed at 1010 (Ah). The
next 3 bits are used as programmable address bits when
cascading multiple devices and/or as internal address bits.
The last bit of the slave address, R/W, specifies whether a
Read (1) or Write (0) operation is to be performed. The 3
address space extension bits are assigned as illustrated in
Figure 3. A2, A1 and A0 must match the state of the external
address pins, and a10, a9 and a8 are internal address bits.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA line
during the 9th clock cycle (Figure 4). The Slave will also
acknowledge the address byte and every data byte presented
in Write mode. In Read mode the Slave shifts out a data byte,
and then releases the SDA line during the 9th clock cycle. As
long as the Master acknowledges the data, the Slave will
continue transmitting. The Master terminates the session by
not acknowledging the last data byte (NoACK) and by
issuing a STOP condition. Bus timing is illustrated in
Figure 5.
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
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5
START
CONDITION
STOP
CONDITION
SDA
SCL
Figure 2. Start/Stop Timing
1010a10 a9a8R/W CAT24C16
1010A2a9a8R/W CAT24C08
1010A2A1a8R/W CAT24C04
1010A2A1A0R/W CAT24C01 and CAT24C02
Figure 3. Slave Address Bits
189
START
SCL FROM
MASTER
BUS RELEASE DELAY (TRANSMITTER) BUS RELEASE DELAY
(RECEIVER)
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACK DELAY (v tAA)
ACK SETUP (w tSU:DAT)
Figure 4. Acknowledge Timing
SCL
SDA IN
SDA OUT
tBUF
Figure 5. Bus Timing
tSU:STO
tSU:DAT
tDH
tR
tLOW
tAA
tHD:DAT
tHIGH
tLOW
tHD:SDA
tF
tSU:STA
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
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6
WRITE OPERATIONS
Byte Write
In Byte Write mode, the Master sends the START
condition and the Slave address with the R/W bit set to zero
to the Slave. After the Slave generates an acknowledge, the
Master sends the byte address that is to be written into the
address pointer of the CAT24Cxx. After receiving another
acknowledge from the Slave, the Master transmits the data
byte to be written into the addressed memory location. The
CAT24Cxx device will acknowledge the data byte and the
Master generates the STOP condition, at which time the
device begins its internal Write cycle to nonvolatile memory
(Figure 6). While this internal cycle is in progress (tWR), the
SDA output will be tristated and the CAT24Cxx will not
respond to any request from the Master device (Figure 7).
Page Write
The CAT24Cxx writes up to 16 bytes of data in a single
write cycle, using the Page Write operation (Figure 8). The
Page Write operation is initiated in the same manner as the
Byte Write operation, however instead of terminating after
the data byte is transmitted, the Master is allowed to send up
to fifteen additional bytes. After each byte has been
transmitted the CAT24Cxx will respond with an
acknowledge and internally increments the four low order
address bits. The high order bits that define the page address
remain unchanged. If the Master transmits more than sixteen
bytes prior to sending the STOP condition, the address
counter ‘wraps around’ to the beginning of page and
previously transmitted data will be overwritten. Once all
sixteen bytes are received and the STOP condition has been
sent by the Master, the internal Write cycle begins. At this
point all received data is written to the CAT24Cxx in a single
write cycle.
Acknowledge Polling
The acknowledge (ACK) polling routine can be used to
take advantage of the typical write cycle time. Once the stop
condition is issued to indicate the end of the host’s write
operation, the CAT24Cxx initiates the internal write cycle.
The ACK polling can be initiated immediately. This
involves issuing the start condition followed by the slave
address for a write operation. If the CAT24Cxx is still busy
with the write operation, NoACK will be returned. If the
CAT24Cxx has completed the internal write operation, an
ACK will be returned and the host can then proceed with the
next read or write operation.
Hardware Write Protection
With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the operation of
the CAT24Cxx. The state of the WP pin is strobed on the last
falling edge of SCL immediately preceding the first data
byte (Figure 9). If the WP pin is HIGH during the strobe
interval, the CAT24Cxx will not acknowledge the data byte
and the Write request will be rejected.
Delivery State
The CAT24Cxx is shipped erased, i.e., all bytes are FFh.
ADDRESS
BYTE
DATA
BYTE
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
S
T
O
P
P
S
T
A
R
T
BUS ACTIVITY:
MASTER
SLAVE
* For the CAT24C01 a7 = 0
a7 a0d7 d0
Figure 6. Byte Write Sequence
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
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7
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
ACK8th Bit
Byte n
SCL
SDA
Figure 7. Write Cycle Timing
A
C
K
A
C
K
A
C
K
S
T
O
P
S
A
C
K
A
C
K
S
T
A
R
T
P
SLAVE
ADDRESS
n = 1
P v 15
ADDRESS
BYTE n n+1 n+P
BUS ACTIVITY:
MASTER
SLAVE
DATA
BYTE DATA
BYTE DATA
BYTE
Figure 8. Page Write Sequence
1891 8
a7a0d7d0
tSU:WP
tHD:WP
ADDRESS
BYTE
DATA
BYTE
SCL
SDA
WP
Figure 9. WP Timing
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
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8
READ OPERATIONS
Immediate Read
Upon receiving a Slave address with the R/W bit set to ‘1’,
the CAT24Cxx will interpret this as a request for data
residing at the current byte address in memory. The
CAT24Cxx will acknowledge the Slave address, will
immediately shift out the data residing at the current address,
and will then wait for the Master to respond. If the Master
does not acknowledge the data (NoACK) and then follows
up with a STOP condition (Figure 10), the CAT24Cxx
returns to Standby mode.
Selective Read
Selective Read operations allow the Master device to
select at random any memory location for a read operation.
The Master device first performs a ‘dummy’ write operation
by sending the START condition, slave address and byte
address of the location it wishes to read. After the
CAT24Cxx acknowledges the byte address, the Master
device resends the START condition and the slave address,
this time with the R/W bit set to one. The CAT24Cxx then
responds with its acknowledge and sends the requested data
byte. The Master device does not acknowledge the data
(NoACK) but will generate a STOP condition (Figure 11).
Sequential Read
If during a Read session, the Master acknowledges the 1st
data byte, then the CAT24Cxx will continue transmitting
data residing at subsequent locations until the Master
responds with a NoACK, followed by a STOP (Figure 12).
In contrast to Page Write, during Sequential Read the
address count will automatically increment to and then
wraparound at end of memory (rather than end of page). In
the CAT24C01, the internal address count will not wrap
around at the end of the 128 byte memory space.
SCL
SDA 8th Bit
STOPNO ACKDATA OUT
89
SLAVE
ADDRESS
S
A
C
K
D ATA
BYTE
N
O
A
C
K
S
T
O
P
P
S
T
A
R
T
BUS ACTIVITY:
MASTER
SLAVE
Figure 10. Immediate Read Sequence and Timing
SLAVE
S
A
C
K
N
O
A
C
K
S
T
O
P
P
S
T
A
R
T
S
A
C
K
SLAVE
ADDRESS
A
C
K
S
T
A
R
T
D ATA
BYTE
ADDRESS
BYTEADDRESS
BUS ACTIVITY:
MASTER
SLAVE
Figure 11. Selective Read Sequence
S
T
O
P
P
SLAVE
ADDRESS
A
C
K
A
C
K
A
C
K
N
O
A
C
K
A
C
K
D ATA
BYTE
n
D ATA
BYTE
n+1
D ATA
BYTE
n+2
D ATA
BYTE
n+x
BUS ACTIVITY:
MASTER
SLAVE
Figure 12. Sequential Read Sequence
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
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9
PACKAGE DIMENSIONS
PDIP8, 300 mils
CASE 646AA01
ISSUE A
E1
D
A
L
eb
b2
A1
A2
E
eB
c
TOP VIEW
SIDE VIEW END VIEW
PIN # 1
IDENTIFICATION
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
SYMBOL MIN NOM MAX
A
A1
A2
b
b2
c
D
e
E1
L
0.38
2.92
0.36
6.10
1.14
0.20
9.02
2.54 BSC
3.30
5.33
4.95
0.56
7.11
1.78
0.36
10.16
eB 7.87 10.92
E 7.62 8.25
2.92 3.80
3.30
0.46
6.35
1.52
0.25
9.27
7.87
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
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10
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD01
ISSUE O
E1 E
A
A1
h
θ
L
c
eb
D
PIN # 1
IDENTIFICATION
TOP VIEW
SIDE VIEW END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
SYMBOL MIN NOM MAX
θ
A
A1
b
c
D
E
E1
e
h
0.10
0.33
0.19
0.25
4.80
5.80
3.80
1.27 BSC
1.75
0.25
0.51
0.25
0.50
5.00
6.20
4.00
L0.40 1.27
1.35
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
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11
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL01
ISSUE O
E1 E
A2
A1
e
b
D
c
A
TOP VIEW
SIDE VIEW END VIEW
q1
L1 L
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
SYMBOL
θ
MIN NOM MAX
A
A1
A2
b
c
D
E
E1
e
L1
L
0.05
0.80
0.19
0.09
0.50
2.90
6.30
4.30
0.65 BSC
1.00 REF
1.20
0.15
1.05
0.30
0.20
0.75
3.10
6.50
4.50
0.90
0.60
3.00
6.40
4.40
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
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12
PACKAGE DIMENSIONS
MSOP 8, 3x3
CASE 846AD01
ISSUE O
E1E
A2
A1 e b
D
c
A
TOP VIEW
SIDE VIEW END VIEW
L1
L2
L
DETAIL A
DETAIL A
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-187.
SYMBOL MIN NOM MAX
q
θ
A
A1
A2
b
c
D
E
E1
e
L
L2
0.05
0.75
0.22
0.13
0.40
2.90
4.80
2.90
0.65 BSC
0.25 BSC
1.10
0.15
0.95
0.38
0.23
0.80
3.10
5.00
3.10
0.60
3.00
4.90
3.00
L1 0.95 REF
0.10
0.85
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
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13
PACKAGE DIMENSIONS
TDFN8, 2x3
CASE 511AK01
ISSUE A
PIN#1
IDENTIFICATIO
N
E2
E
A3
ebD
A2
TOP VIEW SIDE VIEW BOTTOM VIEW
PIN#1 INDEX AREA
FRONT VIEW
A1
A
L
D2
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-229.
SYMBOL MIN NOM MAX
A 0.70 0.75 0.80
A1 0.00 0.02 0.05
A3 0.20 REF
b 0.20 0.25 0.30
D 1.90 2.00 2.10
D2 1.30 1.40 1.50
E 3.00
E2 1.20 1.30 1.40
e
2.90
0.50 TYP
3.10
L 0.20 0.30 0.40
A2 0.45 0.55 0.65
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
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14
PACKAGE DIMENSIONS
TSOT23, 5 LEAD
CASE 419AE01
ISSUE O
E1 E
A2
A1
e
b
D
c
A
TOP VIEW
SIDE VIEW END VIEW
L1
LL2
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-193.
SYMBOL
θ
MIN NOM MAX
q
A
A1
A2
b
c
D
E
E1
e
L
L1
L2
0.01
0.80
0.30
0.12
0.30
0.05
0.87
0.15
2.90 BSC
2.80 BSC
1.60 BSC
0.95 TYP
0.40
0.60 REF
0.25 BSC
1.00
0.10
0.90
0.45
0.20
0.50
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
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15
PACKAGE DIMENSIONS
UDFN8, 2x3 EXTENDED PAD
CASE 517AZ01
ISSUE O
0.065 REF
Copper Exposed
E2
D2
L
E
PIN #1 INDEX AREA
PIN #1
IDENTIFICATION
DAP SIZE 1.8 x 1.8
DETAIL A
D
A1
be
A
TOP VIEW SIDE VIEW
FRONT VIEW
DETAIL A
BOTTOM VIEW
A3
0.065 REF
0.0 - 0.05A3
Notes:
(1) All dimensions are in millimeters.
(2) Refer JEDEC MO-236/MO-252.
SYMBOL MIN NOM MAX
A 0.45 0.50 0.55
A1 0.00 0.02 0.05
A3 0.127 REF
b 0.20 0.25 0.30
D 1.95 2.00 2.05
D2 1.35 1.40 1.45
E 3.00
E2 1.25 1.30 1.35
e
2.95
0.50 REF
3.05
L 0.25 0.30 0.35
A
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
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16
PACKAGE DIMENSIONS
WLCSP4, 0.856x0.832
CASE 567DC01
ISSUE O
SEATING
PLANE
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DATUM C, THE SEATING PLANE, IS DEFINED BY
THE SPHERICAL CROWNS OF THE CONTACT
BALLS.
4. COPLANARITY APPLIES TO SPHERICAL CROWNS
OF THE CONTACT BALLS.
5. DIMENSION b IS MEASURED AT THE MAXIMUM
CONTACT BALL DIAMETER PARALLEL TO DATUM C.
2X
DIM
A
MIN MAX
0.27
MILLIMETERS
A1
D0.856 BSC
E
b0.22 0.28
e0.40 BSC
0.35
ÈÈ
ÈÈ
D
EAB
PIN A1
REFERENCE
e
0.05 C
4X b
12
B
A
0.10 C
A1
A2
C
0.09 0.13
0.832 BSC
0.10 C
2X TOP VIEW
SIDE VIEW
BOTTOM VIEW
NOTE 4
e
A2 0.20 REF
PITCH 0.23
4X
DIMENSIONS: MILLIMETERS
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.40
0.40
RECOMMENDED
A1 PACKAGE
OUTLINE
PITCH
NOTE 3
A2
NOTE 5
A
M
0.10 BC
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
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17
PACKAGE DIMENSIONS
WLCSP5, 0.832x0.856
CASE 567DD01
ISSUE O
SEATING
PLANE
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DATUM C, THE SEATING PLANE, IS DEFINED BY
THE SPHERICAL CROWNS OF THE CONTACT
BALLS.
4. COPLANARITY APPLIES TO SPHERICAL CROWNS
OF THE CONTACT BALLS.
5. DIMENSION b IS MEASURED AT THE MAXIMUM
CONTACT BALL DIAMETER PARALLEL TO DATUM C.
2X
DIM
A
MIN MAX
0.27
MILLIMETERS
A1
D0.832 BSC
E
b0.14 0.18
e0.300 BSC
0.35
ÈÈ
ÈÈ
E
DAB
PIN A1
REFERENCE
e
0.05 C
5X b
12
B
A
0.10 C
A1
A2
C
0.09 0.13
0.856 BSC
0.10 C
2X TOP VIEW
SIDE VIEW
BOTTOM VIEW
NOTE 4
e1
A2 0.20 REF
PITCH 0.16
5X
DIMENSIONS: MILLIMETERS
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.52
0.30
RECOMMENDED
A1 PACKAGE
OUTLINE
PITCH
NOTE 3
A2
NOTE 5
A
M
0.10 BC
e1 0.520 BSC
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
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18
Example of Ordering Information
CAT24C01/02/04/08/16 (Note 11)
Prefix Device # Suffix
Company ID
CAT 24C16 Y
Product Number
24C01
I G
Package
I = Industrial (40°C to +85°C)
E = Extended (40°C to +125°C)
Temperature Range
L: PDIP
W: SOIC, JEDEC
Y: TSSOP
Z: MSOP (Note 12)
VP2: TDFN (2 x 3 mm) (Note 13)
TD: TSOT23
HU4: UDFN (2 x 3 mm)
C4A: WLCSP 4 balls (Note 15)
C5A: WLCSP 5 balls (Note 15)
Lead Finish
G: NiPdAu
Blank: MatteTin
T: Tape & Reel
3: 3000 Units / Reel
24C02
24C04
24C08
24C16
Tape & Reel (Note 16)
T3
9. All packages are RoHScompliant (Leadfree, Halogenfree).
10.The standard lead finish is NiPdAu.
11. The device used in the above example is a CAT24C16YIGT3 (TSSOP, Industrial Temperature, NiPdAu, Tape & Reel, 3,000/Reel).
12.For availability, please contact your nearest ON Semiconductor Sales Office.
13.Not recommended for new designs. Please replace with UDFN 2 x 3 mm (HU4) package.
14.For CAT24C02 Gresham only die, please use the following OPNs: CAT24C02LI-GA, CAT24C02WI-GT3A, CAT24C02YI-GT3A,
CAT24C02ZI-GT3A, CAT24C02VP2IGT3A, CAT24C02TDI-GT3A, CAT24C02HU4IGT3A, CAT24C02LE-GA, CAT24C02WE-GT3A,
CAT24C02YE-GT3A, CAT24C02ZE-GT3A, CAT24C02VP2EGT3A, CAT24C02TDE-GT3A or CAT24C02HU4EGT3A.
15.WLCSP 4 balls and 5 balls configurations are available upon request for the CAT24C04, CAT24C08 and CAT24C16 only. For availability,
please contact your nearest ON Semiconductor Sales office.
16.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
N. American Technical Support: 8002829855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81357733850
CAT24C01/D
ON Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 3036752175 or 8003443860 Toll Free USA/Canada
Fax: 3036752176 or 8003443867 Toll Free USA/Canada
Email: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative