| FAIRCHILD eee SEMICONDUCTOR CD4049UBC - CD4050BC Hex Inverting Buffer Hex Non-Inverting Buffer General Description The GD4049UBC and CD4050BC hex buffers are mono- lithic complementary MOS (CMOS) integrated circuits con- structed with N- and P-channel enhancement mode transistors. These devices feature logic level conversion using only one supply voltage (Vpp). The input signal high level (Viy) can exceed the Vpp supply voltage when these devices are used for logic level conversions. These devices are intended for use as hex buffers, CMOS to DTL/ TTL converters, or as CMOS current drivers, and at Vpp = 5.0V, they can drive directly two DTL/TTL loads over the full operating temperature range. October 1987 Revised January 1999 Features lf Wide supply voltage range: 3.0V to 15V lf Direct drive to 2 TTL loads at 5.0V over full temperature range Mf High source and sink current capability Hf Special input protection permits input voltages greater than Vpp Applications * CMOS hex inverter/buffer * CMOS to DTL/TTL hex converter * CMOS current sink or source driver * CMOS HIGH-to-LOW logic level converter Ordering Code: Order Number Package Number Package Description CD4049UBCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow CD4049UBCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide CD4050BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow CD4050BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. Connection Diagrams Pin Assignments for DIP CD4049UBC NC L=F F Nc K=E E d=0 D ls |. 14 ls |e 1 10 9 [' Y 3 4 5 6 7 8 Vop GHA A H=B B t= c Vg Top View CD4050BC NC L=F F NC OK=E E J=D 0 ls ls 4 I. |. 10 9 | 1 Y 3 4 5 6 7 8 Vpp GA A H=B B t=C c Vs Top View 1999 Fairchild Semiconductor Corporation DS00597 1.prf www.fairchildsemi.com 49jjNg BulJeau]-UON XeH + 490j3Ng Huljieaul X8H OG0SOPGD - OaN6rOradCD4049UBC - CD4050BC Schematic Diagrams CD4049UBC 1 of 6 Identical Units Vpo a INPUT OUTPUT BV ~ 30V CD4050BC 1 of 6 Identical Units v o O J b ao INPUT BV ~ 30V as OUTPUT www.fairchildsemi.com 2Absolute Maximum Ratingsinote 1) (Note 2) Supply Voltage (Vpp) 0.5V to +18V Input Voltage (Vin) 0.5V to +18V Voltage at Any Output Pin (Vout) 0.5V to Vpp + 0.5V Storage Temperature Range (Ts) 65C to +150C Power Dissipation (Pp) Dual-In-Line 700 mW Small Outline 500 mW Lead Temperature (T_) (Soldering, 10 seconds) 260C DC Electrical Characteristics (note 3) Recommended Operating Conditions (Note 2) Supply Voltage (Vpp) 3V to 15V Input Voltage (Vin) OV to 15V Voltage at Any Output Pin (Vour) 0 to Vop Operating Temperature Range (Ta) CD4049UBC, CD4050BC. 40C to +85C Note 1: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices should be operated at these limits. The table of Recom- mended Operating Conditions and Electrical Characteristics provides conditions for actual device operation. Note 2: Vgg = OV unless otherwise specified. 40C +25C +85C Symbol Parameter Conditions . . . Units Min Max Min Typ | Max Min Max lbp Quiescent Device Current Vpp =5V 4 0.03 4.0 30 pA Vpp = 10V 8 0.05 8.0 60 pA Vpp = 15V 16 0.07 | 16.0 120 pA VoL LOW Level Output Voltage Vin = opp: Vit= OV, llol <1 pA Vpp = 5V 0.05 0 0.05 0.05 Vv Vpp = 10V 0.05 0 0.05 0.05 Vv Vpp = 15V 0.05 0 0.05 0.05 Vv Vou HIGH Level Output Voltage Vin = Vpp: Vit= OV, llol <1 pA Vpp = 5V 4.95 4.95 5 4.95 Vv Vpp = 10V 9.95 9.95 10 9.95 Vv Vpp = 15V 14.95 14.95 | 15 14.95 Vv VIL LOW Level Input Voltage [lo] < 1 pA (CD4050BC Only) Vpp = 5Y, Vo = 0.5V 1.5 2.25 1.5 15 Vv Vpp = 10V, Vo = 1V 3.0 45 3.0 3.0 Vv Vpp = 15V, Vo = 1.5V 4.0 6.75 | 4.0 4.0 Vv Vit LOW Level Input Voltage lol < 1 pA (CD4049UBC Only) Vop = 8V, Vo =4.5V 1.0 15 1.0 1.0 Vv Vpp = 10V, Vo = 9V 2.0 25 2.0 2.0 Vv Vpp = 15V, Vo = 13.5V 3.0 3.5 3.0 3.0 Vv Vin HIGH Level Input Voltage lol < 1 pA (CD4050BC Only) Vop = 8V, Vo =4.5V 3.5 3.5 2.75 3.5 Vv Vpp = 10V, Vo = 9V 7.0 7.0 55 7.0 Vv Vpp = 15V, Vo = 13.5V 11.0 11.0 | 8.25 11.0 Vv Vin HIGH Level Input Voltage lol < 1 pA (CD4049UBC Only) Vpp = 5Y, Vo = 0.5V 4.0 4.0 3.5 4.0 Vv Vpp = 10V, Vo = 1V 8.0 8.0 75 8.0 Vv Vpp = 15V, Vo = 1.5V 12.0 12.0 | 11.5 12.0 Vv lot LOW Level Output Current Vin =Vpp> Vit= OV (Note 4) Vopp = 5V, Vo = 0.4V 46 4.0 5 3.2 mA Vpp = 10V, Vo = 0.5V 9.8 8.5 12 6.8 mA Vpp = 15V, Vo = 1.5V 29 25 40 20 mA lou HIGH Level Output Current Vin=Vopp:; Vi_= OV (Note 4) Vopp = 5V, Vo = 4.6V -1.0 0.9 | -1.6 0.72 mA Vpp = 10V, Vo = 9.5V 2.1 -1.9 | -3.6 -1.5 mA Vpp = 15V, Vo = 13.5V 7 6.2 | -12 +5 mA lI Input Current Vpp = 15V, Vin = OV -0.3 -0.3 | -10% 1.0 pA Vpp = 15, Vin = 15V 0.3 0.3 105 1.0 pA Note 3: Vgg = OV unless otherwise specified. www.fairchildsemi.com 980S07d0D * DENn6rorddCD4049UBC - CD4050BC DC Electrical Characteristics (continued) Note 4: These are peak output current capabilities. Continuous output current is rated at 12 mA maximum. The output current should not be allowed to exceed this value for extended periods of time. Ig, and Iq}, are tested one output at a time. AC Electrical Characteristics (vote 5) CD4049UBC Ta = 25C, C_ = 50 pF, R, = 200k, t, = = 20 ns, unless otherwise specified Symbol Parameter Conditions Min Typ Max Units tpHL Propagation Delay Time Vpp =5V 30 65 ns HIGH-to-LOW Level Vpp = 10V 20 40 ns Vpp = 15V 15 30 ns teLy Propagation Delay Time Vpp =5V 45 85 ns LOW-to-HIGH Level Vpp = 10V 25 45 ns Vpp = 15V 20 35 ns true Transition Time Vpp =5V 30 60 ns HIGH-to-LOW Level Vpp = 10V 20 40 ns Vpp = 15V 15 30 ns tTLH Transition Time Vpp =5V 60 120 ns LOW-to-HIGH Level Vpp = 10V 30 55 ns Vpp = 15V 25 45 ns Cin Input Capacitance Any Input 15 22.5 pF Note 5: AC Parameters are guaranteed by DC correlated testing. AC Electrical Characteristics (Note 6) CD4050BC Ta = 25C, C, = 50 pF, Ri = 200k, t, = } = 20 ns, unless otherwise specified Symbol Parameter Conditions Min Typ Max Units tPHL Propagation Delay Time Vpp =5V 60 110 ns HIGH-to-LOW Level Vpp = 10V 25 55 ns Vpp = 15V 20 30 ns teLH Propagation Delay Time Vpp =5V 60 120 ns LOW-to-HIGH Level Vpp = 10V 30 55 ns Vpp = 15V 25 45 ns trHL Transition Time Vpp =5V 30 60 ns HIGH-to-LOW Level Vpp = 10V 20 40 ns Vpp = 15V 15 30 ns ttLy Transition Time Vpp =5V 60 120 ns LOW-to-HIGH Level Vpp = 10V 30 55 ns Vpp = 15V 25 45 ns Cin Input Capacitance Any Input 5 75 pF Note 6: AC Parameters are guaranteed by DC correlated testing. www.fairchildsemi.com 4Switching Time Waveforms ~ t Yoo 30% VIN Y 50% ov 10%s ~~ tPHL V Yop "T73, | 90% OUT 50% cp4049uB 10% ov = sed ATH Voo | a tPLH 90% Vout 50% cD40508 10% o ov tTL Typical Applications CMOS to TLL or CMOS at a Lower Vpp Voo Voo Vee TTL 1 Vo01 cmos oR == Vpp2 = cmos 7 GND GND CD40508C \ sus Vpp1 2 Vop2 In the case of the CD4048UBC the output drive capability increases with increasing input voltage. E.g., If Vpp; = 10V the CD4049UBC could drive 4 TTL loads. 5 www.fairchildsemi.com 980S07d0D * DENn6rorddCD4049UBC - CD4050BC Physical DimensiONS inches (millimeters) unless otherwise noted 0.386 0.394 |e (9.804 10.00) 160615 #14 13 12~=977 109 AAR AAR AAA 0.228 -0.244 (5.791 6.198) 40 TYP fo. ae 2 3 4 5 6 a LEAD NO.1 {1 7 IDENT 0.010 pax (0.254) 0.150 0.157 | (3.8103.988) 0.010-0.020 0.053 0.069 (0.2540.508) 4! |* (1.346 1.753) 0.004 0,010 & MAX TYP (0.102 0.254) ALL LEADS ese 1 Sh | 1 fey Eee ety SEATING , PLANE t | 4 tt 0.008 0.010 0.014 0.050 a a 0 .0160.050 (0.356) oO wl ae (0.203 -0.254) (0.4061.270) OTe TYP 0.008 TYP ALL LEADS 0.004 TYP ALL LEADS >< (0.102) (0.203) ALL LEAD TIPS TYP 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 0.014 ~0.020 yp 10.356 0.508) NGA (REV H) www.fairchildsemi.com 6Physical DimensiONS inches (millimeters) unless otherwise noted (Continued) 0.740 - 0.780 0.090 18.80 19.81 5 ( ) ~| | (2.286) INDEX t AREA 0,250 #0.010 (6.350 0.254) PIN NO. 1 + PIN NO. 1 IDENT IDENT OPTION 01 OPTION 02 0.068 0.130 0.005 0.130 0.005_ 0.060 4 TYP. 0,300 - 0.320 (1.651) y _ G30280.127) >| Fr asa MP "\ > optionaL 7 (7-620-8.128) |" { 0.145 -0.200 | (3.683- 5.080) } CI FI 95 5 0.008 - 0.016 Oo $ 4 MUS = UTS 0.020, in 4 907 4 TYP (0.203- 0.406) (0.508) 0.280 _,| 0.125 = 0.150 0.030 0.015 (7.112) (3.175 = 3.810) 1. ~ (0.762 0.381) MIN 0.014- 0.023 0.100 0.010 0.040 (0.356 0.584) "!/" 0.050 0.010 (2.540 0,254) (0.825 ~o.015 NIGE (REV F TP (1.270 40.254) (8.255 Hote) TYP . 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. Accritical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com Faircrild does not assume any responsibility for use of any circuitry described, no drcuit patent licanses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 49jjNg BulJeau]-UON XeH + 490j3Ng Huljieaul X8H OG0SOPGD - OaN6rOrad