1
December 1997
ICL7136, ICL7137
31/2 Digit LCD/LED , Low Power Displa y,
A/D Con verters with Overrange Recovery
Features
• First Reading Overrange Recovery in One Conversion
Period
• Guaranteed Zero Reading for 0V Input on All Scales
• True Polarity at Zero for Precise Null Detection
• 1pA Typical Input Current
• True Differential Input and Reference, Direct Display Drive
- LCD ICL7136
- LED lCL7137
• Low Noise - Less Than 15µVP-P
• On Chip Clock and Reference
• No Additional Active Circuits Required
• Low Power - Less Than 1mW
• Surface Mount Package Available
• Drop-In Replacement f or ICL7126, No Changes Needed
Description
The Intersil ICL7136 and ICL7137 are high perf ormance, lo w
power 31/2 digit, A/D converters. Included are seven seg-
ment decoders, display drivers, a reference, and a clock.
The ICL7136 is designed to interf ace with a liquid crystal dis-
play (LCD) and includes a multiplexed backplane drive; the
ICL7137 will directly drive an instrument size, light emitting
diode (LED) display.
The ICL7136 and ICL7137 bring together a combination of
high accuracy, versatility, and true economy. It features auto-
zero to less than 10µV, zero drift of less than 1µV/oC, input
bias current of 10pA (Max), and rollover error of less than
one count. True diff erential inputs and ref erence are useful in
all systems, but give the designer an uncommon advantage
when measuring load cells, strain gauges and other bridge
type transducers. Finally, the true economy of single power
supply operation (ICL7136), enables a high performance
panel meter to be built with the addition of only 10 passive
components and a display.
The ICL7136 and ICL7137 are improved versions of the
ICL7126, eliminating the overrange hangover and hysteresis
effects, and should be used in its place in all applications. It
can also be used as a plug-in replacement for the ICL7106
in a wide variety of applications, changing only the passive
components.
Pinouts
Ordering Information
PART NUMBER TEMP.
RANGE (oC) PACKAGE PKG. NO.
ICL7136CPL 0 to 70 40 Ld PDIP E40.6
ICL7136RCPL 0 to 70 40 Ld PDIP (Note) E40.6
ICL7136CM44 0 to 70 44 Ld MQFP Q44.10x10
ICL7137CPL 0 to 70 40 Ld PDIP E40.6
ICL7137RCPL 0 to 70 40 Ld PDIP (Note) E40.6
ICL7137CM44 0 to 70 44 Ld MQFP Q44.10x10
NOTE: “R” indicates device with reversed leads.
(PDIP)
TOP VIEW (MQFP)
TOP VIEW
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
V+
D1
C1
B1
A1
F1
G1
E1
D2
C2
B2
A2
F2
E2
D3
B3
F3
E3
(1000) AB4
POL
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
CREF+
CREF-
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V-
G2 (10’s)
C3
A3
G3
BP/GND
(1’s)
(10’s)
(100’s)
(MINUS)
(100’s)
OSC 2
NC
OSC 3
TEST
NC
NC 1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17
OSC 1
V+
D1
C1
B1
A1 F1 G1 E1 D2 C2
28
27
26
25
24
23
2221201918
B2 A2 F2 E2 D3
B3
F3
E3
AB4
POL
BP/GND
39 38 37 36 35 34
33
32
31
30
29
44 43 42 41 40
IN HI
IN LO
A-Z
BUFF
INT
V-
NC
G2
C3
A3
G3
REF HI
REF LO
CREF+
CREF-
COMMON
File Number 3086.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 |Copyright © Intersil Corporation 1999
2
Absolute Maximum Ratings Thermal Information
Supply Voltage
ICL7136, V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V
ICL7137, V+ to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V
ICL7137, V- to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-9V
Analog Input Voltage (Either Input) (Note 1). . . . . . . . . . . . . V+ to V-
Reference Input Voltage (Either Input) . . . . . . . . . . . . . . . . . V+ to V-
Clock Input
ICL7136 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEST to V+
ICL7137 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND to V+
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC
Thermal Resistance (Typical, Note 2) θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(MQFP - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Input voltages may exceed the supply voltages provided the input current is limited to ±100µA.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications (Note 3)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
SYSTEM PERFORMANCE
Zero Input Reading VIN = 0V, Full Scale = 200mV -000.0 ±000.0 +000.0 Digital
Read-
ing
Ratiometric Reading VlN = VREF, VREF = 100mV 999 999/
1000 1000 Digital
Read-
ing
Rollover Error -VIN = +VlN ≅ 200mV Difference in Reading for Equal
Positive and Negative Inputs Near Full Scale -±0.2 ±1 Counts
Linearity Full Scale = 200mV or Full Scale = 2V Maximum
Deviation from Best Straight Line Fit (Note 5) -±0.2 ±1 Counts
Common Mode Rejection Ratio VCM = ±1V, VIN = 0V, Full Scale = 200mV (Note 5) - 50 - µV/V
Noise VIN = 0V, Full Scale = 200mV (Peak-To-Peak Value Not
Exceeded 95% of Time) (Note 5) -15-µV
Leakage Current Input VlN = 0V (Note 5) - 1 10 pA
Zero Reading Drift VlN = 0V, 0oC To 70oC (Note 5) - 0.2 1 µV/oC
Scale Factor Temperature Coefficient VIN = 199mV, 0oC To 70oC,(Ext. Ref. 0ppm/oC) (Note 5) - 1 5 ppm/oC
COMMON Pin Analog Common Voltage 25kΩ Between Common and Positive Supply (With
Respect to + Supply) 2.4 3.0 3.2 V
Temperature Coefficient of Analog
Common 25kΩ Between Common and Positive Supply (With
Respect to + Supply) (Note 5) - 150 - ppm/oC
SUPPLY CURRENT ICL7136
V+ Supply Current VIN = 0 (Does Not Include Common Current) 16kHz
Oscillator (Note 6) - 70 100 µA
SUPPLY CURRENT ICL7137
V+ Supply Current VIN = 0 (Does Not Include Common Current) 16kHz
Oscillator (Note 6) - 70 200 µA
V- Supply Current -40-µA
DISPLAY DRIVER ICL7136 ONLY
Peak-To-Peak Segment Drive Voltage
Peak-To-Peak Backplane Drive Voltage V+ = to V- = 9V (Note 4) 4 5.5 6 V
ICL7136, ICL7137
3
DISPLAY DRIVER ICL7137 ONLY
Segment Sinking Current V+ = 5V, Segment Voltage = 3V
(Except Pins 19 and 20) 58-mA
Pin 19 Only 10 16 - mA
Pin 20 Only 47-mA
NOTES:
3. Unless otherwise noted, specifications apply to both the ICL7136 and ICL7137 at TA = 25oC, fCLOCK = 48kHz. ICL7136 is tested in the
circuit of Figure 1. ICL7137 is tested in the circuit of Figure 2.
4. Back plane drive is in phase with segment drive for ‘off’ segment, 180 degrees out of phase for ‘on’ segment. Frequency is 20 times
conversion rate. Average DC component is less than 50mV.
5. Not tested, guaranteed by design.
6. 48kHz oscillator increases current by 20µA (Typ).
Electrical Specifications (Note 3) (Continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Typical Applications and Test Circuits
FIGURE 1. ICL7136 TEST CIRCUIT AND TYPICAL APPLICATION WITH LCD DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE
FIGURE 2. ICL7137 TEST CIRCUIT AND TYPICAL APPLICATION WITH LED DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
V+
D1
C1
B1
A1
F1
G1
E1
D2
C2
B2
A2
F2
E2
D3
B3
F3
E3
AB4
POL
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
CREF+
CREF-
COM
IN HI
IN LO
A-Z
BUFF
INT
V-
G2
C3
A3
G3
BP
DISPLAY
DISPLAY
C1C2C3
C4
R3
R1
R4C5
+-
IN
R5
R2
ICL7136
C1= 0.1µF
C2= 0.47µF
C3= 0.047µF
C4= 50pF
C5= 0.01µF
R1= 240kΩ
R2= 180kΩ
R3= 180kΩ
R4= 10kΩ
R5= 1MΩ
9V
+
-
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
V+
D1
C1
B1
A1
F1
G1
E1
D2
C2
B2
A2
F2
E2
D3
B3
F3
E3
AB4
POL
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
CREF+
CREF-
COM
IN HI
IN LO
A-Z
BUFF
INT
V-
G2
C3
A3
G3
GND
DISPLAY
DISPLAY
C1C2C3
C4
R3
R1
R4C5
+-
IN
R5
R2
ICL7137
+5V -5V
C1= 0.1µF
C2= 0.47µF
C3= 0.047µF
C4= 50pF
C5= 0.01µF
R1= 240kΩ
R2= 180kΩ
R3= 180kΩ
R4= 10kΩ
R5= 1MΩ
ICL7136, ICL7137
4
Typical Integrator Amplifier Output Waveform (INT Pin)
Design Information Summary Sheet
• OSCILLATOR FREQUENCY
fOSC = 0.45/RC
COSC > 50pF; ROSC > 50kΩ
fOSC (Typ) = 48kHz
• OSCILLATOR PERIOD
tOSC = RC/0.45
• INTEGRATION CLOCK FREQUENCY
fCLOCK = fOSC/4
• INTEGRATION PERIOD
tINT = 1000 x (4/fOSC)
• 60/50Hz REJECTION CRITERION
tINT/t60Hz or tlNT/t50Hz = Integer
• OPTIMUM INTEGRATION CURRENT
IINT = 1µA
• FULL SCALE ANALOG INPUT VOLTAGE
VlNFS (Typ) = 200mV or 2V
• INTEGRATE RESISTOR
• INTEGRATE CAPACITOR
• INTEGRATOR OUTPUT VOLTAGE SWING
•V
INT MAXIMUM SWING:
(V- + 0.5V) < VINT < (V+ - 0.5V), VINT (Typ) = 2V
• DISPLAY COUNT
• CONVERSION CYCLE
tCYC = tCL0CK x 4000
tCYC = tOSC x 16,000
when fOSC = 48kHz; tCYC = 333ms
• COMMON MODE INPUT VOLTAGE
(V- + 1V) < VlN < (V+ - 0.5V)
• AUTO-ZERO CAPACITOR
0.01µF < CAZ < 1µF
• REFERENCE CAPACITOR
0.1µF < CREF < 1µF
•V
COM
Biased between V+ and V-.
•V
COM ≅ V+ - 2.8V
Regulation lost when V+ to V- < ≅6.8V.
If VCOM is externally pulled down to (V + to V -)/2,
the VCOM circuit will turn off.
• ICL7136 POWER SUPPLY: SINGLE 9V
V+ - V- = 9V
Digital supply is generated internally
VTEST ≅ V+ - 4.5V
• ICL7136 DISPLAY: LCD
Type: Direct drive with digital logic supply amplitude.
• ICL7137 POWER SUPPLY: DUAL ±5.0V
V+ = +5V to GND
V- = -5V to GND
Digital Logic and LED driver supply V+ to GND
• ICL7137 DISPLAY: LED
Type: Non-Multiplexed Common Anode
RINT VINFS
IINT
-----------------=
CINT tINT
()IINT
()
VINT
--------------------------------=
VINT tINT
()IINT
()
CINT
--------------------------------=
COUNT 1000 VIN
VREF
---------------
×=
AUTO ZERO PHASE
(COUNTS)
2999 - 1000
SIGNAL INTEGRATE
PHASE FIXED
1000 COUNTS
DE-INTEGRATE PHASE
0 - 1999 COUNTS
TOTAL CONVERSION TIME = 4000 x tCLOCK = 16,000 x tOSC
ICL7136, ICL7137
5
Pin Descriptions
PIN NUMBER
NAME FUNCTION DESCRIPTION40 PIN DIP 44 PIN
FLATPACK
1 8 V+ Supply Power Supply.
2 9 D1 Output Driver Pin for Segment “D” of the display units digit.
3 10 C1 Output Driver Pin for Segment “C” of the display units digit.
4 11 B1 Output Driver Pin for Segment “B” of the display units digit.
5 12 A1 Output Driver Pin for Segment “A” of the display units digit.
6 13 F1 Output Driver Pin for Segment “F” of the display units digit.
7 14 G1 Output Driver Pin for Segment “G” of the display units digit.
8 15 E1 Output Driver Pin for Segment “E” of the display units digit.
9 16 D2 Output Driver Pin for Segment “D” of the display tens digit.
10 17 C2 Output Driver Pin for Segment “C” of the display tens digit.
11 18 B2 Output Driver Pin for Segment “B” of the display tens digit.
12 19 A2 Output Driver Pin for Segment “A” of the display tens digit.
13 20 F2 Output Driver Pin for Segment “F” of the display tens digit.
14 21 E2 Output Driver Pin for Segment “E” of the display tens digit.
15 22 D3 Output Driver pin for segment “D” of the display hundreds digit.
16 23 B3 Output Driver pin for segment “B” of the display hundreds digit.
17 24 F3 Output Driver pin for segment “F” of the display hundreds digit.
18 25 E3 Output Driver pin for segment “E” of the display hundreds digit.
19 26 AB4 Output Driver pin for both “A” and “B” segments of the display thousands digit.
20 27 POL Output Driver pin for the negative sign of the display.
21 28 BP/GND Output Driver pin for the LCD backplane/Power Supply Ground.
22 29 G3 Output Driver pin for segment “G” of the display hundreds digit.
23 30 A3 Output Driver pin for segment “A” of the display hundreds digit.
24 31 C3 Output Driver pin for segment “C” of the display hundreds digit.
25 32 G2 Output Driver pin for segment “G” of the display tens digit.
26 34 V-Supply Negative power supply.
27 35 INT Output Integrator amplifier output. To be connected to integrating capacitor.
28 36 BUFF Output Input buffer amplifier output. To be connected to integrating resistor.
29 37 A-Z Input Integrator amplifier input.To be connected to auto-zero capacitor.
30
31 38
39 IN LO
IN HI Input Differential inputs. To be connected to input voltage to be measured. LO and HI
designators are for reference and do not imply that LO should be connected to
lower potential, e.g., for negative inputs IN LO has a higher potential than IN HI.
32 40 COMMON Supply/
Output Internal voltage reference output.
33
34 41
42 CREF-
CREF+Connection pins for reference capacitor.
35
36 43
44 REF LO
REF HI Input Input pins for reference voltage to the device. REF HI should be positive
reference to REF LO.
37 3 TEST Input Display test. Turns on all segments when tied to V+.
38
39
40
4
6
7
OSC3
OSC2
OSC1
Output
Output
Input
Device clock generator circuit connection pins.
ICL7136, ICL7137
6
Detailed Description
Analog Section
Figure 3 shows the Analog Section for the ICL7136 and
ICL7137. Each measurement cycle is divided into four
phases. They are (1) auto-zero (A-Z), (2) signal integrate
(INT) and (3) de-integrate (DE), (4) zero integrate (ZI).
Auto-Zero Phase
During auto-zero three things happen. First, input high and low
are disconnected from the pins and internally shorted to analog
COMMON. Second, the reference capacitor is charged to the
reference voltage. Third, a feedback loop is closed around the
system to charge the auto-zero capacitor CAZ to compensate
f or offset voltages in the b uffer amplifier , integ rator , and compar-
ator . Since the comparator is included in the loop , the A-Z accu-
racy is limited only by the noise of the system. In any case, the
offset ref erred to the input is less than 10µV.
Signal Integrate Phase
During signal integrate, the auto-zero loop is opened, the
internal short is remov ed, and the internal input high and low
are connected to the external pins. The converter then
integrates the differential voltage between IN HI and IN LO
for a fixed time. This differential voltage can be within a wide
common mode range: up to 1V from either supply. If, on the
other hand, the input signal has no retur n with respect to the
converter power supply, IN LO can be tied to analog
COMMON to establish the correct common mode v oltage . At
the end of this phase, the polarity of the integrated signal is
determined.
De-Integrate Phase
The final phase is de-integrate, or reference integrate. Input
low is internally connected to analog COMMON and input
high is connected across the previously charged reference
capacitor. Circuitry within the chip ensures that the capacitor
will be connected with the correct polarity to cause the
integrator output to return to zero. The time required for the
output to return to zero is proportional to the input signal.
Specifically the digital reading displayed is:
.
Zero Integrator Phase
The final phase is zero integrator. First, input low is shor ted to
analog COMMON. Second, the reference capacitor is charged
to the reference voltage. Finally, a feedback loop is closed
around the system to IN HI to cause the integrator output to
return to zero. Under normal conditions, this phase lasts for
between 11 to 140 clock pulses, but after a “heavy” overrange
conv ersion, it is extended to 740 clock pulses .
Differential Input
The input can accept differential voltages anywhere within the
common mode range of the input amplifier, or specifically from
0.5V below the positiv e supply to 1V abov e the negative supply.
In this range, the system has a CMRR of 86dB typical. How-
ever, care must be exercised to assure the integrator output
does not saturate. A w orst case condition would be a large pos-
itive common mode voltage with a near full scale negative dif-
ferential input voltage. The negative input signal drives the
integrator positive when most of its swing has been used up by
the positive common mode voltage. For these critical applica-
tions the integrator output swing can be reduced to less than
the recommended 2V full scale swing with little loss of accu-
racy. The integrator output can swing to within 0.3V of either
supply without loss of linearity.
DISPLAY READING = 1000 VIN
VREF
---------------
DE-DE+
CINT
CAZ
RINT
BUFFER A-Z INT
-
+
A-Z
COMPARATOR
IN HI
COMMON
IN LO
31
32
30
DE- DE+
INT
A-Z
34
CREF+
36
REF HI
CREF
REF LO
35
A-Z, A-Z,
33
CREF-
28 29 27
TO
DIGITAL
SECTION
A-Z AND DE(±)
INTEGRATOR
INT
STRAY STRAY
V+
10µA
V-
N
INPUT
HIGH
2.8V
6.2V
V+
1
INPUT
LOW
-
+
-
+
-
+
ZI ZI
AND ZI
ZI
26
FIGURE 3. ANALOG SECTION OF ICL7136 AND ICL7137
ICL7136, ICL7137
7
Differential Reference
The ref erence v oltage can be generated an ywhere within the
power supply voltage of the converter. The main source of
common mode error is a roll-over voltage caused by the
ref erence capacitor losing or gaining charge to stra y capacity
on its nodes. If there is a large common mode voltage, the
ref erence capacitor can gain charge (increase v oltage) when
called up to de-integrate a positive signal but lose charge
(decrease voltage) when called up to de-integ r ate a negative
input signal. This difference in reference for positive or
negative input voltage will give a roll-over error. However, by
selecting the reference capacitor such that it is large enough
in comparison to the stray capacitance, this error can be
held to less than 0.5 count worst case. (See Component
Value Selection.)
Analog COMMON
This pin is included primarily to set the common mode
voltage for battery operation (ICL7136) or for any system
where the input signals are floating with respect to the power
supply. The COMMON pin sets a voltage that is approxi-
mately 2.8V more negative than the positive supply. This is
selected to give a minimum end-of-life battery voltage of
about 6.8V. However, analog COMMON has some of the
attributes of a reference voltage. When the total supply
voltage is large enough to cause the z ener to regulate (>7V),
the COMMON voltage will have a low voltage coefficient
(0.001%/V), low output impedance (≅15Ω), and a
temperature coefficient typically less than 150ppm/oC.
The limitations of the on chip reference should also be
recognized, however. With the ICL7137, the internal heating
which results from the LED drivers can cause some
degradation in performance. Due to their higher thermal resis-
tance, plastic parts are poorer in this respect than ceramic.
The combination of reference Temperature Coefficient (TC),
internal chip dissipation, and package ther mal resistance can
increase noise near full scale from 25µV to 80µVP-P. Also the
linearity in going from a high dissipation count such as 1000
(20 segments on) to a low dissipation count such as 1111 (8
segments on) can suffer by a count or more. Devices with a
positive TC reference ma y require sev er al counts to pull out of
an over range condition. This is because over-range is a low
dissipation mode, with the three least significant digits
blanked. Similarly, units with a negative TC may cycle
between over range and a non-over range count as the die
alternately heats and cools. All these problems are of course
eliminated if an e xternal reference is used.
The ICL7136, with its negligible dissipation, suffers from
none of these problems. In either case, an external
reference can easily be added, as shown in Figure 4.
Analog COMMON is also used as the input low return during
auto-zero and de-integrate. If IN LO is different from analog
COMMON, a common mode voltage exists in the system
and is taken care of by the excellent CMRR of the converter.
However, in some applications IN LO will be set at a fixed
known voltage (power supply common for instance). In this
application, analog COMMON should be tied to the same
point, thus removing the common mode voltage from the
converter. The same holds true for the reference voltage. If
reference can be conveniently tied to analog COMMON, it
should be since this removes the common mode voltage
from the reference system.
Within the lC , analog COMMON is tied to an N-Channel FET
that can sink approximately 3mA of current to hold the
voltage 2.8V below the positive supply (when a load is trying
to pull the common line positive). However, there is only
10µA of source current, so COMMON ma y easily be tied to a
more negative voltage thus overriding the internal reference.
TEST
The TEST pin serves two functions. On the ICL7136 it is
coupled to the internally generated digital supply through a
500Ω resistor. Thus it can be used as the negative supply for
e xternally generated segment drivers such as decimal points
or any other presentation the user may want to include on
the LCD display. Figures 5 and 6 show such an application.
No more than a 1mA load should be applied.
ICL7136
V
REF LO
ICL7137
REF HI
V+
V-
6.8V
ZENER
IZ
FIGURE 4A.
ICL7136
V
REF HI
REF LO
COMMON
V+
ICL8069
1.2V
REFERENCE
6.8kΩ
20kΩ
ICL7137
FIGURE 4B.
FIGURE 4. USING AN EXTERNAL REFERENCE
ICL7136
V+
BP
TEST
21
37 TO LCD
BACKPLANE
TO LCD
DECIMAL
POINT
1MΩ
FIGURE 5. SIMPLE INVERTER FOR FIXED DECIMAL POINT
ICL7136, ICL7137
8
The second function is a “lamp test”. When TEST is pulled
high (to V+) all segments will be turned on and the display
should read “-1888”. The TEST pin will sink about 5mA
under these conditions.
CAUTION: On the ICL7136, in the lamp test mode, the segments have a
constant DC voltage (no square-wave) and may burn the LCD
display if left in this mode for several minutes.
Digital Section
Figures 7 and 8 show the digital section for the ICL7136 and
ICL7137, respectively. In the ICL7136, an internal digital
ground is generated from a 6V Zener diode and a large
P-Channel source follower. This supply is made stiff to
absorb the relative large capacitive currents when the back
plane (BP) voltage is switched. The BP frequency is the
clock frequency divided by 800. For three readings/second
this is a 60Hz square wave with a nominal amplitude of 5V.
The segments are driven at the same frequency and ampli-
tude and are in phase with BP when OFF, but out of phase
when ON. In all cases negligible DC voltage exists across
the segments.
Figure 8 is the Digital Section of the ICL7137. It is identical
to the ICL7136 except that the regulated supply and back
plane drive have been eliminated and the segment drive has
been increased from 2mA to 8mA, typical for instrument size
common anode LED displa ys. Since the 1000 output (pin 19)
must sink current from two LED segments, it has twice the
drive capability or 16mA.
In both devices, the polarity indication is “on” for negative
analog inputs. If IN LO and IN HI are re versed, this indication
can be reversed also, if desired.
ICL7136
V+ BP
TEST
DECIMAL
POINT
SELECT
CD4030
GND
V+
TO LCD
DECIMAL
POINTS
FIGURE 6. EXCLUSIVE ‘OR’ GATE FOR DECIMAL POINT DRIVE
FIGURE 7. ICL7136 DIGITAL SECTION
7
SEGMENT
DECODE
LCD PHASE DRIVER
LATCH
7
SEGMENT
DECODE ÷200
LOGIC CONTROL
INTERNAL VTH = 1V
7
SEGMENT
DECODE
1000’s 100’s 10’s 1’s
TO SWITCH DRIVERS
FROM COMPARATOR OUTPUT
DIGITAL
GROUND
÷4
CLOCK
40 39 38
OSC 1 OSC 2 OSC 3
BACKPLANE
21
V+
TEST
V-
500Ω
37
26
6.2V
COUNTER COUNTER COUNTER COUNTER
1
†
† THREE INVERTERS
ONLY ONE INVERTER SHOWN
FOR CLARITY
SEGMENT
OUTPUT
0.5mA
2mA
INTERNAL DIGITAL GROUND
TYPICAL SEGMENT OUTPUT
V+
c
ab
c
d
fg
e
a
b
ab
c
d
fg
e
ab
c
d
fg
e
ICL7136, ICL7137
9
System Timing
Figure 9 shows the clocking arrangement used in the
ICL7136 and ICL7137. Two basic clocking arrangements
can be used:
1. Figure 9A, an external oscillator connected to pin 40.
2. Figure 9B, an R-C oscillator using all three pins.
The oscillator frequency is divided by f our before it clocks the
decade counters. It is then further divided to form the three
convert-cycle phases. These are signal integrate (1000
counts), reference de-integrate (0 to 2000 counts) and auto-
zero (1000 to 3000 counts). For signals less than full scale,
auto-zero gets the unused portion of reference de-integrate.
This makes a complete measure cycle of 4,000 counts
(16,000 clock pulses) independent of input v oltage . For three
readings/second, an oscillator frequency of 48kHz would be
used.
To achieve maximum rejection of 60Hz pickup, the signal
integrate cycle should be a multiple of 60Hz. Oscillator
frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz,
40kHz, 331/3kHz, etc., should be selected. For 50Hz rejec-
tion, Oscillator frequencies of 200kHz, 100kHz, 662/3kHz,
50kHz, 40kHz, etc. would be suitable. Note that 40kHz (2.5
readings/sec.) will reject both 50Hz and 60Hz (also 400Hz
and 440Hz).
FIGURE 8. ICL7137 DIGITAL SECTION
7
SEGMENT
DECODE
TO
SEGMENT
0.5mA
8mA
DIGITAL GROUND
TYPICAL SEGMENT OUTPUT
V+ LATCH
7
SEGMENT
DECODE
LOGIC CONTROL
7
SEGMENT
DECODE
1000’s 100’s 10’s 1’s
TO SWITCH DRIVERS
FROM COMPARATOR OUTPUT
DIGITAL
GROUND
÷4
CLOCK
40 39 38
OSC 1 OSC 2 OSC 3
V+
TEST
500Ω
COUNTER COUNTER COUNTER COUNTER
1
V+
37
27
† THREE INVERTERS
ONLY ONE INVERTER SHOWN
FOR CLARITY
†
c
ab
c
d
fg
e
a
b
ab
c
d
fg
e
ab
c
d
fg
e
CLOCK
INTERNAL TO PART
40 39 38
GND ICL7137
÷4
TEST ICL7136
CLOCK
INTERNAL TO PART
40 39 38
÷4
RC
FIGURE 9B. RC OSCILLATOR
FIGURE 9. CLOCK CIRCUITS
FIGURE 9A. EXTERNAL OSCILLATOR
ICL7136, ICL7137
10
Component Value Selection
Integrating Resistor
Both the buffer amplifier and the integrator have a class A
output stage with 100µA of quiescent current. They can
supply 1µA of drive current with negligible nonlinearity. The
integrating resistor should be large enough to remain in this
very linear region over the input voltage range, but small
enough that undue leakage requirements are not placed on
the PC board. For 2V full scale, 1.8MΩ is near optimum and
similarly a 180kΩ for a 200mV scale.
Integrating Capacitor
The integrating capacitor should be selected to give the
maximum voltage swing that ensures tolerance buildup will
not saturate the integrator swing (approximately 0.3V from
either supply). In the ICL7136 or the ICL7137, when the
analog COMMON is used as a ref erence, a nominal +2V full-
scale integrator swing is fine. For the ICL7137 with +5V
supplies and analog COMMON tied to supply ground, a
±3.5V to +4V swing is nominal. For three readings/second
(48kHz clock) nominal values for ClNT are 0.047µF and
0.5µF, respectively. Of course, if different oscillator frequen-
cies are used, these values should be changed in inverse
proportion to maintain the same output swing.
An additional requirement of the integrating capacitor is that
it must have a low dielectric absorption to prevent roll-over
errors. While other types of capacitors are adequate for this
application, polypropylene capacitors give undetectable
errors at reasonable cost.
Auto-Zero Capacitor
The size of the auto-zero capacitor has some influence on
the noise of the system. For 200mV full scale where noise is
very impor tant, a 0.47µF capacitor is recommended. On the
2V scale, a 0.047µF capacitor increases the speed of recov-
ery from overload and is adequate for noise on this scale.
Reference Capacitor
A 0.1µF capacitor gives good results in most applications.
However, where a large common mode voltage exists (i.e.,
the REF LO pin is not at analog COMMON) and a 200mV
scale is used, a larger value is required to prevent roll-over
error. Generally 1µF will hold the roll-over error to 0.5 count
in this instance.
Oscillator Components
For all ranges of frequency a 180kΩ resistor is recom-
mended and the capacitor is selected from the equation
Reference Voltage
The analog input required to generate full scale output (2000
counts) is: VlN = 2VREF. Thus, for the 200mV and 2V scale,
VREF should equal 100mV and 1V, respectively. However, in
many applications where the A/D is connected to a
transducer, there will exist a scale factor other than unity
between the input voltage and the digital reading. For
instance, in a weighing system, the designer might like to
have a full scale reading when the voltage from the
transducer is 0.662V. Instead of dividing the input down to
200mV, the designer should use the input voltage directly
and select VREF = 0.341V. Suitable values for integrating
resistor and capacitor would be 330kΩ and 0.047µF. This
makes the system slightly quieter and also avoids a divider
network on the input. The ICL7137 with ±5V supplies can
accept input signals up to ±4V. Another advantage of this
system occurs when a digital reading of zero is desired for
VIN ≠ 0. Temperature and weighing systems with a variable
fare are examples. This offset reading can be conveniently
generated by connecting the voltage transducer between IN
HI and COMMON and the variable (or fixed) offset voltage
between COMMON and IN LO.
ICL7137 Power Supplies
The ICL7137 is designed to work from ±5V supplies.
However, if a negative supply is not available, it can be
generated from the clock output with 2 diodes, 2 capacitors,
and an ine xpensiv e lC . Figure 10 sho ws this application. See
ICL7660 data sheet for an alternative.
In fact, in selected applications no negative supply is
required. The conditions to use a single +5V supply are:
1. The input signal can be ref erenced to the center of the
common mode range of the converter.
2. The signal is less than ±1.5V.
3. An external reference is used.
f0.45
RC
-------------For 48kHz Clock (3 Readings/sec.),=
C 50pF.=
ICL7137
V+
OSC 1
V-
OSC 2
OSC 3
GND
V+
V- = 3.3V
0.047
µF
10
µF
+
-
IN914
IN914
CD4009
FIGURE 10. GENERATING NEGATIVE SUPPLY FROM +5V
ICL7136, ICL7137
11
Typical Applications
The ICL7136 and ICL7137 may be used in a wide variety of
configurations. The circuits which follow show some of the
possibilities, and serve to illustrate the exceptional versatility
of these A/D converters.
The following application notes contain very useful
infor mation on understanding and applying this part and are
available from Intersil semiconductor.
Application Notes
NOTE # DESCRIPTION AnswerFAX
DOC. #
AN016 “Selecting A/D Converters” 9016
AN017 “The Integrating A/D Converter” 9017
AN018 “Do’s and Don’ts of Applying A/D
Converters” 9018
AN023 “Low Cost Digital Panel Meter Designs” 9023
AN032 “Understanding the Auto-Zero and
Common Mode Performance of the
ICL7136/7/9 Family”
9032
AN046 “Building a Battery-Operated Auto
Ranging DVM with the ICL7106” 9046
AN052 “Tips for Using Single Chip 31/2 Digit A/D
Converters” 9052
Typical Applications
FIGURE 11. ICL7136 USING THE INTERNAL REFERENCE FIGURE 12. ICL7137 USING THE INTERNAL REFERENCE
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
CREF
CREF
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V -
G2
C3
A3
G3
BP
50pF
TO PIN 1
SET VREF
= 100mV
0.1µF
0.01µF
1MΩ
180kΩ
20kΩ240kΩ
IN
+
-
9V
180kΩ
0.047µF
0.47µF
TO BACKPLANE
TO DISPLAY
Values shown are for 200mV full scale, 3 readings/sec., floating
supply voltage (9V battery).
+
-
Values shown are for 200mV full scale, 3 readings/sec. IN LO may
be tied to either COMMON for inputs floating with respect to
supplies, or GND for single ended inputs. (See discussion under
Analog COMMON.)
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
CREF
CREF
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V -
G2
C3
A3
G3
GND
50pF
TO PIN 1
SET VREF
= 100mV
0.1µF
0.01µF
1MΩ
180kΩ
20kΩ240kΩ
IN
+
-
180kΩ
0.047µF
0.47µF
TO DISPLAY
+5V
-5V
ICL7136, ICL7137
12
FIGURE 13. ICL7137 WITH AN EXTERNAL BAND-GAP
REFERENCE (1.2V TYPE) FIGURE 14. ICL7137 WITH ZENER DIODE REFERENCE
FIGURE 15. ICL7136 AND ICL7137: RECOMMENDED
COMPONENT VALUES FOR 2V FULL SCALE FIGURE 16. ICL7137 OPERATED FROM SINGLE +5V
Typical Applications
(Continued)
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
CREF
CREF
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V-
G2
C3
A3
G3
BP/GND
50pF
TO PIN 1
SET VREF
= 100mV
0.1µF
0.01µF
1MΩ
100kΩ
20kΩ200kΩ
IN
+
180kΩ
0.47µF
TO DISPLAY
IN LO is tied to supply COMMON establishing the correct common mode
voltage. If COMMON is not shor ted to GND, the input voltage may floa
t
with respect to the power supply and COMMON acts as a pre-regulato
r
for the reference. If COMMON is shorted to GND, the input is single
ended (referred to supply GND) and the pre-regulator is o v erridden.
27kΩ
1.2V (ICL8069)
V -
V+
-
0.047µF
Since low TC zeners have breakdown voltages ~ 6.8V, diode must
be placed across the total supply (10V). As in the case of Figure 14,
IN LO may be tied to either COMMON or GND
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
CREF
CREF
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V -
G2
C3
A3
G3
BP/GND
50pF
TO PIN 1
SET VREF
= 100mV
0.1µF
0.01µF
1MΩ
180kΩ
10kΩ1M
IN
+
-
180kΩ
0.047µF
0.33µF
TO DISPLAY
+5V
-5V
6.8V
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
CREF
CREF
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V -
G2
C3
A3
G3
BP/GND
50pF
TO PIN 1
SET VREF
= 100mV
0.1µF
0.01µF
1MΩ
180kΩ
250kΩ240kΩ
IN
+
-
1.8M
0.047µF
0.01µF
TO DISPLAY
V+
V-
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
CREF
CREF
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V -
G2
C3
A3
G3
BP/GND
50pF
TO PIN 1
SET VREF
= 100mV
0.1µF
0.01µF
1MΩ
180kΩ
20kΩ100kΩ
IN
+
-
180kΩ
0.047µF
0.47µF
TO DISPLAY
An external reference must be used in this application, since the
voltage between V+ and V- is insufficient for correct operation of the
internal reference.
27kΩ
1.2V (ICL8069)
+5V
ICL7136, ICL7137
13
FIGURE 17. ICL7137 MEASURING RA TIOMETRIC VALUES OF
QUAD LOAD CELL FIGURE 18. ICL7136 USED AS A DIGIT AL CENTIGRADE
THERMOMETER
FIGURE 19. CIRCUIT FOR DEVELOPING UNDERRANGE AND
OVERRANGE SIGNAL FROM ICL7136 OUTPUTS FIGURE 20. CIRCUIT FOR DEVELOPING UNDERRANGE AND
OVERRANGE SIGNALS FROM ICL7137 OUTPUT
Typical Applications
(Continued)
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
CREF
CREF
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V -
G2
C3
A3
G3
GND
50pF
TO PIN 1
0.1µF
180kΩ
0.47µF
TO DISPLAY
The resistor values within the bridge are determined by the desired
sensitivity.
V+
0.047µF
180kΩ28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
CREF
CREF
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V -
G2
C3
A3
G3
BP
50pF
TO PIN 1
0.1µF
0.01µF
†
100kΩ1MΩ
9V
390kΩ
†
0.47µF
TO BACKPLANE
TO DISPLAY
A silicon diode-connected transistor has a temperature coefficient
of about -2mV/oC. Calibration is achieved by placing the sensing
transistor in ice water and adjusting the zeroing potentiometer for a
000.0 reading. The sensor should then be placed in boiling water
and the scale-factor potentiometer adjusted for a 100.0 reading.
†Value depends on clock frequency.
SCALE
FACTOR
ADJUST
200kΩ470kΩ
22kΩ
SILICON NPN
MPS 3704 OR
SIMILAR
ZERO
ADJUST
+
-
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
V+
D1
C1
B1
A1
F1
G1
E1
D2
C2
B2
A2
F2
E2
D3
B3
F3
E3
AB4
POL
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
CREF
CREF
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V-
G2
C3
A3
G3
BP
O /RANGE
U /RANGE
CD4023 OR
74C10 CD4077
TO LOGIC
VCC
V+
TO
LOGIC
V-
GND
O /RANGE
U /RANGE
CD4023 OR
74C10
TO LOGIC
VCC
+5V
V-
33kΩ
The LM339 is required to
ensure logic compatibility
with heavy display loading. 13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
V+
D1
C1
B1
A1
F1
G1
E1
D2
C2
B2
A2
F2
E2
D3
B3
F3
E3
AB4
POL
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
CREF
CREF
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V-
G2
C3
A3
G3
BP
12kΩ
+
-
+
-
+
-
+
-
ICL7136, ICL7137
14
FIGURE 21. AC TO DC CONVERTER WITH ICL7136
Typical Applications
(Continued)
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
CREF
CREF
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V-
G2
C3
A3
G3
BP
50pF
TO PIN 1
0.1µF
180kΩ
20kΩ220kΩ
180kΩ
0.047µF
0.47µF
TO BACKPLANE
TO DISPLAY
Test is used as a common-mode reference level to ensure compatibility with most op amps.
10µF
9V
10µF
470kΩ
1µF
4.3kΩ
100pF
(FOR OPTIMUM
BANDWIDTH)
1µF
10kΩ10kΩ
1N914
1µF
0.22µF
5µFCA3140
2.2MΩ
+
-
100kΩ
AC IN
SCALE FACTOR ADJUST
(VREF = 100mV FOR AC TO RMS)
+
-
ICL7136, ICL7137
15
Die Characteristics
DIE DIMENSIONS:
127 mils x 149 mils
METALLIZATION:
Type: Al
Thickness: 10kű1kÅ
PASSIVATION:
Type: PSG Nitride
Thickness: 15kű3kÅ
WORST CASE CURRENT DENSITY:
9.1 x 104 A/cm2
Metallization Mask Layout
ICL7136, ICL7137
A2
(12)
(37) TEST
(39) OSC 2
(40) OSC 1
(2) D1
(4) B1
(27)
INT
(28)
BUFF
(33)
CREF-
A1
(5)
F1
(6)
G1
(7)
E1
(8)
D2
(9)
C2
(10)
B2
(11)
F2
(13)
E2
(14)
B3 (16)
D3 (15)
F3 (17)
E3 (18)
AB4 (19)
POL (20)
BP/GND (21)
G3 (22)
A3 (23)
C3 (24)
G2 (25)
V- (26)
(29)
A/Z
(30)
IN LO
(31)
IN HI
(32)
COMM
(34)
CREF+
(35)
REF
(36)
REF
LO HI
(38) OSC 3
(1) V+
(3) C1
ICL7136, ICL7137
16
ICL7136, ICL7137
Dual-In-Line Plastic Packages (PDIP)
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 1 2 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1 Be
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C A
MBS
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be per-
pendicular to datum .
7. eB and eC are measured at the lead tips with the leads uncon-
strained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will hav e a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
eA-C-
E40.6 (JEDEC MS-011-AC ISSUE B)
40 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.250 - 6.35 4
A1 0.015 - 0.39 - 4
A2 0.125 0.195 3.18 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.030 0.070 0.77 1.77 8
C 0.008 0.015 0.204 0.381 -
D 1.980 2.095 50.3 53.2 5
D1 0.005 - 0.13 - 5
E 0.600 0.625 15.24 15.87 6
E1 0.485 0.580 12.32 14.73 5
e 0.100 BSC 2.54 BSC -
eA0.600 BSC 15.24 BSC 6
eB- 0.700 - 17.78 7
L 0.115 0.200 2.93 5.08 4
N40 409
Rev. 0 12/93
17
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable . However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor f or any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
ICL7136, ICL7137
Metric Plastic Quad Flatpack Packages (MQFP/PQFP)
D
D1
EE1
-A-
PIN 1
A2 A1
A
5o-16o
5o-16o
0o-7o
0.40
0.016 MIN
L
0o MIN
PLANE
B
0.005/0.009
0.13/0.23
WITH PLATING
BASE METAL
SEATING
0.005/0.007
0.13/0.17
B1
-B-
e
0.008
0.20 A-B S
D
S
C
M
0.10
0.004
-C-
-D-
-H-
Q44.10x10 (JEDEC MO-108AA-2 ISSUE A)
44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE
SYM-
BOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.093 - 2.35 -
A1 0.004 0.010 0.10 0.25 -
A2 0.077 0.083 1.95 2.10 -
B 0.012 0.018 0.30 0.45 6
B1 0.012 0.016 0.30 0.40 -
D 0.510 0.530 12.95 13.45 3
D1 0.390 0.398 9.90 10.10 4, 5
E 0.510 0.530 12.95 13.45 3
E1 0.390 0.398 9.90 10.10 4, 5
L 0.026 0.037 0.65 0.95 -
N44 447
e 0.032 BSC 0.80 BSC -
Rev. 1 1/94
NOTES:
1. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
2. All dimensions and tolerances per ANSI Y14.5M-1982.
3. Dimensions D and E to be determined at seating plane .
4. Dimensions D1 and E1 to be determined at datum plane
.
5. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25mm (0.010 inch) per side.
6. Dimension B does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total.
7. “N” is the number of terminal positions.
-C-
-H-
