STWBC-WA Digital controller for wireless battery charger transmitters for wearable and smartwatch applications Datasheet - production data Memory - Flash and EEPROM with read-while-write (RWW) and Error Correction Code (ECC) - Program memory: 32 Kbytes Flash; data retention:15 years at 85 C after 10 kcycles at 25 C - Data memory: 1 Kbyte true data EEPROM; data retention: 15 years at 85 C after 100 kcycles at 85 C - RAM: 6 Kbytes VFQFPN32 Features Digital controller for wireless battery charger transmitters Optimized for < 3 W applications - Smartwatches and healthcare - Internet of Things (IoT) battery-powered smart devices - Remote controllers Cost effective half-bridge topology with integrated drivers Optional full-bridge configuration for 3 W applications Active presence detector Parametric customization via graphical interface 2 firmware options: - Turnkey solution for quick design - APIs available for application customization August 2016 This is information on a product in full production. Operating temperature - -40 C up to 105 C Package - VFQFPN32 : VIN range: 3 V to 5.5 V - Supports USB VIN Peripherals available via APIs - ADC, with 10-bit precision - UART - I2C master fast/slow speed rate - GPIOs Transmitter reference design: - Evaluation board order code: STEVAL-ISB038V1T - 2-layer PCBs - Active object detection - Graphical user interface for application monitoring - Interoperable with receiver: STEVAL-ISB038V1R Table 1. Ordering information Order code Type STWBC-WA Controller (tube) STWBC-WATR Controller (tape and reel) STEVAL-ISB038V1T Transmitter evaluation board STEVAL-ISB038V1R Receiver evaluation board STEVAL-ISB038V1 Transmitter and receiver evaluation kit DocID029660 Rev 1 1/31 www.st.com Contents STWBC-WA Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 STWBC-WA system architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 STWBC-WA pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1.4 Typical current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1.5 Loading capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1.6 Pin output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.4 4.3.1 VOUT external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3.2 Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 13 4.3.3 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3.4 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3.5 Typical output level curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3.6 Fast pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3.7 Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.3.8 I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.3.9 10-bit SAR ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.4.1 Electrostatic discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.4.2 Static latch-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1 2/31 VFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 DocID029660 Rev 1 STWBC-WA Contents 7 STWBC-WA development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 DocID029660 Rev 1 3/31 31 Description 1 STWBC-WA Description The STWBC-WA is STMicroelectronics' wireless battery charger transmitter application optimized for wearable usage. Thanks to its 5 V native supply, the STWBC-WA device is ideal to operate with USB power supplies. Wireless battery charging systems replace the traditional power supply cable by means of electromagnetic induction between a transmitting pad or dongle (TX) and a battery-powered unit (RX), such as a smartwatch or sports gear. The power transmitter unit is responsible for controlling the transmitting coil and generating the correct amount of power requested by the receiver unit. The receiver unit continuously provides the transmitter the correct power level requested, by modulating the transmitter carrier through controlled resistive or capacitive insertion. Generating the correct amount of power guarantees the highest level of end-to-end efficiency due to reduced energy waste. It also helps to maintain a lower operational temperature. The digital wireless battery transmitter can adapt to the amount of energy transferred by the coil by modulating the frequency, duty cycles or coil input voltage. Figure 1. Wireless charging architecture The STWBC-WA firmware sits on the top of the hardware to monitor and control the correct wireless charging operations. 4/31 DocID029660 Rev 1 STWBC-WA 2 STWBC-WA system architecture STWBC-WA system architecture Figure 2 illustrates the overall system blocks implemented in the STWBC-WA architecture. The STWBC-WA is a flexible controller which can be configured to support both half-bridge topologies for < 1 W power levels as well as full-bridge systems for driving < 3 W wearable devices. The integrated drivers require no external components between the STWBC-WA and the power MOSFETs application. Figure 2. STWBC-WA device architecture Firmware The STWBC-WA firmware is available in two separate software packages: Turnkey: the firmware is distributed as a binary file. API customizable: the firmware is designed as a library, and external functions as well as peripherals can be added by means of APIs. The STWBC-WA provides a set of APIs which allows the user to customize the application and tailor the system architecture to his needs. The UART and I2C communication interfaces, ADC and GPIOs can be controlled by the custom firmware via convenient APIs. The software APIs allow a great deal of freedom to customize applications. The STWBCWA device and the API library can be accessed by programming the internal controller via standard programming tools such as the IARTM Workbench(R) Studio. DocID029660 Rev 1 5/31 31 STWBC-WA pinout and pin description 3 STWBC-WA STWBC-WA pinout and pin description This section illustrates the pinout used by the STWBC-WA device. Figure 3. STWBC-WA pin configuration Table 2. Pinout description Pin number Pin name 1 UART_RX(1) 2 6/31 Pin type (1) PWM_AUX/GPIO_2 Turnkey firmware description DI UART RX link DO Not used, must not be connected to any potential 3 I2C_SDA/DIGIN[4](1) - Inactive (internal pull-up) 4 (1) I2C_SCL/DIGIN[5] - Inactive (internal pull-up) 5 DRIVEOUT[3](1) DO Output driver for full-bridge configuration (optional) 6 GPIO_0(1) DO Digital output for the green light indicator 7 (1) DO Digital output for the red light indicator GPIO_1 8 CPP_INT_3 AI Connected to GND 9 CPP_INT_2 AI Connected to GND 10 CPP_REF AI External reference for CPP_INT_3 (if not used, must be tied to GND) 11 CPP_INT_1 AI Connected to GND 12 CPP_INT_0 AI WAVE_SNS signal for symbol detection 13 VDDA PS Analog power supply DocID029660 Rev 1 STWBC-WA STWBC-WA pinout and pin description Table 2. Pinout description (continued) Pin number Pin name Pin type 14 VSSA PS Analog ground 15 RESERVED AI Reserved 16 RESERVED - Reserved (1) Turnkey firmware description 17 SPARE_ADC - Connected to the USB_ID signal 18 NTC_TEMP AI NTC temperature measurement 19 ISENSE AI LC tank current measurement 20 VMAIN AI Vmain monitor 21 DRIVEOUT[0] DO Output driver for the low-side branch 22 (1) DIGIN[0] - Inactive (internal pull-up) 23 DIGIN[1](1) - Inactive (internal pull-up) 24 DRIVEOUT[1] DO Output driver for the high-side branch 25 DRIVEOUT[2] DO Output driver for full-bridge configuration (optional) 26 DIGIN[2](1) - 27 SWIM DIO 28 NRST DI Reset 29 VDD PS Digital and I/O power supply 30 VSS PS Digital and I/O ground 31 VOUT 32 UART_TX Supply (1) DO Not connected Debug interface Internal LDO output UART TX link 1. API configurable. Note: All analog inputs are VDD compliant but can be used only between 0 and 1.2 V. DocID029660 Rev 1 7/31 31 Electrical characteristics STWBC-WA 4 Electrical characteristics 4.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. VDDA and VDD must be connected to the same voltage value. VSS and VSSA must be connected together with the shortest wire loop. 4.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of the ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 C and TA = TA max. (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in Table 3, Table 4 and in the footnotes of Table 6 on page 12 to Table 18 on page 24, and are not tested in production. 4.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 C, VDD and VDDA = 3.3 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range. 4.1.3 Typical curves Unless otherwise specified, all typical curves are given as design guidelines only and are not tested. 4.1.4 Typical current consumption For typical current consumption measurements, VDD and VDDA are connected together as shown in Figure 4. 8/31 DocID029660 Rev 1 STWBC-WA Electrical characteristics Figure 4. Supply current measurement conditions 4.1.5 Loading capacitors The loading conditions used for the pin parameter measurement are shown in Figure 5: Figure 5. Pin loading conditions DocID029660 Rev 1 9/31 31 Electrical characteristics 4.1.6 STWBC-WA Pin output voltage The input voltage measurement on a pin is described in Figure 6. Figure 6. Pin input voltage 4.2 Absolute maximum ratings Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 3. Voltage characteristics Symbol Ratings VDDX - VSSX Supply voltage(1) VIN Input voltage on any other VDD - VDDA Variation between different power pins VESD Electrostatic discharge voltage Max. -0.3 6.5 VSS -0.3 VDD +0.3 - 50 - 50 Unit V pin(2) VSS - VSSA Variation between all the different ground Min. pins(3) mV Refer to absolute maximum ratings (electrical sensitivity) in Section 4.4.1 on page 26. 1. All power VDDX (VDD, VDDA) and ground VSSX (VSS, VSSA) pins must always be connected to the external power supply. 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. 3. VSS and VSSA signals must be interconnected together with a short wire loop. 10/31 DocID029660 Rev 1 STWBC-WA Electrical characteristics Table 4. Current characteristics Symbol IVDDX IVSSX Max.(1) Ratings Total current into VDDX power lines(2) (2) Total current out of VSSX power lines Output current sunk by any I/Os and control pin IIO Output current source by any I/Os and control pin IINJ(PIN)(3), (4) IINJ(TOT)(3), (4), (5) Unit 100 100 Ref. to Table 12 on page 16 mA - Injected current on any pin 4 Sum of injected currents 20 1. Data based on characterization results, not tested in production 2. All power VDDX (VDD, VDDA) and ground VSSX (VSS, VSSA) pins must always be connected to the external power supply. 3. The IINJ(PIN) must never be exceeded. This is implicitly insured if the VIN maximum is respected. If the VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. 4. The negative injection disturbs the analog performance of the device. 5. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with the IINJ(PIN) maximum current injection on four I/O port pins of the device. Table 5. Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature DocID029660 Rev 1 Max. Unit -65 to 150 C 150 C 11/31 31 Electrical characteristics 4.3 STWBC-WA Operating conditions The device must be used in operating conditions that respect the parameters in Table 6. In addition, a full account must be taken for all physical capacitor characteristics and tolerances. Table 6. General operating conditions Symbol Parameter Conditions Min. Typ. Max. - 3(1) - 5.5(1) Nominal operating voltages - 3.3(1) - 5(1) Core digital power supply - - 1.8(2) - 470 - 3300 nF 0.05 - 0.2 - - - - VDD1, VDDA1 Operating voltages VDD, VDDA VOUT CVOUT: capacitance of external capacitor(3) ESR of external capacitor(2) ESL of external at 1 MHz capacitor(2) Unit V JA(4) FR4 multilayer PCB VFQFPN32 - 26 - C/W TA Ambient temperature Pd = 100 mW -40 - 105 C 1. The external power supply can be within the range from 3 V up to 5.5 V. 2. Internal core power supply voltage. 3. Care should be taken when the capacitor is selected due to its tolerance, dependency on temperature, DC bias and frequency. 4. To calculate PDmax (TA), use the formula PDmax = (TJmax - TA)/JA. Table 7. Operating conditions at power-up/power-down Symbol Parameter Min.(1) Typ. Max.(2) Unit VDD rising - 3 - ms tTEMP Reset release delay VIT+ Power-on reset threshold - 2.65 2.8 2.98 VIT- Brownout reset threshold - 2.58 2.73 2.88 V 1. Guaranteed by design, not tested in production. 2. The power supply ramp must be monotone. 12/31 Conditions DocID029660 Rev 1 STWBC-WA 4.3.1 Electrical characteristics VOUT external capacitor The stabilization of the main regulator is achieved by connecting an external capacitor CVOUT(a) to the VOUT pin. The CVOUT is specified in Section 4.3: Operating conditions. Care should be taken to limit the series inductance to less than 15 nH. Figure 7. External capacitor CVOUT 4.3.2 Internal clock sources and timing characteristics HSI RC oscillator The HSI RC oscillator parameters are specified under general operating conditions for VDD and TA. Table 8. HSI RC oscillator Symbol fHSI ACCHSI tSU(HSI) Parameter Conditions Min.(1) Typ. Max.(1) Unit - - 16 - MHz VDD = 3.3 V TA= 25 C -1% - +1% VDD = 3.3 V -40 C TA 105 C -4% - +4% VDD = 5 V -40 C TA 105 C -4% - +4% - - 1 - Frequency Accuracy of the HSI oscillator (factory calibrated)(1), (2) HSI oscillator wakeup time including calibration % s 1. Data based on characterization results, not tested in production. 2. Variation referred to fHSI nominal value. a. ESR is the equivalent series resistance and ESL is the equivalent inductance. DocID029660 Rev 1 13/31 31 Electrical characteristics STWBC-WA LSI RC oscillator The LSI RC oscillator parameters are specified under general operating conditions for VDD and TA. Table 9. LSI RC oscillator Symbol fLSI Parameter Conditions Min.(1) Typ. - - 153.6 - kHz Frequency Max.(1) Unit ACCLSI Accuracy of LSI oscillator 3.3 V VDD 5 V -40 C TA 105 C -10% - 10% % tSU(LSI) LSI oscillator wakeup time - - 7 - s Min Typ. - 16 - - 96 - - - 200 1. Guaranteed by design, not tested in production. PLL internal source clock Table 10. PLL internal source clock Symbol Parameter fIN Input frequency(2) fOUT Output frequency tlock PLL lock time Conditions 3.3 V VDD 5 V -40 C TA 105 C 1. Data based on characterization results, not tested in production. 2. PLL maximum input frequency 16 MHz. 14/31 DocID029660 Rev 1 Max.(1) Unit MHz s STWBC-WA 4.3.3 Electrical characteristics Memory characteristics Flash program and memory/data EEPROM memory General conditions: TA = -40 C to 105 C. Table 11. Flash program memory/data EEPROM memory Symbol tPROG Parameter Conditions - - 6 6.6 ms Fast programming time for 1 block (128 bytes) - - 3 3.3 ms - - 3 3.3 ms TA = 25 C 10 K - - TA = 85 C 100 K - - TA = 105 C 35 K - - Data retention (program memory) after 10 K erase/write cycles at TA= 25 C TRET = 85 C 15 - - Data retention (program memory) after 10 K erase/write cycles at TA= 25 C TRET = 105 C 11 - - Data retention (data memory) after 100 K erase/write cycles at TA= 85 C TRET = 85 C 15 - - Data retention (data memory) after 35 K erase/write cycles at TA= 105 C TRET = 105 C 6 - - Supply current during program and erase cycles -40 C TA 105 C 2 - Erase/write cycles(2) (program memory) tRET IDDPRG Unit Standard programming time (including erase) for the byte/word/block (1 byte/4 bytes/128 bytes) tERASE Erase time for 1 block (128 bytes) NWE Min.(1) Typ.(1) Max.(1) Erase/write cycles(2) (data memory) Cycles Years mA 1. Data based on characterization results, not tested in production. 2. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte. DocID029660 Rev 1 15/31 31 Electrical characteristics 4.3.4 STWBC-WA I/O port pin characteristics The I/O port pin parameters are specified under general operating conditions for VDD and TA unless otherwise specified. Unused input pins should not be left floating. Table 12. Voltage DC characteristics Symbol VIL VIH Description Input low voltage Input high voltage (2) (3) Min.(1) Typ. Max.(1) -0.3 - 0.3 * VDD 0.7 * VDD - VDD - - 0.4(4) VOL1 Output low voltage at 3.3 V VOL2 Output low voltage at 5 V(3) - - 0.5 VOL3 Output low voltage high sink at 3.3 V / 5 V(2),(5), (6) - 0.6(4) - - - - - - - 0.1 * VDD - - 30 45 60 VOH1 VOH2 Output high voltage at 3.3 Output high voltage at 5 V(3) VDD - V(3) 0.4(4) VDD - 0.5 VOH3 Output high voltage high sink at 3.3 V / 5 HVS Hysteresis input voltage(7) RPU Pull-up resistor V(2), (5), (6) VDD - 0.6(4) 1. Data based on characterization result, not tested in production. 2. All signals are not 5 V tolerant (input signals cannot exceed VDDX (VDDX = VDD, VDDA). 3. Parameter applicable to signals: GPIO_[0:2], DRIVEOUT[0:3], PWM_AUX. 4. Electrical threshold voltage not yet characterized at -40 C. 5. The parameter applicable to the signal: SWIM. 6. The parameter applicable to the signal: DIGIN [0]. 7. Applicable to any digital inputs. 16/31 DocID029660 Rev 1 Unit V k STWBC-WA Electrical characteristics Table 13. Current DC characteristics Symbol IOL1 IOL2 Description Standard output low level current at 3.3 V and VOL1(2) Standard output low level current at 5 V and VOL 2 (2) (3) (4) IOLhs1 High sink output low level current at 3.3 V and VOL3 , IOLhs2 High sink output low level current at 5 V and VOL(3),(4) (2) IOH1 Standard output high level current at 3.3 V and VOH1 IOH2 Standard output high level current at 5 V and VOLH2(2) (3), (4) Min. Typ. Max.(1) - - 1.5 - - 3 - - 5 - - 7.75 - - 1.5 - - 3 - - 5 mA IOHhs1 High sink output low level current at 3.3 V and VOH3 IOHhs2 High sink output low level current at 5 V and VOH3(3), (4) - - 7.75 Input leakage current digital - analog VSS VIN VDD - - 1 - - 4 - - 20 ILKg I_lnj I_lnj Injection (5) current(6), (7) Total injection current (sum of all I/O and control pins)(6) Unit A mA 1. Data based on characterization result, not tested in production. 2. The parameter applicable to signals: GPIO_[0:2], DRIVEOUT[0:3], PWM_AUX. 3. The parameter applicable to the signal: SWIM. 4. The parameter applicable to the signal: DIGIN [0]. 5. Applicable to any digital inputs. 6. The maximum value must never be exceeded. 7. The negative injection current on the ADCIN [7:0] signals (product depending) => SPARE_ADC signals have to be avoided since they impact ADC conversion accuracy. DocID029660 Rev 1 17/31 31 Electrical characteristics 4.3.5 STWBC-WA Typical output level curves This section shows the typical output voltage level curves measured on a single output pin for the two-pad family present in the STWBC-WA device. Standard pad This pad is associated to the following signals: DIGIN [0:1], SWIM and GPIO_[0:2] when available. Figure 8. VOH standard pad at 3.3 V Figure 9. VOL standard pad at 3.3 V 18/31 DocID029660 Rev 1 STWBC-WA Electrical characteristics Figure 10. VOH standard pad at 5 V Figure 11. VOL standard pad at 5 V DocID029660 Rev 1 19/31 31 Electrical characteristics 4.3.6 STWBC-WA Fast pad This pad is associated to the DRIVEOUT[0:3], PWM_AUX signals if the external pin is available. Figure 12. VOH fast pad at 3.3 V Figure 13. VOL fast pad at 3.3 V 20/31 DocID029660 Rev 1 STWBC-WA Electrical characteristics Figure 14. VOH fast pad at 5 V Figure 15. VOL fast pad at 5 V DocID029660 Rev 1 21/31 31 Electrical characteristics 4.3.7 STWBC-WA Reset pin characteristics The reset pin parameters are specified under general operating conditions for VDD and TA unless otherwise specified. Table 14. NRST pin characteristics Symbol Parameter Conditions Min.(1) Typ. Max.(1) NRST input low level voltage(1) VIL(NRST) VIH(NRST) - -0.3 - 0.3 x VDD (1) - 0.7 x VDD - VDD + 0.3 (1) IOL = 2 mA - - 0.5 - 30 40 60 - - - 75 - 500 - - - 15 - - NRST input high level voltage NRST output low level voltage VOL(NRST) (2) RPU(NRST) NRST pull-up resistor tIFP(NRST) NRST input filtered pulse(3) NRST not input filtered tINFP(NRST) V k ns pulse(3) NRST output filtered pulse(3) tOP(NRST) Unit s 1. Data based on characterization results, not tested in production. 2. The RPU pull-up equivalent resistor is based on a resistive transistor. 3. Data guaranteed by design, not tested in production. 4.3.8 I2C interface characteristics Table 15. I2C interface characteristics Standard mode Symbol Parameter Fast mode Min.(1) Max.(1) Min.(1) Max.(1) tw(SCLL) SCL clock low time 4.7 - 1.3 - tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - SDA data hold time 0(2) - 0(2) 900(2) th(SDA) Unit s ns tr(SDA) tr(SCL) SDA and SCL rise time (VDD = 3.3 to 5 V)(3) - 1000 - 300 tf(SDA) tf(SCL) SDA and SCL fall time (VDD = 3.3 to 5 V)(3) - 300 - 300 th(STA) START condition hold time 4.0 - 0.6 - tsu(STA) Repeated START condition setup time 4.7 - 0.6 - tsu(STO) STOP condition setup time 4.0 - 0.6 - s STOP to START condition time (bus free) 4.7 - 1.3 - s - 50 - 50 pF tw(STO:STA) Cb s Capacitive load for each bus line(4) 2 1. Data based on the standard I C protocol requirement, not tested in production. 2. The maximum hold time of the start condition need only be met if the interface does not stretch the low time. 3. I2C multifunction signals require the high sink pad configuration and the interconnection of 1 K pull-up resistances. 4. 50 pF is the maximum load capacitance value to meet the I2C std. timing specifications. 22/31 DocID029660 Rev 1 STWBC-WA 4.3.9 Electrical characteristics 10-bit SAR ADC characteristics The 10-bit SAR ADC oscillator parameters are specified under general operating conditions for VDDA and TA unless otherwise specified. Table 16. ADC characteristics Symbol Conditions Min. Typ. Max. Unit Resolution - - 10 - bit ADC input impedance - 1 - - M VIN1 Conversion voltage range for the gain x1 - 0 - 1.25(1), (2) V Vref ADC main reference voltage(3) - - 1.250 - V N RADCIN Parameter 1. The maximum input analog voltage cannot exceed VDDA. 2. Exceeding the maximum voltage on the SPARE_ADC signals for the related conversion scale must be avoided since the ADC conversion accuracy can be impacted. 3. The ADC reference voltage at TA = 25 C. ADC accuracy characteristics at VDD/VDDA 3.3 V Table 17. ADC accuracy characteristics at VDD/VDDA 3.3 V Symbol |ET| Parameter Total unadjusted error(3), (4), (5) error(3), (4), (5) |EO| Offset |EG| Gain error(3), (4), (5), (6) Typ.(1) Min.(2) Max.(2) 2.8 - - 0.3 - - 0.4 - - Offset + gain error(6), (7) - -8.5 9.3 EO+G Offset + gain error(6), (8) - -11 11 EO+G Offset + gain error(6), (9) - -14.3 11.3 0.5 - - 1.4 - - EO+G |ED| |EL| Differential linearity error(1), (2), (3) Integral linearity error(3), (4), (5) Unit LSB 1. Temperature operating: TA = 25 C. 2. Data based on characterization results, not tested in production. 3. ADC accuracy vs. the negative injection current. The injecting negative current on any of the analog input pins should be avoided as this reduces the accuracy of the conversion being performed on another analog input. It is recommended a Schottky diode (pin to ground) to be added to standard analog pins which may potentially inject the negative current. Any positive injection current within the limits specified for IINJ(PIN) and INJ(PIN) in the I/O port pin characteristic section does not affect the ADC accuracy. The ADC accuracy parameters may be also impacted exceeding the ADC maximum input voltage VIN1 or VIN2. 4. Results in the manufacturing test mode. 5. Data aligned with trimming voltage parameters. 6. Gain error evaluation with the two point method. 7. Temperature operating range: 0 C TA 85 C. 8. Temperature operating range: -25 C TA 105 C. 9. Temperature operating range: -40 C TA 105 C. DocID029660 Rev 1 23/31 31 Electrical characteristics STWBC-WA ADC accuracy characteristics at VDD/VDDA 5 V Table 18. ADC accuracy characteristics at VDD/VDDA 5 V Symbol |ET| |EO| |EG| Parameter Total unadjusted error(3) (4), (5) Typ.(1) Min.(2) Max.(2) TBD - - (3) (4) (5) 0.5 - - (3) (4) (5) (6) Offset error , 0.4 - - EO+G (6) (7) Offset + gain error , - -8.3 8.9 EO+G Offset + gain error(6), (8) - -10.9 10.9 EO+G Offset + gain error(6), (9) - -13.8 10.9 0.8 - - 2.0 - - |ED| |EL| Gain error , , , , Differential linearity Integral linearity error(1), (2), (3) error(3), (4), (5) Unit LSB 1. Operating temperature: TA = 25 C. 2. Data based on characterization results, not tested in production. 3. ADC accuracy vs. the negative injection current. The injecting negative current on any of the analog input pins should be avoided as this reduces the accuracy of the conversion being performed on another analog input. It is recommended that a Schottky diode (pin to ground) be to added to standard analog pins which may potentially inject the negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in the I/O port pin characteristic section does not affect the ADC accuracy. The ADC accuracy parameters may be also impacted exceeding the ADC maximum input voltage VIN1 or VIN2. 4. Results in the manufacturing test mode. 5. Data aligned with trimming voltage parameters. 6. Gain error evaluation with the two point method. 7. Operating temperature range: 0 C TA 85 C. 8. Operating temperature range: -25 C TA 105 C. 9. Operating temperature range: -40 C TA 105 C. 24/31 DocID029660 Rev 1 STWBC-WA Electrical characteristics ADC conversion accuracy Figure 16. ADC conversion accuracy ADC accuracy parameter definitions: ET = total unadjusted error: the maximum deviation between the actual and the ideal transfer curves. EO = offset error: the deviation between the first actual transition and the first ideal one. EOG = offset + gain error (1-point gain): the deviation between the last ideal transition and the last actual one. EG = gain error (2-point gain): defined so that EOG = EO + EG (parameter correlated to the deviation of the characteristic slope). ED = differential linearity error: the maximum deviation between actual steps and the ideal one. EL = integral linearity error: the maximum deviation between any actual transition and the end point correlation line. DocID029660 Rev 1 25/31 31 Electrical characteristics STWBC-WA 4.4 EMC characteristics 4.4.1 Electrostatic discharge (ESD) Electrostatic discharges (3 positive and then 3 negative pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts * (n + 1) supply pin). Table 19. ESD absolute maximum ratings Symbol Ratings Conditions Maximum value VESD(HBM) Electrostatic discharge voltage (human body model) TA = 25 C, conforming to JEDEC/JESD22-A114E 2000 VESD(CDM) Electrostatic discharge voltage (charge device model) TA = 25 C, conforming to ANSI/ESD STM 5.3.1 ESDA 500 VESD(MM) Electrostatic discharge voltage (machine model) TA = 25 C, conforming to JEDEC/JESD-A115-A 200 Unit V Data based on characterization results, not tested in production. 4.4.2 Static latch-up Two complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to the each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. Table 20. Electrical sensitivity 26/31 Symbol Parameter Conditions Level LU Static latch-up class TA = 105 C A DocID029660 Rev 1 STWBC-WA 5 Thermal characteristics Thermal characteristics The STWBC-WA functionality cannot be guaranteed when the device, in operation, exceeds the maximum chip junction temperature (TJmax). TJmax, in C, may be calculated using equation: TJmax = TAmax + (PDmax x JA) where: TAmax is the maximum ambient temperature in C JA is the package junction-to-ambient thermal resistance in C/W PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax) PINTmax is the product of IDD and VDD, expressed in watts. This is the maximum chip internal power. PI/Omax represents the maximum power dissipation on output pins where: PI/Omax = (VOL * IOL) + [(VDD - VOH) * IOH], taking into account the actual VOL/IOL and VOH/IOH of the I/Os at the low and high level. Table 21. Package thermal characteristics Symbol JA Parameter VFQFPN32 - thermal resistance junction to ambient(1) Value Unit 26 C/W 1. Thermal resistance is based on the JEDEC JESD51-2 with a 4-layer PCB in a natural convection environment. DocID029660 Rev 1 27/31 31 Package information 6 STWBC-WA Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 6.1 VFQFPN32 package information Figure 17. VFQFPN32 package outline 28/31 DocID029660 Rev 1 STWBC-WA Package information Table 22. VFQFPN32 package mechanical data Dimensions (mm) Symbol Note: Min. Typ. Max. A 0.80 0.90 1.00 A1 0 0.02 0.05 A3 - 0.20 - b 0.18 0.25 0.30 D 4.85 5.00 5.15 D2 3.40 3.45 3.50 E 4.85 5.00 5.15 E2 3.40 3.45 3.50 e - 0.50 0.55 L 0.30 0.40 0.50 ddd - - 0.08 1. VFQFPN stands for "Thermally Enhanced Very thin Fine pitch Quad Flat Package No lead". 2. Very thin profile: 0.80 < A 1.00 mm. 3. Pin 1 can be identified via a package mold or marking option on the top surface. 4. Package outline exclusive of any mold flash dimensions and metal burrs. DocID029660 Rev 1 29/31 31 STWBC-WA development tools 7 STWBC-WA STWBC-WA development tools The development tool for the STWBC-WA controller is provided by the IAR with the C compiler, which provides start-to-finish control of application development including code editing, compilation, optimization and debugging. The hardware tool includes the ST-LINK/V2 in-circuit debugger/programmer (USB/SWIM). 8 Order codes Table 23. Silicon product order codes Order code Package Packaging STWBC-WA Tube VFQFPN32 STWBC-WATR 9 Tape and reel Revision history Table 24. Document revision history 30/31 Date Revision 30-Aug-2016 1 Changes Initial release. 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All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2016 STMicroelectronics - All rights reserved DocID029660 Rev 1 31/31 31