ADP1872-EVALZ/ADP1873-EVALZ User Guide
UG-057
One Technology Way • P. O . Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Evaluating the ADP1872/ADP1873 PWM Buck Controllers
See the last page for an important warning and disclaimers. Rev. A | Page 1 of 20
FEATURES
Wide power input voltage (VIN): 2.75 V to 20 V
Bias supply voltage (VDD) range: 2.75 V to 5.5 V
Available in 1.8 V fixed-output voltage
Available in 300 kHz, 600 kHz, and 1.0 MHz switching
frequency options
Available in power saving mode (PSM) for light loads
(ADP1873 only)
Starts into a precharged or preloaded output
APPLICATIONS
Perform basic evaluation board operations
Evaluate IC and application board performance
GENERAL DESCRIPTION
This document describes the evaluation board hardware for the
ADP1872/ADP1873 PWM buck controllers. The evaluation boards
can be used to evaluate the ADP1872 or ADP1873 and application
circuits using these ICs without requiring any additional software.
The ADP1872/ADP1873 are versatile current-mode, synchronous
step-down controllers that provide superior transient response,
optimal stability, and current limit protection by using a constant
on-time, pseudo-fixed frequency with a programmable current-
sense gain, current-control scheme. The ADP1873 is the power
saving mode (PSM) version of the device and is capable of pulse
skipping to maintain output regulation while achieving improved
system efficiency at light loads (see the ADP1872/ADP1873 data
sheet for more information). Both devices are available in a small,
10-lead MSOP package and can operate over the −40°C to +125°C
temperature range.
The ADP1872/ADP1873 evaluation boards employ a power input
voltage (VIN) that ranges between 2.75 V and 20 V and a bias supply
voltage (VDD) that ranges between 2.75 V and 5.5 V. Both inputs
can be tied together for application input voltage conditions equal
to or less than 5.5 V. The evaluation board is available in a fixed-
output voltage option (VOUT = 1.8 V), as well as in a 300 kHz,
600 kHz, or 1 MHz switching frequency (test trimmed in
production). The ADP1872/ADP1873 evaluation boards offer
an output accuracy of 2% over the full temperature range and
provide a high input voltage (VIN ± 10%) and a full-scale load
current up to 15 A.
TYPICAL APPLICATIONS CIRCUIT
+
COMP/EN BST
FB DRVH
GND SW
VDD DRVL
PGND
VIN
CC
CVDD
CVDD2
CC2
RC
RTOP
RBOT
VOUT
VDD = 2.75V
TO 5.5V
Q1
Q2
RRES
L
COUT
VOUT
CBST
LOAD
5A
CIN
VIN = 2.75V T O 20V
ADP1872/
ADP1873
08548-001
Figure 1.
08548-100
Figure 2. ADP1872 Evaluation Board Configured
for 300 kHz Switching Frequency Operation
The ADP1872/ADP1873 data sheet provides more information,
including details about how to modify the evaluation board while
maintaining system stability throughout the entire load current
range and, therefore, should be consulted in conjunction with
this user guide when using the evaluation boards.
UG-057 ADP1872-EVALZ/ADP1873-EVALZ User Guide
Rev. A | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Typical Applications Circuit ............................................................ 1
Revision History ............................................................................... 2
Evaluation Board Hardware ............................................................ 3
Setting Up the Evaluation Board ................................................ 3
Powering Up and Powering Down the Evaluation Board ....... 4
Enabling and Disabling the ADP1872/ADP1873 .................... 4
Evaluating the Performance of the ADP1872/ADP1873 ........ 4
Modifying the Evaluation Board ................................................ 5
Typical Performance Characteristics ..............................................6
Typical Application Circuits ......................................................... 10
Dual-Input, 300 kHz High Current Application Circuit ...... 10
Evaluation Board Schematics and Layout ................................... 11
1.8 V Output, 300 kHz, 14 A Application Circuit .................. 11
Layer 1 .......................................................................................... 12
Layer 2 .......................................................................................... 13
Layer 3 .......................................................................................... 14
Layer 4 .......................................................................................... 15
Bill of Materials ............................................................................... 16
1.8 V Output, 300 kHz, 14 A Application Circuit .................. 16
REVISION HISTORY
12/13—Rev. 0 to Rev. A
Deleted 3.3 V Fixed-Output Voltage Model ................... Universal
Deleted Single-Input, 600 kHz Application Circuit Section
and Figure 29 ............................................................................... 10
Updated ESD Caution and Legal Terms and Conditions ......... 18
3/10—Revision 0: Initial Version
ADP1872-EVALZ/ADP1873-EVALZ User Guide UG-057
Rev. A | Page 3 of 20
EVALUATION BOARD HARDWARE
Upon receipt of the ADP1872/ADP1873 evaluation board, the
following criteria have already been determined:
• The IC is either the ADP1872 (forced pulse-width modulation
[PWM]) or the ADP1873 (power saving mode [PSM]).
• The switching frequency is 300 kHz, 600 kHz, or 1 MHz.
SETTING UP THE EVALUATION BOARD
Before powering up the system, set up the evaluation board as
follows to ensure that all passive and active components are
properly soldered to the evaluation board:
1. Ensure that the Headers JP2 and J1 connections are correct
for a given application (see Table 1 and the Headers JP2
and J1 section).
2. Ensure that the main power supply (VIN) is off but set to 0 V,
and then connect the main power supply to the evaluation
board, connecting the positive terminal to TP_VIN1 and
the negative terminal to TP_PGND.
3. Optionally, place a current meter in series with the main
power supply to monitor the input current.
4. Ensure that the low input voltage supply (VDD) is off but set
to 0 V, and then connect the low input voltage supply to the
evaluation board, connecting the positive terminal to J1
and the negative terminal to TP_PGND.
5. Ensure that the electronic load is turned off, and then connect
the load to the evaluation board, connecting the positive
terminal to TP_VOUT1 and the negative terminal to
TP_PGND.
6. Optionally, connect a power resistor of the appropriate
value for your application across the TP_VOUT1 and
TP_PGND terminals of the evaluation board.
7. Optionally, to continually monitor VIN, VDD, and VOUT, solder
SMB jacks to each of the following measuring points: VIN1,
VOUT1, and VREG1 (see Figure 33).
Table 1. Header Connections
Header Input Voltage (V) Description of Connection
J1 ≤5.5 Floating (no jumper), single
input configuration.
>5.5 Connect to VDD (dual input
configuration), and, optionally,
add a voltmeter across J1 and
TP_PGND to monitor the low
input voltage.
JP2 ≤5.5 Jumper between VIN and VDD
(single input configuration).
>5.5 Open (no jumper), dual input
configuration.
JP3 N/A Jumper at all times.
Headers JP2 and J1
When the power input voltage is greater than 5.5 V, the device
is in dual input configuration. If this configuration is chosen,
ensure that Header JP2 is open (no jumper), and connect J1 to
VDD. Optionally, you can also add a voltmeter across J1 and
TP_PGND to monitor the low input voltage.
If the power input voltage is less than or equal to 5.5 V, the device is
in single input configuration. In this case, a jumper can be placed
on Header JP2 that connects VIN to VDD. If a jumper is used in
this way, leave Header J1 floating (no jumper), and ensure that
VIN does not exceed 5.5 V.
Header JP3
Always put a jumper on Header JP3 to connect the high voltage
input to Pin 1 (VIN) of the IC.
High Input Voltage Power Source (VIN)
Ensure that the main power supply equipment is turned off but set
to 0 V before connecting the main power supply to the evaluation
board. Place a current meter in series with this power supply to
monitor the input current. Connect the positive terminal (+) of
the power supply to the TP_VIN1 terminal of the evaluation board.
Connect the negative terminal of the power supply (−) to the
TP_PGND terminal of the evaluation board.
Low Input Voltage Supply for Bias (VDD)
Set the low input voltage supply to 0 V and make sure that it is
turned off before connecting the positive terminal (+) to Jumper J1
of the evaluation board. Connect the negative terminal (−) to
the TP_PGND terminal of the evaluation board.
Output Terminal
The output terminal (TP_VOUT1) of the ADP1872/ADP1873
evaluation board is equipped with a banana terminal plug similar
to TP_VIN1 and TP_PGND. The evaluation board is designed to
withstand load immediately upon power-up, but may be damaged
if the load is not properly connected to TP_VOUT1. Ensure that
the electronic load is turned off prior to connecting the positive
terminal (+) and negative terminal (−) to the VOUT and TP_PGND
terminals of the evaluation board, respectively. If a power resistor is
used, connect this device across the TP_VOUT1 and TP_PGND
terminals of the evaluation board.
Ensure that proper current values for your application are
programmed on the electronic load prior to activation and, if
applicable, that the correct power resistor value for your application
is in place before powering up the evaluation board.
DC Voltmeter on VIN, VDD, and VOUT
For more accurate dc measurements of VIN, VDD, and VOUT, add
a dedicated voltmeter for each of these voltage nodes (resources
permitting) to continually monitor VIN, VOUT, and VDD. This can
be done by placing an SMB jack on VIN1, VOUT2, VREG1 (see
Figure 33).
UG-057 ADP1872-EVALZ/ADP1873-EVALZ User Guide
Rev. A | Page 4 of 20
Placeholders for SMB jacks are integrated into each evaluation
board to facilitate such connections. Therefore, to accurately
measure VIN, connect the voltmeter’s positive terminal (+) to
the node where the positive terminal of the high voltage input
capacitors (C3 to C8) and the drain of Q1/Q2 meet, and connect
the voltmeter’s negative terminal (−) to the node where the negative
terminal of the input capacitors and the source terminal of Q3
meet. These SMB terminals are optimally placed to minimize
unnecessary voltage drops that may otherwise produce inaccurate
VIN dc measurements.
Similarly, for output voltage (VOUT) dc measurements, a place-
holder for an SMB terminal is positioned directly across the
positive and negative terminals of the output capacitor that
is farthest from the inductor terminal and source of Q3. For
accurate low input voltage (VDD) dc measurements, an SMB
terminal footprint is positioned as close as possible across C1,
which is laid out near the VDD pin (Pin 5) and the PGND pin
(Pin 7) of the ADP1872/ADP1873.
POWERING UP AND POWERING DOWN
THE EVALUATION BOARD
After completing the procedure described in the Setting Up the
Evaluation Board section, power up the evaluation board as
follows:
1. Apply power to the VDD pin.
2. Apply power to the VIN pin.
3. Slowly increase the VDD supply while monitoring the current
meter until VDD is equal to 5 V.
Because VIN is 0 V, IDD should jump between 120 µA (when
approaching the UVLO threshold of 2.65 V) to less than 1 mA
until VDD is equal to 5 V. Do not exceed 5.5 V on VDD. No
output (VOUT) regulation is expected yet because VIN is 0 V.
4. Slowly increase VIN up to 12 V.
When VIN is increased, VOUT begins regulating to the desired
voltage setpoint (via the VOUT dedicated voltmeter). Continue
to increase VIN up to 12 V. Do not exceed 20 V on VIN. Output
voltage regulation should occur regardless of whether there is
a load connected at the output.
5. After the output voltage is in regulation with the desired input
voltage, increase the electronic load to the desired value.
To power down the evaluation board,
1. Power down VIN.
2. Power down VDD.
ENABLING AND DISABLING
THE ADP1872/ADP1873
The ADP1872/ADP1873 evaluation board has a placeholder for
a switch (normally open) for the COMP/EN pin to allow you to
enable (open) and disable (closed) the ADP1872/ADP1873 on
the evaluation board. When closed, the switch shorts this pin to
ground, disabling the ADP1872/ADP1873. When the switch is
subsequently opened (released), the error amplifier brings the
voltage on this pin above the enable threshold of 285 mV, thus
enabling the IC, which causes the output voltage to regulate.
EVALUATING THE PERFORMANCE
OF THE ADP1872/ADP1873
Verifying the Switching Waveform
To verify the switching waveform,
1. Ensure that the oscilloscope, probe tips, and ground loop clip
are in good working condition; that the probe tips have been
calibrated per the manufacturer’s instructions and are clear
of debris and dirt; and that the ground loops do not have any
breaks or peels.
2. Set the operating mode of the respective oscilloscope to
DC Coupling in the oscilloscope’s Channel menu.
3. Set the bandwidth to its maximum value (≥150 MHz).
4. Set the vertical scale to 5 V per division and the timescale
(x-axis) to 1/(2 × fSW) per division, where fSW is the switching
frequency of the evaluation board.
5. Securely attach the ground loop clip onto the TP_PGND
terminal of the evaluation board. Ideally, the loop should
be as close as possible to the negative terminal of the high
input voltage capacitors (C3 to C8) and to the source of
MOSFET Q1.
6. Land or securely attach the probe tip to the drain of Q1.
7. Observe the subsequent switching waveform and jitter.
The resultant switching waveform should be between 0 V and
the value of VIN (that is, 12 V), and the jitter should be less than
or equal to 100 ns.
Observing the Output Voltage Ripple
To observe the output voltage ripple,
1. Set the operating mode of the respective oscilloscope to
AC Coupling in the oscilloscope’s Channel menu.
2. Set the vertical scale to 100 mV per division and the timescale
to 1/(2 × fSW).
3. Securely attach the ground loop clip onto the TP_PGND
terminal of the evaluation board. Ideally, the loop should
be as close as possible to the negative terminal (−) of the
farthest output capacitor from the inductor terminal, and
the probe tip should touch the positive terminal (+) of the
same output capacitor.
4. Observe the output voltage ripple.
Evaluating the Inductor Current Waveform
To evaluate the inductor current waveform,
1. Calibrate the current probe per the manufacturer’s
instructions.
2. Power up the system (see the Powering Up and Powering
Down the Evaluation Board section).
3. Solder a 3 inch wire loop (from 10 gauge to 14 gauge) between
the source of Q1 and the inductor terminal. The current probe
has a clamping mechanism and can clamp onto this wire to
measure the current traveling through the wire.
ADP1872-EVALZ/ADP1873-EVALZ User Guide UG-057
Rev. A | Page 5 of 20
4. Ensure that the current direction is toward the output voltage
(TP_VOUT1) and that the clamp of the current probe is in the
closed, or locked, position.
5. Set the vertical scale to one-third of the total load current that
the converter is designed to deliver.
6. Set the timescale similar to how the switching and output
ripple waveforms were set.
7. Observe the inductor current waveform.
Obtaining Efficiency Measurements
To obtain more accurate efficiency measurements,
1. Power down the device.
2. Remove the 3 inch wire loop between the source of Q1 and
the inductor terminal.
3. Power up the device.
4. Record the current and voltage readings.
Efficiency is calculated based on the measurements made between
the output and the input of the converter:
ININ
OUT
OUT
IV
IV
η×
×
=
where:
VOUT is the dc voltage readout by the voltmeter that is connected to
the SMB terminal of the evaluation board or by the voltmeter
that is connected across the output capacitor that is located
farthest from the inductor terminal.
IOUT is the digital readout produced by the electronic load
equipment.
VIN is the dc voltage readout by the voltmeter.
IIN is the current readout from the current meter in series
between the high input voltage supply equipment and the
TP_VIN1 terminal of the evaluation board.
Assessing Line Regulation
To assess the line regulation,
1. Var y the high input voltage.
2. Record the resultant changes on the dc level of the output
voltage (VOUT).
Examining Load Regulation
To examine the load regulation,
1. Var y the load current through electronic load adjustments.
2. Record the resultant changes on the dc level of the output
voltage (VOUT).
Observing Transient Response
To observe the transient response,
1. Power up the system (see the Powering Up and Powering
Down the Evaluation Board section).
2. Solder a 3 inch wire loop (from 10 gauge to 14 gauge)
between the source of Q1 and the inductor terminal.
3. Record instances where the output transient is out of phase
with the load. Such occurrences are caused by sudden changes
in the output load current and can be recorded by capturing
the inductor ripple current waveform and the output voltage
ac transient using the single acquisition feature of the
oscilloscope.
Evaluating Short-Circuit Protection
To evaluate the self-protection scheme of the ADP1873 during
output short-circuit events,
1. Achieve steady state regulation.
2. Short the voltage output (TP_VOUT1) to TP_PGND.
The system then enters hiccup mode and remains in this mode
until the violation disappears (see the ADP1872/ADP1873 data
sheet for more details).
MODIFYING THE EVALUATION BOARD
For any given ADP1872/ADP1873 evaluation board, an ADP1872
or ADP1873 IC can be used interchangeably as long as the pre-
trimmed frequency setpoint is the same for both ICs.
To maintain system stability throughout the entire load current
range, one component (passive or active) cannot be modified
without modifying the rest. Refer to the ADP1872/ADP1873
data sheet for information about how each of the following
elements can be adjusted, keeping in mind that any change
affects the entire system:
• Feedback resistor divider
• Inductor
• Output capacitor
• Compensation network
• Output filter impedance (ZFILT)
• Error amplifier output impedance (ZCOMP)
• Error amplifier gain (GM)
• Current-sense loop gain (GCS)
• Programmable current-sense gain (ACS)
• Valley current limit setting
• Crossover frequency
UG-057 ADP1872-EVALZ/ADP1873-EVALZ User Guide
Rev. A | Page 6 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
For the most up-to-date typical performance characteristics, see the ADP1872/ADP1873 data sheet.
100
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100 100k10k1k
EF FICIENCY ( %)
LOAD CURRENT ( mA)
WURTH IND: 744325120, L = 1.2µH, DCR: 2.0mΩ
INF INEO N F ETS : BS C04 2 N0 3MS G ( UPPER/LOW ER)
TA = 25°C
V
DD
= 5.5V, V
IN
= 5.5V ( PSM)
V
DD
= 5.5V, V
IN
= 16 . 5 V (PSM)
V
DD
= 5.5V, V
IN
= 5.5V
V
DD
= 5.5V, V
IN
= 16.5V
V
DD
= 5.5V, V
IN
= 13 V ( PSM)
V
DD
= 3.6V, V
IN
= 3.6V
V
DD
= 5.5V, V
IN
= 13V
V
DD
= 3.6V, V
IN
= 5.5V
08548-005
Figure 3. Efficiency—300 kHz, VOUT = 1.8 V
08548-010
100
20
30
25
35
40
45
50
55
60
65
70
75
80
85
90
95
100 100k10k1k
EF FICIENCY ( %)
LOAD CURRENT ( mA)
WURTH IND: 744303022, L = 0.22µH, DCR: 0.33mΩ
INF INEO N F ETs : BSC04 2 N03 MS G ( UPPER/LOW ER)
TA = 25°C
V
DD
= 5.5V,
V
IN
= 16 . 5 V (PSM) V
DD
= 5.5V, V
IN
= 5V (PSM )
V
DD
= 5.5V, V
IN
= 16.5V
V
DD
= 3.6V, V
IN
= 13V
V
DD
= 3.6V, V
IN
= 16.5V
V
DD
= 5.5V,
V
IN
= 13V
(PSM)
V
DD
= 5.5V, V
IN
= 13V
V
DD
= 5.5V,
V
IN
= 5V
Figure 4. Efficiency—1 MHz, VOUT = 1.8 V
1.821
1.816
1.811
1.806
1.801
1.796
1.791
5.50 6.95 8.40 9.85 11.30 12.75 14.20 15.65 17.10 18.55 20.00
OUTPUT VOLTAGE (V)
VIN (V)
LOAD = 15A
NO LOAD
VDD = 5V
TA = 25° C
08548-101
Figure 5. Line Regulation Plot for fSW = 300 kHz, VOUT = 1.8 V
1.815
1.813
1.811
1.809
1.807
1.805
1.803
1.801
01500 3000 4500 6000 7500 9000 10,500 12,000 13,500 15,000
OUTPUT VOLTAGE (V)
LOAD CURRENT ( mA)
V
IN
= 16.5V
V
IN
= 13V
08548-102
Figure 6. Load Regulation Plot for fSW = 300 kHz, VOUT = 1.8 V
Figure 7. Output Voltage Accuracy—300 kHz, VOUT = 1.8 V
2.649
2.658
2.657
2.656
2.655
2.654
2.653
2.652
2.651
2.650
–40 120100806040200–20
UVLO (V)
TEMPERATURE (°C)
08548-034
Figure 8. UVLO vs. Temperature
ADP1872-EVALZ/ADP1873-EVALZ User Guide UG-057
Rev. A | Page 7 of 20
CH1 50mV BWCH2 5A Ω
CH3 10V BWCH4 5V M400ns A CH2 3.90A
T 35.8%
1
2
3
4
OUTPUT VOLTAGE
INDUCTOR CURRE NT
SW NODE
LOW SIDE
08548-043
Figure 9. Power Saving Mode (PSM) Operational Waveform, 100 mA
CH1 50mV BWCH2 5A Ω
CH3 10V BWCH4 5V M4.0µs A CH2 3.90A
T 35.8%
1
2
3
4
OUTPUT VOLTAGE
INDUCTOR CURRE NT
SW NODE
LOW SIDE
08548-044
Figure 10. PSM Waveform at Light Load, 500 mA
CH1 5A Ω
CH3 10V CH4 100mV BW
M400ns A CH3 2.20V
T 30.6%
1
3
4
OUTPUT VOLTAGE
INDUCTOR CURRE NT
SW NODE
08548-045
Figure 11. CCM Operation at Heavy Load, 18 A
(See Figure 28 for Application Circuit)
CH1 10A Ω CH2 200mV BW
CH3 20V CH4 5V M2ms A CH1 3. 40A
T 75.6%
1
2
3
4
OUTPUT VOLTAGE
20A ST E P
SW NODE
LOW SIDE
08548-046
Figure 12. Load Transient Step—PSM Enabled, 20 A
(See Figure 28 for Application Circuit)
CH1 10A Ω CH2 200mV
BW
CH3 20V CH4 5V M20µs A CH1 3.40A
T 30.6%
1
2
3
4
OUTPUT VOLTAGE
20A POSI T I VE ST EP
SW NODE
LOW SIDE
08548-047
Figure 13. Positive Step During Heavy Load Transient Behavior—PSM Enabled,
20 A, VOUT = 1.8 V (See Figure 28 for Application Circuit)
CH1 10A Ω CH2 200mV
BW
CH3 20V CH4 5V M20µs A CH1 3.40A
T 48.2%
1
2
3
4
OUTPUT VOLTAGE
20A NEG ATIV E S TEP
SW NODE
LOW SIDE
08548-048
Figure 14. Negative Step During Heavy Load Transient Behavior—PSM Enabled,
20 A (See Figure 28 for Application Circuit)
UG-057 ADP1872-EVALZ/ADP1873-EVALZ User Guide
Rev. A | Page 8 of 20
CH1 10A Ω CH2 5V
CH3 20V CH4 200mV BW
M2ms A CH1 6. 20A
T 15.6%
1
2
3
4
OUTPUT VOLTAGE
20A ST E P
SW NODE
LOW SIDE
08548-049
Figure 15. Load Transient Step—Forced PWM at Light Load, 20 A
(See Figure 28 for Application Circuit)
CH1 10A Ω CH2 5V
CH3 20V CH4 200mV BW
M20µs A CH1 6.20A
T 43.8%
1
2
3
4
OUTPUT VOLTAGE
20A POSI T I VE ST EP
SW NODE
LOW SIDE
08548-050
Figure 16. Positive Step During Heavy Load Transient Behavior—Forced PWM
at Light Load, 20 A, VOUT = 1.8 V (See Figure 28 for Application Circuit)
CH1 10A Ω CH2 200mV
BW
CH3 20V CH4 5V M10µs A CH1 5.60A
T 23.8%
1
2
3
4
OUTPUT VOLTAGE
20A NEG ATIV E S TEP
SW NODE
LOW
SIDE
08548-051
Figure 17. Negative Step During Heavy Load Transient Behavior—Forced PWM
at Light Load, 20 A (See Figure 28 for Application Circuit)
CH1 2V
BW
CH2 5A Ω
CH3 10V CH4 5V M4ms A CH1 920mV
T 49.4%
1
2
3
4
OUTPUT VOLTAGE
INDUCTOR CURRE NT
SW NODE
LOW SIDE
08548-052
Figure 18. Output Short-Circuit Behavior Leading to Hiccup Mode
CH1 5V
BW
CH2 10A Ω
CH3 10V CH4 5V M10µs A CH2 8.20A
T 36.2%
1
2
3
4
OUTPUT VOLTAGE
INDUCTOR CURRE NT
SW NODE
LOW SIDE
08548-053
Figure 19. Magnified Waveform During Hiccup Mode
CH1 2V
BW
CH2 5A Ω
CH3 10V CH4 5V M2ms A CH1 720mV
T 32.8%
1
2
3
4
OUTPUT VOLTAGE
INDUCTOR CURRE NT
SW NODE
LOW SIDE
08548-054
Figure 20. Start-Up Behavior at Heavy Load, 18 A, 300 kHz
(See Figure 28 for Application Circuit)
ADP1872-EVALZ/ADP1873-EVALZ User Guide UG-057
Rev. A | Page 9 of 20
CH1 2V
BW
CH2 5A Ω
CH3 10V CH4 5V M4ms A CH1 720mV
T 41.6%
1
2
3
4
OUTPUT VOLTAGE
INDUCTOR CURRE NT
SW NODE
LOW SIDE
08548-055
Figure 21. Power-Down Waveform During Heavy Load
CH1 50mV BWCH2 5A Ω
CH3 10V BWCH4 5V M2µs A CH2 3.90A
T 35.8%
1
2
3
4
OUTPUT VOLTAGE
INDUCTOR CURRE NT
SW NODE
LOW SIDE
08548-056
Figure 22. Output Voltage Ripple Waveform During PSM Operation
at Light Load, 2 A
CH1 1V BWCH2 5A Ω
CH3 10V BWCH4 2V M1ms A CH1 1. 56V
T 63.2%
1
2
3
4
OUTPUT VOLTAGE
INDUCTOR CURRE NT
SW NODE
LOW SIDE
08548-057
Figure 23. Soft Start and RES Detect Waveform
2
CH2 5V
CH3 5V
MAT H 2V 40ns CH4 2V M40ns A CH2 4.20V
T 29.0%
3
M
4
HIGH SI DE
HS MINUS
SW
SW NODE
LOW SIDE T
A
= 25° C
08548-058
Figure 24. Output Drivers and SW Node Waveforms
2
CH2 5V
CH3 5V
MAT H 2V 40ns CH4 2V M40ns A CH2 4.20V
T 29.0%
3
M
4
HIGH SI DE
HS MINUS
SW
SW NODE
LOW SIDE 16ns (
t
f
, DRVL
)
25ns (
t
r
, DRVH
)
22ns (
t
pdh
, DRVH
)
T
A
= 25° C
08548-059
Figure 25. Upper-Side Driver Rising and Lower-Side Falling Edge Waveforms,
CIN = 4.3 nF (Upper-/Lower-Side MOSFET),
QTOTAL = 27 nC (VGS = 4.4 V (Q1), VGS = 5 V (Q3)
2
CH2 5V
CH3 5V
MAT H 2V 20ns CH4 2V M20ns A CH2 4.20V
T 39.2%
3
M
4
HIGH SI DE
HS MINUS
SW SW NODE
LOW SIDE
18ns (
t
r
, DRVL
)
24ns (
t
pdh
, DRVL
)
11ns (
t
f
, DRVH
)
T
A
= 25° C
08548-060
Figure 26. Upper-Side Driver Falling and Lower-Side Rising Edge Waveforms,
CIN = 4.3 nF (Upper-/Lower-Side MOSFET),
QTOTAL = 27 nC (VGS = 4.4 V (Q1), VGS = 5 V (Q3)
UG-057 ADP1872-EVALZ/ADP1873-EVALZ User Guide
Rev. A | Page 10 of 20
TYPICAL APPLICATION CIRCUITS
DUAL-INPUT, 300 kHz HIGH CURRENT APPLICATION CIRCUIT
MURAT A: ( HIGH V OL TAGE INPUT CAP ACIT ORS)
22µF , 25V, X7R, 1210 GRM32ER71E 226KE 15L
PANASONIC: ( OUT P UT CAPACI TORS )
270µF (SP-SERIES) 4V, 7mΩ EEFUE0G271LR
INFINEON MOSFETs:
BSC042N03MS G (BO TT OM)
BSC080N03MS G (T OP)
WURTH INDUCTO RS :
1µH, 3.3mΩ, 20A 7443552100
R5
100kΩ
Q3 Q4
Q1 Q2
HIGH VOLTAGE INPUT
V
IN
= 12V
C12
100nF
V
OUT
= 1.8V , 15A
C3
22µF C4
22µF C5
22µF C6
22µF C7
22µF
C23
270µF +
C22
270µF +
C21
270µF +
C20
270µF +
1.0µH
R6
2Ω
C13
1.5nF
R1 30kΩ
R2
15kΩ
V
OUT
1
VIN
10
BST
2
COMP/EN
9
SW
3
FB
8
DRVH
4
GND
7
PGND
5
VDD
6
DRVL
ADP1872/
ADP1873
C11
571pF
C10
57pF R3
47kΩ
C1
1µF
C2
0.1µF
LOW VOLTAGE INPUT
V
DD
= 5.0V
JP2
08548-088
JP3
Figure 27. Application Circuit for 12 V Input, 1.8 V Output, 15 A, 300 kHz (Q2/Q4 No Connect)
MURAT A: ( HIGH V OL TAGE INPUT CAP ACIT ORS)
22µF , 25V, X7R, 1210 GRM32ER71E 226KE 15L
PANASONIC: ( OUT P UT CAPACI TORS )
270µF (SP-SERIES) 4V, 7mΩ EEFUE0G271LR
INFINEON MOSFETs:
BSC042N03MS G (BO TT OM)
BSC080N03MS G (T OP)
WURTH INDUCTO RS :
0.72µH, 1.65mΩ, 35A 744325072
Q3 Q4
Q1 Q2
HIGH VOLTAGE INPUT
V
IN
= 13V
LOW VOLTAGE INPUT
V
DD
= 5V
C12
100nF
V
OUT
= 1.8V , 20A
C3
22µF C4
22µF C5
22µF C6
22µF C7
22µF
C23
270µF +
C22
270µF +
C21
270µF +
C20
270µF +
0.8µH
R6
2Ω
C13
1.5nF
R1 30kΩ
R2
15kΩ
V
OUT
1
VIN
10
BST
2
COMP/EN
9
SW
3
FB
8
DRVH
4
GND
7
PGND
5
VDD
6
DRVL
ADP1872/
ADP1873
C11
800pF
C10
80pF R3
33.5kΩ
C1
1µF
C2
0.1µF
JP2
08548-090
JP3
Figure 28. Application Circuit for 13 V Input, 1.8 V Output, 20 A, 300 kHz (Q2/Q4 No Connect)
ADP1872-EVALZ/ADP1873-EVALZ User Guide UG-057
Rev. A | Page 11 of 20
EVALUATION BOARD SCHEMATICS AND LAYOUT
This section provides the schematics for the 1.8 V output, 300 kHz, 14 A application circuit. For other application circuits, see the
ADP1872/ADP1873 data sheet for the recommended values for the external components.
1.8 V OUTPUT, 300 kHz, 14 A APPLICATION CIRCUIT
08548-103
R5
100kΩ
Q3 Q4
Q1 Q2
HIGH VOLTAGE INPUT
V
IN
= 13V
C12
100nF
V
OUT
= 1.8V , 14A
C3
22µF
C14
N/A C15
N/A C16
N/A C17
N/A C18
N/A C19
N/A
C4
22µF C5
22µF C6
22µF C7
22µF
VIN1 (SMB)
TP_VOUT1
(BANANA PLUG)
VOUT2 (SMB)
VREG1 (SMB)
C8
N/A
C24
N/A +
C22
270µF +C23
270µF +
C21
270µF +
C20
270µF +
L1
1.0µH
R6
2Ω
C13
1.5nF
R1 30kΩ
R2
15kΩ R4
0kΩ
V
OUT
1
VIN
10
BST
2
COMP/EN
9
SW
3
FB
8
DRVH
4
GND
7
PGND
5
VDD
6
DRVL
U1
ADP1872
C11
571pF
C10
57pF R3
47kΩ
C1
1µF
C2
0.1µF
LOW VOLTAGE INPUT
V
DD
= 5.0V
JP2
(HEADER)
(J1 HEADE R) TP _V IN1 (BANANA PLUG )
FB1 ( S M B)
TP_PGND
(BANANA PLUG)
JP3
Figure 29. 1.8 V Output, 300 kHz, 14 A Application Circuit
UG-057 ADP1872-EVALZ/ADP1873-EVALZ User Guide
Rev. A | Page 12 of 20
LAYER 1
08548-082
Figure 30. Layer 1
ADP1872-EVALZ/ADP1873-EVALZ User Guide UG-057
Rev. A | Page 13 of 20
LAYER 2
08548-083
Figure 31. Layer 2
UG-057 ADP1872-EVALZ/ADP1873-EVALZ User Guide
Rev. A | Page 14 of 20
LAYER 3
08548-084
Figure 32. Layer 3
ADP1872-EVALZ/ADP1873-EVALZ User Guide UG-057
Rev. A | Page 15 of 20
LAYER 4
08548-085
Figure 33. Layer 4
UG-057 ADP1872-EVALZ/ADP1873-EVALZ User Guide
Rev. A | Page 16 of 20
BILL OF MATERIALS
1.8 V OUTPUT, 300 kHz, 14 A APPLICATION CIRCUIT
Table 2.
Name
Reference
Designator Value Unit Manufacturer Description/Model
CVDD C1 1.0 µF Taiyo Yuden 1.0 µF, 6.3 V, X5R ceramic capacitor (0402), JMK105BJ105KV-F
CVDD C2 0.1 µF TDK 0.1 µF, 25 V, X5R ceramic capacitor (0402), C1005X5R1E104K
CIN C3 22 µF Murata 25 V, X7R, 1210 (3.2 mm × 2.5 mm × 2.5 mm) GRM32ER71E226KE15L
CIN C4 22 µF Murata 25 V, X7R, 1210 (3.2 mm × 2.5 mm × 2.5 mm) GRM32ER71E226KE15L
CIN C5 22 µF Murata 25 V, X7R, 1210 (3.2 mm × 2.5 mm × 2.5 mm) GRM32ER71E226KE15L
CIN C6 22 µF Murata 25 V, X7R, 1210 (3.2 mm × 2.5 mm × 2.5 mm) GRM32ER71E226KE15L
CIN C7 22 µF Murata 25 V, X7R, 1210 (3.2 mm × 2.5 mm × 2.5 mm) GRM32ER71E226KE15L
CIN C8 N/A N/A
CPAR C10 57 pF Taiyo Yuden1 ±10%, 50 V, X7R ceramic capacitor (0402)
CC C11 571 pF Taiyo Yuden1 ±5%, 50 V, C0H ceramic capacitor (0402)
CBST C12 100 nF Taiyo Yuden1 ±10%, 50 V, X7R ceramic capacitors (0603)
CSNUBBER C13 1.5 nF Taiyo Yuden1 ±10%, 50 V, X7R ceramic capacitors (0603)
COUT C14 N/A N/A
C
OUT
C15
N/A
N/A
COUT C16 N/A N/A
COUT C17 N/A N/A
COUT C18 N/A N/A
COUT C19 N/A N/A
C
OUT
C20
270
µF
Panasonic
SP-series, 4 V, 7 mΩ, 3.7 A EEFUE0G271LR (4.3 mm × 7.3 mm × 4.2 mm)
COUT C21 270 µF Panasonic SP-series, 4 V, 7 mΩ, 3.7 A EEFUE0G271LR (4.3 mm × 7.3 mm × 4.2 mm)
COUT C22 270 µF Panasonic SP-series, 4 V, 7 mΩ, 3.7 A EEFUE0G271LR (4.3 mm × 7.3 mm × 4.2 mm)
COUT C23 270 µF Panasonic SP-series, 4 V, 7 mΩ, 3.7 A EEFUE0G271LR (4.3 mm × 7.3 mm × 4.2 mm)
COUT C24 N/A N/A
RTOP R1 30 kΩ Vishay1 ±1% resistors (0603)
RBOT R2 15 kΩ Vishay1 ±1% resistors (0603)
RC R3 47 kΩ Vishay1 ±1% resistors (0603)
RGAT E R4 0 kΩ Vishay1 ±1% resistors (0603)
RRES R5 100 kΩ Vishay1 ±1% resistors (0603)
RSNUBBER R6 2 Ω Vishay1 ±1% resistors (0603)
Top MOSFET Q1 N/A N/A Infineon BSC080N03MS G
Top MOSFET Q2 N/A N/A Infineon BSC080N03MS G
Bottom MOSFET Q3 N/A N/A Infineon BSC080N03MS G
Bottom MOSFET Q4 N/A N/A Infineon BSC080N03MS G
Inductor L1 1.0 µH Würth Elek 7443251200
Header
J1
N/A
N/A
Header
JP2
N/A
N/A
Header JP3 N/A N/A
Banana Plugs TP_VIN1 N/A N/A
Banana Plugs TP_PGND N/A N/A
Banana Plugs TP_VOUT1 N/A N/A
Controller/Driver U1 N/A N/A Analog Devices ADP1872ARMZ-0.3-R72 (LDT) or ADP1873ARMZ-0.3-R72 (LDF)
Diode D3 N/A N/A
1 Components from other manufacturers can also be used, as long as the characteristics listed in the corresponding description are met.
2 Z = RoHS Compliant Part.
ADP1872-EVALZ/ADP1873-EVALZ User Guide UG-057
Rev. A | Page 17 of 20
NOTES
UG-057 ADP1872-EVALZ/ADP1873-EVALZ User Guide
Rev. A | Page 18 of 20
NOTES
ADP1872-EVALZ/ADP1873-EVALZ User Guide UG-057
Rev. A | Page 19 of 20
NOTES
UG-057 ADP1872-EVALZ/ADP1873-EVALZ User Guide
Rev. A | Page 20 of 20
NOTES
ESD Caution
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circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
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