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FDMS86300 N-Channel PowerTrench(R) MOSFET 80 V, 122 A, 3.9 m Features General Description Max rDS(on) = 3.9 m at VGS = 10 V, ID = 19 A This N-Channel MOSFET has been designed specifically to improve the overall efficiency and to minimize switch node ringing of DC/DC converters using either synchronous or conventional switching PWM controllers.It has been optimized for low gate charge, low rDS(on), fast switching speed and body diode reverse recovery performance. Max rDS(on) = 5.5 m at VGS = 8 V, ID = 15.5 A Advanced Package and Silicon combination for low rDS(on) and high efficiency Next generation enhanced engineered for soft recovery body diode technology, Applications MSL1 robust package design OringFET / Load Switching 100% UIL tested DC-DC Conversion RoHS Compliant Bottom Top Pin 1 S D D D S S G D 5 4 G D 6 3 S D 7 2 S D 8 1 S D Power 56 MOSFET Maximum Ratings TA = 25 C unless otherwise noted Symbol VDS Drain to Source Voltage Parameter VGS Gate to Source Voltage Drain Current -Continuous ID TC = 25 C -Continuous TC = 100 C TA = 25 C -Pulsed PD TJ, TSTG Power Dissipation TC = 25 C Power Dissipation TA = 25 C Units V 20 V 122 -Continuous Single Pulse Avalanche Energy EAS Ratings 80 78 (Note 1a) 19 (Note 4) 556 (Note 3) 252 104 (Note 1a) Operating and Storage Junction Temperature Range 2.5 -55 to +150 A mJ W C Thermal Characteristics RJC Thermal Resistance, Junction to Case RJA Thermal Resistance, Junction to Ambient 1.2 (Note 1a) 50 C/W Package Marking and Ordering Information Device Marking FDMS86300 Device FDMS86300 (c)2012 Fairchild Semiconductor Corporation FDMS86300 Rev.1.4 Package Power 56 1 Reel Size 13 '' Tape Width 12 mm Quantity 3000 units www.fairchildsemi.com FDMS86300 N-Channel PowerTrench(R) MOSFET December 2015 Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 A, VGS = 0 V BVDSS TJ Breakdown Voltage Temperature Coefficient ID = 250 A, referenced to 25 C IDSS Zero Gate Voltage Drain Current VDS = 64 V, VGS = 0 V 1 A IGSS Gate to Source Leakage Current VGS = 20 V, VDS = 0 V 100 nA 4.5 V 80 V 39 mV/C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 A VGS(th) TJ Gate to Source Threshold Voltage Temperature Coefficient ID = 250 A, referenced to 25 C -11 VGS = 10 V, ID = 19 A 3.2 rDS(on) Static Drain to Source On Resistance VGS = 8 V, ID = 15.5 A 3.8 5.5 VGS = 10 V, ID = 19 A, TJ = 125 C 5.0 5.8 VDS = 10 V, ID = 19 A 60 gFS Forward Transconductance 2.5 3.4 mV/C 3.9 m S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate Resistance VDS = 40 V, VGS = 0 V, f = 1 MHz 5325 7082 pF 957 1272 pF 26 63 pF 1.2 Switching Characteristics td(on) Turn-On Delay Time 31 50 tr Rise Time 43 ns td(off) Turn-Off Delay Time VDD = 40 V, ID = 19 A, VGS = 10 V, RGEN = 6 26 36 58 ns tf Fall Time 9 18 ns Qg Total Gate Charge VGS = 0 V to 10 V 72 86 nC Qg Total Gate Charge VGS = 0 V to 8 V 59 71 Qgs Gate to Source Charge Qgd Gate to Drain "Miller" Charge VDD = 40 V, ID = 19 A ns nC 28.2 nC 14.9 nC Drain-Source Diode Characteristics VSD Source to Drain Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0 V, IS = 2.1 A (Note 2) 0.71 1.2 VGS = 0 V, IS = 19 A (Note 2) 0.81 1.3 IF = 19 A, di/dt = 100 A/s IF = 19 A, di/dt = 300 A/s V 57 90 ns 50 80 nC 48 77 ns 103 165 nC Notes: 1. RJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RJC is guaranteed by design while RCA is determined by the user's board design. a) 50 C/W when mounted on a 1 in2 pad of 2 oz copper b) 125 C/W when mounted on a minimum pad of 2 oz copper. 2. Pulse Test: Pulse Width < 300 s, Duty cycle < 2.0%. 3. EAS of 252 mJ is based on starting TJ = 25 C, L = 0.3 mH, IAS = 41 A, VDD = 72 V, VGS = 10 V. 4. Pulse Id limited by junction temperature, td 100 s, please refer to SOA curve for more details. (c)2012 Fairchild Semiconductor Corporation FDMS86300 Rev.1.4 2 www.fairchildsemi.com FDMS86300 N-Channel PowerTrench(R) MOSFET Electrical Characteristics TJ = 25 C unless otherwise noted 250 ID, DRAIN CURRENT (A) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 5 VGS = 8 V VGS = 7 V 200 VGS = 6.5 V VGS = 10 V 150 VGS = 6 V 100 VGS = 5.5 V 50 PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX 0 0 1 2 3 4 5 VGS = 5.5 V 4 VGS = 6 V VGS = 6.5 V 3 VGS = 7 V 2 VGS = 8 V 1 0 0 50 Figure 1. On-Region Characteristics 200 250 12 ID = 19 A VGS = 10 V rDS(on), DRAIN TO 1.6 1.4 1.2 1.0 0.8 0.6 -75 -50 SOURCE ON-RESISTANCE (m) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 150 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 1.8 IS, REVERSE DRAIN CURRENT (A) 200 VDS = 5 V 150 TJ = 150 oC 100 TJ = 25 oC 50 TJ = -55 oC 4 5 6 7 TJ = 125 oC 6 3 TJ = 25 oC 6 7 8 9 300 100 10 TJ = 150 oC 1 TJ = 25 oC 0.1 TJ = -55 oC 0.01 0.001 0.0 8 VGS = 0 V 0.2 0.4 0.6 0.8 1.0 VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics Figure 6. Source to Drain Diode Forward Voltage vs Source Current (c)2012 Fairchild Semiconductor Corporation FDMS86300 Rev.1.4 10 Figure 4. On-Resistance vs Gate to Source Voltage PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX 3 9 VGS, GATE TO SOURCE VOLTAGE (V) 250 2 PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX ID = 19 A 0 5 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (oC) Figure 3. Normalized On- Resistance vs Junction Temperature ID, DRAIN CURRENT (A) 100 ID, DRAIN CURRENT (A) VDS, DRAIN TO SOURCE VOLTAGE (V) 0 VGS = 10 V PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX 3 1.2 www.fairchildsemi.com FDMS86300 N-Channel PowerTrench(R) MOSFET Typical Characteristics TJ = 25 C unless otherwise noted 10000 VGS, GATE TO SOURCE VOLTAGE (V) 10 ID = 19 A Ciss VDD = 40 V VDD = 30 V CAPACITANCE (pF) 8 VDD = 50 V 6 4 1000 2 Coss 100 10 Crss f = 1 MHz VGS = 0 V 0 0 10 20 30 40 50 60 70 1 0.1 80 1 Figure 7. Gate Charge Characteristics 80 Figure 8. Capacitance vs Drain to Source Voltage 140 ID, DRAIN CURRENT (A) 100 IAS, AVALANCHE CURRENT (A) 10 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) TJ = 25 oC TJ = 100 oC 10 TJ = 125 oC 105 VGS = 10 V 70 VGS = 6 V 35 o RJC = 1.2 C/W 1 0.01 0.1 1 10 100 0 25 500 50 75 20000 P(PK), PEAK TRANSIENT POWER (W) ID, DRAIN CURRENT (A) 100 10 s THIS AREA IS LIMITED BY rDS(on) 100 s SINGLE PULSE TJ = MAX RATED 1 ms RJC = 1.2 oC/W TC = 25 oC 0.1 0.1 150 Figure 10. Maximum Continuous Drain Current vs Case Temperature 1000 1 125 o Figure 9. Unclamped Inductive Switching Capability 10 100 TC, CASE TEMPERATURE ( C) tAV, TIME IN AVALANCHE (ms) CURVE BENT TO MEASURED DATA 1 10 10 ms 100 ms/DC 100 500 TC = 25 oC 1000 100 50 -5 10 -4 10 -3 10 -2 10 -1 10 1 t, PULSE WIDTH (sec) VDS, DRAIN to SOURCE VOLTAGE (V) Figure 11. Forward Bias Safe Operating Area (c)2012 Fairchild Semiconductor Corporation FDMS86300 Rev.1.4 SINGLE PULSE RJC = 1.2 oC/W 10000 Figure 12. Single Pulse Maximum Power Dissipation 4 www.fairchildsemi.com FDMS86300 N-Channel PowerTrench(R) MOSFET Typical Characteristics TJ = 25 C unless otherwise noted 2 NORMALIZED THERMAL IMPEDANCE, ZJC 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 NOTES: ZJC(t) = r(t) x RJC 0.01 RJC = 1.2 C/W Peak TJ = PDM x ZJC(t) + TC Duty Cycle, D = t1 / t2 SINGLE PULSE 0.001 -5 10 -4 10 -3 -2 10 10 -1 10 1 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Case Transient Thermal Response Curve (c)2012 Fairchild Semiconductor Corporation FDMS86300 Rev.1.4 5 www.fairchildsemi.com FDMS86300 N-Channel PowerTrench(R) MOSFET Typical Characteristics TJ = 25 C unless otherwise noted PQFN8 5X6, 1.27P CASE 483AE ISSUE A 5.10 PKG CL 8 5.10 3.91 A SEE DETAIL B B 5 1.27 8 7 6 5 0.77 4.52 PKG CL 5.85 5.65 6.15 3.75 6.61 KEEP OUT AREA 1.27 1 4 1 TOP VIEW 2 3 4 0.61 1.27 3.81 OPTIONAL DRAFT ANGLE MAY APPEAR ON FOUR SIDES OF THE PACKAGE SEE DETAIL C 5.00 4.80 LAND PATTERN RECOMMENDATION 0.35 0.15 0.10 C 0.05 0.00 SIDE VIEW 8X 0.08 C 5.20 4.80 1.10 0.90 3.81 0.35 0.15 DETAIL C SCALE: 2:1 1.27 0.51 (8X) 0.31 (0.34) 0.10 1 2 3 C A B 4 0.76 0.51 (0.52) 6.25 5.90 3.48+0.30 -0.10 (0.50) (0.30) (2X) 8 0.20+0.10 -0.15 (8X) 7 6 3.96 3.61 BOTTOM VIEW 0.30 0.05 5 C SEATING PLANE DETAIL B SCALE: 2:1 NOTES: UNLESS OTHERWISE SPECIFIED A. PACKAGE STANDARD REFERENCE: JEDEC MO-240, ISSUE A, VAR. AA,. B. DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. C. ALL DIMENSIONS ARE IN MILLIMETERS. D. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-2009. E. IT IS RECOMMENDED TO HAVE NO TRACES OR VIAS WITHIN THE KEEP OUT AREA. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. "Typical" parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. 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