CS5342 105 dB, 192 kHz, Multi-bit Audio A/D Converter Features General Description The CS5342 is a complete analog-to-digital converter for digital audio systems. It performs sampling, analog-todigital conversion and anti-alias filtering, generating 24-bit values for both left and right inputs in serial form at sample rates up to 200 kHz per channel. Advanced Multi-bit Delta-Sigma Architecture 24-bit Conversion Supports all audio sample rates including 192 kHz. 105 dB Dynamic Range at 5 V The CS5342 uses a 5th-order, multi-bit Delta-Sigma modulator followed by digital filtering and decimation, which removes the need for an external anti-alias filter. -98 dB THD+N High-pass Filter to Remove DC Offsets Low-latency Digital Filter The CS5342 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as set-top boxes, DVD-karaoke players, DVD recorders, A/V receivers, and automotive applications. Automatic Mode Selection ORDERING INFORMATION Analog/Digital Core Supplies From 3.3 V to 5 V Supports logic levels between 2.5 V and 5 V. CS5342-CZZ Lead-free CS5342-DZZ Lead-free CDB5342 Supports 384x MCLK/LRCK Ratios. VQ FILT+ VL 2.5V - 5.0V SCLK LRCK SDOUT REFGND -10 to 70 C -40 to 85 C MCLK RST Serial Output Interface Voltage Reference 16-pin TSSOP 16-pin TSSOP Evaluation Board M0 M1 + AINL LP Filter Q S/H Digital Decimation Filter High Pass Filter Digital Decimation Filter High Pass Filter DAC + AINR LP Filter Q S/H DAC VA 3.3V - 5.0V GND VD 3.3V - 5.0V Preliminary Product Information This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. www.cirrus.com Copyright (c) Cirrus Logic, Inc. 2004 (All Rights Reserved) AUG `04 DS608PP2 CS5342 TABLE OF CONTENTS 1 CHARACTERISTICS AND SPECIFICATIONS ......................................................................... 4 SPECIFIED OPERATING CONDITIONS ................................................................................. 4 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 4 ANALOG CHARACTERISTICS (CS5342-CZZ) ....................................................................... 5 DIGITAL FILTER CHARACTERISTICS.................................................................................... 7 DC ELECTRICAL CHARACTERISTICS................................................................................. 10 DIGITAL CHARACTERISTICS ............................................................................................... 10 THERMAL CHARACTERISTICS............................................................................................ 10 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT ................................................. 11 2 PIN DESCRIPTION ................................................................................................................. 13 3 TYPICAL CONNECTION DIAGRAM ....................................................................................... 14 4 APPLICATIONS ....................................................................................................................... 15 4.1 Single, Double, and Quad Speed Modes ......................................................................... 15 4.2 Operation as Either a Clock Master or Slave ................................................................... 15 4.2.1 Operation as a Clock Master ............................................................................... 16 4.2.2 Operation as a Clock Slave ................................................................................. 16 4.2.3 Master Clock ....................................................................................................... 17 4.3 Serial Audio Interface ....................................................................................................... 17 4.4 Power-up Sequence ........................................................................................................ 18 4.5 Analog Connections ......................................................................................................... 18 4.6 Grounding and Power Supply Decoupling ....................................................................... 18 4.7 Synchronization of Multiple Devices ................................................................................ 19 4.8 Capacitor Size on the Reference Pin (FILT+) .................................................................. 19 5 PARAMETER DEFINITIONS ................................................................................................... 20 6 PACKAGE DIMENSIONS ....................................................................................................... 21 7. REVISION HISTORY .............................................................................................................. 22 Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com/ IMPORTANT NOTICE LEGAL NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. 2 DS608PP2 CS5342 LIST OF FIGURES Figure 1. Single Speed Stopband Rejection .................................................................................. 8 Figure 2. Single Speed Stopband Rejection (detail) ...................................................................... 8 Figure 3. Single Speed Transition Band (detail) ............................................................................ 8 Figure 4. Single Speed Passband Ripple ...................................................................................... 8 Figure 5. Double Speed Stopband Rejection ................................................................................. 8 Figure 6. Double Speed Stopband Rejection (detail) ..................................................................... 8 Figure 7. Double Speed Transition Band (detail) ........................................................................... 9 Figure 8. Double Speed Passband Ripple ..................................................................................... 9 Figure 9. Quad Speed Stopband Rejection ................................................................................... 9 Figure 10. Quad Speed Stopband Rejection (detail) ..................................................................... 9 Figure 11. Quad Speed Transition Band (detail) ............................................................................ 9 Figure 12. Quad Speed Passband Ripple ...................................................................................... 9 Figure 13. Master Mode, Left Justified SAI .................................................................................. 12 Figure 14. Slave Mode, Left Justified SAI .................................................................................... 12 Figure 15. Master Mode, I2S SAI ................................................................................................. 12 Figure 16. Slave Mode, I2S SAI ................................................................................................... 12 Figure 17. Typical Connection Diagram ....................................................................................... 14 Figure 18. CS5342 Master Mode Clocking .................................................................................. 16 Figure 19. Left-Justified Serial Audio Interface ............................................................................ 17 Figure 20. I2S Serial Audio Interface ............................................................................................ 17 Figure 21. CS5342 Recommended Analog Input Buffer .............................................................. 18 Figure 22. CS5342 THD+N versus Frequency ............................................................................ 19 LIST OF TABLES Table 1. Speed Modes and the Associated Output Sample Rates (Fs)........................................ 15 Table 2. CS5342 Mode Control..................................................................................................... 15 Table 3. Master Clock (MCLK) Ratios........................................................................................... 17 Table 4. Master Clock (MCLK) Frequencies for Standard Audio Sample Rates .......................... 17 Table 5. Revision History .............................................................................................................. 22 DS608PP2 3 CS5342 1 CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at typical supply voltages and TA = 25C.) SPECIFIED OPERATING CONDITIONS (GND = 0 V, all voltages with respect to 0 V.) Parameter Symbol Min Typ Max Unit Analog Digital Logic VA VD VL 3.14 3.14 2.38 (Note 1) 3.3 3.3 5.25 5.25 5.25 V V V Commercial (-CZZ) TAC -10 - 70 C Power Supplies (Notes 2, 3) Ambient Operating Temperature Notes: 1. This part is specified at typical analog voltages of 3.3 V and 5.0 V. See Analog Characteristics (CS5342CZZ) below for details. 2. In Quad-Speed Slave Mode, the CS5342 is only specified for operation with VA and VD at 5 V, 5%. ABSOLUTE MAXIMUM RATINGS (GND = 0 V, All voltages with respect to ground.) (Note 3) Parameter Symbol Min Max Units Analog Logic Digital VA VL VD -0.3 -0.3 -0.3 +6.0 +6.0 +6.0 V V V Input Current (Note 4) Iin - 10 mA Analog Input Voltage (Note 5) VIN GND-0.7 VA+0.7 V Digital Input Voltage (Note 5) DC Power Supplies: VIND -0.7 VL+0.7 V Ambient Operating Temperature (Power Applied) TA -50 +95 C Storage Temperature Tstg -65 +150 C Notes: 3. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 4. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SRC latch-up. 5. The maximum over/under voltage is limited by the input current. 4 DS608PP2 CS5342 ANALOG CHARACTERISTICS (CS5342-CZZ) Test conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz. Parameter VA = 3.3 V Single Speed Mode Fs = 48 kHz Dynamic Range A-weighted unweighted Total Harmonic Distortion + Noise (Note 6) -1 dB -20 dB -60 dB Double Speed Mode Fs = 96 kHz Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise (Note 6) -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB Quad Speed Mode (Note 2) Fs = 192 kHz Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise (Note 6) -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB VA = 5.0 V Single Speed Mode Fs = 48 kHz Dynamic Range A-weighted unweighted Total Harmonic Distortion + Noise (Note 6) -1 dB -20 dB -60 dB Double Speed Mode Fs = 96 kHz Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise 40 kHz bandwidth DS608PP2 (Note 6) -1 dB -20 dB -60 dB -1 dB Symbol Min Typ Max Unit 96 93 102 99 - dB dB - -95 -79 -39 -89 - dB dB dB 96 93 - 102 99 96 - dB dB dB - -95 -79 -39 -87 -89 - dB dB dB dB 96 93 - 102 99 96 - dB dB dB - -95 -79 -39 -87 -89 - dB dB dB dB 99 96 105 102 - dB dB - -98 -82 -42 -92 - dB dB dB 99 96 - 105 102 99 - dB dB dB - -98 -82 -42 -95 -92 - dB dB dB dB THD+N THD+N THD+N THD+N THD+N 5 CS5342 Quad Speed Mode (Note 2) Dynamic Range Fs = 192 kHz A-weighted unweighted 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise (Note 6) -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB Dynamic Performance for All Modes Interchannel Isolation DC Accuracy Interchannel Gain Mismatch Gain Error Input Impedance 6 105 102 99 - dB dB dB - -98 -82 -42 -95 -92 - dB dB dB dB - 90 - dB -3 0.1 - - dB % - THD+N Gain Drift Analog Input Characteristics Full-scale Input Voltage Note: 99 96 - 100 3 - ppm/C 0.54*VA 0.56*VA 0.58*VA Vpp 18 - - k 6. Referred to the typical full-scale input voltage DS608PP2 CS5342 DIGITAL FILTER CHARACTERISTICS Parameter (Note 7) Symbol Min Typ Max Unit 0 - 0.4896 Fs -0.1 - 0.035 dB 0.5688 - - Fs Single Speed Mode Passband (-0.1 dB) Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) tgd 70 - - dB - 12/Fs - s 0 - 0.4896 Fs Double Speed Mode Passband (-0.1 dB) Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) tgd -0.1 - 0.058 dB 0.5604 - - Fs 69 - - dB - 9/Fs - s 0 - 0.2604 Fs -0.1 - 0.058 dB 0.5000 - - Fs Quad Speed Mode (Note 2) Passband (-0.1 dB) Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) tgd 60 - - dB - 5/Fs - s - 1 20 - Hz Hz - 10 - Deg - - 0 dB High Pass Filter Characteristics Frequency Response Phase Deviation Passband Ripple Filter Settling Time Note: -3.0 dB -0.13 dB (Note 7) @ 20 Hz (Note 7) 105/Fs s 7. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 1 to 12) are normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. DS608PP2 7 0 0 -10 -2 0 -10 -2 0 -3 0 -4 0 -3 0 -4 0 Amplitude (dB) Amplitude (dB) CS5342 - 50 -6 0 - 70 -8 0 -9 0 - 10 0 - 110 - 12 0 - 13 0 - 50 -6 0 - 70 -8 0 -9 0 - 10 0 - 110 - 12 0 - 13 0 - 14 0 0 .0 0 .1 0 .2 0 .3 0 .4 0 .5 0 .6 0 .7 0 .8 0 .9 - 14 0 0 .4 0 1.0 0 .4 2 Fr e qu e n cy (no r m aliz e d to Fs ) 0 .10 0 .0 8 -2 0 .0 6 Amplitude (dB) Amplitude (dB) 0 -3 -4 -5 -6 0 .52 0 .54 0 .56 0 .58 0 .6 0 -7 0 .0 2 0 .0 0 -0 .0 2 -0 .0 4 -8 -0 .0 6 -9 -0 .0 8 -0 .10 0 .4 6 0 .4 7 0 .4 8 0 .4 9 0 .5 0 .51 0 .52 0 .53 0 .54 0 0 .55 0 .0 5 0 .2 0 .3 0 .4 0 .5 0 .6 0 .7 0 .8 0 .15 0 .2 0 .2 5 0 .3 0 .3 5 0 .4 0 .4 5 0 .5 Figure 4. Single Speed Passband Ripple Amplitude (dB) 0 -10 -2 0 -3 0 -4 0 -50 -6 0 -70 -8 0 -9 0 -10 0 -110 -12 0 -13 0 -14 0 0 .1 0 .1 Fr e qu e n cy (n or m aliz e d to Fs ) Figure 3. Single Speed Transition Band (detail) Amplitude (dB) 0 .50 0 .0 4 Fr e qu e n cy (n or m aliz e d to Fs ) 0 .9 1.0 Fr e qu e n cy (no r m aliz e d to Fs ) Figure 5. Double Speed Stopband Rejection 8 0 .4 8 Figure 2. Single Speed Stopband Rejection (detail) -1 0 .0 0 .4 6 Fr e q ue n cy (no r m aliz e d to Fs ) Figure 1. Single Speed Stopband Rejection -10 0 .4 5 0 .4 4 0 -10 -2 0 -3 0 -4 0 -50 -6 0 -70 -8 0 -9 0 -10 0 -110 -12 0 -13 0 -14 0 0 .4 0 0 .4 2 0 .4 4 0 .4 6 0 .4 8 0 .50 0 .52 0 .54 0 .56 0 .58 0 .6 0 Fr e q ue n cy (no r m aliz e d to Fs ) Figure 6. Double Speed Stopband Rejection (detail) DS608PP2 0 0 .10 -1 0 .0 8 -2 0 .0 6 Amplitude (dB) Amplitude (dB) CS5342 -3 -4 -5 -6 -7 0 .0 4 0 .0 2 0 .0 0 -0 .0 2 -0 .0 4 -8 -0 .0 6 -9 -0 .0 8 -10 0 .4 6 0 .4 7 0 .4 8 0 .4 9 0 .50 0 .51 -0 .10 0 .0 0 0 .52 Fr e qu e n cy (n or m aliz e d to Fs ) 0 .2 0 .3 0 .4 0 .5 0 .6 0 .7 0 .8 0 .15 0 .2 0 0 .2 5 0 .3 0 0 .3 5 0 .4 0 0 .4 5 0 .50 Figure 8. Double Speed Passband Ripple Amplitude (dB) Amplitude (dB) 0 -10 -2 0 -3 0 -4 0 -50 -6 0 -70 -8 0 -9 0 -10 0 -110 -12 0 -13 0 -14 0 0 .1 0 .10 Fr e qu e n cy (n or m aliz e d to Fs ) Figure 7. Double Speed Transition Band (detail) 0 .0 0 .0 5 0 .9 0 -10 -2 0 -3 0 -4 0 -50 -6 0 -70 -8 0 -9 0 -10 0 -110 -12 0 -13 0 -14 0 1.0 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 Fr e qu e n cy (no r m aliz e d to Fs ) Fr e qu e n cy (no r m aliz e d to Fs ) Figure 9. Quad Speed Stopband Rejection Figure 10. Quad Speed Stopband Rejection (detail) 0 .10 -2 0 .0 8 -3 0 .0 6 Amplitude (dB) Amplitude (dB) 0 -1 -4 -5 -6 -7 -8 -9 -10 0 .10 0 .0 2 0 .0 0 -0 .0 2 -0 .0 4 -0 .0 6 -0 .0 8 0 .15 0 .2 0 0 .2 5 0 .3 0 0 .3 5 0 .4 0 0 .4 5 0 .50 Fr e qu e n cy (n or m aliz e d to Fs ) Figure 11. Quad Speed Transition Band (detail) DS608PP2 0 .0 4 -0 .10 0 .0 0 0 .0 3 0 .0 5 0 .0 8 0 .10 0 .13 0 .15 0 .18 0 .2 0 0 .2 3 0 .2 5 0 .2 8 Fr e qu e ncy (n or m aliz e d to Fs ) Figure 12. Quad Speed Passband Ripple 9 CS5342 DC ELECTRICAL CHARACTERISTICS (GND = 0 V, all voltages with respect to 0 V. MCLK=18.432 MHz; Master Mode; refer to Note 2) Parameter Symbol Min Typ Max Unit Positive Analog Positive Digital Positive Logic VA VD VL 3.14 3.14 2.38 - 5.25 5.25 5.25 V V V VA = 5 V VA = 3.3 V VL,VD = 5 V VL,VD = 3.3 V IA IA ID ID - 21 18.2 15 9 23.1 20 16.5 10 mA mA mA mA VA = 5 V VL,VD=5 V IA ID - 1.5 0.4 - mA mA VL, VD, VA = 5 V VL, VD, VA = 3.3 V (Power-Down Mode) - - 180 90 9.5 198 100 - mW mW mW PSRR - 65 - dB VQ Nominal Voltage Output Impedance - VA/2 25 - k Filt+ Nominal Voltage Output Impedance Maximum allowable DC current source/sink - VA 36 0.01 - DC Power Supplies: Power Supply Current (Normal Operation) Power Supply Current (Power-down Mode) (Note 8) Power Consumption (Normal Operation) Power Supply Rejection Ratio (1 kHz) (Note 9) V V k mA Notes: 8. Power-down Mode is defined as RST = Low with all clocks and data lines held static. 9. Valid with the recommended capacitor values on FILT+ and VQ as shown in the "Typical Connection Diagram". DIGITAL CHARACTERISTICS Parameter Symbol Min Typ Max Units High-level Input Voltage (% of VL) VIH 70% - - V Low-level Input Voltage (% of VL) VIL - - 30% V High-level Output Voltage at Io = 100 A (% of VL) VOH 70% - - V Low-level Output Voltage at Io =100 A (% of VL) VOL - - 15% V Iin - - 10 A Typ Max Unit - - 135 C - 75 - C/W Input Leakage Current THERMAL CHARACTERISTICS Parameter Symbol Allowable Junction Temperature Junction-to-ambient Thermal Impedance 10 JA Min DS608PP2 CS5342 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT (Logic "0" = GND = 0 V; Logic "1" = VL, C L = 20 pF) Parameter Symbol Min Typ Max Unit tclkw 26 - 31 ns MCLK Specifications MCLK Period 52 - 1303 ns 40 - 60 % tmslr -20 - 20 ns tsdo - - 32 ns - 50 50 33 - % % % MCLK Pulse Duty Cycle Master Mode SCLK falling to LRCK SCLK falling to SDOUT valid SCLK Duty Cycle Single-Speed Double-Speed Quad-Speed Slave Mode Single Speed* LRCK Duty Cycle SCLK Period tsclkw SCLK Duty Cycle SDOUT valid before SCLK rising tstp 40 - 60 % 290 - - ns 45 - 55 % 10 - - ns SDOUT valid after SCLK rising thld 5 - - ns SCLK falling to LRCK edge tslrd -20 - 20 ns 40 - 60 % 193 - - ns 45 - 55 % Double Speed* LRCK Duty Cycle SCLK Period (Note 9) tsclkw SCLK Duty Cycle SDOUT valid before SCLK rising tstp 10 - - ns SDOUT valid after SCLK rising thld 5 - - ns SCLK falling to LRCK edge tslrd -20 - 20 ns 40 - 60 % tsclkw 104 - - ns 40 - 50 % SDOUT valid before SCLK rising tstp 10 - - ns SDOUT valid after SCLK rising thld 5 - - ns SCLK falling to LRCK edge tslrd -8 - 8 ns Quad Speed* (Note 2) LRCK Duty Cycle SCLK Period (Note 9) SCLK Duty Cycle * For a description of Speed Modes, please refer to Table 1 on page 15 Notes: 9. SCLK must be derived synchronously from MCLK and the ratio of SCLK/LRCK must be equal to 48. DS608PP2 11 CS5342 LRCK output LRCK input t sclkw t slrd tmslr SCLK input SCLK output t stp thld tsdo SDOUT MSB-1 MSB Figure 13. Master Mode, Left Justified SAI SDOUT MSB MSB-1 Figure 14. Slave Mode, Left Justified SAI LRCK input LRCK output t slrd tmslr tsclkw SCLK input SCLK output t stp thld t sdo SDOUT MSB Figure 15. Master Mode, I2S SAI 12 MSB-1 SDOUT MSB Figure 16. Slave Mode, I2S SAI DS608PP2 CS5342 2 PIN DESCRIPTION M0 MCLK VL SDOUT GND VD SCLK LRCK 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 M1 FILT+ REFGND VA AINR VQ AINL RST Pin Name # Pin Description M0 M1 1 16 Mode Selection (Input) - Determines the operational mode of the device. MCLK 2 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. VL 3 Logic Power (Input) - Positive power for the digital input/output. SDOUT 4 Serial Audio Data Output (Output) - Output for two's complement serial audio data. GND 5 Ground (Input) - Ground reference. Must be connected to analog ground. VD 6 Digital Power (Input) - Positive power supply for the digital section. SCLK 7 Serial Clock (Input/Output) - Serial clock for the serial audio interface. LRCK 8 Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. RST 9 Reset (Input) - The device enters a low power mode when low. AINL AINR 10 12 Analog Input (Input) - The full scale analog input level is specified in the Analog Characteristics specification table. VQ 11 Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage. VA 13 Analog Power (Input) - Positive power supply for the analog section. REFGND 14 Reference Ground (Output) - Ground reference for the internal sampling circuits. FILT+ 15 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. DS608PP2 13 CS5342 3 TYPICAL CONNECTION DIAGRAM 4 3.3V to 5V + 1 F 0.1 F + 0.1 F 2.5V to 5V 1 F 2 4 3.3V to 5V + 1 F 0.1 F 5.1 VA 0.1 F VL VD FILT+ 3 1 F + 0.1 F REFGND + 1 F 0.1 F VQ CS5342 RST M0 M1 Power Down and Mode Settings 1 VL or GND A/D CONVERTER 10 k A INL Audio Data Processor SDOUT Analog Input Buffer Figure 15 AI NR MCLK Timing Logic and Clock LRCK SCLK 1 Pull-up to VL for I2S Pull-down to GND for LJ GND 2 Resistor may only be used if VD is derived from VA. If used, do not drive any other logic from VD 3 Capacitor value affects low frequency distortion performance as described in Section 4.8 4 See Note 2 on page 4 Figure 17. Typical Connection Diagram 14 DS608PP2 CS5342 4 APPLICATIONS 4.1 Single, Double, and Quad Speed Modes The CS5342 can support output sample rates from 2 kHz to 200 kHz. The proper speed mode can be determined by the desired output sample rate and the external MCLK/LRCK ratio, as shown in Table 1. Speed Mode Single Speed Mode Double Speed Mode Quad Speed Mode MCLK/LRCK Ratio Output Sample Rate Range (kHz) 768x 43 - 54 384x 2 - 54 384x 86 - 108 192x 50 - 108 192x 172 - 200 96x* 100 - 200 * Quad Speed Mode, 96x only available in Master Mode. Table 1. Speed Modes and the Associated Output Sample Rates (Fs) 4.2 Operation as Either a Clock Master or Slave The CS5342 supports operation as either a clock master or slave. As a clock master, the LRCK and SCLK pins are outputs with the left/right and serial clocks synchronously generated on-chip. As a clock slave, the LRCK and SCLK pins are inputs and require the left/right and serial clocks to be externally generated. The selection of clock master or slave is made via the Mode pins as shown in Table 2. M1 (Pin 16) 0 0 1 1 M0 (Pin 1) 0 1 0 1 Clock Clock Clock Clock MODE Master, Single Speed Mode Master, Double Speed Mode Master, Quad Speed Mode Slave, All Speed Modes Table 2. CS5342 Mode Control DS608PP2 15 CS5342 4.2.1 Operation as a Clock Master As a clock master, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally derived from the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as shown in Figure 18. / 1.5 / 256 Single Speed 00 / 128 Double Speed 01 / 64 Quad Speed 10 LRCK Output (Equal to Fs) 0 MCLK M[1:0] /3 1 Auto-Select /4 Single Speed 00 /2 Double Speed 01 /1 Quad Speed 10 SCLK Output Figure 18. CS5342 Master Mode Clocking 4.2.2 Operation as a Clock Slave LRCK and SCLK operate as inputs in clock slave mode. It is recommended that the left/right clock be synchronously derived from the master clock and must be equal to Fs. It is also recommended that the serial clock be synchronously derived from the master clock and equal to 48x Fs or 64x Fs in Single-Speed Mode. In DoubleSpeed and Quad-Speed Modes the serial clock must be derived synchronously from the master clock and equal to 48x Fs. Additionally, Quad-Speed Slave Mode is only specified for operation with a VA and VD at 5 V, 5%. A unique feature of the CS5342 is the automatic selection of either Single, Double or Quad speed mode when operating as a clock slave. The auto-mode select feature negates the need to configure the Mode pins to correspond to the desired mode. The auto-mode selection feature supports all standard audio sample rates from 2 to 200 kHz. However, there are ranges of non-standard audio sample rates that are not supported when operating with a fast MCLK (768x, 384x, and 192x for Single, Double, and Quad Speed Modes respectively). Please refer to Table 1 on page 15 for supported sample rate ranges. 16 DS608PP2 CS5342 4.2.3 Master Clock The CS5342 requires a Master clock (MCLK) which runs the internal sampling circuits and digital filters. There is also an internal MCLK divider which is automatically activated based on the frequency of the MCLK. Table 3 shows a listing of the external MCLK/LRCK ratios that are required. Table 4 lists some common audio output sample rates and the required MCLK frequency. Please note that not all of the listed sample rates are supported when operating with a fast MCLK (768x, 384x, 192x for Single, Double, and Quad Speed Modes respectively). Single Speed Mode Double Speed Mode Quad Speed Mode 384x, 768x 192x, 384x 96x*, 192x MCLK/LRCK Ratio * Quad Speed, 96x only available in Master Mode. Table 3. Master Clock (MCLK) Ratios SAMPLE RATE (kHz) 32 44.1 MCLK (MHz) 12.288 16.9344 33.8688 18.432 36.864 12.288 16.9344 33.8688 18.432 36.864 36.864 48 64 88.2 96 192 Table 4. Master Clock (MCLK) Frequencies for Standard Audio Sample Rates 4.3 Serial Audio Interface The CS5342 supports both I2S and Left Justified serial audio formats. Upon start-up, the CS5342 will detect the logic level on SDOUT (pin 4). A 10 k pull-up resistor to VL is needed to select I2S format, and a 10 k pull-down resistor to GND is needed to select Left Justified format. Please see Figures 13 through 16 on page 12, for more information on the required timing for the two serial audio interface formats. LRCK Left Channel Right Channel SCLK SDATA 23 22 9 8 7 6 5 4 3 2 1 0 23 22 9 8 7 6 5 4 3 2 1 0 23 22 0 23 22 Figure 19. Left-Justified Serial Audio Interface LRCK Left Channel Right Channel SCLK SDATA 23 22 9 8 7 6 5 4 3 2 1 0 23 22 9 8 7 6 5 4 3 2 1 Figure 20. I2S Serial Audio Interface DS608PP2 17 CS5342 4.4 Power-up Sequence Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and configuration pins are stable. It is also recommended that reset be enabled if the analog or digital supplies drop below the minimum specified operating voltages to prevent power glitch related issues. 4.5 Analog Connections The analog modulator samples the input at 6.144 MHz. The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are multiples of the input sampling frequency (n x 6.144 MHz), where n=0,1,2,... Refer to Figure 15 which shows the suggested filter that will attenuate any noise energy at 6.144 MHz, in addition to providing the optimum source impedance for the modulators. The use of capacitors which have a large voltage coefficient (such as general purpose ceramics) must be avoided since these can degrade signal linearity. 634 VA 470 pF COG 100 k 4.7 uF 91 CS5342 AINL AINL 100 k 2200 pF VA 4.7 uF 100 k 91 AINL CS5342 AINL 100 k COG 470 pF 2200 pF 634 Figure 21. CS5342 Recommended Analog Input Buffer 4.6 Grounding and Power Supply Decoupling As with any high resolution converter, the CS5342 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 17 shows the recommended power arrangements, with VA and VL connected to clean supplies. VD, which powers the digital filter, may be run from the system logic supply or may be powered from the analog supply via a resistor. In this case, no additional devices should be powered from VD. Decoupling capacitors should be as near to the ADC as possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 F, must be positioned to minimize the electrical path from FILT+ and REF_GND. The CDB5342 evaluation board demonstrates the optimum layout and power supply arrangements. To minimize digital noise, connect the ADC digital outputs only to CMOS inputs. 18 DS608PP2 CS5342 4.7 Synchronization of Multiple Devices In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure synchronous sampling, the MCLK and LRCK must be the same for all of the CS5342's in the system. 4.8 Capacitor Size on the Reference Pin (FILT+) The CS5342 requires an external capacitance on the internal reference voltage pin, FILT+. The size of this decoupling capacitor will affect the low frequency distortion performance as shown in Figure 22, with larger capacitor values used to optimize low frequency distortion performance. The THD+N curves in Figure 22 were measured with VA = VD = VL = 5 V in Single-Speed Master Mode using a 1 kHz input tone of magnitude -1 dB Full-Scale. 1 uF 2.2 uF 3.3 uF 4.7 uF 5.6 uF 6.8 uF 10 uF 22 uF 47 uF 100 uF Figure 22. CS5342 THD+N versus Frequency DS608PP2 19 CS5342 5 PARAMETER DEFINITIONS Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog input for a full-scale digital output. Gain Drift The change in gain value with temperature. Units in ppm/C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV. 20 DS608PP2 CS5342 6 PACKAGE DIMENSIONS 16L TSSOP (4.4 mm BODY) PACKAGE DRAWING N D E11 A2 E A e b2 SIDE VIEW A1 L END VIEW SEATING PLANE 1 2 3 TOP VIEW DIM A A1 A2 b D E E1 e L MIN -0.002 0.03346 0.00748 0.193 0.248 0.169 -0.020 0 INCHES NOM -0.004 0.0354 0.0096 0.1969 0.2519 0.1732 0.026 BSC 0.024 4 MAX 0.043 0.006 0.037 0.012 0.201 0.256 0.177 -0.028 8 MIN -0.05 0.85 0.19 4.90 6.30 4.30 -0.50 0 MILLIMETERS NOM --0.90 0.245 5.00 6.40 4.40 0.065 BSC 0.60 4 NOTE MAX 1.10 0.15 0.95 0.30 5.10 6.50 4.50 -0.70 8 2,3 1 1 JEDEC #: MO-153 Controlling Dimension is Millimeters Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. DS608PP2 21 CS5342 7. REVISION HISTORY Release Date Changes A1 April 2003 -Initial Advance Release. A2 July 2003 -Modify serial port timing specs. -Add Applications section on speed mode detect. PP1 August 2004 -Change 2700 pF capacitors to 2200 pF in analog input buffer diagram. -Update Output Sample Range table. -Add new Applications section about capacitor on FILT+ pin. -Correct Max MCLK period under "Switching Characteristics." -Replace MCLK low/high timing specifications with duty cycle specification. -Redefine slave mode timing specifications under "Switching Characteristics." -Add requirement of SCLK/LRCK = 48x in Double and Quad Speed Modes. -Increase minimum VL specification from 1.7 V to 2.38 V. -Specify VA and VD at 5 V, 5% for Quad-Speed Slave Mode. -Reduce gain error specification under Analog Characteristics. -Improve minimum and maximum specifications for full-scale input voltage. -Initial Preliminary Release. PP2 Aug 2004 Update to include lead-free device ordering information. Table 5. Revision History 22 DS608PP2