SAA7715AH - Philips Semiconductors / NXP Semiconductors

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Preliminary speciﬁcation 2003 Mar 13

INTEGRATED CIRCUITS

SAA7715AH

Digital Signal Processor

2003 Mar 13 2

Philips Semiconductors Preliminary speciﬁcation

Digital Signal Processor SAA7715AH

CONTENTS

1 FEATURES

1.1 Hardware

1.2 Possible firmware

2 APPLICATIONS

3 GENERAL DESCRIPTION

4 QUICK REFERENCE DATA

5 ORDERING INFORMATION

6 BLOCK DIAGRAM

7 PINNING

8 FUNCTIONAL DESCRIPTION

8.1 PLL clock division factors for different clock

inputs

8.2 The word select PLL

8.3 The Filter Stream DAC (FSDAC)

8.3.1 Interpolation filter

8.3.2 Noise shaper

8.3.3 Function of pin POM

8.3.4 Power off plop suppression

8.3.5 Pin VREFDA for internal reference

8.3.6 Supply of the analog outputs

8.4 External control pins

8.5 Digital serial inputs/outputs and SPDIF inputs

8.5.1 Digital serial inputs/outputs

8.5.2 SPDIF inputs

8.6 I2C-bus interface (pins SCL and SDA)

8.7 Reset

8.8 Power-down mode

8.9 Power supply connection and EMC

8.10 Test mode connections (pins TSCAN, RTCB

and SHTCB)

C-BUS PROTOCOL

9.1 Addressing

9.2 Slave address (pin A0)

9.3 Write cycles

9.4 Read cycles

9.5 Program RAM

9.6 Data word alignment

9.7 I2C-bus memory map specification

9.8 I2C-bus memory map definition

9.9 Table definitions

10 SOFTWARE IN ROM DESCRIPTION

11 LIMITING VALUES

12 THERMAL CHARACTERISTICS

13 CHARACTERISTICS

14 I2S-BUS TIMING

15 I2C-BUS TIMING

16 APPLICATION DIAGRAM

17 PACKAGE OUTLINE

18 SOLDERING

18.1 Introduction to soldering surface mount

packages

18.2 Reflow soldering

18.3 Wave soldering

18.4 Manual soldering

18.5 Suitability of surface mount IC packages for

wave and reflow soldering methods

19 DATA SHEET STATUS

20 DEFINITIONS

21 DISCLAIMERS

22 PURCHASE OF PHILIPS I2C COMPONENTS

2003 Mar 13 3

Philips Semiconductors Preliminary speciﬁcation

Digital Signal Processor SAA7715AH

1 FEATURES

1.1 Hardware

•24-bit Philips 70 MIPS DSP core (24-bit data path and

12/24-bit coefficient path)

•1.5 kbyte of downloadable DSP program memory

(PRAM)

•2 kbyte of DSP program memory (PROM)

•2.875 kbyte of re-programmable DSP data memory

(XRAM)

•1.5 kbyte of re-programmable DSP coefficient memory

(YRAM)

•Four stereo digital serial inputs (8 channels) with

common BCK and WS. To these inputs the I2S-bus

format or LSB-justified formats can be applied

•One stereo bitstream DAC (2 channels) with 64 fold

oversampling and noise shaping

•Selectable clock output (pin SYSCLK) for external slave

devices (128fsto 512fs)

•Four stereo digital serial outputs (8 channels) with

selectable I2S-bus or LSB-justified format

•Two SPDIF inputs combined with digital serial input

•On-board WS_PLL generates clock for on-board DAC

and output pin SYSCLK

•I2C-bus controlled (including fast mode)

•Programmable Phase-Locked Loop (PLL) derives the

clock for the DSP from the CLK_IN input

•−40 to +85 °C operating temperature range

•Supply voltage only 3.3 V

•All digital inputs are tolerant for 5 V input levels

•Power-down mode for low current consumption in

standby mode

•Optimized pinning for applications with other Philips

DACs (such as UDA1334, UDA1355 and UDA1328).

1.2 Possible ﬁrmware

•Dolby®(1) Pro Logic decoding

•Smoothed volume control (without zipper noise)

•Automatic Volume Levelling (AVL)

•Dynamic bass enhancement

•Ultra bass

•Incredible surround

•Incredible mono (Imono)

•DPL virtualizer

•Dolby digital virtualizer (DVD post-processing)

•Dynamic compressor

•Spectral enhancer

•Equalizer with peaking/shelving filters

•DC filters

•Bass/treble control

•Dynamic loudness

•Tone/noise generator

•Graphical spectrum analyser

•Configurable Delay Unit (DLU)

•Sound steering/elevation for car applications

•Sample Rate Conversion (SRC).

2 APPLICATIONS

•As co-processor for a car radio DSP in a car radio

application for additional acoustic enhancements

(sound steering/sound elevation/signal processing)

•Multichannel audio: in DVD and Home theatre

applications as post-processing device such as signal

virtualization (virtual 3D surround) and acoustic

enhancement, tone control, volume control and

equalizers

•Multichannel decoding: Dolby Pro Logic and virtual

3D surround

•PC/USB audio applications: stereo widening (Incredible

surround), sound steering, sound positioning and

speaker equalization.

(1) Dolby — Available only to licensees of Dolby Laboratories

Licensing Corporation, San Francisco, CA94111, USA, from

whom licensing and application information must be obtained.

Dolby is a registered trade-mark of Dolby Laboratories

Licensing Corporation.

2003 Mar 13 4

Philips Semiconductors Preliminary speciﬁcation

Digital Signal Processor SAA7715AH

3 GENERAL DESCRIPTION

The SAA7715AH is a cost effective and powerful high

performance 24-bit programmable DSP for a variety of

digital audio applications. This DSP device integrates a

24-bit DSP core with programmable memories (program

RAM/ROM, data and coefficient RAM), 4 digital serial

inputs, 4 digital serial outputs, 2 separate SPDIF

receivers, a stereo FSDAC, a standard Philips I2C-bus

interface, a phase-locked loop for the DSP clock

generation and a second phase-locked loop for system

clock generation (internal and external DAC clocks).

The SAA7715AH can be configured for various audio

applications by downloading the dedicated DSP program

code into the DSP program RAM or using the ROM or a

combination of both. During the Power-down mode the

contents of the memories and all other settings will keep

their values. The SAA7715AH can be initialized using the

I2C-bus interface.

Several system application examples, based on this

existing SAA7715AH, are available for a wide range of

audio applications (e.g car radio DSP,

DVD post-processing, Dolby Pro Logic, PC/USB audio

and more) which can be used as a reference design for

customers.

4 QUICK REFERENCE DATA

5 ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

VDD operating supply voltage all pins VDD with respect to

pins VSS

3.15 3.3 3.45 V

IDDD supply current of the digital

part high activity of the DSP at

DSPFREQ frequency −95 −mA

IDDA supply current of the analog

part zero input and output

signal −20 −mA

Ptot total power dissipation high activity of the DSP at

DSPFREQ frequency −380 −mW

IPOWERDOWN DC supplycurrentof thetotal

chip in Power-down mode pin POWERDOWN

enabled −400 −µA

ssample frequency at IIS_WS1, SPDIF1 or

SPDIF2 input 32 44.1 96 kHz

(THD + N)/SDAC total harmonic

distortion-plus-noise to

signal ratio of DAC

at 0 dB −−85 −dB(A)

at −60 dB −−37 −dB(A)

S/NDAC signal-to-noise ratio of DAC code = 0 −100 −dB(A)

fCLK_IN clock input frequency DIV_CLK_IN = LOW 8.192 11.2896 12.288 MHz

DIV_CLK_IN = HIGH 16.384 −24.576 MHz

DSPFREQ maximum DSP clock

frequency −−70 MHz

TYPE NUMBER PACKAGE

NAME DESCRIPTION VERSION

SAA7715AH QFP44 plastic quad ﬂat package; 44 leads (lead length 1.3 mm);

body 10 ×10 ×1.75 mm SOT307-2

2003 Mar 13 5

Philips Semiconductors Preliminary speciﬁcation

Digital Signal Processor SAA7715AH

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6 BLOCK DIAGRAM

handbook, full pagewidth

MHC320

SAA7715AH

TCB

PRAM PROM

DSP CORE

STEREO

DAC

n × fs

CLOCK

I2C-BUS WS_PLL

÷ 2 PLL

IIS_BCK1 2

24 25 4

IIS_WS1 3

IIS_IN1 5

IIS_IN4

IIS_OUT1

IIS_OUT2

IIS_OUT3

IIS_OUT4

VOUTL

VOUTR

IIS_BCK

IIS_WS

POM

VREFDA

22 41

IIS_IN3

CLK_IN

DIV_CLK_IN

DSP CLOCK

IIS_IN2

XRAM YRAM

DSP_INOUT7

DSP_INOUT6

DSP_INOUT5

SHTCB

RTCB

VSSI2

TSCAN

VSSI1

VSSE

VSSA2

VDDI1

VDDE

VDDA2

VDDA1

SPDIF2

SPDIF1

RESERVED1

VSSA1

SYSCLK

DSP_RESET

SDA

SCL

POWERDOWN

RESERVED2

RESERVED3

Fig.1 Block diagram.

2003 Mar 13 6

Philips Semiconductors Preliminary speciﬁcation

Digital Signal Processor SAA7715AH

7 PINNING

SYMBOL PIN PIN TYPE DESCRIPTION

IIS_BCK1 1 ipthdt5v bit clock signal belonging to data of digital serial inputs 1 to 4

IIS_WS1 2 ipthdt5v word select signal belonging to data of digital serial inputs 1 to 4

IIS_IN1 3 ipthdt5v data pin of digital serial input 1

RESERVED1 4 ipthdt5v not to be connected externally

IIS_IN4 5 ipthdt5v data pin of digital serial input 4

IIS_IN2 6 ipthdt5v data pin of digital serial input 2

RESERVED2 7 ipthdt5v not to be connected externally

RESERVED3 8 ipthdt5v not to be connected externally

IIS_IN3 9 ipthdt5v data pin of digital serial input 3

VSSI2 10 vssi ground supply (core only) (bond out to 2 pads)

A0 11 ipthdt5v slave sub-address I2C-bus selection/serial data input test control block

SCL 12 iptht5v clock input of I2C-bus

SDA 13 iic400kt5v data input/output of I2C-bus

VSSI1 14 vssis ground supply (core only)

VSSA2 15 vssco ground supply analog of PLL, WS_PLL, SPDIF input stage

VDDI1 16 vddi positive supply (core only) (bond out to 2 pads)

VDDA2 17 vddco positive supply analog of PLL, WS_PLL, SPDIF input stage

DSP_RESET 18 ipthut5v general reset of chip (active LOW)

RTCB 19 ipthdt5v asynchronous reset test control block, connect to ground (internal pull down)

SHTCB 20 ipthdt5v shift clock test control block (internal pull down)

VSSE 21 vsse ground supply (peripheral cells only)

CLK_IN 22 iptht5v system clock input

VDDE 23 vdde positive supply (peripheral cells only)

SPDIF2 24 apio SPDIF2 data input (internally multiplexed with digital serial input 3)

SPDIF1 25 apio SPDIF1 data input (internally multiplexed with digital serial input 2)

TSCAN 26 ipthdt5v scan control active HIGH (internal pull down)

SYSCLK 27 bpt4mthdt5v n ×fs output of SAA7715AH

IIS_OUT4 28 ops5c data pin of digital serial output 4

IIS_OUT3 29 ops5c data pin of digital serial output 3

IIS_OUT2 30 ops5c data pin of digital serial output 2

IIS_OUT1 31 ops5c data pin of digital serial output 1

IIS_WS 32 ops5c word select output belonging to digital serial output 1 to 4

IIS_BCK 33 ops5c bit clock output belonging to digital serial output 1 to 4

VOUTL 34 apio analog left output pin.

VDDA1 35 vddo FSDAC positive supply voltage (bond out to 2 pads)

VOUTR 36 apio analog right output pin

VSSA1 37 vsso FSDAC ground supply voltage (bond out to 2 pads)

VREFDA 38 apio voltage reference pin of FSDAC

POM 39 apio power-on mute pin of FSDAC

POWERDOWN 40 iptht5v standby mode of chip

2003 Mar 13 7

Philips Semiconductors Preliminary speciﬁcation

Digital Signal Processor SAA7715AH

Table 1 Brief explanation of used pin types

DIV_CLK_IN 41 ipthdt5v divide the input frequency on pin CLK_IN by two

DSP_INOUT5 42 bpts5thdt5v digital input/output ﬂag of the DSP-core (F5 of the status register)

DSP_INOUT6 43 bpts5thdt5v digital input/output ﬂag of the DSP-core (F6 of the status register)

DSP_INOUT7 44 bpts5thdt5v digital input/output ﬂag of the DSP-core (F7 of the status register)

PIN TYPE EXPLANATION

apio analog I/O pad cell; actually pin type vddco

bpts5thdt5v 43 MHz bidirectional pad; push-pull input; 3-state output; 5 ns slew rate control; TTL; hysteresis;

pull-down; 5 V tolerant

bpts5tht5v 43 MHz bidirectional pad; push-pull input; 3-state output; 5 ns slew rate control; TTL; hysteresis; 5 V

tolerant

bpt4mthdt5v bidirectional pad; push-pull input; 3-state output; 4 mA output drive; TTL; hysteresis; pull-down; 5 V

tolerant

iic400kt5v I2C-bus pad; 400 kHz I2C-bus speciﬁcation; 5 V tolerant

ipthdt5v input pad buffer; TTL; hysteresis; pull-down; 5 V tolerant

iptht5v input pad buffer; TTL; hysteresis; 5 V tolerant

ipthut5v input pad buffer; TTL; hysteresis; pull-up; 5 V tolerant

ops5c output pad; push-pull; 5 ns slew rate control; CMOS

op4mc output pad; push-pull; 4 mA output drive

vddco VDD supply to core only

vdde VDD supply to peripheral only

vddi VDD supply to core only

vddo VDD supply to core only

vssco VSS supply to core only (vssco does not connect the substrate)

vsse VSS supply to peripheral only

vssi VSS supply to core and peripheral

vssis VSS supply to core only; with substrate connection

vsso VSS supply to core only

SYMBOL PIN PIN TYPE DESCRIPTION

2003 Mar 13 8

Philips Semiconductors Preliminary speciﬁcation

Digital Signal Processor SAA7715AH

handbook, full pagewidth

SAA7715AH

MHC319

IIS_BCK

IIS_WS

IIS_OUT1

IIS_OUT2

IIS_OUT4

SYSCLK

TSCAN

SPDIF1

SPDIF2

VDDE

IIS_BCK1

IIS_WS1

IIS_IN1

RESERVED1

IIS_IN4

IIS_IN2

RESERVED3

IIS_IN3

IIS_OUT3

DSP_INOUT6

DSP_INOUT5

DIV_CLK_IN

POWERDOWN

POM

VREFDA

VOUTR

VDDA1

VOUTL

DSP_INOUT7

VSSA1

SDA

VSSI1

VSSA2

VDDI1

VDDA2

DSP_RESET

SHTCB

VSSE

CLK_IN

SCL

RTCB

RESERVED2

VSSI2

Fig.2 Pin configuration.

2003 Mar 13 9

Philips Semiconductors Preliminary speciﬁcation

Digital Signal Processor SAA7715AH

8 FUNCTIONAL DESCRIPTION

8.1 PLL clock division factors for different clock inputs

Anon-chip PLL generates the clockfor theDSP. The DSPruns ata selectable frequency of maximum70 MHz. Theclock

is generated with the PLL that uses the CLK_IN of the chip to generate the DSP clock. Table 2 gives the PLL clock

division factor and the values of the dsp_turbo and the DIV_CLK_IN bits that need to be set via the I2C-bus (see

Table 10).

Table 2 PLL clock division factor per clock input.

The above table does NOT imply that the clock input is restricted to the values given in this table. The clock input is

restricted to be within the range of 8.192 to 12.228 MHz. For higher clock frequencies pin DIV_CLK_IN should be set to

logic 1 performing a divide-by-2 of the CLK_IN signal and thereby doubling the CLK_IN frequency range that is allowed

(16.384 to 24.576 MHz).

8.2 The word select PLL

A second on-chip PLL generates a selectable multiple of the sample rate frequency supplied on the word select

pin IIS_WS (= IIS_WS1). The clock generated by this so called WS_PLL is available for the user at pin SYSCLK.

Tables 3 and 4 show the I2C-bus settings needed to generate the n ×fs clock. The memory map of the I2C-bus bits is

shown in Table 10.

Table 3 Word select input range selection

Table 4 Selection of n ×fs clock at SYSCLK output

CLK_IN (MHz) pll_div[4:0] N dsp_turbo DIV_CLK_IN DSP CLOCK

(MHz)

8.192 (32 kHz ×256) 10H 272 1 0 69.632

9.728 (38 kHz ×256) 09H 227 1 0 69.008

11.2896 (44.1 kHz ×256) 03H 198 1 0 69.854

12.288 (48 kHz ×256) 00H 181 1 0 69.504

16.384 (32 kHz ×512) 10H 272 1 1 69.632

18.432 (32 kHz ×576) 0BH 244 1 1 68.544

19.456 (38 kHz ×512) 09H 227 1 1 69.008

24.576 (96 kHz ×256) 00H 181 1 1 69.504

SAMPLE RATE OF fs (kHz) sel_loop_div[1:0]

32 to 50 01

50 to 96 00

sel2 sel1 sel0 SYSCLK (n ×IIS_WS1) DUTY FACTOR

1 0 0 512 50% for 32 to 50 kHz input;

66% for 50 to 96 kHz input

0 1 1 384 50%

0 1 0 256 50%

0 0 1 192 50%

0 0 0 128 50%

2003 Mar 13 10

Philips Semiconductors Preliminary speciﬁcation

Digital Signal Processor SAA7715AH

8.3 The Filter Stream DAC (FSDAC)

The FSDAC is a semi-digital reconstruction filter that

converts the 1-bit data stream of the noise shaper to an

analog output voltage. The filter coefficients are

implemented as current sources and are summed at

virtual ground of the output operational amplifier. In this

way very high signal-to-noise performance and low clock

jitter sensitivity is achieved. A post-filter is not needed due

to the inherent filter function of the DAC. On-board

amplifiers convert the FSDAC output current to an output

voltage signal capable of driving a line output.

The output voltage of the FSDAC scales proportionally

with the power supply voltage.

8.3.1 INTERPOLATION FILTER

The digital filter interpolates from 1 to 64fs by means of a

cascade of a recursive filter and an FIR filter.

Table 5 Digital interpolation ﬁlter characteristics

8.3.2 NOISE SHAPER

The 5th-order noise shaper operates at 64fs. It shifts

in-band quantization noise to frequencies well above the

audio band. This noise shaping technique enables high

signal-to-noise ratios to be achieved. The noise shaper

output is converted into an analog signal using a filter

stream digital-to-analog converter.

8.3.3 FUNCTION OF PIN POM

With pin POM it is possible to switch off the reference

current of the DAC. The capacitor on pin POM determines

the time after which this current has a soft switch-on. So at

power-on the current audio signal outputs are always

muted. The loading of the external capacitor is done in two

stagesvia two differentcurrent sources. Theloading starts

ata currentlevel thatis lowerthan the current loading after

the voltage on pin POM has passed a particular level. This

results in an almost dB-linear behaviour. This prevents

‘plop’ effects during power on/off.

8.3.4 POWER OFF PLOP SUPPRESSION

To avoid plops in a power amplifier, the supply voltage of

the analog part of the DAC and the rest of the chip can be

fedfromaseparatesupplyof3.3 V.A capacitorconnected

to this supply enables to provide power to the analog part

at the moment the digital voltage is switching off fast.

In this event the output voltage will decrease gradually

allowing the power amplifier some extra time to switch off

without audible plops.

8.3.5 PIN VREFDA FOR INTERNAL REFERENCE

With two internal resistors half the supply voltage VDDA1 is

obtainedandusedasan internal reference. Thisreference

voltage is used as DC voltage for the output operational

amplifiers and as reference for the DAC. In order to obtain

the lowest noise and to have the best ripple rejection, a

filter capacitor has to be added between this pin and

ground, preferably close to the analog pin VSSA1.

8.3.6 SUPPLY OF THE ANALOG OUTPUTS

The entire analog circuitry of the DACs and the OPAMPS

are supplied by 2 supply pins, VDDA1 and VSSA1. The

VDDA1 must have sufficient decoupling to prevent THD

degradationand to ensureagood PowerSupplyRejection

Ratio (PSRR). The digital part of the DAC is fully supplied

from the chip core supply.

8.4 External control pins

The flags DSP_INOUT5 to DSP_INOUT7 are available as

external pins. The flags can be used by the DSP

depending on the downloaded software.

ITEM CONDITIONS VALUE (dB)

Pass band ripple 0 to 0.45fs±0.03

Stop band >0.55fs−50

Dynamic range 0 to 0.45fs116.5

Gain DC −3.5

2003 Mar 13 11

Philips Semiconductors Preliminary speciﬁcation

Digital Signal Processor SAA7715AH

8.5 Digital serial inputs/outputs and SPDIF inputs

8.5.1 DIGITAL SERIAL INPUTS/OUTPUTS

For communication with external digital sources a digital

serial bus is implemented. It is a serial 3-line bus, having

one line for data, one line for clock and one line for the

word select. For external digital sources the SAA7715AH

acts as a slave, so the external source is master and

supplies the clock.

For the I2S-bus format itself see the official specification

from Philips.

The digital serial input is capable of handling Philips

I2S-busandLSB-justifiedformatsof 16, 18, 20 and 24bits

word sizes. The sampling frequency can be 32 up to

96 kHz. See “9.8 I2C-bus memory map definition” for the

bits that must be programmed, for selection of the desired

serial format.

See Fig.3 for the general waveforms of the possible

formats.

When the applied word length exceeds 24 bits, the LSBs

are skipped.

The digital serial input/output circuitry is limited in handling

the number of BCK pulses per WS period. The maximum

allowed number of bit clocks per WS period is 256. Also

the number of bit clocks during WS LOW and HIGH must

be equal (50% WS duty factor) only for the LSB-justified

formats.

There are two modes in which the digital inputs can be

used (the mode is selectable via an I2C-bus bit):

•Use up to 4 digital serial inputs (8ch) with common WS

and BCK signal (8ch IN and 8ch OUT + 2ch FSDAC

output)

•Use one of the 2 SPDIF inputs as source instead of the

use of the digital serial inputs (2ch IN and

8ch OUT + One 2ch FSDAC output).

8.5.2 SPDIF INPUTS

Two separate SPDIF receivers are available, one shared

with digital serial input 2 (SPDIF1) and one with the digital

serial input 3 (SPDIF2). The sample frequency at which

the SPDIF inputs can be used must be in the range of

32 to 96 kHz.

There are few control signals available from the SPDIF

input stage. These are connected to flags of the DSP:

•A lock signal indicating if the SPDIF input 1 or 2 is in

lock

•Thepcm_audio/non-pcm_audiobitindicating if an audio

or data stream is detected on SPDIF input 1 or 2. The

FSDAC output will NOT be muted in the event of

non-audio PCM stream. This status bit can be read via

the I2C-bus, the microprocessor controller can decide to

put the DAC into MUTE (via pin POM).

Handling of channel status bits: The first 40 (of 192)

channel status bits of the selected SPDIF source (0FFBH,

bit 20), will come available in the I2C-bus registers

0FF2H to 0FF5H. Two registers 0FF2H to 0FF3H contain

the information for the right channel, the other two

(0FF4H to 0FF5H) contain the information for the left

channel. The information can be read via I2C-bus or by the

DSP program.

The design fulfils the digital audio interface specification

“IEC 60958-1 Ed2, part 1, general part IEC 60958-3 Ed2,

part 3, consumer applications”

2003 Mar 13 12

Philips Semiconductors Preliminary speciﬁcation

Digital Signal Processor SAA7715AH

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handbook, full pagewidth

MGR751

B5 B6 B7 B8 B9 B10

LEFT

LSB-JUSTIFIED FORMAT 24 BITS

BCK

DATA

RIGHT

1518 1720 1922 212324 2 1

B3 B4

MSB B2 B23 LSB

B5 B6 B7 B8 B9 B10

1518 1720 1922 212324 21

B3 B4

MSB B2 B23 LSB

MSB B2 B3 B4 B5 B6

LEFT

LSB-JUSTIFIED FORMAT 20 BITS

BCK

DATA

RIGHT

1518 1720 19 2 1

B19 LSB

MSB B2 B3 B4 B5 B6

1518 1720 19 2 1

B19 LSB

MSB B2 B3 B4

LEFT

LSB-JUSTIFIED FORMAT 18 BITS

BCK

DATA

RIGHT

1518 17 2 1

MSB B2 B3 B4

B17 LSB

16 1518 17 2 1

B17 LSB

MSB B2

LEFT

LSB-JUSTIFIED FORMAT 16 BITS

BCK

DATA

RIGHT

15 2 1

B15 LSB

MSB B2

15 2 1

B15 LSB

MSB MSBB2

21> = 812 3

LEFT

INPUT FORMAT I2S-BUS

BCK

DATA

RIGHT

3> = 8

MSB B2

Fig.3 All serial data input/output formats.

2003 Mar 13 13

Philips Semiconductors Preliminary speciﬁcation

Digital Signal Processor SAA7715AH

8.6 I2C-bus interface (pins SCL and SDA)

The I2C-bus format is described in

“The I

C-bus and how

to use it”

, order no. 9398 393 40011.

For the external control of the SAA7715AH a fast I2C-bus

is implemented. This is a 400 kHz bus which is downward

compatible with the standard 100 kHz bus.

There are two different types of control instructions:

•Loading of the Program RAM (PRAM) with the required

DSP program

– Programming the coefficient RAM (YRAM)

– Instructions to control the DSP program.

•Selection of the digital serial input/output format to be

used, the DSP clock speed.

The detailed description of the I2C-bus and the description

of the different bits in the memory map is given in

Chapter 9.

8.7 Reset

The reset (pin DSP_RESET) is active LOW and needs an

external 22 kΩ pull-up resistor. Between this pin and the

VSSI ground a capacitor of 1 µF should be connected to

allow a proper switch-on of the supply voltage. The

capacitor value is such that the chip is in reset as long as

the power supply is not stabilized. A more or less fixed

relationship between the DSP reset and the POM time

constantisobligatory.Thevoltageonpin POM determines

the current flowing in the DACs.

The reset sets all I2C-bus bits to their default value and it

restarts the DSP program.

8.8 Power-down mode

ThePower-down mode switches off all activity onthe chip.

The Power-down mode can be switched on and off using

pin POWERDOWN. This pin needs to be connected to

ground if not used. The following applies for the

Power-down mode:

•Power-down mode may only be switched on when there

is no I2C-bus activity to or from the SAA7715AH

•Power-down mode may not be switched on before the

complete chip has been reset (DSP_RESET

active LOW)

•The clock signal on pin CLK_IN should be running

during Power-down mode

•It is advised to set pin POM to logic 0 before switching

on the Power-down mode and set it back to logic 1 after

the chip actually returns from Power-down mode as

shown in Fig.4

•Allon-chip registers andmemories will keeptheir values

during Power-down mode

•Digitalserialoutputs are notmuted, the lastvalueis kept

on the output

•The SAA7715AH will not ‘lock-up’ the I2C-bus during

Power-down mode (SDA line).

Figure 4shows the timethe chipactually is inPower-down

mode after switching on/off pin POWERDOWN.

handbook, full pagewidth

MGT828

tAtB

POWERDOWN

device actually in

Power-down mode

POM

CLK_IN

Fig.4 Power-down mode.

tA=4×(256/CLK_IN); 8.192 MHz < CLK_IN < 12.288 MHz.

tA=4×(512/CLK_IN); 16.384 MHz < CLK_IN < 24.576 MHz. tB= 128 ×(256/CLK_IN); 8.192 MHz < CLK_IN < 12.288 MHz.

tB= 128 ×(512/CLK_IN); 16.384 MHz < CLK_IN < 24.576 MHz.

2003 Mar 13 14

Philips Semiconductors Preliminary speciﬁcation

Digital Signal Processor SAA7715AH

8.9 Power supply connection and EMC

Thedigital part ofthe chip hasintotal 4 positivesupply line

connections and 5 ground connections. To minimize

radiation the chip should be put on a double layer

printed-circuitboardwithononesidealargegroundplane.

The ground supply lines should have a short connection to

this ground plane. A coil/capacitor network in the positive

supply line of the peripheral power supply line can be used

as high frequency filter. The core supply lines (VDDI) have

an on-chip decoupling capacitance, for EMC reasons an

external decoupling capacitance must not be used on this

pin. A series resistor plus capacitance is required for

proper operation on pin VDDA2, see Fig.9.

8.10 Test mode connections (pins TSCAN, RTCB

and SHTCB)

Pins TSCAN, RTCB and SHTCB are used to put the chip

in test mode and to test the internal connections. Each pin

has an internal pull-down resistor to ground. In the

application these pins can be left open or connected to

ground.

C-BUS PROTOCOL

9.1 Addressing

Before any data is transmitted on the I2C-bus, the device

that should respond is addressed first. The addressing is

always done with the first byte transmitted after the start

procedure.

9.2 Slave address (pin A0)

The SAA7715AH acts as a slave receiver or a slave

transmitter.Therefore the clock signal SCLis onlyan input

signal. The data signal SDA is a bidirectional line. The

slave address is shown in Table 6.

Table 6 Slave address

The sub-address bit A0 corresponds to the hardware

address pin A0 which allows the device to have 2 different

addresses.TheA0 inputisalsoused in testmodeasserial

input of the test control block.

9.3 Write cycles

The I2C-bus configuration for a write cycle is shown

in Fig.5. The write cycle is used to write the bytes to the

DSP for manipulating the data and coefficients. More

details can be found in the I2C-bus memory map, see

Table 8.

The data length is 2, 3 or 4 bytes depending on the

accessed memory. If the Y-memory is addressed the data

length is 2 bytes, in the event of the X-memory the length

is 3 bytes. The slave receiver detects the address and

adjusts the number of bytes accordingly.

For this RAM-based product the internal P-memory

(PRAM) can be accessed via the I2C-bus interface. The

transmitted data stream should be 4 bytes.

9.4 Read cycles

The I2C-bus configuration for a read cycle is shown

in Fig.6. The read cycle is used to read the data values

from XRAM, YRAM or PRAM. The master starts with a

START condition S, the SAA7715AH address ‘0011110’

and a logic 0 (write) for the read/write bit. This is followed

by an acknowledge of the SAA7715AH. Then the master

writes the high memory address (ADDR H) and low

memory address (ADDR L) where the reading of the

memory content of the SAA7715AH must start. The

SAA7715AH acknowledges these addresses both.

The master generates a repeated START (Sr) and again

the SAA7715AH address ‘0011110’ but this time followed

by a logic 1 (read) of the read/write bit. From this moment

on the SAA7715AH will send the memory content in

groups of 3 (X/Y-memory or registers) or 4 (P-memory)

bytes to the I2C-bus each time acknowledged by the

master. The master stops this cycle by generating a

negative acknowledge, then the SAA7715AH frees the

I2C-bus and the master can generate a STOP condition.

The data is transferred from the DSP register to the

I2C-bus register at execution of the MPI instruction in the

DSP program. Therefore at least once every DSP routine

an MPI instruction should be added.

MSB LSB

0 0 1 1 1 1 A0 R/W

2003 Mar 13 15

Philips Semiconductors Preliminary speciﬁcation

Digital Signal Processor SAA7715AH

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0111100A

address

S0 ADDR H ADDR L DATA 1 DATA ...

R/W

MGU331

auto increment if repeated n-groups of 2, 3 or 4 bytes

DATA 4

Fig.5 Master transmitter writes to the SAA7715AH registers.

S = START condition.

P = STOP condition.

ACK = acknowledge from SAA7715AH.

ADDR H and ADDR L = address DSP register.

DATA 1 to DATA 4 = 2, 3 or 4 bytes data word.

0111100A

address

S0011 1110

r0ADDR H ADDR L DATA 1

R/W

MGU330

auto increment if repeated n-groups of 2, 3 or 4 bytes

DATA ... DATA 4

R/W

Fig.6 Master transmitter reads from the SAA7715AH registers.

S = START condition.

Sr = repeated START condition.

P = STOP condition.

ACK = acknowledge from SAA7715AH (SDA LOW).

R = repeat n-times the 2, 3 or 4 bytes data group.

NA = Negative Acknowledge master (SDA HIGH).

ADDR H and ADDR L = address DSP register.

DATA 1 to DATA 4 = 2, 3 or 4 bytes data word.

2003 Mar 13 16

Philips Semiconductors Preliminary speciﬁcation

Digital Signal Processor SAA7715AH

9.5 Program RAM

The SAA7715AH has a 1.5 kbyte PRAM to store the DSP

instruction code into. Also a 2 kbyte PROM is on-chip

available and can be accessed (memory mapped) without

the need of selecting the PROM or PRAM. The DSP

instructioncode can be downloaded into the PRAMvia the

I2C-bus. The write and read cycle are shown in Figs 5

and 6 respectively.

The DSP has an instruction word width of 32 bits which

means that this space should be accessed with 4 bytes in

consecutive order and does have the auto-increment

function.

9.6 Data word alignment

It is possible to transfer data via the I2C-bus to a

destination where it can have different data word length.

Those destinations with data word are shown in Table 7.

Table 7 Data word alignment

SOURCE DESTINATION DATA WORD BYTES

(NUMBER)

I2C-bus DSP-PRAM MBBB BBBB BBBB BBBB BBBB BBBB BBBB BBBL 4

I2C-bus DSP and general control MBBB BBBB BBBB BBBB BBBB BBBL 3

I2C-bus I2C-bus registers MBBB BBBB BBBB BBBB BBBB BBBL 3

I2C-bus DSP-XRAM MBBB BBBB BBBB BBBB BBBB BBBL 3

I2C-bus DSP-YRAM XXXX MBBB BBBB BBBL 2

2003 Mar 13 17

Philips Semiconductors Preliminary speciﬁcation

Digital Signal Processor SAA7715AH

9.7 I2C-bus memory map speciﬁcation

The I2C-bus memory map contains all defined I2C-bus bits. The map is split up in two different sections: the hardware

memory registers and the RAM definitions. In Table 8 the preliminary memory map is depicted. The hardware registers

are memory map on the XRAM of DSP. Table 9 shows the detailed memory map of those locations. All locations are

acknowledged by the SAA7715AH even if the user tries to write to a reserved space. The data in these sections will be

lost. Reading from these locations will result in undefined data words.

Table 8 I2C-bus memory map

Table 9 I2C-bus memory map overview

ADDRESS FUNCTION SIZE

8000H to 87FFH DSP to PROM (not readable via I2C-bus) 2k ×32 bits

602FH DSP and general control 1 ×24 bits

2000H to 25FFH DSP to PRAM 1.5k ×32 bits

1000H to 15FFH DSP to YRAM 1.5k ×12 bits

0FF2H to 0FF5H, 0FFBH I2C-bus register 5 ×24 bits

0000H to 0B7FH DSP to XRAM 2.875k ×24 bits

ADDRESS DESCRIPTION

Hardware registers

0FFBH Selector register 1

0FF5H SPDIF IN channel status register 1 left

0FF4H SPDIF IN channel status register 2 left

0FF3H SPDIF IN channel status register 1 right

0FF2H SPDIF IN channel status register 2 right

DSP control

602FH DSP and general control register

2003 Mar 13 18

Philips Semiconductors Preliminary speciﬁcation

Digital Signal Processor SAA7715AH

9.8 I2C-bus memory map deﬁnition

Table 10 DSP and general control register (602FH)

Table 11 SPDIF IN channel status register 2 right (0FF2H)

Table 12 SPDIF IN channel status register 1 right (0FF3H)

NAME SIZE

(BITS) DESCRIPTION DEFAULT BIT

POSITION

1 reserved 0 0

pll_div[4:0] 5 PLL clock division factor according to Table 2 00011 5 to 1

dsp_turbo 1 PLL output frequency 1 6

1: double

0: no doubling

1 reserved 1 7

pc_reset_dsp 1 program counter reset DSP 0 8

1: reset on

0: reset off

2 reserved 00 10 to 9

sel[2:0] 3 selection of n ×fs clock at SYSCLK output according to

Table 4 010 13 to 11

sel_loop_div[1:0] 2 word select input range selection for WS_PLL according

to Table 3 01 15 to 14

2 reserved 00 17 to 16

sel_FSDAC_clk 2 clock source for FSDAC 00 19 to 18

00: WS_PLL if no signal to pin CLK_IN

01: 512fs to pin CLK_IN

11: 256fs to pin CLK_IN

dis_SYSCLK 1 output on pin SYSCLK 0 20

1: disable

0: enable

256fs_n*Fs 1 signal on pin SYSCLK 0 21

1: fixed 256fs clock

0: n ×fs clock; determined by bits 13 to 11

2 reserved 00 23 to 22

NAME SIZE

(BITS) DESCRIPTION DEFAULT BIT

POSITION

ch_stat_in right lsb 20 channel status SPDIF in right LSB bits 19 to 0 00000H 19 to 0

NAME SIZE

(BITS) DESCRIPTION DEFAULT BIT

POSITION

ch_stat_in right msb 20 channel status SPDIF in right MSB bits 39 to 20 00000H 19 to 0

2003 Mar 13 19

Philips Semiconductors Preliminary speciﬁcation

Digital Signal Processor SAA7715AH

Table 13 SPDIF IN channel status register 2 left (0FF4H)

Table 14 SPDIF IN channel status register 1 left (0FF5H)

Table 15 Selector register 1 (0FFBH)

NAME SIZE

(BITS) DESCRIPTION DEFAULT BIT

POSITION

ch_stat_in left lsb 20 channel status SPDIF in2 left LSB bits 19 to 0 00000H 19 to 0

NAME SIZE

(BITS) DESCRIPTION DEFAULT BIT

POSITION

ch_stat_in left msb 20 channel status SPDIF in2 left MSB bits 39 to 20 00000H 19 to 0

NAME SIZE

(BITS) DESCRIPTION DEFAULT BIT

POSITION

format_in1 3 digital serial inputs 1 and 4 data format according to

Table 17 011 2 to 0

format_in2 3 digital serial input 2 data format according to Table 17 011 5 to 3

format_in3 3 digital serial input 3 data format according to Table 17 011 8 to 6

format_out 3 digital serial outputs 1 to 4 data format according to

Table 18 000 11 to 9

en_output 1 enable or disable digital serial outputs 1 12

1: enable

0: disable

1 reserved 0 13

master_source 4 source selection 0000 17 to 14

0000: digital serial input 1

0101: digital serial input 2 or SPDIF 1 (see bit 18)

1010: digital serial input 3 or SPDIF 2 (see bit 19)

all other values are reserved

spdif_sel1 1 SPDIF1 or digital serial input 2 0 18

1: SPDIF1

0: digital serial input 2

spdif_sel2 1 SPDIF2 or digital serial input 3 0 19

1: SPDIF2

0: digital serial input 3

sel_spdiﬁn_chstat 1 select channel status information taken from SPDIF1 or

SPDIF2 020

1: from input SPDIF2

0: from input SPDIF1

3 reserved 000 23 to 21

2003 Mar 13 20

Philips Semiconductors Preliminary speciﬁcation

Digital Signal Processor SAA7715AH

Table 16 Default settings of I2C-bus registers after power-up and reset

9.9 Table deﬁnitions

Table 17 Digital serial format for inputs 1 to 4

Table 18 Digital serial formats for outputs 1 to 4

10 SOFTWARE IN ROM DESCRIPTION

The function of this chip is related to the PROM code (ROM code dependent).

I2C-BUS ADDRESS DEFAULT VALUE

602FH 0050C6H

0FFBH 0010DBH

0FF5H 000000H

0FF4H 000000H

0FF3H 000000H

0FF2H 000000H

format_in1, 2 and 3 INPUT

BIT 2 BIT 1 BIT 0

0 1 1 standard I2S-bus

1 0 0 LSB-justiﬁed, 16 bits

1 0 1 LSB-justiﬁed, 18 bits

1 1 0 LSB-justiﬁed, 20 bits

1 1 1 LSB-justiﬁed, 24 bits

format_out OUTPUT

BIT 2 BIT 1 BIT 0

0 0 0 standard I2S-bus

1 0 0 LSB-justiﬁed, 16 bits

1 0 1 LSB-justiﬁed, 18 bits

1 1 0 LSB-justiﬁed, 20 bits

1 1 1 LSB-justiﬁed, 24 bits

2003 Mar 13 21

Philips Semiconductors Preliminary speciﬁcation

Digital Signal Processor SAA7715AH

11 LIMITING VALUES

In accordance with the Absolute Maximum Ratings System (IEC 60134).

Notes

1. Machine model (R = 0 Ω; C = 100 pF; L = 2.5 µH).

2. Human body model (R = 1500 Ω; C = 100 pF).

12 THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VDD supply voltage −0.5 +3.6 V

VIinput voltage −0.5 +5.5 V

IIK input clamping diode current VI<−0.5 V or VI>V

DD + 0.5 V −±10 mA

IOK output clamping diode current VO<−0.5 V or VO>V

DD + 0.5 V −±20 mA

IO(sink/source) output source or sink current −0.5V<V

O<V

DD + 0.5 V −±20 mA

IDD,ISS VDD or VSS current per supply pin −±50 mA

Tamb ambient temperature −40 +85 °C

Tstg storage temperature −65 +125 °C

VESD electrostatic handling voltage note 1 200 −V

note 2 2000 −V

Ilu(prot) latch-up protection current CIC speciﬁcation/test method 100 −mA

Ptot total power dissipation −600 mW

SYMBOL PARAMETER CONDITIONS VALUE UNIT

Rth(j-a) thermal resistance from junction to

ambient mounted on printed-circuit board 60 K/W

2003 Mar 13 22

Philips Semiconductors Preliminary speciﬁcation

Digital Signal Processor SAA7715AH

13 CHARACTERISTICS

VDD = 3.15 to 3.45 V; unless otherwise speciﬁed.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies; Tamb =−40 to +85 °C

VDD operating supply voltage all pins VDD with

respect to pins VSS

3.15 3.3 3.45 V

IDDD supply current of the digital part −95 −mA

IDDD(core) supply current of the digital core

part high activity of the

DSP at DSPFREQ

frequency

−90 −mA

IDDD(peri) supply current of the digital

periphery part no external load to

ground −5−mA

IDDA supply current of the analog part zero input and output

signal −20 −mA

IDDA(DAC) supply current of the DAC zero input and output

signal −6.5 13 mA

Power-down mode −250 −µA

DDA(SPDIF) supply current of the SPDIF

inputs, on-chip PLL and WSPLL zero input and output

signals −13.5 27 mA

Ptot total power dissipation −380 −mW

IPOWERDOWN DC supply current of the total chip

in Power-down mode pin POWERDOWN

enabled −400 −µA

Digital I/O; Tamb =−40 to +85 °C; VDD = 3.15 to 3.45 V; unless otherwise speciﬁed

VIH HIGH-level input voltage all digital

inputs and I/Os 2.0 −−V

IL LOW-level input voltage all digital

inputs and I/Os −−0.8 V

Vhys Schmitt-trigger hysteresis 0.4 −−V

OH HIGH-level output voltage standard output;

IO=−4mA V

DD −0.4 −−V

5 ns slew rate output;

IO=−4mA V

DD −0.4 −−V

10 ns slew rate

output; IO=−2mA V

DD −0.4 −−V

20 ns slew rate

output; IO=−1mA V

DD −0.4 −−V

2003 Mar 13 23

Philips Semiconductors Preliminary speciﬁcation

Digital Signal Processor SAA7715AH

VOL LOW-level output voltage standard output;

IO=4mA −−0.4 V

5 ns slew rate output;

IO=4mA −−0.4 V

10 ns slew rate

output; IO=2mA −−0.4 V

20 ns slew rate

output; IO=1mA −−0.4 V

I2C-bus output;

IO=4mA −−0.4 V

ILO output leakage current 3-state

outputs VO= 0 V or VDD −−±5µA

pd internal pull-down resistor to VSS 24 50 140 kΩ

Rpu internal pull-up resistor to VDD 30 50 100 kΩ

Ciinput capacitance −−3.5 pF

ti(r),ti(f) input rise and fall times VDD = 3.45 V −6 200 ns

to(t) output transition time standard output;

CL=30pF −3.5 −ns

5 ns slew rate output;

CL=30pF −5−ns

10 ns slew rate

output; CL=30pF −10 −ns

20 ns slew rate

output; CL=30pF −20 −ns

I2C-bus output;

CL= 400 pF 60 −300 ns

AC characteristics SPDIF1 and SPDIF2 inputs; Tamb =25°C; VDDA2 = 3.3 V; unless otherwise speciﬁed

Vi(p-p) AC input level (peak-to-peak level) 0.2 0.5 3.3 V

Riinput impedance at 1 kHz −6−kΩ

Vhys hysteresis of input voltage −40 −mV

Analog DAC outputs; VDDA1 = 3.3 V; fs= 44.1 kHz; Tamb =25°C; RL=5kΩ; all voltages referenced to ground;

unless otherwise speciﬁed

DC CHARACTERISTICS

Ro(DAC) DAC output resistance −0.13 3.0 Ω

Io(max) maximum output current (THD + N)/S < 0.1%

RL=5kΩ−0.22 −mA

RLload resistance 3 −−kΩ

Lload capacitance −−200 pF

Ro(VREFDA) VREFDA output resistance −28 −kΩ

AC CHARACTERISTICS

Vo(rms) output voltage (RMS value) −1000 −mV

∆Vounbalance between channels −0.1 −dB

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

2003 Mar 13 24

Philips Semiconductors Preliminary speciﬁcation

Digital Signal Processor SAA7715AH

(THD + N)/S total harmonic distortion plus

noise-to-signal ratio at 0 dB −−85 −dB(A)

at −60 dB −−37 −dB(A)

S/N signal-to-noise ratio code = 0 −100 −dB(A)

αcs channel separation −80 −dB

PSRR power supply rejection ratio fripple = 1 kHz;

Vripple(p-p) =1% −50 −dB

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

2003 Mar 13 25

Philips Semiconductors Preliminary speciﬁcation

Digital Signal Processor SAA7715AH

14 I2S-BUS TIMING

handbook, full pagewidth

BCK

DATA IN

RIGHT

LSB MSB

LEFT

tsu(WS)

th(WS)

tsu(D) th(D)

tBCK(H)

td(D)

tBCK(L)

Tcy

trtf

MGM129

DATA OUT LSB MSB

Fig.7 Timing of the digital serial audio data inputs and outputs.

Table 19 Timing of the digital serial audio data inputs and outputs (see Fig.7)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Tcy bit clock cycle time 162 −−ns

trrise time Tcy =50ns −−0.15Tcy ns

tffall time Tcy =50ns −−0.15Tcy ns

tBCK(H) bit clock HIGH time Tcy = 50 ns 0.35Tcy −−ns

tBCK(L) bit clock LOW time Tcy = 50 ns 0.35Tcy −−ns

tsu(D) data set-up time Tcy = 50 ns 0.2Tcy −−ns

th(D) data hold time Tcy = 50 ns 0.2Tcy −−ns

td(D) data delay time Tcy =50ns −−0.15Tcy ns

tsu(WS) word select set-up time Tcy = 50 ns 0.2Tcy −−ns

th(WS) word select hold time Tcy = 50 ns 0.2Tcy −−ns

2003 Mar 13 26

Philips Semiconductors Preliminary speciﬁcation

Digital Signal Processor SAA7715AH

15 I2C-BUS TIMING

handbook, full pagewidth

MSC610

SSr tSU;STO

tSU;STA

tHD;STA tHIGH

tLOW tSU;DAT

tHD;DAT

SDA

SCL

tBUF

trtSP

tHD;STA

Fig.8 Timing of the I2C-bus.

Table 20 Timing of the I2C-bus (see Fig.8)

SYMBOL PARAMETER CONDITIONS STANDARD MODE

I2C-BUS FAST MODE I2C-BUS UNIT

MIN. MAX. MIN. MAX.

fSCL SCL clock frequency 0 100 0 400 kHz

tBUF bus free time between a

STOP and START

condition

4.7 −1.3 −µs

HD;STA hold time (repeated)

START condition; after this

period, the ﬁrst clock pulse

is generated

4.0 −0.6 −µs

LOW SCL LOW period 4.7 −1.3 −µs

HIGH SCL HIGH period 4.0 −0.6 −µs

SU;STA set-up time for a repeated

START condition 4.7 −0.6 −µs

HD;DAT DATA hold time 0 −0 0.9 µs

tSU;DAT DATA set-up time 250 −100 −ns

trrise time of both SDA and

SCL signals Cbin pF −1000 20 + 0.1Cb300 ns

tffall time of both SDA and

SCL signals Cbin pF −300 20 + 0.1Cb300 ns

tSU;STO set-up time for STOP

condition 4.0 −0.6 −µs

bcapacitive load for each

bus line −400 −400 pF

tSP pulse width of spikes to be

suppressed by input ﬁlter not applicable 0 50 ns

2003 Mar 13 27

Philips Semiconductors Preliminary speciﬁcation

Digital Signal Processor SAA7715AH

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16 APPLICATION DIAGRAM

handbook, full pagewidth

MHC321

4.7 kΩ4.7 kΩ

22 kΩ

100 Ω

10 kΩ10 kΩ

22 kΩ

47 µF

1 µF(1)

100 nF

100

nF 100

4.7 µF

+5 V +5 V

+3.3 V

SAA7715AH

TCB

PRAM PROM

DSP CORE

STEREO

DAC

n × fs

CLOCK

I2C-BUS WS_PLL

I2C-bus

÷ 2 PLL

1IIS_BCK1

24 25

IIS_WS1

3IIS_IN1

5IIS_IN4

IIS_OUT131

IIS_OUT230

IIS_OUT329

IIS_OUT428

VOUTL34

VOUTR36

IIS_BCK33

IIS_WS32

POM39

VREFDA38

digital

inputs

digital

outputs

22 41

IIS_IN3

CLK_IN

DIV_CLK_IN

DSP CLOCK

DSP flags

microcontroller

right output

left output

IIS_IN2

XRAM YRAM

DSP_INOUT7

DSP_INOUT6

DSP_INOUT5

SHTCB

RTCB

VSSI2

TSCAN

VSSI1

VSSE

VSSA2

VDDI1

VDDE

VDDA2

VDDA1

SPDIF2

SPDIF1

VSSA1

SYSCLK

DSP_RESET

SDA

SCL

POWERDOWN

10 Ω

75 Ω

47 µF

µF47

µF

100 nF

SPDIF

input signals

100 nF

100 pF

75 Ω

100 pF

RESERVED1

RESERVED2

RESERVED3

Fig.9 Application diagram.

(1) Omit this capacitor when a microcontroller is used.

2003 Mar 13 28

Philips Semiconductors Preliminary speciﬁcation

Digital Signal Processor SAA7715AH

17 PACKAGE OUTLINE

UNIT A1A2A3bpcE

(1) eH

pZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.25

0.05 1.85

1.65 0.25 0.4

0.2 0.25

0.14 10.1

9.9 0.8 1.3

12.9

12.3 1.2

0.8 10

0.15 0.10.15

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.95

0.55

SOT307-2 97-08-01

03-02-25

D(1) (1)(1)

10.1

9.9

12.9

12.3

1.2

0.8

vMA

34 33 23 22

detail X

(A )

pin 1 index

HvMB

0 2.5 5 mm

scale

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2

max.

2.1

2003 Mar 13 29

Philips Semiconductors Preliminary speciﬁcation

Digital Signal Processor SAA7715AH

18 SOLDERING

18.1 Introduction to soldering surface mount

packages

Thistextgivesaverybrief insight to acomplextechnology.

A more in-depth account of soldering ICs can be found in

our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering can still be used for

certainsurfacemountICs,butitisnotsuitableforfinepitch

SMDs. In these situations reflow soldering is

recommended.

18.2 Reﬂow soldering

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

tothe printed-circuit boardby screen printing,stencilling or

pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,

convection or convection/infrared heating in a conveyor

type oven. Throughput times (preheating, soldering and

cooling) vary between 100 and 200 seconds depending

on heating method.

Typical reflow peak temperatures range from

215 to 250 °C. The top-surface temperature of the

packages should preferable be kept below 220 °C for

thick/large packages, and below 235 °C for small/thin

packages.

18.3 Wave soldering

Conventional single wave soldering is not recommended

forsurfacemountdevices(SMDs)orprinted-circuitboards

with a high component density, as solder bridging and

non-wetting can present major problems.

To overcome these problems the double-wave soldering

method was specifically developed.

If wave soldering is used the following conditions must be

observed for optimal results:

•Use a double-wave soldering method comprising a

turbulent wave with high upward pressure followed by a

smooth laminar wave.

•For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the

transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the

printed-circuit board.

The footprint must incorporate solder thieves at the

downstream end.

•Forpackageswithleadsonfoursides,thefootprintmust

be placed at a 45°angle to the transport direction of the

printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

18.4 Manual soldering

Fix the component by first soldering two

diagonally-opposite end leads. Use a low voltage (24 V or

less) soldering iron applied to the flat part of the lead.

Contact time must be limited to 10 seconds at up to

300 °C.

When using a dedicated tool, all other leads can be

soldered in one operation within 2 to 5 seconds between

270 and 320 °C.

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18.5 Suitability of surface mount IC packages for wave and reﬂow soldering methods

Notes

1. Formoredetailed information onthe BGA packagesreferto the

“(LF)BGAApplication Note

”(AN01026);order a copy

from your Philips Semiconductors sales office.

2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package

cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the

Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder

cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,

the solder might be deposited on the heatsink surface.

4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not

suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

PACKAGE(1) SOLDERING METHOD

WAVE REFLOW(2)

BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable

HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN,

HVSON, SMS not suitable(3) suitable

PLCC(4), SO, SOJ suitable suitable

LQFP, QFP, TQFP not recommended(4)(5) suitable

SSOP, TSSOP, VSO not recommended(6) suitable

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19 DATA SHEET STATUS

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was

published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

DATA SHEET STATUS(1) PRODUCT

STATUS(2) DEFINITIONS

Objective data Development This data sheet contains data from the objective specification for product

development. Philips Semiconductors reserves the right to change the

speciﬁcation in any manner without notice.

Preliminary data Qualiﬁcation This data sheet contains data from the preliminary specification.

Supplementary data will be published at a later date. Philips

Semiconductors reserves the right to change the speciﬁcation without

notice, in order to improve the design and supply the best possible

product.

Product data Production This data sheet contains data from the product specification. Philips

Semiconductors reserves the right to make changes at any time in order

to improve the design, manufacturing and supply. Changes will be

communicated according to the Customer Product/Process Change

Notiﬁcation (CPCN) procedure SNW-SQ-650A.

20 DEFINITIONS

Short-form specification  The data in a short-form

specification is extracted from a full data sheet with the

same type number and title. For detailed information see

the relevant data sheet or data handbook.

Limiting values definition Limiting values given are in

accordance with the Absolute Maximum Rating System

(IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device.

These are stress ratings only and operation of the device

attheseorat any otherconditionsabovethosegiven in the

Characteristics sections of the specification is not implied.

Exposure to limiting values for extended periods may

affect device reliability.

Application information  Applications that are

described herein for any of these products are for

illustrative purposes only. Philips Semiconductors make

norepresentationor warranty that suchapplicationswillbe

suitable for the specified use without further testing or

modification.

21 DISCLAIMERS

Life support applications  These products are not

designed for use in life support appliances, devices, or

systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips

Semiconductorscustomersusing orsellingtheseproducts

for use in such applications do so at their own risk and

agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Right to make changes  Philips Semiconductors

reserves the right to make changes, without notice, in the

products, including circuits, standard cells, and/or

software, described or contained herein in order to

improve design and/or performance. Philips

Semiconductors assumes no responsibility or liability for

theuseofanyoftheseproducts,conveysnolicenceortitle

under any patent, copyright, or mask work right to these

products,andmakes no representationsorwarranties that

these products are free from patent, copyright, or mask

work right infringement, unless otherwise specified.

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22 PURCHASE OF PHILIPS I2C COMPONENTS

Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the

components in the I2C system provided the system conforms to the I2C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

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NOTES

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Digital Signal Processor SAA7715AH

NOTES

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Philips Semiconductors Preliminary speciﬁcation

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NOTES

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Philips Semiconductors – a world wide company

Contact information

For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825

For sales ofﬁces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.

Printed in The Netherlands 753503/01/pp36 Date of release: 2003 Mar 13 Document order number: 9397 750 10206