IS41LV44052B 4M x 4 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE JANUARY 2010 FEATURES DESCRIPTION * Fast Page Mode Access Cycle * TTL compatible inputs and outputs * Refresh Interval: -- 2,048 cycles/32 ms * Refresh Mode: RAS-Only, CAS-before-RAS (CBR), and Hidden * Single power supply: 3.3V 10% * Byte Write and Byte Read operation via two CAS * Industrial temperature range -40C to 85C The ISSI IS41LV44052B is a 4,194,304 x 4-bit high-performance CMOS Dynamic Random Access Memory. The Fast Page Mode allows 2,048 or 4096 random accesses within a single row with access cycle time as short as 20 ns per 4-bit word. These features make the IS41LV44052B ideally suited for high-bandwidth graphics, digital signal processing, high-performance computing systems, and peripheral applications. The IS41LV44052B is packaged in a 24-pin TSOP-II with JEDEC standard pinouts. PRODUCT SERIES OVERVIEW KEY TIMING PARAMETERS Part No. IS41LV44052B Refresh 2K Voltage 3.3V 10% Parameter RAS Access Time (trac) CAS Access Time (tcac) Column Address Access Time (taa) Fast Page Mode Cycle Time (tpc) Read/Write Cycle Time (trc) -50 50 13 25 20 84 -60 60 15 30 25 104 Unit ns ns ns ns ns PIN CONFIGURATION 24 (26) Pin TSOP-II PIN DESCRIPTIONS VCC 1 24 GND I/O0 2 23 I/O3 I/O1 3 22 I/O2 WE 4 21 CAS RAS 5 20 OE *A11(NC) 6 19 A9 A10 7 18 A8 A0 8 17 A7 A1 9 16 A6 A2 10 15 A5 A3 11 14 A4 VCC 12 13 GND A0-A10 I/O0-3 WE OE RAS CAS Vcc GND NC Address Inputs (2K Refresh) Data Inputs/Outputs Write Enable Output Enable Row Address Strobe Column Address Strobe Power Ground No Connection * A11 is NC for 2K Refresh devices. Copyright (c) 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. C 12/21/09 1 IS41LV44052B FUNCTIONAL BLOCK DIAGRAM OE WE CAS CAS CONTROL LOGIC WE CONTROL LOGICS CAS WE OE CONTROL LOGIC OE DATA I/O BUS COLUMN DECODERS SENSE AMPLIFIERS A0-A10(A11) ADDRESS BUFFERS ROW DECODER REFRESH COUNTER MEMORY ARRAY 4,194,304 x 4 DATA I/O BUFFERS RAS CLOCK GENERATOR RAS RAS I/O0-I/O3 TRUTH TABLE Function Standby Read Write: Word (Early Write) Read-Write Hidden Refresh Read Write(1) RAS-Only Refresh CBR Refresh RAS H L L L LHL LHL HL HL CAS H L L L L L H L WE X H L HL H L X X OE X L X LH L X X X Address tr/tc X ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL ROW/NA X I/O High-Z Dout Din Dout, Din Dout Dout High-Z High-Z Note: 1. EARLY WRITE only. 2 Integrated Silicon Solution, Inc. Rev. C 12/21/09 IS41LV44052B Functional Description Auto Refresh Cycle The IS41LV44052B is a CMOS DRAM optimized for highspeed bandwidth, low power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 11 address bits. These are entered 11 bits (A0-A10) at a time for the 2K refresh device. The row address is latched by the Row Address Strobe (RAS). The column address is latched by the Column Address Strobe (CAS). RAS is used to latch the first nine bits and CAS is used the latter ten bits. To retain data, 2,048 refresh cycles are required in each 32 ms period. There are two ways to refresh the memory: Memory Cycle A memory cycle is initiated by bring RAS LOW and it is terminated by returning both RAS and CAS HIGH. To ensures proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum tras time has expired. A new cycle must not be initiated until the minimum precharge time trp, tcp has elapsed. Read Cycle A read cycle is initiated by the falling edge of CAS or OE, whichever occurs last, while holding WE HIGH.The column address must be held for a minimum time specified by tar. Data Out becomes valid only when trac, taa, tcac and toea are all satisfied. As a result, the access time is dependent on the timing relationships between these parameters. 1. By clocking each of the 2,048 row addresses (A0 through A10) with RAS at least once every 32 ms. Any read, write, read-modify-write or RAS-only cycle refreshes the addressed row. 2. Using a CAS-before-RAS refresh cycle. CAS-before-RAS refresh is activated by the falling edge of RAS, while holding CAS LOW. In CAS-before-RAS refresh cycle, an internal 9-bit counter provides the row addresses and the external address inputs are ignored. CAS-before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle. Power-On After application of the Vcc supply, an initial pause of 200 s is required followed by a minimum of eight initialization cycles (any combination of cycles containing a RAS signal). During power-on, it is recommended that RAS track with Vcc or be held at a valid Vih to avoid current surges. Write Cycle A write cycle is initiated by the falling edge of CAS and WE, whichever occurs last. The input data must be valid at or before the falling edge of CAS or WE, whichever occurs last. Integrated Silicon Solution, Inc. Rev. C 12/21/09 3 IS41LV44052B ABSOLUTE MAXIMUM RATINGS(1) Symbol Vt Vcc Iout Pd Ta Tstg Parameters Voltage on Any Pin Relative to GND 3.3V Supply Voltage 3.3V Output Current Power Dissipation Commercial Operation Temperature Industrial Operation Temperature Storage Temperature Rating -0.5 to +4.6 -0.5 to +4.6 50 1 0 to +70 -40 to +85 -55 to +125 Unit V V mA W C C Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.) Symbol Vcc Vih Vil Ta Parameter Supply Voltage 3.3V Input High Voltage 3.3V Input Low Voltage 3.3V Commercial Ambient Temperature Industrial Ambient Temperature Min. 3.0 2.0 -0.3 0 -40 Typ. 3.3 -- -- -- -- Max. 3.6 Vcc + 0.3 0.8 70 85 Unit V V V C C CAPACITANCE(1,2) Symbol Cin1 Cin2 Cio Parameter Input Capacitance: A0-A10 Input Capacitance: RAS, CAS, WE, OE Data Input/Output Capacitance: I/O0-I/O3 Max. 5 7 7 Unit pF pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25C, f = 1 MHz. 4 Integrated Silicon Solution, Inc. Rev. C 12/21/09 IS41LV44052B ELECTRICAL CHARACTERISTICS(1) (Recommended Operating Conditions unless otherwise noted.) Symbol Parameter Test Condition Vcc Speed Iil Input Leakage Current Any input 0V Vin Vcc Other inputs not under test = 0V Iio Output Leakage Current Output is disabled (Hi-Z) 0V Vout Vcc Voh Output High Voltage Level Ioh = -2.0 mA, Vcc = 3.3V Vol Output Low Voltage Level Iol = 2 mA, Vcc = 3.3V Icc1 Standby Current: TTL RAS, CAS Vih Commercial 3.3V Industrial 3.3V Icc2 Standby Current: CMOS RAS, CAS Vcc - 0.2V 3.3V Icc3 Operating Current: RAS, CAS, -50 Random Read/Write(2,3) Address Cycling, trc = trc (min.) -60 Average Power Supply Current Icc4 Operating Current: RAS= Vil, CAS Vih -50 Fast Page Mode(2,3,4) trc = trc (min.) -60 Average Power Supply Current Icc4 Refresh Current: RAS Cycling, CAS Vih -50 RAS-Only(2,3) trc = trc (min.) -60 Average Power Supply Current Icc5 Refresh Current: RAS, CAS Cycling -50 CBR(2,3,5) trc = trc (min.) -60 Average Power Supply Current Min. -5 Max. 5 Unit A -5 5 A 2.4 -- -- -- -- -- -- -- 0.4 0.5 2 0.5 120 110 V V mA -- -- 90 80 mA -- -- 120 110 mA -- -- 120 110 mA mA mA Notes: 1. An initial pause of 200 s is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tref refresh requirement is exceeded. 2. Dependent on cycle rates. 3. Specified values are obtained with minimum cycle time and the output open. 4. Column-address is changed once each Fast Page cycle. 5. Enables on-chip refresh and address counters. Integrated Silicon Solution, Inc. Rev. C 12/21/09 5 IS41LV44052B AC CHARACTERISTICS(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) -50 -60 Symbol Parameter Min. Max. Min. Max. trc Random READ or WRITE Cycle Time 84 -- 104 -- trac Access Time from RAS(6, 7) -- 50 -- 60 tcac Access Time from CAS(6, 8, 15) -- 13 -- 15 (6) taa Access Time from Column-Address -- 25 -- 30 tras RAS Pulse Width 50 10K 60 10K trp RAS Precharge Time 30 -- 40 -- (23) tcas CAS Pulse Width 8 10K 10 10K (9) tcp CAS Precharge Time 9 -- 9 -- (21) tcsh CAS Hold Time 38 -- 40 -- trcd RAS to CAS Delay Time(10, 20) 12 37 14 45 tasr Row-Address Setup Time 0 -- 0 -- trah Row-Address Hold Time 8 -- 10 -- (20) tasc Column-Address Setup Time 0 -- 0 -- tcah Column-Address Hold Time(20) 8 -- 10 -- tar Column-Address Hold Time 30 -- 40 -- (referenced to RAS) trad RAS to Column-Address Delay Time(11) 10 25 12 30 tral Column-Address to RAS Lead Time 25 -- 30 -- trpc RAS to CAS Precharge Time 5 -- 5 -- trsh RAS Hold Time 8 -- 10 -- trhcp RAS Hold Time from CAS Precharge 30 -- 35 -- (15, 24) tclz CAS to Output in Low-Z 0 -- 0 -- tcrp CAS to RAS Precharge Time(21) 5 -- 5 -- (19, 24) tod Output Disable Time 3 15 3 15 (15, 16) toe Output Enable Time -- 12 -- 15 toed Output Enable Data Delay (Write) 12 -- 15 -- toehc OE HIGH Hold Time from CAS HIGH 5 -- 5 -- toep OE HIGH Pulse Width 10 -- 10 -- toes OE LOW to CAS HIGH Setup Time 5 -- 5 -- (17, 20) trcs Read Command Setup Time 0 -- 0 -- trrh Read Command Hold Time 0 -- 0 -- (referenced to RAS)(12) trch Read Command Hold Time 0 -- 0 -- (referenced to CAS)(12, 17, 21) twch Write Command Hold Time(17) 8 -- 10 -- twcr Write Command Hold Time 40 -- 50 -- (referenced to RAS)(17) twp Write Command Pulse Width(17) 8 -- 10 -- twpz WE Pulse Widths to Disable Outputs 7 -- 7 -- 6 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Integrated Silicon Solution, Inc. Rev. C 12/21/09 IS41LV44052B AC CHARACTERISTICS (Continued)(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) -50 -60 Symbol Parameter Min. Max. Min. Max. (17) trwl Write Command to RAS Lead Time 13 -- 15 -- tcwl Write Command to CAS Lead Time(17, 21) 8 -- 10 -- twcs Write Command Setup Time(14, 17, 20) 0 -- 0 -- tdhr Data-in Hold Time (referenced to RAS) 39 -- 39 -- tach Column-Address Setup Time to CAS 15 -- 15 -- Precharge during WRITE Cycle toeh OE Hold Time from WE during 8 -- 10 -- READ-MODIFY-WRITE cycle(18) tds Data-In Setup Time(15, 22) 0 -- 0 -- (15, 22) tdh Data-In Hold Time 8 -- 10 -- trwc READ-MODIFY-WRITE Cycle Time 108 -- 133 -- trwd RAS to WE Delay Time during 64 -- 77 -- READ-MODIFY-WRITE Cycle(14) tcwd CAS to WE Delay Time(14, 20) 26 -- 32 -- (14) tawd Column-Address to WE Delay Time 39 -- 47 -- tpc Fast Page Mode READ or WRITE 20 -- 25 -- Cycle Time trasp RAS Pulse Width 50 100K 60 100K tcpa Access Time from CAS Precharge(15) -- 30 -- 35 (24) tprwc READ-WRITE Cycle Time 56 -- 68 -- tcoh Data Output Hold after CAS LOW 5 -- 5 -- toff Output Buffer Turn-Off Delay from 0 12 0 15 CAS or RAS(13,15,19, 24) twhz Output Disable Delay from WE 3 10 3 10 (20, 25) tcsr CAS Setup Time (CBR REFRESH) 5 -- 5 -- tchr CAS Hold Time (CBR REFRESH)( 21, 25) 8 -- 10 -- tord OE Setup Time prior to RAS during 0 -- 0 -- HIDDEN REFRESH Cycle tref Auto Refresh Period 2,048 Cycles -- 32 -- 32 (2, 3) tt Transition Time (Rise or Fall) 1 50 1 50 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns AC TEST CONDITIONS Output load: One TTL Load and 50 pF (Vcc = 3.3V 10%) Input timing reference levels: Vih = 2.0V, Vil = 0.8V (Vcc = 3.3V 10%) Output timing reference levels: Voh = 2.0V, Vol = 0.8V (Vcc = 3.3V 10%) Integrated Silicon Solution, Inc. Rev. C 12/21/09 7 IS41LV44052B Notes: 1. An initial pause of 200 s is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tref refresh requirement is exceeded. 2. Vih (MIN) and Vil (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between Vih and Vil (or between Vil and Vih) and assume to be 1 ns for all inputs. 3. In addition to meeting the transition rate specification, all input signals must transit between Vih and Vil (or between Vil and Vih) in a monotonic manner. 4. If CAS and RAS = Vih, data output is High-Z. 5. If CAS = Vil, data output may contain data from the last valid READ cycle. 6. Measured with a load equivalent to one TTL gate and 50 pF. 7. Assumes that trcd trcd (MAX). If trcd is greater than the maximum recommended value shown in this table, trac will increase by the amount that trcd exceeds the value shown. 8. Assumes that trcd trcd (MAX). 9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the data output buffer, CAS and RAS must be pulsed for tcp. 10. Operation with the trcd (MAX) limit ensures that trac (MAX) can be met. trcd (MAX) is specified as a reference point only; if trcd is greater than the specified trcd (MAX) limit, access time is controlled exclusively by tcac. 11. Operation within the trad (MAX) limit ensures that trcd (MAX) can be met. trad (MAX) is specified as a reference point only; if trad is greater than the specified trad (MAX) limit, access time is controlled exclusively by taa. 12. Either trch or trrh must be satisfied for a READ cycle. 13. toff (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to Voh or Vol. 14. twcs, trwd, tawd and tcwd are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If twcs twcs (MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If trwd trwd (MIN), tawd tawd (MIN) and tcwd tcwd (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to Vih) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle. 15. Output parameter (I/O) is referenced to corresponding CAS input. 16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE WRITE or READ-MODIFY-WRITE is not possible. 17. Write command is defined as WE going low. 18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tod and toeh met (OE HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW and OE is taken back to LOW after toeh is met. 19. The I/Os are in open during READ cycles once tod or toff occur. 20. Determined by falling edge of CAS. 21. Determined by rising edge of CAS. 22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READMODIFY-WRITE cycles. 23. CAS must meet minimum pulse width. 24. The 3 ns minimum is a parameter guaranteed by design. 25. Enables on-chip refresh and address counters. 8 Integrated Silicon Solution, Inc. Rev. C 12/21/09 IS41LV44052B FAST-PAGE-MODE READ CYCLE tRC tRAS tRP RAS tCSH tCRP tRSH tCAS tCLCH tRCD tRRH CAS tAR tRAD tRAH tASR ADDRESS tRAL tCAH tASC Row Column Row tRCS tRCH WE tAA tRAC tCAC tCLC I/O tOFF(1) Open Open Valid Data tOE tOD OE tOES Don't Care Integrated Silicon Solution, Inc. Rev. C 12/21/09 9 IS41LV44052B FAST PAGE MODE READ-MODIFY-WRITE CYCLE tRASP tRP RAS tPRWC tCAS tCSH tCRP tCAS tRCD tRSH tCAS tCP tCRP tCP CAS tAR tRAH tASR ADDRESS tCPWD tRAL tCAH tCPWD tRAD tASC Row tCAH tAR Column tASC Column tCWL tRWD tAWD tCWD tRCS tCAH tASC Column tCWL tRWL tCWL tAWD tCWD tWP tAWD tCWD tWP tWP WE tAA tAA tCAC tOEA OE tCAC tOEA tOEZ tOED tRAC OUT IN tOEA tOEZ tOED tDH tDS tCLZ tCLZ I/O tAA tCAC tDS OUT IN tDH tOEZ tOED tCLZ OUT tDS tDH IN Don't Care 10 Integrated Silicon Solution, Inc. Rev. C 12/21/09 IS41LV44052B FAST-PAGE-MODE EARLY WRITE CYCLE (OE = DON'T CARE) tRC tRAS tRP RAS tCSH tCRP tRSH tCAS tCLCH tRCD CAS tAR tRAD tASR ADDRESS tRAH tRAL tCAH tACH tASC Row Column Row tCWL tRWL tWCR tWCS tWCH tWP WE tDHR tDS I/O tDH Valid Data Don't Care Integrated Silicon Solution, Inc. Rev. C 12/21/09 11 IS41LV44052B FAST-PAGE-MODE READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles) tRWC tRAS tRP RAS tCSH tCRP tRSH tCAS tCLCH tRCD CAS tAR tRAD tRAH tASR tRAL tCAH tASC tACH ADDRESS Row Column Row tRWD tCWL tRWL tCWD tAWD tRCS tWP WE tAA tRAC tCAC tCLZ I/O tDS Open Valid DOUT tOE tOD tDH Valid DIN Open tOEH OE Don't Care 12 Integrated Silicon Solution, Inc. Rev. C 12/21/09 IS41LV44052B FAST PAGE MODE EARLY WRITE CYCLE tRASP tRP RAS tCRP tCAS tRCD tRHCP tRSH tCAS tPC tCAS tCSH tCP tCP tCRP CAS tAR tRAH tRAD tASC tASR ADDRESS Row tCAH tASC tAR Column tWCH tASC Column tCWL tWCS tRAL tCAH Column tCWL tCWL tWCH tWCS tWCS tWP tCAH tWP tWCH tWP WE tWCR OE tDHR tDS I/O tDH Valid DIN tDS tDH Valid DIN tDS tDH Valid DIN Don't Care Integrated Silicon Solution, Inc. Rev. C 12/21/09 13 IS41LV44052B AC WAVEFORMS READ CYCLE (With WE-Controlled Disable) RAS tCSH tCRP tRCD tCP tCAS CAS tAR tRAD tRAH tASR ADDRESS tCAH tASC Row tASC Column Column tRCS tRCH tRCS WE tAA tRAC tCAC tCLZ Open I/O tWHZ tCLZ Valid Data Open tOE tOD OE Don't Care RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE) tRC tRAS tRP RAS tCRP tRPC CAS tASR ADDRESS I/O tRAH Row Row Open Don't Care 14 Integrated Silicon Solution, Inc. Rev. C 12/21/09 IS41LV44052B CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE) tRP tRAS tRP tRAS RAS tCHR tRPC tCP tCHR tRPC tCSR tCSR CAS Open I/O Don't Care HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW) tRAS tRP tRAS RAS tCRP tRCD tRSH tCHR CAS tAR tRAD tRAH tASC tASR ADDRESS Row tRAL tCAH Column tAA tRAC tOFF(2) tCAC tCLZ I/O Open Valid Data tOE Open tOD tORD OE Don't Care Integrated Silicon Solution, Inc. Rev. C 12/21/09 15 IS41LV44052B ORDERING INFORMATION Commercial Range: 0C to 70C Voltage: 3.3V Speed (ns) 50 60 Order Part No. IS41LV44052B-50TL IS41LV44052B-60TL Refresh 2K 2K Package 300-mil TSOP-II, Alloy42 leadframe plated with matte Sn 300-mil TSOP-II, Alloy42 leadframe plated with matte Sn Order Part No. Refresh IS41LV44052B-50TLI 2K IS41LV44052B-50CTGI 2K IS41LV44052B-60TLI 2K Package 300-mil TSOP-II, Alloy42 leadframe plated with matte Sn 300-mil TSOP-II, Cu leadframe plated with matte SnBi 300-mil TSOP-II, Alloy42 leadframe plated with matte Sn Industrial Range: -40C to +85C Voltage: 3.3V Speed (ns) 50 60 Notes: 1. Part numbers with TL, TLI, CTG, or CTGI are lead-free, and RoHS compliant. 2. For the "G" option, Bi is 3% or less of SnBi plating. 16 Integrated Silicon Solution, Inc. Rev. C 12/21/09 Integrated Silicon Solution, Inc. Rev. C 12/21/09 Package Outline 4. REFERENCE DOCUMENT : JEDEC SPEC. MS-025 , A 07/07/2008 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. 2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION. 1. CONTROLLING DIMENSION : MM NOTE : IS41LV44052B 17