Integrated Silicon Solution, Inc. — 1-800-379-4774 1
Rev. C
12/21/09
IS41LV44052B
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
FEATURES
• FastPageModeAccessCycle
• TTLcompatibleinputsandoutputs
• RefreshInterval:
-- 2,048 cycles/32 ms
• RefreshMode:RAS-Only,
CAS-before-RAS(CBR),andHidden
• Singlepowersupply:
3.3V ± 10%
• ByteWriteandByteReadoperationviatwoCAS
• Industrialtemperaturerange-40°Cto85°C
DESCRIPTION
TheISSIIS41LV44052Bisa4,194,304x4-bithigh-performance
CMOSDynamicRandomAccessMemory.TheFastPage
Mode allows 2,048 or 4096 random accesses within a
single row with access cycle time as short as 20 ns per
4-bit word.
These features make the IS41LV44052B ideally suited
for high-bandwidth graphics, digital signal processing,
high-performance computing systems, and peripheral
applications.
TheIS41LV44052Bispackagedina24-pinTSOP-IIwith
JEDECstandardpinouts.
4M x 4 (16-MBIT) DYNAMIC RAM
WITH FAST PAGE MODE JANUARY 2010
KEY TIMING PARAMETERS
Parameter -50 -60 Unit
RAS AccessTime(tr a c ) 50 60 ns
CASAccessTime(tc a c ) 13 15 ns
ColumnAddressAccessTime(ta a )
25 30 ns
FastPageModeCycleTime(tp c )
20 25 ns
Read/WriteCycleTime(tr c ) 84 104 ns
PRODUCT SERIES OVERVIEW
Part No. Refresh Voltage
IS41LV44052B 2K 3.3V±10%
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I/O0
I/O1
WE
RAS
*A11(NC)
A10
A0
A1
A2
A3
VCC
GND
I/O3
I/O2
CAS
OE
A9
A8
A7
A6
A5
A4
GND
*A11isNCfor2KRefreshdevices.
PIN DESCRIPTIONS
A0-A10 AddressInputs(2KRefresh)
I/O0-3 DataInputs/Outputs
WE WriteEnable
OE Output Enable
RAS RowAddressStrobe
CAS Column Address Strobe
Vcc Power
GND Ground
NC No Connection
PIN CONFIGURATION
24 (26) Pin TSOP-II
2 Integrated Silicon Solution, Inc.
Rev. C
12/21/09
IS41LV44052B
FUNCTIONAL BLOCK DIAGRAM
OE
WE
CAS CAS WE
OE
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
MEMORY ARRAY
4,194,304 x 4
ROW DECODER
DATA I/O BUFFERS
CAS
CONTROL
LOGIC
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
I/O0-I/O3
RAS
RAS
A0-A10(A11)
RAS
CLOCK
GENERATOR
REFRESH
COUNTER
ADDRESS
BUFFERS
TRUTH TABLE
Function RAS CAS WE OE Address tR/tC I/O
Standby H H X X X High-Z
Read L L H L ROW/COL Do u t
Write:Word(EarlyWrite) L L L X ROW/COL Di n
Read-Write L L H→L L→H ROW/COL Do u t ,Di n
HiddenRefresh Read L→H→L L H L ROW/COL Do u t
Write(1)L→H→L L L X ROW/COL Do u t
RAS-OnlyRefresh H→L H X X ROW/NA High-Z
CBRRefresh H→L L X X X High-Z
Note:
1. EARLYWRITEonly.
Integrated Silicon Solution, Inc. 3
Rev. C
12/21/09
IS41LV44052B
Functional Description
TheIS41LV44052BisaCMOSDRAM
optimized for high-
speed
bandwidth,lowpowerapplications.DuringREAD
orWRITEcycles,eachbitisuniquelyaddressedthrough
the11addressbits.Theseareentered11bits(A0-A10)
atatimeforthe2Krefreshdevice.Therowaddressis
latchedbytheRowAddressStrobe(RAS).Thecolumn
address is latched by the Column Address Strobe (CAS).
RAS is used to latch the first nine bits and CAS is used
the latter ten bits.
Memory Cycle
A memory cycle is initiated by bring RASLOWanditis
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or aborted
before the minimum tr a s timehasexpired.Anewcycle
must not be initiated until the minimum precharge time
tr p , tc p has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WEHIGH.Thecolumn
address must be held for a minimum time specified by ta r .
DataOutbecomesvalidonlywhentr a c , ta a , tc a c and to e a
are all satisfied. As a result, the access time is dependent
on the timing relationships between these parameters.
Write Cycle
A write cycle is initiated by the falling edge of CAS and
WE,whicheveroccurslast.Theinputdatamustbevalid
at or before the falling edge of CAS or WE, whichever
occurs last.
Auto Refresh Cycle
Toretaindata,2,048refreshcyclesarerequiredineach
32msperiod.Therearetwowaystorefreshthemem-
ory:
1. By clocking each of the 2,048 row addresses (A0 through
A10)withRASatleastonceevery 32ms.Anyread,
write,read-modify-writeorRAS-onlycycle refreshes
the addressed row.
2.
Using a CAS-before-RAS refresh cycle. CAS-before-RAS
refresh is activated by the falling edge of RAS, while
holding CASLOW.InCAS-before-RAS refresh cycle,
an internal 9-bit counter provides the row addresses
andtheexternaladdressinputsareignored.
CAS-before-RAS is a refresh-only mode and no data
accessor deviceselection isallowed.Thus,theoutput
remainsintheHigh-Zstateduringthecycle.
Power-On
After application of the Vc c supply, an initial pause of
200 µs is required followed by a minimum of eight ini-
tialization cycles (any combination of cycles containing a
RASsignal).
Duringpower-on,itisrecommendedthatRAS track with
Vc c or be held at a valid Vi h to avoid current surges.
4 Integrated Silicon Solution, Inc.
Rev. C
12/21/09
IS41LV44052B
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameters Rating Unit
Vt VoltageonAnyPinRelativetoGND 3.3V –0.5to+4.6 V
Vc c SupplyVoltage 3.3V –0.5to+4.6 V
Io u t Output Current 50 mA
Pd PowerDissipation 1 W
Ta CommercialOperationTemperature 0to+70 °C
IndustrialOperationTemperature -40to+85
Ts t g StorageTemperature –55to+125 °C
Note:
1. StressgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGSmaycausepermanentdamagetothedevice.
Thisisastressratingonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethoseindi-
catedintheoperationalsectionsofthisspecicationisnotimplied.Exposuretoabsolutemaximumratingconditions
forextendedperiodsmayaffectreliability.
RECOMMENDED OPERATING CONDITIONS (VoltagesarereferencedtoGND.)
Symbol Parameter Min. Typ. Max. Unit
Vc c SupplyVoltage 3.3V 3.0 3.3 3.6 V
Vi h InputHighVoltage 3.3V 2.0 — Vc c +0.3 V
Vi l InputLowVoltage 3.3V –0.3 — 0.8 V
Ta CommercialAmbientTemperature 0 — 70 °C
IndustrialAmbientTemperature -40 — 85 °C
CAPACITANCE(1,2)
Symbol Parameter Max. Unit
Ci n 1 InputCapacitance:A0-A10 5 pF
Ci n 2 InputCapacitance:RAS, CAS, WE, OE 7 pF
Ci o DataInput/OutputCapacitance:I/O0-I/O3 7 pF
Notes:
1. Testedinitiallyandafteranydesignorprocesschangesthatmayaffecttheseparameters.
2. Testconditions:T
a=25°C,f=1MHz.
Integrated Silicon Solution, Inc. 5
Rev. C
12/21/09
IS41LV44052B
ELECTRICAL CHARACTERISTICS(1)
(RecommendedOperatingConditionsunlessotherwisenoted.)
Symbol Parameter Test Condition VC C Speed Min. Max. Unit
ii l InputLeakageCurrent Anyinput0V≤ Vi n ≤Vcc –5 5 µA
Other inputs not under test = 0V
ii o OutputLeakageCurrent Outputisdisabled(Hi-Z) –5 5 µA
0V ≤ Vo u t ≤ Vcc
Vo h
OutputHighVoltageLevel
io h =–2.0mA,Vcc=3.3V 2.4 — V
Vo l
OutputLowVoltageLevel
io l =2mA,Vcc=3.3V — 0.4 V
ic c 1 StandbyCurrent:TTL RAS, CAS ≥ Vi h
Commercial
3.3V — 0.5 mA
Industrial
3.3V — 2
ic c 2 StandbyCurrent:CMOS RAS, CAS ≥ Vc c –0.2V 3.3V — 0.5 mA
ic c 3 OperatingCurrent: RAS, CAS, -50 — 120 mA
RandomRead/Write(2,3)
Address Cycling, tr c = tr c (min.)
-60 — 110
AveragePowerSupplyCurrent
ic c 4 OperatingCurrent: RAS= Vi l , CAS ≥ Vi h -50 — 90 mA
FastPageMode(2,3,4) tr c = tr c (min.) -60 — 80
AveragePowerSupplyCurrent
ic c 4 RefreshCurrent: RAS Cycling, CAS ≥ Vi h -50 — 120 mA
RAS-Only(2,3) tr c = tr c (min.) -60 — 110
AveragePowerSupplyCurrent
ic c 5 RefreshCurrent: RAS, CASCycling -50 — 120 mA
CBR(2,3,5) tr c = tr c (min.) -60 — 110
AveragePowerSupplyCurrent
Notes:
1. Aninitialpauseof200µsisrequiredafterpower-upfollowedbyeightRAS refresh cycles (RAS-OnlyorCBR)beforeproperdevice
operationisassured.TheeightRAS cycles wake-up should be repeated any time the tr e f refreshrequirementisexceeded.
2. Dependentoncyclerates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-addressischangedonceeachFastPagecycle.
5. Enables on-chip refresh and address counters.
6 Integrated Silicon Solution, Inc.
Rev. C
12/21/09
IS41LV44052B
AC CHARACTERISTICS(1,2,3,4,5,6)
(RecommendedOperatingConditionsunlessotherwisenoted.)
-50 -60
Symbol Parameter Min. Max. Min. Max. Units
tr c RandomREADorWRITECycleTime 84 — 104 — ns
tr a c AccessTimefromRAS(6,7) — 50 — 60 ns
tc a c AccessTimefromCAS(6,8,15) — 13 — 15 ns
ta a AccessTimefromColumn-Address(6) — 25 — 30 ns
tr a s RASPulseWidth 50 10K 60 10K ns
tr p RASPrechargeTime 30 — 40 — ns
tc a s CASPulseWidth(23) 8 10K 10 10K ns
tc p CASPrechargeTime(9) 9 — 9 — ns
tc s h CASHoldTime(21) 38 — 40 — ns
tr c d RAS to CASDelayTime(10,20) 12 37 14 45 ns
ta s r Row-AddressSetupTime 0 — 0 — ns
tr a h Row-AddressHoldTime 8 — 10 — ns
ta s c Column-AddressSetupTime(20) 0 — 0 — ns
tc a h Column-AddressHoldTime(20) 8 — 10 — ns
ta r Column-AddressHoldTime 30 — 40 — ns
(referenced to RAS)
tr a d RAStoColumn-AddressDelayTime(11) 10 25 12 30 ns
tr a l Column-Address to RASLeadTime 25 — 30 — ns
tr p c RAS to CASPrechargeTime 5 — 5 — ns
tr s h RASHoldTime 8 — 10 — ns
tr h c p RASHoldTimefromCASPrecharge 30 — 35 — ns
tc l z CAStoOutputinLow-Z(15,24) 0 — 0 — ns
tc r p CAS to RASPrechargeTime(21) 5 — 5 — ns
to d OutputDisableTime(19,24) 3 15 3 15 ns
to e OutputEnableTime(15,16) — 12 — 15 ns
to e d OutputEnableDataDelay(Write) 12 — 15 — ns
to e h c OEHIGHHoldTimefromCASHIGH 5 — 5 — ns
to e p OEHIGHPulseWidth 10 — 10 — ns
to e s OELOWtoCASHIGHSetupTime 5 — 5 — ns
tr c s ReadCommandSetupTime(17,20) 0 — 0 — ns
tr r h ReadCommandHoldTime 0 — 0 — ns
(referenced to RAS)(12)
tr c h ReadCommandHoldTime 0 — 0 — ns
(referenced to CAS)(12,17,21)
tw c h WriteCommandHoldTime(17) 8 — 10 — ns
tw c r WriteCommandHoldTime 40 — 50 — ns
(referenced to RAS)(17)
tw p WriteCommandPulseWidth(17) 8 — 10 — ns
tw p z WEPulseWidthstoDisableOutputs 7 — 7 — ns
Integrated Silicon Solution, Inc.7
Rev. C
12/21/09
IS41LV44052B
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(RecommendedOperatingConditionsunlessotherwisenoted.)
-50 -60
Symbol Parameter Min. Max. Min. Max. Units
tr w l WriteCommandtoRASLeadTime(17) 13 — 15 — ns
tc w l WriteCommandtoCASLeadTime(17,21) 8 — 10 — ns
tw c s WriteCommandSetupTime(14,17,20) 0 — 0 — ns
td h r Data-inHoldTime(referencedtoRAS) 39 — 39 — ns
ta c h Column-AddressSetupTimetoCAS 15 — 15 — ns
PrechargeduringWRITECycle
to e h OEHoldTimefromWEduring 8 — 10 — ns
READ-MODIFY-WRITEcycle(18)
td s Data-InSetupTime(15,22) 0 — 0 — ns
td h Data-InHoldTime(15,22) 8 — 10 — ns
tr w c READ-MODIFY-WRITECycleTime 108 — 133 — ns
tr w d RAS to WEDelayTimeduring 64 — 77 — ns
READ-MODIFY-WRITECycle(14)
tc w d CAS to WEDelayTime(14,20) 26 — 32 — ns
ta w d Column-Address to WEDelayTime(14) 39 — 47 — ns
tp c FastPageModeREADorWRITE 20 — 25 — ns
CycleTime
tr a s p RASPulseWidth 50 100K 60 100K ns
tc p a AccessTimefromCASPrecharge(15) — 30 — 35 ns
tp r w c READ-WRITECycleTime(24) 56 — 68 — ns
tc o h DataOutputHoldafterCASLOW 5 — 5 — ns
to f f OutputBufferTurn-OffDelayfrom 0 12 0 15 ns
CAS or RAS(13,15,19,24)
tw h z OutputDisableDelayfromWE 3 10 3 10 ns
tc s r CASSetupTime(CBRREFRESH)(20,25) 5 — 5 — ns
tc h r CASHoldTime(CBRREFRESH)(21,25) 8 — 10 — ns
to r d OESetupTimepriortoRASduring 0 — 0 — ns
HIDDENREFRESHCycle
tr e f AutoRefreshPeriod 2,048Cycles — 32 — 32 ms
tt TransitionTime(RiseorFall)(2,3) 1 50 1 50 ns
AC TEST CONDITIONS
Outputload: OneTTLLoadand50pF(Vcc=3.3V±10%)
Inputtimingreferencelevels: Vi h = 2.0V, Vi l =0.8V(Vcc=3.3V±10%)
Outputtimingreferencelevels:Vo h = 2.0V, Vo l =0.8V(Vcc=3.3V±10%)
8 Integrated Silicon Solution, Inc.
Rev. C
12/21/09
IS41LV44052B
Notes:
1.Aninitialpauseof200µsisrequiredafterpower-upfollowedbyeightRAS refresh cycle (RAS-OnlyorCBR)beforeproperdevice
operationisassured.TheeightRAS cycles wake-up should be repeated any time the tr e f refreshrequirementisexceeded.
2. Vi h (MIN)andVi l (MAX)arereferencelevelsformeasuringtimingofinputsignals.Transitiontimes,aremeasuredbetweenVi h
and Vi l (or between Vi l and Vi h )andassumetobe1nsforallinputs.
3. In addition to meeting the transition rate specification, all input signals must transit between Vi h and Vi l (or between Vi l and Vi h )
in a monotonic manner.
4. If CAS and RAS = Vi h ,dataoutputisHigh-Z.
5. If CAS = Vi l ,dataoutputmaycontaindatafromthelastvalidREADcycle.
6.MeasuredwithaloadequivalenttooneTTLgateand50pF.
7.Assumesthattr c d tr c d (MAX).Iftr c d isgreaterthanthemaximumrecommendedvalueshowninthistable,tr a c will increase by
the amount that tr c d exceedsthevalueshown.
8. Assumes that tr c d ž tr c d (MAX).
9. If CASisLOWatthefallingedgeofRAS,dataoutwillbemaintainedfromthepreviouscycle.Toinitiateanewcycleandclearthe
data output buffer, CAS and RAS must be pulsed for tc p .
10. Operation with the tr c d (MAX)limitensuresthattr a c (MAX)canbemet.tr c d (MAX)isspeciedasareferencepointonly;iftr c d
is greater than the specified tr c d (MAX)limit,accesstimeiscontrolledexclusivelybytc a c .
11. Operation within the tr a d (MAX)limitensuresthattr c d (MAX)canbemet.tr a d (MAX)isspeciedasareferencepointonly;iftr a d
is greater than the specified tr a d (MAX)limit,accesstimeiscontrolledexclusivelybyta a .
12. Either tr c h or tr r h mustbesatisedforaREADcycle.
13. to f f (MAX)denesthetimeatwhichtheoutputachievestheopencircuitcondition;itisnotareferencetoVo h or Vo l .
14. tw c s , tr w d , ta w d and tc w d arerestrictiveoperatingparametersinLATEWRITEandREAD-MODIFY-WRITEcycleonly.Iftw c s ž
tw c s (MIN),thecycleisanEARLYWRITEcycleandthedataoutputwillremainopencircuitthroughouttheentirecycle.Iftr w d ž
tr w d (MIN),ta w d ž ta w d (MIN)andtc w d ž tc w d (MIN),thecycleisaREAD-WRITEcycleandthedataoutputwillcontaindataread
from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go
back to Vi h )isindeterminate.OEheldHIGHandWEtakenLOWafterCASgoesLOWresultinaLATEWRITE(OE-controlled)
cycle.
15.Outputparameter(I/O)isreferencedtocorrespondingCAS input.
16.DuringaREADcycle,ifOEisLOWthentakenHIGHbeforeCASgoesHIGH,I/Ogoesopen.IfOEistiedpermanentlyLOW,a
LATEWRITEorREAD-MODIFY-WRITEisnotpossible.
17.WritecommandisdenedasWE going low.
18.LATEWRITEandREAD-MODIFY-WRITEcyclesmusthavebothto d and to e h met (OEHIGHduringWRITEcycle)inorderto
ensurethattheoutputbufferswillbeopenduringtheWRITEcycle.TheI/OswillprovidethepreviouslywrittendataifCAS remains
LOWandOEistakenbacktoLOWafterto e h is met.
19.TheI/OsareinopenduringREADcyclesonceto d or to f f occur.
20.DeterminedbyfallingedgeofCAS.
21.DeterminedbyrisingedgeofCAS.
22.TheseparametersarereferencedtoCASleadingedgeinEARLYWRITEcyclesandWEleadingedgeinLATEWRITEorREAD-
MODIFY-WRITEcycles.
23. CAS must meet minimum pulse width.
24.The3nsminimumisaparameterguaranteedbydesign.
25. Enables on-chip refresh and address counters.
Integrated Silicon Solution, Inc. 9
Rev. C
12/21/09
IS41LV44052B
FAST-PAGE-MODE READ CYCLE
tRAS
tRC
tRP
tAR
tCAH
tASC
tRAD tRAL
OE
I/O
WE
ADDRESS
CAS
RAS
Row Column Row
Open Open
Valid Data
tCSH
tCAS
tRSH
tCRP tCLCH
tRCD
tRAHtASR
tRRH
tRCHtRCS
tAA
tCAC tOFF(1)
tRAC
tCLC
tOES
tOE tOD
Don’tCare
10 Integrated Silicon Solution, Inc.
Rev. C
12/21/09
IS41LV44052B
FAST PAGE MODE READ-MODIFY-WRITE CYCLE
OUT
t
AR
t
RWD
t
AWD
I/O
WE
OE
ADDRESS
CAS
RAS
Row Column Column Column
t
AR
t
CSH
t
CAS
t
CAS
t
CAS
t
RASP
t
RSH
t
PRWC
t
RCD
t
CWD
t
CWD
t
CWD
t
CRP
t
ASR
t
RAD
t
RCS
t
ASC
t
ASC
t
ASC
t
RAL
t
CAH
t
CP
t
CP
t
RP
t
CAH
t
AWD
t
AWD
t
CAC
t
AA
t
DH
t
CLZ
t
RAC
t
DH
t
DH
t
OEA
t
CLZ
t
CAC
t
OEA
t
CAC
t
OEA
OUT
OUT ININ IN
t
OEZ
t
OEZ
t
OED
t
OED
t
DS
t
OEZ
t
OED
t
DS
t
CLZ
t
AA
t
AA
t
WP
t
RAH
t
WP
t
WP
t
CWL
t
CWL
t
CWL
t
RWL
t
CPWD
t
CPWD
t
CAH
t
CRP
t
DS
Don’tCare
Integrated Silicon Solution, Inc. 11
Rev. C
12/21/09
IS41LV44052B
FAST-PAGE-MODE EARLY WRITE CYCLE (OE=DON'TCARE)
tRAS
tRC
tRP
tAR
tCAH
tASC
tRAD tRAL
tACH
I/O
WE
ADDRESS
CAS
RAS
Row Column Row
tCSH
tCAS
tRSH
tCRP tCLCH
tRCD
tRAHtASR
tCWL
tWCR
tWCH
tRWL
tWP
tWCS
tDH
tDS
tDHR
Valid Data
Don’tCare
12 Integrated Silicon Solution, Inc.
Rev. C
12/21/09
IS41LV44052B
FAST-PAGE-MODE READ WRITE CYCLE (LATEWRITEandREAD-MODIFY-WRITECycles)
t
RAS
t
RWC
t
RP
t
AR
t
CAH
t
ASC
t
RAD
t
RAL
t
ACH
WE
OE
ADDRESS
CAS
RAS
Row Column Row
t
CSH
t
CAS
t
RSH
t
CRP
t
CLCH
t
RCD
t
RAH
t
ASR
t
RWD
t
CWL
t
CWD
t
RWL
t
AWD
t
WP
t
RCS
t
CAC
t
CLZ
t
DS
t
DH
t
OEH
t
OD
t
OE
t
RAC
t
AA
I/O Open Open
Valid D
OUT
Valid D
IN
Don’tCare
Integrated Silicon Solution, Inc. 13
Rev. C
12/21/09
IS41LV44052B
FAST PAGE MODE EARLY WRITE CYCLE
t
AR
I/O
WE
OE
ADDRESS
CAS
RAS
Row Column Column Column
t
AR
t
CWL
t
WCR
t
DHR
t
CSH
t
CAS
t
CAS
t
CAS
t
RASP
t
RSH
t
RHCP
t
PC
t
RCD
t
CRP
t
ASR
t
WCS
t
DS
t
RAD
t
ASC
t
ASC
t
ASC
t
RAL
t
CAH
t
WCH
t
DH
t
DS
t
DS
t
DH
t
DH
t
CP
t
CP
t
RP
t
CAH
t
RAH
t
CAH
t
CRP
t
CWL
t
WCS
t
WCS
t
WCH
t
WP
t
WP
t
CWL
t
WCH
t
WP
Valid DIN Valid DIN
Valid DIN
Don’tCare
14 Integrated Silicon Solution, Inc.
Rev. C
12/21/09
IS41LV44052B
AC WAVEFORMS
READ CYCLE (WithWE-ControlledDisable)
RAS-ONLY REFRESH CYCLE (OE, WE=DON'TCARE)
tAR
tCAH tASC
tASC
tRAD
OE
I/O
WE
ADDRESS
CAS
RAS
Row Column
Open Open
Valid Data
tCSH
tCAS
tCRP tRCD tCP
tRAHtASR
tRCH tRCStRCS
tAA
tCAC
tWHZ
tRAC
tCLZ
tCLZ
tOE tOD
Column
t
RAS
t
RC
t
RP
I/O
ADDRESS
CAS
RAS
Row Row
Open
t
CRP
t
RAH
t
ASR
t
RPC
Don’tCare
Don’tCare
Integrated Silicon Solution, Inc. 15
Rev. C
12/21/09
IS41LV44052B
HIDDEN REFRESH CYCLE(1) (WE=HIGH;OE=LOW)
CBR REFRESH CYCLE (Addresses;WE, OE=DON'TCARE)
t
RAS
t
RAS
t
RP
t
RP
I/O
CAS
RAS
Open
t
CP
t
RPC
t
CSR
t
CHR
t
RPC
t
CSR
t
CHR
t
RAS
t
RAS
t
RP
CAS
RAS
t
CRP
t
RCD
t
RSH
t
CHR
t
AR
t
ASC
t
RAD
ADDRESS Row Column
t
RAH
t
ASR
t
RAL
t
CAH
I/O Open Open
Valid Data
t
AA
t
CAC
t
RAC
t
CLZ
t
OFF
(2)
OE
t
OE
t
ORD
t
OD
Don’tCare
Don’tCare
16 Integrated Silicon Solution, Inc.
Rev. C
12/21/09
IS41LV44052B
ORDERING INFORMATION
Commercial Range: 0°C to 70°C
Voltage: 3.3V
Speed (ns) Order Part No. Refresh Package
50 IS41LV44052B-50TL 2K 300-milTSOP-II,Alloy42leadframeplatedwithmatteSn
60 IS41LV44052B-60TL 2K 300-milTSOP-II,Alloy42leadframeplatedwithmatteSn
Industrial Range: -40°C to +85°C
Voltage: 3.3V
Speed (ns) Order Part No. Refresh Package
50 IS41LV44052B-50TLI 2K 300-milTSOP-II,Alloy42leadframeplatedwithmatteSn
IS41LV44052B-50CTGI 2K 300-milTSOP-II,CuleadframeplatedwithmatteSnBi
60 IS41LV44052B-60TLI 2K 300-milTSOP-II,Alloy42leadframeplatedwithmatteSn
Notes:
1. Part numbers with TL, TLI, CTG, or CTGI are lead-free, and RoHS compliant.
2. For the "G" option, Bi is 3% or less of SnBi plating.
Integrated Silicon Solution, Inc. 17
Rev. C
12/21/09
IS41LV44052B
Θ
Θ
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION.
4. REFERENCE DOCUMENT : JEDEC SPEC. MS-025 , A
1. CONTROLLING DIMENSION : MM
2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION.
NOTE :
07/07/2008
Package Outline