8 Integrated Silicon Solution, Inc.
Rev. C
12/21/09
IS41LV44052B
Notes:
1.Aninitialpauseof200µsisrequiredafterpower-upfollowedbyeightRAS refresh cycle (RAS-OnlyorCBR)beforeproperdevice
operationisassured.TheeightRAS cycles wake-up should be repeated any time the tr e f refreshrequirementisexceeded.
2. Vi h (MIN)andVi l (MAX)arereferencelevelsformeasuringtimingofinputsignals.Transitiontimes,aremeasuredbetweenVi h
and Vi l (or between Vi l and Vi h )andassumetobe1nsforallinputs.
3. In addition to meeting the transition rate specification, all input signals must transit between Vi h and Vi l (or between Vi l and Vi h )
in a monotonic manner.
4. If CAS and RAS = Vi h ,dataoutputisHigh-Z.
5. If CAS = Vi l ,dataoutputmaycontaindatafromthelastvalidREADcycle.
6.MeasuredwithaloadequivalenttooneTTLgateand50pF.
7.Assumesthattr c d tr c d (MAX).Iftr c d isgreaterthanthemaximumrecommendedvalueshowninthistable,tr a c will increase by
the amount that tr c d exceedsthevalueshown.
8. Assumes that tr c d ž tr c d (MAX).
9. If CASisLOWatthefallingedgeofRAS,dataoutwillbemaintainedfromthepreviouscycle.Toinitiateanewcycleandclearthe
data output buffer, CAS and RAS must be pulsed for tc p .
10. Operation with the tr c d (MAX)limitensuresthattr a c (MAX)canbemet.tr c d (MAX)isspeciedasareferencepointonly;iftr c d
is greater than the specified tr c d (MAX)limit,accesstimeiscontrolledexclusivelybytc a c .
11. Operation within the tr a d (MAX)limitensuresthattr c d (MAX)canbemet.tr a d (MAX)isspeciedasareferencepointonly;iftr a d
is greater than the specified tr a d (MAX)limit,accesstimeiscontrolledexclusivelybyta a .
12. Either tr c h or tr r h mustbesatisedforaREADcycle.
13. to f f (MAX)denesthetimeatwhichtheoutputachievestheopencircuitcondition;itisnotareferencetoVo h or Vo l .
14. tw c s , tr w d , ta w d and tc w d arerestrictiveoperatingparametersinLATEWRITEandREAD-MODIFY-WRITEcycleonly.Iftw c s ž
tw c s (MIN),thecycleisanEARLYWRITEcycleandthedataoutputwillremainopencircuitthroughouttheentirecycle.Iftr w d ž
tr w d (MIN),ta w d ž ta w d (MIN)andtc w d ž tc w d (MIN),thecycleisaREAD-WRITEcycleandthedataoutputwillcontaindataread
from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go
back to Vi h )isindeterminate.OEheldHIGHandWEtakenLOWafterCASgoesLOWresultinaLATEWRITE(OE-controlled)
cycle.
15.Outputparameter(I/O)isreferencedtocorrespondingCAS input.
16.DuringaREADcycle,ifOEisLOWthentakenHIGHbeforeCASgoesHIGH,I/Ogoesopen.IfOEistiedpermanentlyLOW,a
LATEWRITEorREAD-MODIFY-WRITEisnotpossible.
17.WritecommandisdenedasWE going low.
18.LATEWRITEandREAD-MODIFY-WRITEcyclesmusthavebothto d and to e h met (OEHIGHduringWRITEcycle)inorderto
ensurethattheoutputbufferswillbeopenduringtheWRITEcycle.TheI/OswillprovidethepreviouslywrittendataifCAS remains
LOWandOEistakenbacktoLOWafterto e h is met.
19.TheI/OsareinopenduringREADcyclesonceto d or to f f occur.
20.DeterminedbyfallingedgeofCAS.
21.DeterminedbyrisingedgeofCAS.
22.TheseparametersarereferencedtoCASleadingedgeinEARLYWRITEcyclesandWEleadingedgeinLATEWRITEorREAD-
MODIFY-WRITEcycles.
23. CAS must meet minimum pulse width.
24.The3nsminimumisaparameterguaranteedbydesign.
25. Enables on-chip refresh and address counters.