ZL50075GAC - Zarlink Semiconductor, Inc.

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

Features

• 32,768 channel x 32,768 channel non -blockin g

digital Time Division Multiplex (TDM) switch at

65.536 Mbps or 32.768 Mbps or using a

combination of rates

• 16,384 channel x 16,384 channel non-blockin g

digital TDM switch at 16.384 Mbps

• 8,192 channel x 8,192 channel non-blocking

digital TDM switch at 8.192 Mbps

• High jitter tolerance with multiple input clock

sources and frequencies

• Up to 64 serial TDM input streams, divided in to

32 groups with 2 input streams per gro up

• Up to 64 serial TDM output streams, divided into

32 groups with 2 output streams per group

• Per-group input and output data rate conversion

selection at 65.536 Mbps, 32.768 Mbps,

16.384 Mbps and 8.192 Mbps. Input and output

data group rates can differ

• Per-group input bit delay for flexible sampling

point selection

• Per-group output fractional bit advancement

• Two sets of output timing signals for interfacing

additional device s

• Per-channel A-Law/µ-Law Translation

• Per-channel constant or variable throughput delay

for frame integrity and low latency applications

• Per-stream Bit Error Rate (BER) test circuits

• Per-channel high impedance output control

• Per-channel force high output control

• Per-channel message mode

• Control interface compatible with Intel an d

Motorola 16 bit non-multiplexed buses

• Connection memory block pro gramming

• Supports ST-BUS and GCI-Bus standards for

input and output timing

• IEEE 1149.1 (JTAG) test port

• 3.3 V I/O with 5V tolerant inputs; 1.8 V core

voltage

July 2004

Ordering Information

ZL50075GAC 324 Ball PBGA

-40°C to +85°C

ZL50075

32 K Channel Digital Switch with High Jitter

Tolerance, Rate Conversion per Group of

2 Streams (8, 16, 32 or 64 Mbps),

and 64 Inputs and 64 Outputs

Data Sheet

Figure 1 - ZL50075 Functional Block Diagram

Test Access

VSSVDD_IO

TDi

TDo

TCK

TRST

TMS

SToA0

PWR

Connection M emory

STiA0

ODE

Data Memory

S/P

Microproces sor Interfa ce

SToB0

STiB0

VDD_CORE

Converter

Timing

P/S

Converter

D15-0

BERR

WAIT

DTA

R/W

A18-0

FPi0

CKi0

CK_SEL1-0

FPo1-0

CKo1-0 Port

SIZ1-0

and Control Registers

Output

Input

Timing Timing

STiA31

STiB31

Input

Group 0

Input

Group 31

Output

Group 0 Output

Group 31

SToA31

SToB31

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

Applications

• Large Switching Platforms

• Central Office Switches

• Wireless Base Stations

• Multi-service Access Platforms

• Media Gateways

Description

The ZL50075 is a non-blocking Time Division Multiplex (TDM) switch with maximum 32,768 x 32,768 chan nels. The

device can switch 64 kbps and Nx64 kbps TDM channels from any input stream to any output stream. With a

number of enhanced features, the ZL50075 is designed for high capacity voice and data switching applications.

The ZL50075 has 64 input and 64 output data streams which can operate at 8.192 Mbps, 16.384 Mbps,

32.768 Mbps or 65.536 Mbps. The large number of inputs and outputs maintains full 32 K x 32 K channel switching

capacity at bit rates of 65 Mbps and 32 Mbps. Up to 32 input and output data streams may operate at 65 Mbps. Up

to 64 input and output data streams may operate at 32 Mbps, 16 Mbps or 8 Mbps. The data rate can be

independently set in groups of 2 input or output streams. In this way it is possible to provide rate conversion from

input data channel to output data channel.

The ZL50075 uses a master clock (CKi0) and frame pulse (FPi0) to define the TDM data stream frame boundary

and timing. A high speed system clock is derived internally from CKi0 and FPi0. The input and output data streams

can independently reference their timings to the input clock or to the internal system clock.

The ZL50075 has a variety of user configurable options designed to provide flexibility when data streams are

connected to multiple TDM components or circuits. These include:

• Variable input bit delay an d output advancement, to accommod ate delays and frame offsets of streams

connected through different data paths

• Two timing outputs, CKo1 - 0 and FPo1 - 0, which can be co nfigured indepe ndently to provide a va riety of

clock and frame pulse options

• Support of both ST-BUS and GCI-B us formats

The ZL50075 also has a number of value added features for voice and data applications:

• Per-channel variable delay mode for low latency applications and cons tant delay mode for fram e integrity

applications

• Per-channel A-Law/µ-Law Conversio ns for both voice and data

• 64 separate Pseudo-random Bit Sequenc e (PRBS) tes t circuit s; one p er stream. This prov ides an integ rated Bit

Error Rate (BER) test capability to facilitate data path integrity checking

The ZL50075 has two major modes of operation: Connection Mode (normal) and Message Mode. In Connection

Mode, data bytes received at the TDM inputs are switched to timeslots in the output data streams, with mapping

controlled by the Connection Memories. Using Zarlink's Message Mode capability, microprocessor data can be

broadcast to the output data streams on a per-channel basis. This feature is useful for transferring control and

status information to external circuits or other TDM devices.

A non-multiplexed microprocessor port provides access to the internal Data Memory, Connection Memory and

Control Registers used to program ZL5007 5 options. The port is configurable to interface with either 16 bit Motorola

or Intel-type microprocessors.

The mandatory requirements of IEEE 1149.1 standard are supported via the dedicated Test Access Port.

ZL50075 Data Sheet

Table of Contents

Zarlink Semiconductor Inc.

1.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

1.2 Switch Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.3 Stream Provisioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.4 Input and Output Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

1.4.1 Per Group Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

1.5 Rate Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

2.0 Input Clock (CKi) and Input Frame Pulse (FPi) Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.0 Output Clock (CKo) and Output Frame Pulse (FPo) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.0 Output Channel Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

5.0 Data Input Delay and Data Output Advancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

5.1 Input Sampling Point Delay Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

5.2 Fractional Bit Advancement on Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6.0 Message Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6.1 Data Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

6.2 Connection Memory Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

7.0 Data Delay Through the Switching Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7.1 Constant Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

7.2 Variable Delay Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

8.0 Per-Channel A-Law/m-Law Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

9.0 Bit Error Rate Tester . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

10.0 Microprocessor Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

10.1 Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

10.1.1 Read Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

10.1.2 Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

11.0 Power-up and Initialization of the ZL50075 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

11.1 Device Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

11.2 Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

11.3 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

12.0 IEEE 1149.1 Test Access Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

12.1 Test Access Port (TAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

12.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

12.3 Test Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

12.4 Boundary Scan Description Language (BSDL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

13.0 Memory Map of ZL50075 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

14.0 Detailed Memory and Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

14.1 Connection Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

14.1.1 Connection Memory Bit Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

14.1.2 Connection Memory LSB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

14.2 Data Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

14.3 BER Control Memory and Error Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

14.3.1 Input BER Enable Control Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

14.3.2 BER Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

14.4 Group Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

14.5 Input Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

14.6 Output Clock Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

14.7 Block Init Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

14.8 Block Init Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

15.0 DC/AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

ZL50075 Data Sheet

List of Figures

Zarlink Semiconductor Inc.

Figure 1 - ZL50075 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2 - 32 K x 32 K Channel Basic Switch Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3 - Input and Output Data Rate Conversion Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 4 - Input Sampling Point Delay Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 5 - Output Bit Advancement Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 6 - Data Throughput Delay for Constant Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 7 - Data Throughput Delay for Variable Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 8 - Example PRBS Timeslot Insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 9 - Read Cycle Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 10 - Write Cycle Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 11 - Frame Pulse Input and Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 12 - Serial Data Timing to CKi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 13 - Serial Data Timing to CKo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 14 - Microprocessor Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 15 - Intel Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 16 - IEEE 1149.1 Test Port & PWR Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

ZL50075 Data Sheet

List of Tables

Zarlink Semiconductor Inc.

Table 1 - Data Rate and Maximum Switch Size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 2 - TDM Stream Bit Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 3 - CKi0 and FPi0 Setting via CK_SEL1 - 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 4 - Input and Output Voice and Data Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 5 - Example of Address and Byte Significance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 6 - Byte Enable Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 7 - Memory Data Word Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 8 - Data Bus Word Alignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 9 - Byte Address Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 10 - Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 11 - Connection Memory Group Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 12 - Connection Memory Stream Address Offset at Various Output Rates . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 13 - Connection Memory Timeslot Address Offset Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 14 - Connection Memory Bits (CMB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 15 - Connection Memory LSB Group Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 16 - Connection Memory LSB Stream Address Offset at Various Output Rates . . . . . . . . . . . . . . . . . . . . . 29

Table 17 - Data Memory Group Address Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 18 - Data Memory Stream Address Offset at Various Output Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 19 - BER Enable Control Memory Group Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 20 - BER Enable Control Memory Stream Address Offset at Various Output Rates . . . . . . . . . . . . . . . . . . 32

Table 21 - BER Counter Group and Stream Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 22 - Group Control Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 23 - Group Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 24 - Input Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 25 - Output Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 26 - Block and Power-up Initialization Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

Pin Diagram - ZL50075 19 mm x 19 mm 324 Ball PBGA (as viewed through top of package)

A1 corner identified by metallized marking.

123456789101112131415161718

AD[15] D[14] D[5] D[4] D[3] A[18] A[17] A[13] A[12] A[11] A[8] A[4] A[2] A[0] R/W DS IC DTA

BSTOA

[1] IM D[11] D[10] D[8] D[7] D[6] D[1] A[15] A[10] A[5] A[1] NC CS SIZ[0] PWR STOA

[31] SIZ[1]

CSTIA

[2] STIB

[1] STIA

[0] STIB

[0] STOA

[0] D[13] D[9] D[0] A[14] A[9] A[6] BERR WAIT STIB

[31] TDO STIA

[31] TRST NC

DSTOB

[2] CKO

[0] STIA

[1] STOB

[0] VDD_

CORE D[12] D[2] VDD_

CORE A[16] VDD_

IO A[7] A[3] VDD_

IO TCK VDD_

CORE TMS STOB

[30] STOB

[31]

ESTIA

[3] STIB

[2] STOB

[1] FPO

[0] VSS VSS VDD_

CORE VDD_

IO VSS VDD_

CORE VDD_

IO VSS VDD_

CORE VDD_

IO TDI STOA

[30] STIB

[30] STIA

[30]

FSTOB

[3] STIB

[3] STOA

[2] VDD_

CORE VDD_

IO VSS VSS VDD_

CORE VDD_

IO VSS VDD_

CORE VDD_

IO VSS VDD_

CORE STOB

[29] STIB

[29] STOA

[29] STIA

[29]

GSTOA

[3] STIB

[4] STIA

[4] VDD_

IO VDD_

CORE VDD_

IO VSS VSS VSS VSS VSS VSS VDD_

IO VSS VDD_

IO STIB

[28] STOB

[28] STOA

[28]

HVSS VSS STOA

[4] STOB

[4] VSS VDD_

CORE VSS VSS VSS VSS VSS VSS VDD_

CORE VDD_

IO VSS STOA

[27] STOB

[27] STIA

[28]

JSTIA

[5] STOA

[5] STIB

[5] STOB

[5] VDD_

IO VSS VSS VSS VSS VSS VSS VSS VSS VDD_

CORE STOA

[26] STOB

[26] VSS STIB

[27]

KODE STIA

[6] STIA

[7] STOA

[6] VDD_

CORE VDD_

IO VSS VSS VSS VSS VSS VSS VDD_

IO VSS STIB

[25] IC STOA

[25] STIA

[27]

LSTIB

[6] STOB

[6] IC STIA

[8] VSS VDD_

CORE VSS VSS VSS VSS VSS VSS VDD_

CORE VDD_

IO STIA

[24] STOA

[24] STOB

[24] IC

MSTIB

[7] STOA

[7] STOB

[8] VDD_

CORE VDD_

IO VDD_

IO VSS VSS VSS VSS VSS VSS VDD_

IO VDD_

CORE VDD_

CORE STIA

[23] STOB

[23] STIB

[26]

NSTOB

[7] STIB

[8] STIB

[9] VDD_

IO VDD_

CORE VSS VSS VDD_

CORE VDD_

IO VSS VDD_

CORE VDD_

IO VSS VSS VDD_

IO STOA

[22] STOB

[22] STIA

[26]

PIC STIA

[9] STIA

[10] STOB

[10] VSS VSS VDD_

CORE VDD_

IO VSS VDD_

CORE VSS VSS VDD_

CORE VDD_

IO STOA

[21] STOB

[21] NC STOB

[25]

RSTOA

[8] STOB

[9] STOA

[10] STIA

[12] VDD_

IO STOA

[13] STIA

[15] VDD_

CORE STOA

[15] VDD_

IO STIB

[17] IC VDD_

IO STIB

[19] VDD_

CORE STIA

[21] STIA

[22] STIA

[25]

TSTOA

[9] STIB

[10] STIA

[11] STOA

[12] STIA

[13] STOB

[13] STIB

[15] STOB

[16] FPI

[0] STIA

[17] IC STIA

[18] STIA

[19] STIA

[20] STOA

[20] NC STIB

[24]

USTIB

[11] STOB

[11] STIB

[12] CKO

[1] STIA

[14] STIB

[14] STOB

[15] STIA

[16] STOA

[16] IC NC STOB

[17] CK_

SEL[0 STOB

[18] STOB

[19] STOB

[20] STIB

[21] STOA

[23]

VSTOB

[12] FPO

[1] STIB

[13] STOA

[14] STOB

[14] STIB

[16] CKI

[0] NC IC IC STOA

[17] CK_

SEL[1] STIB

[18] STOA

[19] STIB

[20] STIB

[22] STIB

[23]

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

Pin Description

Pin Name Description

TDM Interface

C3, D3, C1, E1,

G3, J1, K2, K3,

L4, P2, P3, T3,

R4, T6, U5, R7,

U8, T1 1 , T13, T14, T15, R16,

R17, M16, L15, R18, N18,

K18, H18, F18, E18, C16,

STiA0-31 Serial TDM Input Data ’A’ Streams (5 V Tolerant Input with

Internal Pull-down)

The data rate of these input streams can be sele cted in a group of 2

to be either 8.192 Mbps, 16.384 Mbps, 32.678 Mbps or

65.536 Mbps. Refer to Section 1.4 for rate programming options.

The data streams can be selecte d to be either inverted or

non-inverted, programmed by the Group Control Registers (Section

14.4).

Unused inputs are pulled low by interna l pull-down resistors and

may be left unconn ected.

C4, C2, E2, F2,

G2, J3, L1, M1,

N2, N3, T2, U1,

U3, V3, U6, T8,

V6, R11, V13, R14, V16,

U17, V17, V18, T18, K15,

M18, J18, G16, F16, E17,

C14

STiB0-31 Serial TDM Input Data ’B’ Streams (5 V Tolerant Input with

Internal Pull-down)

The data rate of these input streams can be sele cted in a group of 2

to be either 8.192 Mbps, 16.384 Mbps, or 32.678 Mbps. The stream

is unused when its input grou p rate is 65.536 Mbps. Refer to

Section 1.4 for rate programming options.

The data streams can be selecte d to be either inverted or

non-inverted, programmed by the Group Control Registers (Section

14.4).

Unused inputs are pulled low by interna l pull-down resistors and

may be left unconn ected.

C5, B1, F3, G1,

H3, J2, K4, M2,

R1, T1, R3, T4,

T5, R6, V4, R9,

U9, V11, V14, V15, T16,

P15, N16, U18, L16, K17,

J15, H16, G18, F17, E16,

B17

SToA0-31 Serial TDM Output Data ’A’ Streams (5 V Tolerant , 3.3 V

Tri-state Slew-Rate Controlled Outputs)

The data rate of these o utput streams ca n be selected in a group of

2 to be either 8.192 Mbps, 16.384 Mbps, 32.678 Mbps or

65.536 Mbps. Refer to Section 1.4 for rate programming options.

The data streams can be selecte d to be either inverted or

non-inverted, programmed by the Group Control Registers (Section

14.4).

D4, E3, D1, F1,

H4, J4, L2, N1,

M3, R2, P4, U2,

V1, T7, V5, U7,

T9, U12, U14, U15, U16,

P16, N17, M17, L17, P18,

J16, H17, G17, F15, D17,

D18

SToB0-31 Serial TDM Output Data ’B’ Str eams (5 V Tolerant, 3.3 V

Tri-state Slew-Rate Controlled Outputs)

The data rate of these o utput streams ca n be selected in a group of

2 to be either 8.192 Mbps, 16.384 Mbps or 32.678 Mbps. The

stream is unused when its output group rate is 65.536 Mbps. Refer

to Secti o n 1. 4 for rate prog r am m ing optio ns.

The data streams can be selecte d to be either inverted or

non-inverted, programmed by the Group Control Registers (Section

14.4).

Unused outputs are tristated and may be left unconnecte d.

V7 CKi0ST-BUS/GCI-Bus Clock Input (5 V Tolerant Schmitt-Triggered

Input)

This pin accepts an 8.192 MHz, 16.384 MHz, 32.678 MHz or

65.536 MHz clock. This clock must be provided for correct

operation of the ZL50075. The frequency of the CKi0 input is

selected by the CK_SEL1-0 inputs. The active clock edge may be

either rising or falling, programmed by the Input Clock Control

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

T10 FPi0ST-BUS/GCI-Bus Frame Pulse Input (5 V Tolerant Input)

This pin accepts the 8 kHz frame pulse which marks the frame

boundary of the TDM data streams. The pulse width is nominally

one CKi0 clock period (assuming ST-BUS mode) selected by the

CK_SEL1-0 inputs. The active state of the frame pulse may be

either high or low, programmed by the Input Clock Control Register

(Section 14.5).

D2, U4 CKo0-1 ST-BUS/GCI-Bus Clock Outputs (3.3 V Outputs with Slew-Rate

Control)

These clock outputs can be programmed to generate 8.192 MHz,

16.384 MHz, 32.678 MHz or 65.536 MHz TDM clock outputs. The

active edge can be programmed to be either rising or falling. The

source of the clock outputs can be derived from either the CKi0

inputs or the internal system clock. The frequency, active edge and

source of each clock output can be programmed independently by

the Output Clock Control Register (Section 14.6).

E4, V2 FPo0-1 ST-BUS/GCI-Bus Frame Pulse Outputs (3.3 V Outputs with

Slew-Rate Cont ro l)

These 8 kHz output pulses mark the frame bound ary of the TDM

data streams. The pulse width is nominally one clock period of the

corresponding CKo output. The active state of each frame pulse

may be either high or low, independently programmed by the

Output Clock Control Register (Section 14.6).

U13, V12 CK_SEL0-1 TDM Master Clock Input Select

Inputs us ed to select the frequency and frame alignment of CKi0

and FPi0:

CK_SEL1 = 0, CK_SEL0 = 0, 8.192 MHz

CK_SEL1 = 0, CK_SEL0 = 1, 16.384 MHz

CK_SEL1 = 1, CK_SEL0 = 0, 32.768 MHz

CK_SEL1 = 1, CK_SEL0 = 1, 65.536 MHz

K1 ODE Output Drive Enable (5 V Tolerant Input with Internal Pull-up)

This is the asynchronous output enable control for the output

streams. When it is high, the streams are enabled. When it is low,

the output streams are tristated.

Microprocessor Port and Reset

A1, A2, C6, D6,

B3, B4, C7, B5,

B6, B7, A3, A4,

A5, D7, B8, C8

D15-0 Microprocessor Port Data Bus (5 V Tolerant Bi-directional with

Slew-Rate Outp u t Co n t r ol)

16 bit bi-directional data bus. Used for microprocessor access to

internal memories and registers.

A6, A7, D9, B9, C9, A8, A9,

A10, B10, C10, A11, D11,

C11, B11, A12, D12, A13,

B12, A14

A18-0 Microprocessor Port Address Bus (5 V Tolerant Input s)

19 bit address bus for the internal memories and re gisters. Note A0

is not used and should be connected to a defined logic level.

B14 CS Chip Select Input (5 V Tolerant Input)

Active low input used with DS to enable read and write access to

the ZL50075.

Pin Description (continued)

Pin Name Description

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

A16 DS Data Strobe Input (5 V Tolerant Input)

Active low input used with CS to enable read and write access to

the ZL50075.

A15 R/W Read/Write Input (5 V Tolerant Input)

Input signal that controls the type of microprocessor access:

0 - Microprocessor write to the ZL50075

1 - Microprocessor read from the ZL50075

A18 DTA Data T rans fer Acknowledge (5 V T oleran t, 3.3 V T ri-st ate Output

with Slew-Rate)

Active low output which indicates that a data bus transfer is

complete. An external pull-up resistor is required to hold this pin

HIGH when output is high-impedance.

C12 BERR T ransfer Bus Error Output with Slew Rate Control (5 V T olera nt,

3.3 V Tri-state Outputs with Slew-Rate Control)

This pin goes low whenever the microprocess or attempts to access

an invalid memory space inside the device. In Motorola bus mode , if

this bus error signal is activated, the data transfer acknowledge

signal, DTA, will not be generated. In Intel bus mode, the generation

of the DTA is not affected by this BERR signal. An external pull-up

resistor is required to hold a HIGH level when output is

high-impedance.

C13 WAIT Data Transfer Wait Output (5 V Tolerant, 3.3 V Tri-st ate Output

with Slew Rate)

Active low wait signal output. An external pull-up resistor is required

to hold a HIGH level when output is high-impe dance.

B15, B18 SIZ0-1 Data Transfer Size/Upper and Lower Data Strobe Inputs (5 V

Tolerant Inputs)

Motorola mode: SIZ0 - LDS, SIZ1 - UDS.

Active low upper and lower data strobes, UDS and LDS, indicate

whether the upper byte, D15-8, and/or lower byte, D7-0, is being

transferred.

Intel mode: SIZ0 - BE0, SIZ1 - BE1.

Active low Intel type bus-enable signal BE1 and BE0 signals

B2 IM Microprocessor Port Bus Mode Select (5 V Tolerant Input)

Control input:

0 = Motorola mode

1 = Intel mode

B16 PWR Device Reset (5 V Tolerant Schmitt-Triggered Input)

Asynchronous reset input used to ini tialize the ZL50075.

0 = Reset

1 = Normal

See Section 11.0, Power-up and Initialization of the ZL50075 for

detailed descrip tion of Reset state.

IEEE 1149.1 (JTAG) Test Access Port (TAP)

E15 TDI Test Data (5 V Tolerant Input with Internal Pull-up)

Serial test data input. When not used, this input may be left

unconnected.

Pin Description (continued)

Pin Name Description

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

C15 TDO Test Data (3.3 V Output)

Serial test data output.

D14 TCK Test Clock (5 V Tolerant Schmitt-Triggered Input with Internal

Pull-up)

Clock input used by TAP Controller. When not used, this input may

be left unconnected.

D16 TMS Test Reset (5 V Tolerant Schmitt-Triggered Input with Internal

Pull-up)

Input which controls the state transitions of the TAP Controller.

When not used, this pin is pulled high by an internal pull-up resistor

and may be left unconnected.

C17 TRST Test Mode Select (5 V Tolerant Inp ut with Internal Pull-up)

Asynchronously initializes the JTAG TAP controller by putting it in

the Test-Logic-Reset state. This pin should be pulsed low during

power-up to ensure that the device is in th e normal functional mode.

When JTAG is not being used, this pin should be pulled low during

normal operation.

Unused

U10, V9, V10, R12, L18,

A17, L3, P1, T12, K16 IC Internal Connections

In normal mode these pins MUST be connected low.

B13, C18, P17, T17, U11, V8 NC No Connection

In normal mode these pins MUST be left unconnected.

Power

E5, E6, E9, E12, F6, F7, F10,

F13, G7, G8, G9, G10, G11,

G12, G14, H1, H2, H5, H7,

H8, H9, H10, H11, H12, H15,

J6, J7, J8, J9, J10, J11, J12,

J13, J17, K7, K8, K9, K10,

K11, K12, K14, L5, L7, L8,

L9, L10, L11, L12, M7, M8,

M9, M10, M11, M12, N6, N7,

N10, N13, N14, P5, P6, P9,

P11, P12

VSS Ground

D5, D8, D15, E7, E10, E13,

F4, F8, F11, F14, G5, H6,

H13, J14, K5, L13, L6, M4,

M14, M15, N5, N8, N11, P7,

P10, P13, R8, R15

VDD_CORE Power Supply for the Core Logic: +1.8 V

Pin Description (continued)

Pin Name Description

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

1.0 Functional Description

1.1 Overview

The device has 64 ST-BUS/GCI-Bus inputs (STiA0 - 31 and STiB0 - 31) and 64 ST-BUS/GCI-Bus outputs (SToA0 -

31 and SToB0 - 31). It is a non-blocking digital switch with 32,768 64 kbps channels and is capable of performing

rate conversion between groups of 2 inputs and 2 outputs. The inputs accept serial input data streams with data

rates of 8.192 Mbps, 16.384 Mbps, 32.768 Mbps or 65.536 Mbps. There are 32 input groups with each group

consisting of 2 streams (‘A’ and ‘B’). Each group can be set to any of the data rates. The outputs deliver serial data

streams with data rates of 8.192 Mbps, 16.384 Mbps, 32.768 Mbps or 65.536 Mbps. There are 32 output groups

with each group consisting of 2 streams (‘A’ and ‘B’). Each group can be set to any of the data rates.

By using Zarlink’s message mode capability, the microprocessor can store data in the connection memory which

can be broadcast to the output streams on a per-channel basis. This feature is useful for transferring control and

status information for external circuits or other ST-BUS/GCI-Bus devices.

The ZL50075 uses the ST-BUS/GCI-Bus master input frame pulse (FPi0) and the ST-BUS/GCI-Bus master input

clock (CKi0) to define the input frame boundary and timing for sampling the ST-BUS/GCI-Bus input streams with

various data rates (8.192 Mbps, 16.384 Mbps, 32.768 Mbps or 65.536 Mbps). The rate of the input clock is defined

by setting the CK_SEL1 - 0 pins.

A selectable Motorola or Intel compatible non-multiplexed microprocessor port allows users to program the device

to operate in various modes under different switching configurations. Users can use the microprocessor port to

perform internal register and memory read and write operations. The microprocessor port has 16 bit data bus and

17 bit address bus (in A18-0, A0 is not used, and A1 is used for word alignment). There are seven control signals

(CS, DS, R/W, DTA, WAIT, BERR and IM).

The device supports the mandatory requirements for the IEEE 1149.1 (JTAG) standard via the test port.

1.2 Switch Operation

The ZL50075 switches 64 kbps and Nx64 kbps data and voice channels from the TDM input streams, to timeslots

in the TDM output streams. The device is non-blocking; all 32 K input channels can be switched through to the

outputs. Any input channel can be switched to any av ailable output channel.

D10, D13, E8, E11, E14, F5,

F9, F12, G4, G6, G13, G15,

H14, J5, K6, K13, L14, M5,

M6, M13, N4, N9, N12, N15,

P8, P14, R5, R10, R13

VDD_IO Power Supply for the I/O: +3.3 V

Pin Description (continued)

Pin Name Description

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

Figure 2 - 32 K x 32 K Channel Basic Switch Configuration

The maximum channel switching capacity is determined by the number of streams and their rate of operation, as

shown in Table 1.

† The maximum capacity shown is when all streams are at the same rate, and none are operating at 16.384 Mbps or 8.192 Mbps.

‡ Switch capacity is limited to less than 32 K channels, only when streams are provisioned at 16 Mbps or 8 Mbps. The maximum switch capac-

ity in this case is given by 32,768 - (M x 256) - (N x 384), where M is the number of 16 Mbps input or output streams, and N is the number of

8 Mbps input or output streams.

1.3 Stream Provisioning

The ZL50075 is a large switch with a comprehensive list of user configurable, ’per-group’ programmable features.

In order to facilitate ease of use, the ZL50075 offers a simple programming model. Streams are grouped in sets of

two, with each group sharing the same configured characteristics. In this way it is possible to reduce programming

complexity, while still maintaining flexible ’per-stream’ configuration options:

• Input and output rate selection, see Section 1.4

• Input stream clock source selection, see Section 2.0

• Output stream clock source selection, see Se ction 2.0

• Input stream sampling point selection , see Section 5.1

• Output stream fractional bit advance, see Section 5.2

• Input and output stream inversio n control, see Section 14.4

The streams are grouped, one from the TDM ’A’ streams, combined with the corresponding ’B’ streams. For

example, input stream group #12 is STiA12 and STiB12, and output stream group #4 is SToA4 and SToB4. There

are 32 input and 32 output groups. Depending on the data rate set for the group there will be between 1 and 2

streams activated. If the data rate is set for 65.536 Mbps, the ‘A’ stream will be activated and the ‘B’ stream will not

be activated. If the data rate is set for 32.768 Mbps, 16.384 Mbps or 8.192 Mbps, the ‘A’ and ‘B’ streams will be

TDM Group

Data Rate

Maximum Number

of Input TDM Dat a

Streams

Maximum Number

of Output TDM

Data Streams

Number of

64 kbps Channels

per Stream

Maximum Switch

Capacity† (streams

x channels = total)

65.536 Mbps 32 32 1024 32 x 1024 = 32,768

32.768 Mbps 64 64 512 64 x 512 = 32,768

16.384 Mbps 64 64 256 64 x 256 = 16,384‡

8.192 Mbps 64 64 128 64 x 128 = 8,192‡

Table 1 - Data Rate and Maximum Switch Size

ZL50075

TDM INPUT TDM OUTPUT

64 Streams 64 Streams

STiA0 SToA0

32 K x 32 K

Input Group 0 STiB0

STiA31

STiB31

Input Group 31

SToB0 Output Group 0

SToA31

SToB31 Output Group 31

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

activated. The maximum channel cap acity of a group is 1024 channe ls when operating at 65 Mbps or 32 Mbps. The

switch capacity is reduced to 512 channels when operating at 16 Mbps and to 256 channels when operating at

8Mbps.

1.4 Input and Output Rate Selection

Table 1 shows the maximum number of streams available at different bit rates. The ZL50075 deactivates unused

streams when operating at the higher bit rates as shown in Table 2.

For 65 Mbps operation, only those input s and output s in the TDM ’A’ streams are active. For 32 Mbps, 16 Mbps and

8 Mbps operation, the inputs and outputs in the TDM ’A’ and ’B’ streams are active.

Note that if the internal system clock is not used as the clock source, there are limitations on the maximum data

rate. See Section 2.0 for more details.

1.4.1 Per Group Rate Selection

See Section 14.4, G roup Control Registers, for programming details. The data rates are set with the Input Stream

Bit Rate (bits 3 - 2) and the Output Stream Bit Rate (bits 19 - 18) in the Group Control Registers 0 - 31 (GCR0 - 31).

For the ZL50075, the bit rates of the inputs and outputs are programmed independently, in groups of 2 streams.

Depending on the rate programmed, the active streams in the group will be as indicated in Table 2.

For example:

• if input stream group #1 is programmed for 65 Mbps: STiA1 is active; STiB1 is not active

• if output stream group #15 is programmed for 32 Mbps, 16 Mbps or 8 Mbps: SToA15 and SToB15 are active

1.5 Rate Conversion

The ZL50075 supports rate conversion from any input stream rate to any output stream rate.

An example of ZL50075 rate conversion is given in Figure 3. The output stream rates do not have to follow the input

stream rates. In this example, on the input side of the switch you can have 24 streams operating at 65.536 Mbps

(24,576 channels - 24 group s with 1 stream in each group), 8 streams o perating at 32.768 Mbps (4096 channels - 4

groups with 2 streams in each group) and 8 streams operating at 16.384 Mbps (2048 channels - 4 groups with 2

streams in each group) with no streams operating at 8.192 Mbps. This results in an input capacity of 30,720 input

channels. This is less than the full capacity of the device as some groups are operating at less than 32 Mbps. As

the output streams do not have to follow the input streams, they can be configured so that 15 streams operate at

65.536 Mbps (15,360 channels - 15 groups with 1 stream in each group), 28 streams operate at 32.768 Mbps

(14,336 channels - 14 groups with 2 streams in each group), 2 streams operate at 16.384 Mbps (512 channels - 1

group with 2 streams in the group) and 4 streams opera te at 8.192 Mbps (512 channels - 2 group s with 2 streams in

each group). This results in an output capacity of 30,720 output channels. This is less than the full capacity of the

device as some group s are operating at less than 32 Mbps.

Input or Output Group n

(n = 0 - 31) 65 Mbps 32 Mbps 16 Mbps 8 Mbps

STiAn / SToAn Active Active Active Active

STiBn / SToBn Not Active Active Active Active

Table 2 - TDM Stream Bit Rates

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

Figure 3 - Input and Output Data Rate Conversion Example

2.0 Input Clock (CKi) and Input Frame Pulse (FPi) Timing

The input timing for the ZL50075 can be set for one of four different frequencies. They can also be set for ST-BUS

or GCI-Bus mode with positive or negative input. The CKi0 and FPi0 input timing must be provided in order for the

device to be used. There are two additional input clocks and frame pulses that can be provided. CKi0 is used to

generate the internal clock. This clock is used for all the internal logic and can be used as one of the clocks that

defines the timing for the input and output data. The input stream clock sourc e is se lected by th e IS SRC1 - 0 (bit s 1

- 0) in the Group Control Register. The output stream clock source is selected by the OSSRC1 - 0 (bits 17 - 16) in

the Group Control Register.

The CKi0 and FPi0 input frequency is set via the CK_SEL1 - 0 pins as shown in Table 3. By default the CKi0 and

FPi0 pins accept ST-BUS, negative input timing. The input frame pulse format (ST-BUS/GCI-Bus), frame pulse

polarity, and clock polarity can be programmed by the GCISEL0 (bit 2), FPIPOL0 (bit 1), and CKIPSL0 (bit 0) in the

Input Clock Control Register (ICCR), as described in Section 14.5.

The input streams, output streams, and output clocks / frame pulses can use either the internal system clock or the

input CKi0 and FPi0 as clock sources. The input streams’ clock sources are controlled by the ISSRC1-0 (bits 1 - 0)

in the Group Control Registers (GCR). The output streams’ clock sources are controlled by the OSSRC1-0 (bits 17

- 16) in the Group Control Registers (GCR). The output clocks’ / frame pulses’ clock sources are controlled by the

CKO1SRC1-0 (bits 8-7) and CKO0SRC1-0 (bits 1-0) in the Output Clock Control Register (OCCR). Using the input

CK_SEL1 CK_SEL0 Input CKi0 and FPi0

0 0 8.192 MHz

0 1 16.384 MHz

1 0 32.768 MHz

1 1 65.536 MHz

Table 3 - CKi0 and FPi0 Setting via CK_SEL1 - 0

Example:

Input Groups 0 - 23 at 65 Mbps; Output Groups 0 - 14 at 65 Mbps

Input Groups 24 - 27 at 32 Mbps; Output Gr oups 15 - 28 a t 32 Mbps

Input Groups 28 - 31 at 16 Mbps; Output Group 29 at 16 Mbps

Input Groups STiA0 - 23 at 65 Mbps

STiB0 - 23 Not Active

0 - 23 at 65 Mbps

Input Groups STiA24 - 27 at 32 Mbps

STiB24 - 27 at 32 Mbps

Input Groups STiA28 - 31 at 16 Mbps

STiB28 - 31 at 16 Mbps

28 - 31 at 16 Mbps

24 - 27 at 32 Mbps

SToA0 - 14 at 65 Mbps

STo B 0 - 14 Not Activ e

SToA15 - 28 at 32 Mbps

SToB15 - 28 at 32 Mbps

SToA29 at 16 Mbps

SToB29 at 16 Mbps

Output Groups

Output Group

29 at 16 Mbps

15 - 28 at 32 Mbps

0 - 14 at 65 Mbps

SToA30 - 31 at 8 Mbps

SToB30 - 31 at 8 Mbps Output Groups

30 - 31 at 8 Mbps

Output Grou ps 30 - 31 at 8 Mbps

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

CKi0 and FPi0 as clock source provides a direct inte rface to jittery periphera ls, while using the internal system clock

as clock source provides the best data rate and clock rate flexibility.

When the internal system clock is not used as the clock source, there are limitations to the data rate and the output

clock rate. For all the input and output stream groups that do not use the intern al system clock as their clock source,

the data rate is limited to be no higher than the selected clock source’s rate (e.g., if CKi0 runs at 16.384 MHz and it

is selected as the clock source for input stream group 3, then the maximum data rate of STiA3 and STiB3 is

16.384 Mbps). Similarly, for all the output clocks that do not use the internal system clock as their clock source, the

clock rate is limited to be no higher than the selected clock source’s rate (e.g., if CKi0 runs at 32.768 MHz and it is

selected as the clock source for output clock CKo0, then the maximum clock rate of CKo0 is 32.768 MHz).

3.0 Output Clock (CKo) and Output Frame Pulse (FPo) Timing

There are two output timing pairs, CKo1 - 0 and FPo1 - 0. By default these signals generate ST-BUS, negative

timing, and use the internal system clock as reference clock source. Their default clock rates are 65.536 MHz for

CKo0 and 32.768 MHz for CKo1. Their properties can also be individually progra mmed in the Output Clock Control

rate (8.192 MHz, 16.384 MHz, 32.768 MHz or 65.536 MHz), and reference clock source. Refer to Section 14.6 for

programming details. No te that the refe rence clock source can b e set to eith er the intern al system c lock or the input

CKi0 and FPi0 signals. If the input CKi0 and FPi0 is selected as the reference source, the output clock cannot be

programmed to generate a higher clock frequency than the reference source. As each output timing pair has its

own bit settings, they can be set to provide diffe rent output timings.

4.0 Output Channel Control

To be able to interface with external buffers, the output signals can be set to enter a high impedance or drive high

state on a per-channel basis. The Per Channel Function (bits 31 - 29) in the Connection Memory Bits can be set to

001 to drive the channel output high, or to 000, 110 or 111 to set the channel into a high impedance state.

5.0 Data Input Delay and Data Output Advancement

The Group Control Registers (GCR) are used to adjust the input delay and output advancement for each input and

output data groups. Each group is independently programmed.

5.1 Input Sampling Point Delay Programming

The input sampling point delay programming feature provides users with the flexibility of handling different wire

delays when incoming traffic is from different sources.

By default, all input streams have zero delay, such that bit 7 is the first bit that appears after the input frame

boundary (assuming ST-BUS formatting). The nominal input sampling point with zero delay is at the 3/4 bit time.

The input delay is enabled by the Input Sample Point Delay (bit 8 - 4) in the Group Control Registers 0 - 31 (GCR0

- 31) as described in Section 14.4 on page 32. The input sampling point delay can range from 0 to 7 3/4 bit delay

with a 1/4 bit resolution on a per group basis.

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

Figure 4 - Input Sampling Point Delay Programming

There are limitations when the ZL50075 is programmed to use CKi0 as the input stream clock source as opposed

to the internal clock:

• The granularity of the delay becomes 1/2 the selected reference clock period, o r 1/4 bit, whichever is longer

• If the selected re ference clock frequency is the same as the stream bit rate, the granularity of the delay is 1/2 bit.

In this case, the leas t significa nt bit of the ISPD register is not u sed; the rema ining 4 bit s select the total delay in

1/2 bit increments, to a maximum of 7 1/2 bits. Also, the 0 bit delay reference point changes from the 3/4 bit

position to the 1/2 bit position.

5.2 Fractional Bit Advancemen t on Output

See Section 14.4, Group Control Registers, for programming details.

This feature is used to advance the output data with respect to the output frame boundary. Each group has its own

bit advancement value which can be programmed in the Group Control Registers 0 - 31 (GCR0 - 31).

By default all output streams have zero bit advancement such that bit 7 is the first bit that appears after the output

frame boundary (assuming ST-BUS formatting). The output advancement is enabled by the Output Stream Bit

Advancement (bits 21 - 20) of the Group Control Registers 0 - 31 (GCR0 - 31), as described in Section 14.4. The

output delay can vary from 0 to 22.8 ns with a 7.6 ns increment. The exception to this is output streams

programmed at 65 Mbps, in which case the increment is 3.8 ns with a total advancement of 11.4 ns.

Nominal Channel n+1 Boundary

00000 (Default)

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

STi[n]

Nominal Channel n Boundary

Example: With a setting of 01111 the sampling point for bit 7 will be 3 1/2 bits

70 54321076

01110

01111

11110

11101

11100

11011

11010

11001

11000

10111

10110

10101

10100

10011

10010

10001

10000

11111

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

Figure 5 - Output Bit Advancement Timing

This programming feature is provided to assist in designs where per stream routing delays are significant and

different.

The OSBA bits in the Group Control Registers are used to set the bit-advancement for each of the corresponding

serial output stream groups. Figure 5 illustrates the effect of the OSBA settings on the output timing.

There are limit ations when the ZL50075 is programmed to use CKi0 as the output stream clock source:

• If the selected reference clock frequency is 65 MHz or 32 M Hz, the granularity of the advan cement is

reduced to 1/2 the clock period

• If the selected reference clock frequency is 16 MHz or 8 MHz, bit advancem ent is not available and the

output streams are driven at the nominal times

6.0 Message Mode

In Message Mode (MSG), microprocessor data can be broadcast to the output data streams on a per-channel

basis. This feature is useful for transferring control and st atus info rmation to external c ircu its or other TDM devices.

For a given output channe l, w hen the c orres pond ing Per Chann el Functio n (bit s 31 - 29) in the Con nection Memory

are set to Message Mode (010), the Connection Memory’s lowest data byte (bits 7 - 0) is output in the timeslot.

Refer to Section 14.1.1, Connection Memory Bit Functions , for programming details

Nominal 32/65 M Hz

Clock

7.6ns (~3.8 ns at 65 Mbps)

15.2ns (~7.6 ns at 65 M bps)

22.8ns (~11.4 ns at 65 Mbps)

Nominal Outp ut

Bit Timing

Level 1

Advance

Level 2

Advance

Level 3

Advance

OSBA = 00

OSBA = 01

OSBA = 10

OSBA = 11

Nominal 16 MHz

Clock

Nominal 8 MHz

Clock

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

To increase programming bandwidth, the ZL50075 has separate addressable 32 bit memory locations, called

Connection Memory Least Significant Bytes (LSB), which provide direct access to the Connection Memories’

Lowest data bytes (bits 7 - 0). Up to four consecutive message mode channels can be set with one Connection

Memory LSB access. Refer to Section 14.1.2, Connection Memory LSB, for programming details.

6.1 Data Memory Read

All TDM input channels can be read via the microprocessor port. This feature is useful for receiving control and

status information from external circuit s or other TDM devices. Each 32 bit Data Memory access e nables up to four

consecutive input channels to be monitored. The Data Memory field is read only; any attempt to write to this

address range will result in a bus error condition signalled back to the host processor. Refer to Section 14.2, Data

Memory, for programming details.

The latency of data reads is up to 3 frames, depending on when the input timeslots are sampled.

6.2 Connection Memory Block Programmin g

See Section 14.7, Block Init Register, and Section 14.8, Blo ck Init Enable Register, for programming details.

This feature allows for fast initialization of the connection memory after power up. When the block programming

mode is enabled, the contents of Block Init Register are written to all Connection Memory Bits. This operation

completes in one 125 µs frame. During Connection Memory initialization, all TDM output streams are set to high

impedance.

7.0 Data Delay Through the Switching Paths

See Secti on 14 .1 . 1, Connection Me m o ry Bit Functions, for progr amm ing details.

The switching of information from the input serial streams to the output serial streams results in a throughput delay.

The device can be programmed to perform timeslot interchange functions with different throughput delay

capabilities on a per-channel basis. For voice applications, select variable throughput delay to ensure minimum

delay between input and output data. In wideband data application, select constant delay to maintain the frame

integrity of the information through the switch. The delay through the device varies according to the type of

throughput delay selected by programming the Per Channel Function (bits 31 - 29) in the Connection Memories.

When these bits are set to 011, the channel is in variable delay mode. When they are set to 100, the channel is in

constant delay mode.

7.1 Constant Delay Mode

In this mode the frame integrity is maintained in all switching configurations. The delay though the switch is 2

frames - Input Channel + Output Channel. This can result in a minimum delay of 1 frame + 1 channel if the last

channel of a stream is switched to the first channel of a stream. The maximum delay is 1 channel short of 3 frames

delay. This occurs when the first channel of a stream is switched to the last channel of a stream.

The data throughput delay is expressed as a function of ST-BUS/GCI-Bus frames, input channel number (n) and

output channel number (m). The data throughput delay (T) is:

T = 2 frames + (n - m)

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

Figure 6 - Data Throughput Delay for Constant Delay

7.2 Variab le Delay Mode

Variable delay mode causes the output channel to be transmitted as soon as possible. This is a useful mode for

voice applications where the minimum throughput delay is more import ant than data in tegrity. The delay through the

switch is minimum 3 channels and maximum 1 frame + 2 channels.

Figure 7 - Data Throughput Delay for Variable Delay

N-2 N-1 CH0 CH1 CH2 CH3 N-2 N-1 CH0 CH1 CH2 CH3 N-2 N-1 CH0 CH1 CH2 CH3

N-2 N-1 CH0 CH1 CH2 CH3 N-2 N-1 CH0 CH1 CH2 CH3

CH4 CH5 CH6

CH7 CH8 CH9

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

8.0 Per-Channel A -Law/µ-Law Translation

The ZL50075 provides p er channel code translation to be used to adapt pulse cod e modulation (PCM) voice or data

traffic between networks which use different encoding laws. Code translation is available in both Connection Mode

and Message Mode.

This feature is controlled by the Connection Memories. The V/D (bit 28) defines if the traffic in the channel is voice

or data. The ICL1 - 0 (bits 27 - 26) define the input coding law and the OCL1 - 0 (bits 25 - 24) define the output

coding law. The different coding options are shown in Table 4:

For voice coding options, the ITU-T G.711 A-Law and ITU-T G.711 µ-Law are the standard rules for encoding. The

A-Law without Alternate Bit Inversion (ABI) is an alternative code that does not invert the even bits (6, 4, 2, 0). The

µ-Law without Magnitude Inve rsion (MI) is an alternative code that does not perform In version of magnitude bits (6,

5, 4, 3, 2, 1, 0).

When performing data code options, No Code does not invert the bits. The Alternate Bit Inversion (ABI) option

inverts the even bit s (6, 4, 2, 0) while the Inverted Altern ate Bit Inversion (ABI) in verts the odd bit s (7, 5, 3, 1). When

All Bits Inverted is selected, all of the bits (7, 6, 5, 4, 3, 2, 1, 0) are inverted.

The input channel and output channel encoding law are configured independently. If the output channel coding is

set to be dif ferent from the input channel, the ZL50075 performs translation between the two standards. If the input

and output encoding laws are set to the same standard, no translation occurs.

9.0 Bit Error Rate Tester

The ZL50075 has one Bit Error Rate (BER) transmitter and one BER receiver for each pair of input and output

streams, resulting in 64 transmitters connected to the output streams and 64 receivers associated with the input

streams. Each transmitter can generate a BER sequence with a pattern of 215-1 Pseudo-Random Code (ITU

O.151). Each transmitter can start at any location on the stream and will last for a minimum of 1 channel to a

maximum of 1 frame time (125 µs). The BER transmitters are enabled by programming the Per Channel Function

(bit 31 - 29) to 101 (PRBS Generator mode) in the Connection Memories.

Multiple Connection Memory locations can be programmed for BER tests. These locations are not required to be

consecutive. However, when read back, the BER locations must be received in the same order that they were

transmitted. If the BER locations are not received in the same order, the BER test will produce errors.

The PRBS bit pattern is sequentially loaded into the output timeslots. An example is shown in Figure 8.

Input Cod ing

(ICL1- 0) Output Coding

(OCL1 - 0) Voice Coding

(V/D bit = 0) Data Coding

(V/D bit = 1)

00 00 ITU-T G.711 A-Law No Code

01 01 ITU-T G.711 µ-Law Alternate Bit Inversion (ABI)

10 10 A-Law without Alternate Bit

Inversion (ABI) Inverted Alternate Bit

Inversion (ABI)

11 11 µ-Law without Magnitude

Inversion (MI) All Bits Inverted

Table 4 - Input and Output Voice and Data Coding

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

Figure 8 - Example PRBS Timeslot Insertion

Each PRBS detector can be configured to monitor for bit errors in one or more timeslots. The selection of timeslots

is configured by the Input BER Enable Control Memory (IBERECM). See Section 14.3.1 for programming details,

Each detector has an associated 16 bit error counter accessible vi a the microprocessor interface, as described in

Section 14.3.2, BER Counters. The value of the counter represents the total number of errors detected on the

corresponding input stream. Bit errors are accumulated until the counter is either reset (by writing to the counter or

by resetting the device), or the counter reaches its maximum value, 65,535 (decimal). If more than 65,535 errors

are detected, the counter will hold at the maximum value until reset.

Any number of timeslot s may be config ured fo r bit error rate testing; however the user must ensure the follow ing for

correct operation of the BER test function:

1. The number of timeslots enabled for PRBS detection on the input stream must equal the number of timeslots

enabled for PRBS generation on the source output stream

2. The arrival order of timeslot s a t the PRBS detector mu st be the same as the orde r in which timeslots were trans-

mitted by the PRBS generator. For example, in Figure 8 above, the timeslot order a, b, c must be maintained

through the external path from source TDM output stream to destination TDM input stream.

10.0 Microprocessor Port

The ZL50075 has a generic 16-bit microprocessor port that provides access to the 32-bit internal Data Memory

(read access only), Connection Memory and Control Registers. D15 on the bus maps to Bit 31 and Bit 15 of the

internal 32 bit memory or register, D14 maps to Bit 30 and Bit 14, etc.

The IM pin is used to select between Motorola bus control and Intel bus control. If the IM input is low, then a

Motorola control is selected. If the IM bit is high, then an Intel control is selected. Regardless of which bus

configuration is selected, the bus cycle termination signals WAIT & DTA are both provided.

The Data Memory, Connection Memory and Control Registers are assigned 32 bit fields in the ZL50075 memory

space. Eac h 32 bit memory or registe r location spans 4 consecutive addresses. Example:

• The 32 bit Group Control Register for TDM Group 0 is lo cated at address ra nge 40200 - 40203 Hex

The Least Significant address identifies the Most Significant Byte (MSB) in the 32 bit field, as illustrated in Table 5.

a cb

Frame m

a cb

Frame m+1

..010111001101101111001010110110001011111011010011100001101...

Example segm en t of seria l bi t pattern

Stream N with Channels

from Stream N PRBS Generator

a, b and c enabled

for PRBS insertion

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

The Address Bus, A1 8 - 0, controls access to each 32 bit location . A0 is not use d and must be conne cted to defined

logic level. Address bit A1 and the Data Transfer Size inputs, SIZ1 - 0, identify which bytes are being accessed.

In Motorola Bus Mod e (IM = 0), SIZ1 - 0 form active low data strob e signals, consistent with UDS and LDS available

on the MC68000 and MC68302 processors, as shown in Table 6.

In Intel Bus Mode (IM = 1), SIZ1 - 0 form active low byte enable signals, consistent with BE1 and BE0 available on

the Intel i960 processor, as shown in Table 6.

In both Intel and Motorola modes , the A1 ad dress input is used to identify the word alignment in internal memory, as

shown in Table 7.

Data bus word align m ents are shown in Table 8. An example of byte addressing is given in Table 9.

Address (Hex) Memory/Register Bits

40200 Bits 31:24 (MSB)

40201 Bits 23:16

40202 Bits 15:8

40203 Bits 7:0 (LSB)

Table 5 - Example of Addres s and Byte Significance

Pin Name Motorola Mode MC68000, MC68302

Equivalent Function

IM = 0

Intel Mode i960

Equivalent Function

IM = 1 Data Bus Bytes Enabled

SIZ1 UDS BE1 D15-8

SIZ0 LDS BE0 D7-0

Table 6 - Byte Enable Signals

A1 Memory Data Word Alignment

0 Bits 31:16

1Bits 15:0

Tabl e 7 - Memo ry Data Word Alignment

Microprocessor

16 Bit Data Bus SIZ1 SIZ0 A1 Interna l 32-Bit Memory

or Register

D15 - 8 0 1 0 B i ts 31 :2 4

011 Bits 15:8

D7 - 0 1 0 0 Bits 23:16

101 Bits 7:0

D15 - 0 0 0 0 B i ts 31 :1 6

001 Bits 15:0

11X

1. X - Don’t Care

No access

Table 8 - Data Bus Word Alignment

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

† - Don’t Care. A0 is not used.

10.1 Bus Operation

10.1.1 R ead C ycle

The operation of a read cycle is illustrated in Figure 9.

• The microprocessor asserts the R/W control signal high, to signal a read cycle. It also drives the ad dress A,

transfer size, SIZ1 - 0, and chip select logic drives the CS signal active low to select the ZL500 75

• The microprocessor then drives the DS signal a ctive low, to signal the start of the bus cycle. The DS signal

is held low for the duration of the bus cycle

•WAIT

is asserted active low

• The ZL50075 accesses the requested me mory or register locatio n(s), and places the requested data onto

the data bus, D15 - 0. All data bus pins are driven, whether or not they are being used for the specific data

transfer. Unused pins will present unknown data. If the address is to an unused area of the memory space,

unknown data is presented on the d ata bus

• The ZL50075 then de-asserts WAIT, and asserts either DTA or BERR , depending on the validity of the data

transfer

• When the microprocessor observes the active low state of the DTA or the BERR signal, it terminates the bus

cycle by driving the DS pin inactive high

• When the ZL50075 sees the DS sig nal go inactive high, it removes the assertions on the DTA or BERR

signals by driving them inactive high

• When the ZL50075 sees the CS sig nal go inactive high, it tri-states the data bus, D15 - 0 and the DTA and

BERR signals. However, if CS goes inactive hig h before DS goes inactive high, the DTA and BERR signals

are driven inactive high before they are tri-stated

• In Intel mode, DTA is always driven to signal the end of a bus cycle, regardless of BERR

Address

(Hex) Register

Description Register

Byte A18 - 0 (binary) SIZ1 SIZ0 Comments

40200 or

40201 Group Control

40282 or

40283 Input Clock Control

40286 or

40287 Output Clock

Control Register Bits 15:0 100 0000 0010 1000 011X†0 0 16 bit transfer

40284 or

40285 Output Clock

Control Register Bits 31:16 100 0000 0010 1000 010X†0 0 16 bit transfer

Table 9 - B yte Address Examples

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

Figure 9 - Read Cycle Operation

10.1.2 Write Cycle

The operation of the write cycle is illustrated in Figure 10.

• The microprocessor asserts the R/W control signal low, to sig nal a write cycle. It also drives the addre ss A,

data transfer size, SIZ1 - 0, and chip select logic drives the CS signal active low to select th e ZL50075

• The microprocessor then drives the data bus, D15 - 0 with the data to be written, and then drives the DS

signal active low, to signal the start of the bus cycle. The DS signal is held low for the duration of the bus

cycle

•WAIT

is asserted active low

• The ZL50075 transfers the data presented on the data bus pins into the indicated memory or register

location(s). If the address is to an unused area of the memory space, or to the data memory, no data is

transferred. The microprocessor port cannot write to the Data Memory

• The ZL50075 then de-asserts WAIT, and asserts either DTA or BERR , depending on the validity of th e data

transfer

• When the microprocessor observes the active low state of the DTA or the BERR signal, it terminates the bus

cycle by driving the DS pin inactive high

• When the ZL50075 sees the DS sig nal go inactive high, it removes the assertions on the DTA or BERR

signals by driving them inactive high

• When the ZL50075 sees the CS sig nal go inactive high, it tri-states the DTA and BERR signals. Howe ver, if

CS goes inactive high before DS goes in active high, the DTA and BERR signa ls are driven inactive high

before they are tri-stated

• In Intel mode, DTA is always driven to signal the end of a bus cycle, regardless of BERR

Address A,

SIZ1 - 0

R/W

Data

DTA

BERR

Hi-Z

WAIT

The cycle te rmination sign als WAIT & DTA a re provid ed for all b us configur ations.

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

Figure 10 - Write Cycle Operation

11.0 Power-up and Initialization of the ZL50075

11.1 Device Reset and Initialization

The PWR pin is used to reset the ZL50075. When this pin is low, the following functions are performed:

• Asynchronously puts the microprocessor port in a reset state

• Tristates all of the output streams (SToA0 - 31, SToB0 - 31)

• Preloads all of the registers with their default values (refer to the individual registers for defau lt values)

• Clears all internal counters

11 .2 Power Supply Sequencing

The ZL50075 has two separate power supplies: VDD_IO (3.3 V) and VDD_CORE (1.8 V). The recommended

power-up sequence is for VDD_IO to be applied first, followed by the VDD_CORE supply. VDD_CORE should not lead

VDD_IO supply by more than 0.3 V. Both supplies may be powered-down simultaneously.

11.3 Initialization

Upon power up, the ZL50075 should be initialized as follows:

•Assert PWR to low immediately after power is applied

• Set the TRST pin low to disable the JTAG TAP controller

• Deassert the PWR pin.

• Apply the Master Clock Input (CKi0) and Master Frame Pulse Input (FPi 0) to the values define d by the

CK_SEL1 - 0 pins

• Set the ODE p in low to disa ble the output stream s

Hi-Z

Address

SIZ1 - 0

R/W

Data

DTA

BERR

WAIT

The cycle term ination signals WAIT & DTA are provided for all bus configurations.

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

Note: After the PWR reset is removed, and on the application of a suitable master clock input, it takes

approximately 1 ms for the internal initialization to complete

• Automatic block initialization of the Connection Memory to all zeros occurs, without microprocessor

intervention

• All Group Control Registers are preset to 000C000C hex, corresp onding to rates of 65 Mbps, no link

inversions, no fractional output bit advancements, internal clock source, and no input sample po int delays

• The Input Clock Control Re gister is preset to 0DB hex, corresponding to:

- All clock inputs set to negative logic sense

- All frame pulse inputs set to negative logic sense

- All input frame pulses set to ST-BUS timing

• The Output Clock Control Register is pre-set to 060D1 C3C hex, corres ponding to :

- All clock outputs se t to negative logic sense

- All frame pulse output s set to negative logic sense

- All output frame pulses set to ST-BUS timing

- All output clock source selections to internal

- Clock outputs, CKo0 - 1 are preset to rates of 65 MHz and 32 MHz, respectively

Note: If the master clock input, CKi0, is not available, the microprocessor port will assert BERR on all accesses and

read cycles.

12.0 IEEE 1149.1 Test Access Port

The JTAG test port is implemented to meet the mandatory requirements of the IEEE 1149.1 (JTAG) standard. The

operation of the boundary-scan circuity is controlled by an external Test Access Port (TAP) Controller.

The ZL50075 uses the public instructions defin ed in IEEE 1149.1, with the provision of a 16-bit Instruction Register,

and three scannable Test Data Registers: Boundary Scan Register, Bypass Register and Device Identification

12.1 Test Access P ort (TAP)

The Test Access Port (TAP) accesses the ZL50075 test functions. The interface consists of 4 input and 1 output

signal. as follows:

•Test Clock (TCK) - TCK provides the clock for the test lo gic. The TCK does no t interfere with any on-chip

clock and thus remains independent in the fu nctional mode . The TCK pe rm its shifting of test data into or out

of the Boundary-Scan register cells concurrently with the operation of the device and without interfering with

the on-chip log ic.

•Test Mode Select (TMS) - The TAP Controller uses the logic signals received at th e TMS input to control

test operations. T he TMS signals are sam pled at the rising edge of the TCK pulse. This pin is internally

pulled to VDD_IO when it is not driven from an external source.

•Test Data Input (TDi) - Serial input data applied to this port is fed either into the instruction register or into a

test data register, depen ding on the sequence previously applied to the TMS input. Both registers are

described in a subsequent section. The received input data is sampled at the rising edge of TCK pulses.

This pin is internally pulled to VDD_IO when it is no t driven from an external source.

•Test Data Output (TDo) - Depending on the sequence previously applied to the TMS input, the contents of

either the instruction register or data register are serially shifted out towards the TDo. The data out of the

TDo is clocked on the falling edge of the TCK pulses. When no data is shifted through the boundary scan

cells, the TDo driver is set to a high impedance state.

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

•Test Reset (TRST) - Resets the JTAG scan structure. This pin is interna lly pulled to VDD_IO when it is not

driven from an external source. When JTAG is not in use, this pin must be tied low for normal op eration.

The TAP signals are only applied when the Z L50075 is required to be in test mode. When in normal, non-test mode,

TRST must be connected low to disable the test logic. The remaining test pins may be left unconnected.

12.2 Instruct ion Regis ter

The ZL50075 uses the public instructions defined in the IEEE 1149.1 standard. The JTAG interface contains a

16-bit instruction register. Instructions are serially loaded into the instruction register from the TDi when the TAP

controller is in its shifted-OR state. These instructions are subsequently decoded to achieve two basic functions: to

select the test data register that may operate while the instruction is current and to define the serial test data

12.3 Te st D ata Register

As specified in the IEEE 1149.1 standard, the ZL50075 JTAG Interface contains three test data registers:

•The Boundary-Scan Register - The Boundary-Scan register consists of a series of Boundary-Scan cells

arranged to form a scan path around the boundary of the ZL50075 core logic.

•The Bypass Register - The Bypass register is a single stage shift register that pr ovides a o ne-bit path from

TDi to TDo.

•The Device Identification Register - The JTAG device ID for the ZL5007 5 is C39B1 4BH

12.4 Boundary Scan Descriptio n Language (BSDL)

A Boundary Scan Description Language (BSDL) file is available from Zarlink Semiconductor to aid in th e use of the

IEEE 1149.1 test interface.

Version <31:28> 0000

Part Number <27:12> 1100 0011 1001 1011

Manufacturer ID <11:1> 0001 0100 101

LSB <0> 1

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

13.0 Memory Map of ZL50075

The memory map for the ZL50075 is given in Table 10.

14.0 Detailed Memory and Register Descriptions

This section describes all the memories and registers that are used in this device.

14.1 Connection Mem ory

Address range 00000 - 1FFFF hex.

On power-up, all Connection Memory locations are initialized automatically to 00000000 hex, using the Block

Initialization feature, as described in Section 14.7 and Section 14.8.

The 32 bit Connection Memory has 32,768 locations. Each 32 bit long-word is used to program the desired source

data and any other per-channel characteristics of one output time-slot.

The memory map for the Connection Memory is sub-divided into 32 blocks, each corresponding to one of the

possible 32 output stream group numbers. The address ranges for these blocks are illustrated in Table 11.

Address (Hex) Description

00000 - 1FFFF Connection Memory

20000 - 27FFF Connection Memory LSB

28000 - 2FFFF Data Memory: Read only; Bus error on write (BERR)

30000 - 37FFF Input BER Enable Con trol Memory

38000 - 3FFFF Invalid Address. Access causes Bus error (BERR)

40000 - 401FF BER Counters

40200 - 4027F Group Control Registers

40280 - 40283 Input Clock Control Register

40284 - 40287 Output Clock Control Register

40288 - 4028B Block Init Register

4028C - 4028F Block Init Enable

40290- 7FFFF Invalid Address. Access causes Bus error (BERR)

Table 10 - Memory Map

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

The mapping of each output stream, SToAn and SToBn, depends on the programmed bit rate. The address offset

range for each stream is illustrated in Table 12.

The address range for a particular stream is given by adding the group start address, as indicated in Table 11, to

the appropriate stream offset range, as indicated in Table 12. For example, the Connection Memory address range

for SToB12 operating at 32 Mbps is 00C800-00CFFF.

Output

Group

Start

Address

(Hex)

Address Range

(Hex) Output

Group

Start

Address

(Hex)

Address Range

(Hex)

0 000000 000000 - 000FFF 16 010000 010000 - 010FFF

1 001000 001000 - 001FFF 17 011000 011000 - 011FFF

2 002000 002000 - 002FFF 18 012000 012000 - 012FFF

3 003000 003000 - 003FFF 19 013000 013000 - 013FFF

4 004000 004000 - 004FFF 20 014000 014000 - 014FFF

5 005000 005000 - 005FFF 21 015000 015000 - 015FFF

6 006000 006000 - 006FFF 22 016000 016000 - 016FFF

7 007000 007000 - 007FFF 23 017000 017000 - 017FFF

8 008000 008000 - 008FFF 24 018000 018000 - 018FFF

9 009000 009000 - 009FFF 25 019000 019000 - 019FFF

10 00A000 00A000 - 00AFFF 26 01A000 01A000 - 01AFFF

11 00B000 00B000 - 00BFFF 27 01B000 01B000 - 01BFFF

12 00C000 00C000 - 00CFFF 28 01C000 01C000 - 01CFFF

13 00D000 00D000 - 00DFFF 29 01D000 01D000 - 01DFFF

14 00E000 00E000 - 00EFFF 30 01E000 01E000 - 01EFFF

15 00F000 00F000 - 00FFFF 31 01F000 01F000 - 01FFFF

Table 11 - Connection Memory Group Address Mapping

Output Group Data Rate Timeslot Range Output Stream Stream Address Offset Range (Hex)

65 Mbps 0 - 1023 SToAn00000 - 00FFF

SToBnN/A

32 Mbps 0 - 511 SToAn00000 - 007FF

SToBn00800 - 00FFF

16 Mbps 0 - 255 SToAn00000 - 003FF

SToBn00400 - 007FF

N/A BERR 00800 - 00FFF

8 Mbps 0 - 127 SToAn00000 - 001FF

SToBn00200 - 003FF

N/A BERR 00400 - 00FFF

Table 12 - Connection Memo ry Stream Address Offset at Various Output Rates

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

Each output channel timeslot occupies a range of 4 addresses in the Connection Memories. The timeslot address

offset is illustrated in Table 13. It shows the maximum number of timeslots that a stream can have, but the actual

number of timeslot s available depends on the output data rates, as illustrated in Table 1 and Table 12.

Timeslot Address

Offset hex

SToAnSToBn

00 000

11 004

22 008

-- -

510 510 7F8

511 511 7FC

512 800

513 804

1021 FF4

1022 FF8

1023 FFC

Table 13 - Connection Memory Timeslot Address Offs et Range

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

14.1.1 Connec tion Memory Bit Function s

The bit functions of the connection memory are illustrated in Table 14.

Bit Name Description

31 - 29 PCF2 - 0 Per Channel Function

28 V/D Voice/Data Control

When this bit is low, the corresponding channel is for voice.

When this bit is high, the corresponding ch annel is for data.

27 - 26 ICL1 - 0 Input Coding Law

Table 14 - Connection Memory Bits (CMB)

External Read/Write Address: 000000H

Reset Value: 0000H

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PCF

2PCF

1PCF

0V/D ICL

1ICL

0OCL

1OCL

00 00 0 0 000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0GP

4GP

3GP

2GP

1GP

0STCH

9STCH

8STCH

7STCH

6STCH

5STCH

4STCH

3STCH

2STCH

1STCH

PCF2 - 0 Function Description

000 OT Output is tri-stated

001 FH Output drives high always

010 MSG Output is in message mode

011 VAR Variable delay connection mode

100 CD Constant delay connection mode

101 PRBS PRBS Genera tor

110 OT Output is tri-stated

111 OT Output is tri-stated

ICL1 - 0 Input Coding Law

For Voice (V/D bit = 0) For Data (V/D bit = 1)

00 CCITT.ITU A-Law No Code

01 CCITT.ITU µ-Law ABI

10 A-Law w/o ABI Inverted ABI

11 µ-Law w/o Mag. Inv All Bits Inverted

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

14.1.2 Connection Memory LSB

The Connection Memory Least Significant Byte field is provided to give a convenient alternative way to modify the

output data for a stream in message mode. In this memory address range, all of the connection memory least

significant byte s (bits 7 - 0 ) are available fo r read/write in consecutive addre ss locations. This featur e is provided for

programming convenience. It can allow higher programming bandwidth on message mode streams. For example,

one longword access to this memory space can read or set the message bytes in four consecutive connection

memory locations. Access to this memory space is big-endian, with the most significant bytes on the data bus

accessing the lower address of the connection memory. Addressing into each of the streams is illustrated in Table

15.

25 - 24 OCL1 - 0 Output Coding Law

23 - 15 Unused Reserved. In normal functional mode, these bits MUST be set to zero.

14 - 10 GP4 - 0 Source Group Selection. These bits define the input/source group numb er (31 - 0)

9 - 0 STCH

9 - 0 Source Stream and Channel Selection / Message Mode Data

In connection mode (constant/variable delay), these bits define the input/source stream

and channel number, depending on the data rate.

For 65.536 Mbps, bits 9 - 0 select the input channel (0 - 1023).

For 32.768 Mbps, bits 9 - 1 select the input channel (0 - 511). Bit 0 selects stream STiA

(0) or STiB (1).

For 16.869 Mbps, bit s 9 - 2 select the input channel (0 - 255). Bit 0 selects stream STiA

(0) or STiB (1). Bit 1 MUST be set to 0.

For 8.192 Mbps, bit s 9 - 3 select the input channel (0 - 127). Bit 0 selects stream ST iA (0)

or STiB (1). Bit 2-1 MUST be set to 00.

In message mode, bits 7 - 0 define the output data. The data is output sequentially with

bit 7 being output first. Bits 9 - 8 are not used.

Bit Name Description

Table 14 - Connectio n Memory Bits (CMB) (continued)

External Read/Write Address: 000000H

Reset Value: 0000H

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PCF

2PCF

1PCF

0V/D ICL

1ICL

0OCL

1OCL

00 00 0 0 000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0GP

4GP

3GP

2GP

1GP

0STCH

9STCH

8STCH

7STCH

6STCH

5STCH

4STCH

3STCH

2STCH

1STCH

OCL1 - 0 Output Coding Law

For Voice (V/D bit = 0) For Data (V/D bit = 1)

00 CCITT.ITU A-Law No Code

01 CCITT.ITU µ-Law ABI

10 A-Law w/o ABI Inverted ABI

11 µ-Law w/o Mag. Inv All Bits Inverted

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

Within each stream group, the mapping of each of the actual output streams, SToAn and SToBn, depends on the

output rate programmed into the Group Control Registers. The address offsets to these control areas for each of

the output streams are illustrated in Table 16.

Output

Group

Start

Address

(Hex)

Address Range

(Hex) Output

Group

Start

Address

(Hex)

Address Range

(Hex)

0 020000 020000 - 0203FF 16 024000 024000 - 0243FF

1 020400 020400 - 0207FF 17 024400 024400 - 0247FF

2 020800 020800 - 020BFF 18 024800 024800 - 024B FF

3 020C00 020C00 - 020FFF 19 024C00 024C00 - 024FFF

4 021000 021000 - 0213FF 20 025000 025000 - 0253FF

5 021400 021400 - 0217FF 21 025400 025400 - 0257FF

6 021800 021800 - 021BFF 22 025800 025800 - 025B FF

7 021C00 021C00 - 021FFF 23 025C00 025C00 - 025FFF

8 022000 022000 - 0223FF 24 026000 026000 - 0263FF

9 022400 022400 - 0227FF 25 026400 026400 - 0267FF

10 022800 022800 - 022BFF 26 026800 026800 - 026BFF

11 022C00 022C00 - 022FFF 27 026C00 026C00 - 026FFF

12 023000 023000 - 0233FF 28 027000 027000 - 0273FF

13 023400 023400 - 0237FF 29 027400 027400 - 0277FF

14 023800 023800 - 023BFF 30 027800 027800 - 027BFF

15 023C00 023C00 - 023FFF 31 027C00 027C00 - 027FFF

Table 15 - Connec tion Memory LSB Group Address Map ping

Output Group Data Rate Timeslot Range Output Stream Stre am Address Offset Range (Hex)

65 Mbps 0 - 1023 SToAn00000 - 003FF

SToBnN/A

32 Mbps 0 - 511 SToAn00000 - 001FF

SToBn00200 - 003FF

16 Mbps 0 - 255 SToAn00000 - 000FF

SToBn00100 - 001FF

N/A BERR 00200 - 003FF

8 Mbps 0 - 127 SToAn00000 - 0007F

SToBn00080 - 000FF

N/A BERR 00100 - 003FF

Table 16 - Connection Memory LSB Stream Address Offset at Various Output Rates

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

14.2 Da ta Memory

The data memory field is a read only address range used to monitor the data being received by the input streams.

Addressing into each of the streams is illustrated in Table 17.

Within each stream gro up, the mapping of e ach of the actual in put streams, STiAn and STiBn, depends on th e input

rate programmed into the Group Control Registers. The address offsets to these data areas for each of the input

streams are illustrated in Table 18.

Input

Group

Start

Address

(Hex)

Address Range

(Hex) Input

Group

Start

Address

(Hex)

Address Range

(Hex)

0 028000 028000 - 0283FF 16 02C000 02C000 - 02C3FF

1 028400 028400 - 0287FF 17 02C400 02C400 - 02C7FF

2 028800 028800 - 028BFF 18 02C800 02C800 - 02CBFF

3 028C00 028C00 - 028FFF 19 02CC00 02CC00 - 02CFFF

4 029000 029000 - 0293FF 20 02D000 02D000 - 02D3FF

5 029400 029400 - 0297FF 21 02D400 02D400 - 02D7FF

6 029800 029800 - 029BFF 22 02D800 02D800 - 02DBFF

7 029C00 029C00 - 029FFF 23 02DC00 02DC00 - 02DFFF

8 02A000 02A000 - 02A3FF 24 02E000 02E000 - 02E3FF

9 02A400 02A400 - 02A7FF 25 02E400 02E400 - 02E7FF

10 02A800 02A800 - 02ABFF 26 02E800 02E800 - 02EBFF

11 02AC00 02AC00 - 02AFFF 27 02EC00 02EC00 - 02EFFF

12 02B000 02B000 - 02B3FF 28 02F000 02F000 - 02F3FF

13 02B400 02B400 - 02B7FF 29 02F400 02F400 - 02F7FF

14 02B800 02B800 - 02BBFF 30 02F800 02F800 - 02FBFF

15 02BC00 02BC00 - 02BFFF 31 02FC00 02FC00 - 02FFFF

Table 17 - Data Memory Group Address Mapping

Input Group Data Rate Time-slot Range Input Streams Address Offset Range (Hex)

65 Mbps 0 - 1023 STiAn00000 - 003FF

STiBnN/A

32 Mbps 0 - 511 ST iA n00000 - 001FF

STiBn00200 - 003FF

16 Mbps 0 - 255 STiAn00000 - 000FF

STiBn00100 - 001FF

N/A BERR 00200 - 003FF

8 Mbps 0 - 127 STiAn00000 - 0007F

STiBn00080 - 000FF

N/A BERR 00100 - 003FF

Table 18 - Data Memory Strea m Address Offs et at Various Output Rates

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

The address ranges for the data memory portion corresponding to each of the actual input streams, STiAn and

STiBn, for any particular input group number is calculated by adding the Start Address for the particular group, as

indicated in Table 17, to the appropriate Address Offset Range, as indicated in Table 18. The time-slots map

linearly into the appropriate address offset range. (i.e., timeslots 0, 1, 2,... map into addresses 00000, 00001,

00002,...)

The entire data memory is a read only structure. Any write attempts will result in a bus error. BERR is driven active

low to terminate the bus cycle.

14.3 BER Control Memory and Error Counters

14.3.1 Input BER En able Contr ol Memory

The BER Enable Control Memory (IBERECM) is a read/write memory block. Each memory location is used to

control the BER counter of one incoming timeslot. Address ing in to each of the streams is illustrated in Table 19.

Each byte locatio n of the BER Ena ble Memory c ontains one read/write BER counter enable (BCE) bit, mapped into

the D0 location. If the BCE bit is s et, then th e BER coun ter for the corresponding strea m and timeslot is enabled for

the duration of that timeslot. If the BCE bit is cleared the counter is disabled.

Input

Group

Start

Address

(Hex)

Address Range

(Hex) Input

Group

Start

Address

(Hex)

Address Range

(Hex)

0 030000 030000 - 0303FF 16 034000 034000 - 0343FF

1 030400 030400 - 0307FF 17 034400 034400 - 0347FF

2 030800 030800 - 030BFF 18 034800 034800 - 034B FF

3 030C00 030C00 - 030FFF 19 034C00 034C00 - 034FFF

4 031000 031000 - 0313FF 20 035000 035000 - 0353FF

5 031400 031400 - 0317FF 21 035400 035400 - 0357FF

6 031800 031800 - 031BFF 22 035800 035800 - 035B FF

7 031C00 031C00 - 031FFF 23 035C00 035C00 - 035FFF

8 032000 032000 - 0323FF 24 036000 036000 - 0363FF

9 032400 032400 - 0327FF 25 036400 036400 - 0367FF

10 032800 032800 - 032BFF 26 036800 036800 - 036BFF

11 032C00 032C00 - 032FFF 27 036C00 036C00 - 036FFF

12 033000 033000 - 0333FF 28 037000 037000 - 0373FF

13 033400 033400 - 0337FF 29 037400 037400 - 0377FF

14 033800 033800 - 033BFF 30 037800 037800 - 037BFF

15 033C00 033C00 - 033FFF 31 037C00 037C00 - 037FFF

Table 19 - BER Enable C ontrol Memory Group Address M apping

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

14.3.2 BER Count ers

There are a total of 64 Bit Error Counters, corresponding to the 64 serial input streams. Each count value is 32 bits

wide, but only the least significant 16 bits are used. The most significant 16 bits of the bit error counters will always

read back zero. A write operation to any byte of the counter, including the 16 most significant bits, will clear that

counter.

Each bit error counter contains the number of single bit errors detected on the corresponding stream, since the

counter was last cleared. If the number of bit errors detected exceeds 65535 (decimal), the counter will hold that

value until it is cleared.

14.4 Group Contro l Register s

The ZL50075 addresses the issues of a simple programming model an d auto matic stream con figuration by defining

a basic switching bit rate of 65.536 Mbps and by grouping the I/O streams. Each TDM I/O group contains 2 input

and 2 output streams. The 2 input streams in the same group have identical input characteristics, and similarly, the

2 output streams in the same group have identical output characteristics. However, input and output streams in the

same group can have different input and output operation characteristics.

Input Group Data Rate Time-slot Range Input St reams Address Offset Range (Hex)

65 Mbps 0 - 1023 STiAn00000 - 003FF

STiBnN/A

32 Mbps 0 - 511 STiAn00000 - 001FF

STiBn00200 - 003FF

16 Mbps 0 - 255 STiAn00000 - 000FF

STiBn00100 - 001FF

N/A BERR 00200 - 003FF

8 Mbps 0 - 127 STiAn00000 - 0007F

STiBn00080 - 000FF

N/A BERR 00100 - 003FF

Table 20 - BER Enable Co ntrol Memory Stream Address Offset at Various Output Rates

BER Input Group BER Input Stream Start Address (Hex) Address Range (Hex)

0 STiA0 040000 040000 - 040003

STiB0 040004 040004 - 040007

N/A BERR 040008 - 04000F

1 STiA1 040010 040010 - 040013

STiB1 040014 040014 - 040017

N/A BERR 040018 - 04001F

31 STiA31 0401F0 0401F0 - 0401F3

STiB31 0401F4 0401F4 - 0401F7

N/A BERR 0401F8 - 0401FF

Table 21 - BER Coun ter Group and Stream Address Mapping

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

The Group Control Registers are provided for setting the operating characteristics of the TDM input and output

streams. All of the Group Control Registers are mapped long-word aligned on 32 bit boundaries in the memory

space. Eac h of the 32 registers is used to control one group. The mapping of the Group Contro l Reg isters to the I/O

group numbers is illustrated in Table 22. The bit functions of each of the Group Control Register s are illustrated in

Table 23.

TDM Group Group Control Register Address (Hex)

0 40200 - 40203

1 40204 - 40207

2 40208 - 4020B

3 4020C - 4020F

29 40274 - 40277

30 40278 - 4027B

31 4027C - 4027F

Table 22 - Group Control Register Addressin g

Bit Name Description

31 - 23 Unused Reserved. In normal functional mode, these bits MUST be set to zero.

22 OSI Output St ream Inversion

For normal operation, this bit is set low.

To invert the output stream, set this bit high.

21 - 20 OSBA1 - 0 Output S t ream Bit Advan cement

Table 23 - Group Control Register

External Read/Write Address: 40200H - 4027FH

Reset Value: 000C000CH

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

00 0 0 0 0 0 0 0 OSI

OSBA

1OSBA

0OSBR

1OSBR

0OSSRC

1OSSRC

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 ISI ISPD

4ISPD

3ISPD

2ISPD

1ISPD

0ISBR

1ISBR

0ISSRC

1ISSRC

OSBA1 - 0 Non-65 Mbps 65 Mbps

00 0 ns 0 ns

01 7.6 ns 3.8 ns

10 15.2 ns 7.6 ns

11 22.8 ns 11.4 ns

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

19 - 18 OSBR1 - 0 Output Stream Bit Rate

Unused streams are tri-stated.

If the internal system clock is used as the clock source, all the above data rates are

available. Otherwise, the data rate cannot exceed the selected clock source’s rate.

17 - 16 OSSRC1 - 0 Output Stream Clock Source Select

15 - 10 Unused Reserved. In normal functional mode, these bits MUST be set to zero.

9ISIInput Stream Inversion

For normal operation, this bit is set low.

To invert the input stream, set this bit high.

8 - 4 ISPD4 - 0 Input Sampling Point Delay

Default Sampling Point is 3/4. Adjust according to Figure 4 on page 12.

Bit Name Description

Table 23 - Group Control Register (continued)

External Read/Write Address: 40200H - 4027FH

Reset Value: 000C000CH

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

00 0 0 0 0 0 0 0 OSI

OSBA

1OSBA

0OSBR

1OSBR

0OSSRC

1OSSRC

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 ISI ISPD

4ISPD

3ISPD

2ISPD

1ISPD

0ISBR

1ISBR

0ISSRC

1ISSRC

OSBR1 - 0 Bit Rates Per Group

SToA SToB

00 8.192 Mbps 8.192 Mbps

01 16.384 Mbps 16.384 Mbps

10 32.768 Mbps 32.768 Mbps

11 65.536 Mbps Not Used

OSSRC1 - 0 Output Timing Sourc e

00 Internal System Clock

01 CKi0 and FPi0

10 Reserved

11 Reserved

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

The Group Control Register is a static c ontrol register. Changes to bit settings may disrupt dat a flow on the se lected

port for a maximum of 2 frames.

3 - 2 ISBR1 - 0 Input Stream Bit Rate

Unused streams must be connected to ground.

If the internal system clock is used as the clock source, all the above data rates are

available. Otherwise, the data rate cannot exceed the selected clock source’s rate.

1 - 0 ISSRC1 - 0 Input Stream Clock Source Select

Bit Name Description

Table 23 - Group Control Register (continued)

External Read/Write Address: 40200H - 4027FH

Reset Value: 000C000CH

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

00 0 0 0 0 0 0 0 OSI

OSBA

1OSBA

0OSBR

1OSBR

0OSSRC

1OSSRC

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 ISI ISPD

4ISPD

3ISPD

2ISPD

1ISPD

0ISBR

1ISBR

0ISSRC

1ISSRC

ISBR1 - 0 Bit Rates Per Group

STiA STiB

00 8.192 Mbps 8.192 Mbps

01 16.384 Mbps 16.384 Mbps

10 32.768 Mbps 32.768 Mbps

11 65.536 Mbps Not Used

ISSRC1 - 0 Input Timing Source

00 Internal System Clock

01 CKi0 and FPi0

10 Reserved

11 Reserved

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

14.5 Input Clock Control Register

The Input Clock Control Register is used to select the logic sense of the input clock.

Bit Name Description

31 - 9 Unused Reserved. In normal functional mode, these bits MUST be set to zero.

8 - 3 Unused Reserved. In normal functional mode, these bits MUST be set to 011011.

2 GCISEL0 GCI-Bus Selection for FPi0

When this bit is low, FPi0 is set for ST-BUS mode.

When this bit is high, FPi0 is set for GCI-Bus mode.

1 FPIPOL0 Frame Pulse Polarity Selection for FPi0

When this bit is low, FPi0 is set for the positive cl ock edge.

When this bit is high, FPi0 is set for negative.

0CKIPOL0Clock Polari ty Selection for CKi0

When this bit is low, CKi0 is set for the positive clock edge.

When this bit is high, CKi0 is set for negative.

Table 24 - Input Clock Control Register

External Read/Write Address: 40280H

Reset Value: 0DBH

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

00000000 00000000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

00000000 11011GCI

SEL0 FPI

POL0 CKI

POL0

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

14.6 Output Clock Control Register

The Output Clock Control Register is used to select the desired source, frequency, and logic sense of the output

clocks. The bit functions of the Output Clock Control Register are illustrated in Table 25.

Bit Name Description

31 - 28 Unused Reserved. In normal func tional mode, these bits MUST be s et to zero.

27 - 14 Unused Reserved. In normal functional mode, these bits MUST be set to 01100000110100.

13 GCO

SEL1 GCI-Bus Selection for FPo1

When this bit is low, FPo1 is set for ST-BUS mode.

When this bit is high, FPo1 is set for GCI-Bus mode.

12 FPO

POL1 Frame Pulse Polarity Selection for FPo1

When this bit is low, FPo1 is set for the positive clock edge.

When this bit is high, FPo1 is set for the negative clock edge.

11 CKO

POL1 Clock Polarity Selection for CKo1

When this bit is low, CKo1 is set for the positive clock edge.

When this bit is high, CKo1 is set for the negative clock edge.

10 - 9 CKO1

RATE

1 - 0

Output Clock Rate for CKo1 and FPo1

The output clock rate can not exceed the selected clock source rate. All rates are avail-

able when the internal system clock is selected as clock source.

8 - 7 C KO1

SRC

1 - 0

Output Clock Source for CKo1 and FPo1

Table 25 - Output Clock Control Register

External Read/Write Address: 40284H

Reset Value: 060D1C3CH

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

00 000 1 10 0 000 1 101

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GCO

SEL1 FPO

POL1 CKO

POL1 CKO1

RATE1 CKO1

RATE0 CKO1

SRC1 CKO1

SRC0 GCO

SEL0 FPO

POL0 CKO

POL0 CKO0

RATE1 CKO0

RATE0 CKO0

SRC1 CKO0

SRC0

CKO1RATE1 - 0 CKo1FPo1

00 8.192 MHz 120 ns

01 16.384 MHz 60 ns

10 32.768 MHz 30 ns

11 65.536 MHz 15 ns

CKO1SRC1 - 0 Output Timing Source

00 Internal System Clock

01 CKi0 and FPi0

10 Reserved

11 Reserved

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

6GCO

SEL0 GCI-Bus Selection for FPo0

When this bit is low, FPo0 is set for ST-BUS mode.

When this bit is high, FPo0 is set for GCI-Bus mode.

5FPO

POL0 Frame Pulse Polarity Selection for FPo0

When this bit is low, FPo0 is set for the positive clock edge.

When this bit is high, FPo0 is set for the negative clock edge.

4CKO

POL0 Clock Polarity Selection for CKo0

When this bit is low, CKo0 is set for the positive clock edge.

When this bit is high, CKo0 is set for the negative clock edge.

3 - 2 C KO0

RATE

1 - 0

Output Clock Rate for CKo0 and FPo0

The output clock rate can not exceed the selected clock source rate. All rates are avail-

able when the internal system clock is selected as clock source.

1 - 0 C KO0

SRC

1 - 0

Output Clock Source for CKo0 and FPo0

Bit Name Description

Table 25 - Output Clock Con trol Register (continue d)

External Read/Write Address: 40284H

Reset Value: 060D1C3CH

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

00 000 1 10 0 000 1 101

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GCO

SEL1 FPO

POL1 CKO

POL1 CKO1

RATE1 CKO1

RATE0 CKO1

SRC1 CKO1

SRC0 GCO

SEL0 FPO

POL0 CKO

POL0 CKO0

RATE1 CKO0

RATE0 CKO0

SRC1 CKO0

SRC0

CKO0RATE1 - 0 CKo0FPo0

00 8.192 MHz 120 ns

01 16.384 MHz 60 ns

10 32.768 MHz 30 ns

11 65.536 MHz 15 ns

CKO0SRC1 - 0 Output Timing Source

00 Internal System Clock

01 CKi0 and FPi0

10 Reserved

11 Reserved

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

14.7 Block Init R egister

The Block Init Register is a 32 bit read/write register at address 040288 - 04028BH.

The Block Init Register is used during block initialization of the connection memory. A block initialization

automatically occurs at power-up. However, it is possible to perform a block initialization at any time. During Block

Initialization, the value of the Block Init Register is copied to all connection memory locations in an operation that

runs in about 120 µs. If the Block Init Register is modified during a block initialization, the new value used is

ignored.

14.8 Block Init En able Regis ter

The Block Init Enable Registe r is a 32 bit read/write register at address 04028C - 04028FH.

The Block Init Enable Regis ter is used to initiate a block initialization of the connection memory. A block initialization

automatically occurs at power-up. Since the Block Init Register is cleared at power-up this automatic block

initialization will write all zeros to all Connection Me mory Bi t s. However, it is possible to perform a block initialization

at any time. To begin a block initialization, the hex value 31415926 must be written to the Block Init Enable

Register. If a block initialization is signaled while one is in progress, the signal is ignored, and the currently active

block initialization is allowed to complete.

The value read back from the Block Init Enable Register is different from the value written. It represents both the

block initialization status, and the power-up reset initialization status. The meaning of the initialization status bits is

illustrated in Table 26. The bits 31 - 2 always read back 0.

Any access to the connection memory or the data memory during a block initialization or a reset initialization will

result in a bus error, BERR. All TDM outputs are tri-stated during any block initialization.

Bit Name Description

0 Block Init S tatus 0 if Block initialization is completed;

1 if Block initialization is in progress

1 Reset Init Status 0 if Reset initialization is completed

1 if Reset initialization is in progress

Table 26 - Blo ck and Power-u p Initialization Status Bits

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

15.0 DC/AC Electrical Characteristics

Note 1: Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

Note 2: Typical fig ures are at 2 5°C, VDD_CORE at 1.8 V and VDD_IO at 3. 3 V and ar e for de sign aid on ly: not guar anteed an d not

subject to production testing.

Note 1: Typical fig ures are at 2 5°C, VDD_CORE at 1.8 V and VDD_IO at 3. 3 V and ar e for de sign aid on ly: not guar anteed an d not

subject to production testing.

Absolute Maximum Ratings1 - Voltages are with respect to ground (VSS) unless otherwise stated.

Characteristics Sym. Min. Typ.2Max. Unit

1 Chip I/O S u pp ly Voltage V DD_IO -0.5 5.0 V

2 Chip Cor e S u pp ly Voltage VDD_CORE -0.5 5.0 V

3 Input Voltage (non-5 V tolerant inputs) VI_3V -0.5 VDD_IO +

0.5 V

4 Input Voltage (5 V tolerant inputs) VI_5V -0.5 7.0 V

5 Continuous Current at digit al outputs Io15 mA

6 Package power dissipation PD2.1 W

7 Storage temperature TS- 55 +125 °C

Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.

Characteristics Sym. Min. Typ.1Max. Unit

1 Operating Temperature TOP -40 25 +85 °C

2 Positive Supply Core VDD_CORE 1.71 1.8 1.89 V

3 Positive Supply I/O VDD_IO 3.0 3.3 3.6 V

4 Input Voltage (non-5 V tolerant inputs) VI_3V 0V

DD_IO V

5 Input Voltage (5 V tolerant inputs) VI_5V 05.5

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

Note 1: Typical fig ures are at 2 5°C, VDD_CORE at 1.8 V and VDD_IO at 3. 3 V and ar e for de sign aid on ly: not guar anteed an d not

subject to production testing.

Note 2: StoA = 65 Mbps with random patterns. CKo0 = 65 MHz, CKo1 = 32 MHz.

Note 3: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (Vin).

DC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated.

Characteristics Sym. Min. Typ.1Max. Unit Test Conditions

1 Core Supply Current2IDD_CORE 500 mA

2 I/O Supply Current IDD_IO 62 mA Outputs Unloaded

3 Leakage Cur r e nt IDDQ 105 uA

4 Dynamic Power Dissipation PDD 1.2 W Outputs Unloaded

5 Input High Voltage VIH 2.0 V

6 Input Low Voltage VIL 0.8 V

7 Input Leakage-input pins3IIL 5µA0≤<VI ≤VDD_IO

8 Input Leakage-bidirectional pin s IBL 5uA0≤<VI ≤VDD_IO

9 Pull-up Current IPU -33 µA Input at 0V

10 Pull-down Current IPD 33 µA Input at VDD_IO

11 Input Pin Capacitance CI3pF

12 Output High Voltage VOH 2.4 V IOH = 8 mA

13 Output Low Voltage VOL 0.4 V IOL = 8 mA

AC Electrical Characteristics1 - T iming Parameter Measurement Voltage Levels - Volt ages are with resp ect to grou nd

(VSS) unless otherwise stated.

1. Characteristics are over recommended operating conditions unless otherwise stated.

Characteristics Sym. Level Unit Test Conditions

1 CMOS Threshold VCT 0.5 VDD_IO V

2 Rise/Fall Threshold Voltage High VHM 0.7 VDD_IO V

3 Rise/Fall Threshold Voltage Low VLM 0.3 VDD_IO V

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

Note 1: Characteristics are over recommended operating conditions unless otherwise stated.

Note 2: Typical fig ures are at 2 5°C, VDD_CORE at 1.8 V and VDD_IO at 3. 3 V and ar e for de sign aid on ly: not guar anteed an d not

subject to production testing.

Note 3: When using internal APLL clock source and the CKi0 frequency is less than or equal to the data rate.

Note 4: When using input clock source CKi0 instead of the intern al APLL clock sour ce.

Note 5: When using internal APLL clock source and the CKi0 frequency is higher than or equal to twice the data rate.

Figure 11 - Frame Pulse Input and Clock Input

AC Electrical Characteristics1 - FPi and CKi Timing

No. Characteristic (Figure 11) Sym. Min. Typ.2Max. Units Notes

1FPi

Input Frame Pulse Setup Time tFPIS 3ns

2FPi

Input Frame Pulse Hold Time tFPIH 2ns

3CKi

Input Clock Period (average

value, does not consider the

effects of jitter)

tCKIP 15 15.26 15.5 ns 65.536 MHz

30 30.5 31 ns 32.768 MHz

60 61 62 ns 16.384 MHz

120 122 124 ns 8.192 MHz

4CKi

Input Clock High Time tCKIH 4ns

5CKi

Input Clock Low Time tCKIL 4ns

6CKi

Input Clock Rise/Fall Time trCKI,

tfCKI 06ns

7CKi

Input Clock Cycle to Cycle

Variation tCVC 2 ns p-p Standard rating3.

STi at 65 Mbps

4 ns p-p Standard rating3.

STi at 32 Mbps

10 ns p-p Standard rating3.

STi at 16 Mbps

20 ns p-p Standard rating3.

STi at 8 Mbps

20% of

tCKIP p-p Extended rating.

With alternate

clock source4 or

high CKi0 rate5

FPi

tFPH

tCKIH tCKIL

tFPIS tCKIP

CKi

Input Frame Boundary

trCKI tfCKI

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

Note 1: Characteristics are over recommended operating conditions unless other wise stated.

Note 2: All of these specifications refer to ST-BUS inputs and outputs with clock source set to CKi.

Note 3: Typical fig ures are at 2 5°C, VDD_CORE at 1.8 V and VDD_IO at 3. 3 V and ar e for de sign aid on ly: not guar anteed an d not

subject to production testing.

Note 4: Loads on all serial outputs set to 30 pF.

Note 5: High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge

CL.

AC Electrical Characteristics1 - Serial Data Timing2 to CKi

No. Characteristic (Figure 12) Sym. Min. Typ.3Max. Units Notes4

1CKi to CKo Propagation Delay tCKD 312nsCKo clock source =

CKi

312nsCKo

Clock source =

Internal 131 MHz

APLL output

2 STi to posedge CKi setup tSIPS 0ns

3 STi to posedge CKi hold tSIPH 7.5 ns

4 STi to negedge CKi setup tSINS 0ns

5 STi to negedge CKi hold tSINH 7.5 ns

6 Posedge CKi to Output Data Valid tSIPV 312.5nsSToA

313nsSToB

7 Negedge CKi to Output Data Valid tSINV 314nsSToA

316nsSToB

8 Posedge CKi to Output Data

tri-state tSIPZ 14 ns SToA5

15 ns SToB5

9 Negedge CKi to Output Data

tri-state tSINZ 14 ns SToA5

15 ns SToB5

10 ODE to Output Data tri-state tSOZ 10 ns SToA

CL =30pF, R

L = 1 K 5

11 ns SToB

CL = 30 pF, RL = 1 K5

11 ODE to Output Data Enable tSOE 4.5 15 ns SToA5

620nsSToB

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

Figure 12 - Serial Data Timing to CKi

AC Electrical Characteristics - Serial Data Timing1 to CKo2

No. Characteristic (Figure 13) Sym. Min. Typ.3Max. Units Notes4

1 STi to posedge CKo setup tSOPS 7.5 ns

2 STi to posedge CKo hold tSOPH 0ns

3 STi to negedge CKo setup tSONS 7.5 ns

4 STi to negedge CKo hold tSONH 0ns

5 Posedge CKo to Output Data Va li d t SOPV 15nsSToA

15nsSToB

6 Negedge CKo to Output Data Valid tSONV 15nsSToA

15nsSToB

7 Posedge CKo to Output Data tri-state tSOPZ 9nsSToA

11 ns SToB4

CKi

VALID DATA

tSIPS tSIPH

STin

tSINS tSINH

STin

STon

tSIPV

tSIPZ

STon

tSINV

tSINZ

STon

ODE

tSOZ tSOE

CKo

tCKD

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

Note 1: Data Capture points vary with respect to CKo e dge depend ing on clock rates & frac tional delay settings.

Note 2: CKo output set to in ternal clock sou rce.

Note 3: Typical fig ures are at 2 5°C, VDD_CORE at 1.8 V and VDD_IO at 3. 3 V and ar e for de sign aid on ly: not guar anteed an d not

subject to production testing.

Note 4: Loads on all serial outputs set to 30 pF.

Figure 13 - Serial Data Timing to CKo

8 Negedge CKo to Output Data tri-state tSONZ 9nsSToA

11 ns SToB4

AC Electrical Characteristics - Microproce ssor Bus Interface

No Characteristics (Figure 14, & Figure 15) Sym. Min. Typ.1Max. Units Notes

1DS Recovery tDSRE 5ns

2CS

Recovery tCSRE 0ns

3CS

asserted setup to DS asserted tCSS 0ns

4 Address, SIZ1-0, R/W setup to DS asserted tADS 0ns

5CS

hold from DS deasserted tCSH 0ns

6 Address, SIZ0-1, R/W hold from DS

deasserted tADH 0ns

AC Electrical Characteristics - Serial Data Timing1 to CKo2

No. Characteristic (Figure 13) Sym. Min. Typ.3Max. Units Notes4

CKo

VALID DATA

tSOPS tSOPH

STin

tSONS tSONH

STin

STon

tSOPV

tSOPZ

STon

tSONV

tSONZ

STon

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

Note 1: Typical fig ures are at 2 5°C, VDD_CORE at 1.8 V and VDD_IO at 3. 3 V and ar e for de sign aid on ly: not guar anteed an d not

subject to production testing.

Note 2: High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge

CL.

7 Data valid to DTA asserted on read tDSR 0nsC

L= 50 pF,

RL= 1 k2

8CS deasserted to Dat a tri-stated on read tDZ 5nsC

L= 50 pF,

RL=1k

9 Data setup to DS asserted on write tWDS 0ns

10 CS asserted to WAIT deasserted tCSWA 9ns CL = 30 pF,

RL = 1K2

11 Data hold from DTA asserted on write tDHW 0ns

12 DS asserted to WAIT Asserted tWDD 9nsC

L=50pF,

RL=1k

13 WAIT deasserted to DTA/BERR asserted

skew tAKS 10 ns CL=50pF,

RL=1k

14 DS asserted to DTA Asserted tAKD 35 155 ns Connection

Memory

50 75 ns All other

registers

15 DS deasserted to DTA Deasserted tAKH 7nsC

L=30pF,

RL=1K

16 CS deasserted to DTA tri-stated tDTHZ 13 ns CL=30pF,

RL=1K

17 CS deasserted to WAIT tri-stated tWAHZ 6ns CL = 30 pF,

RL = 1K2

18 BE or UDS/LDS skew tDSK 20 ns

19 BE or UDS/LDS to DS set- up tBEDS 0

AC Electrical Characteristics - Microproce ssor Bus Interface

No Characteristics (Figure 14, & Figure 15) Sym. Min. Typ.1Max. Units Notes

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

Figure 14 - Microprocessor Bus Interface Timing

Figure 15 - Intel Mode Timing

A18-A0

D31-D0

READ

WRITE

tCSH

tADH

tDZ

tADS

tDHW

tAKD

tWDS

tDSR

tAKH

DTA

VALID

VALID READ DATA

tCSS

(UDS,LDS)

tWDD

WAIT

tDTHZ

Hi-Z

VALID WRITE DATA

RWN,SIZ

BERR

Hi-Z

tCSRE

tAKS tWAHZ

Hi-Z

tCSWA

tDSR

(BE1-0 or

UDS, LDS)tDSK

tBEDS

ZL50075 Data Sheet

Zarlink Semiconductor Inc.

Note 1: Characteristics are over recommended operating conditions unless otherwise stated.

Note 2: Typical fig ures are at 2 5°C, VDD_CORE at 1.8 V and VDD_IO at 3. 3 V and ar e for de sign aid on ly: not guar anteed an d not

subject to production testing.

Figure 16 - IEEE 1149.1 Test Port & PWR Reset Timing

AC Electrical Characteristics1 - IEEE 1149.1 Test Port and PWR Pin Timing

No. Characteristic (Figure 16) Sym. Min. Typ.2Max. Units Notes

1 TCK Clock Period tTCKP 100 ns

2 TCK Clock Frequency tTCKF 10 MHz

3 TCK Clock Pulse Width High tTCKH 20 ns

4 TCK Clock Pulse Width Low tTCKL 20 ns

5 TMS Set-up T i me tTMSS 10 ns

6 TMS Hold Ti me tTMSH 10 ns

7 TDi Input Set-up Time tTDIS 20 ns

8 TDi Input Hold Ti me tTDIH 60 ns

9 TDo Output Delay tTDOD 20 ns CL=30pF

10 TRST pulse width tTRSTW 20 ns

11 PWR pulse width tTPWR 20 ns

tTMSH

tTMSS

tTCKL tTCKH tTCKP

tTDIS tTDIH

tTDOD

tTRSTW

TMS

TCK

TDi

TDo

TRST

tTPWR

PWR

APPRD.

ISSUE

DATE

ACN

15 Jul 03

1Previous package codes

Package Code

www.zarlink.com

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