DATA SHEET
CX74002: Tx ASIC for CDMA, PCS, and AMPS Applications
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Cellular and PCS band phones
CDMA and AMPS phones in the cellular band:
− CDMA-US
− CDMA-Japan
CDMA mode in PCS band:
− PCS-US
− PCS-Korea
FEATURES
Device controlled via serial bus interface
Low power consumption in all operating modes
Three drivers: one cellular band, two PCS for use with split-
band filters
Image reject upconverter saves two RF Surface Acoustic
Waves (SAWs) in a dual-band application
Tx power control with 90 dB dynamic range
Variable gain RF block for improved in-band SNR
200 MHz to 700 MHz VHF VCO (external tank)
VCO_ON feature to increase the talk time of the radio
Two separate Phase Lock Loop (PLL) synthesizers: dual-
loop multi-band operation, power-save mode for both
standby and lower frequency of operation
Fully programmable PLL dividers, selectable charge-pump
currents for multi-VCO applications
6 mm x 6 mm RF Land Grid Array (RFLGA™) package with
downset paddle
Tx puncture pin disables programmable portions of device
C1195
VCC_IF
Q+
Q–
VCC_IQ_MOD
I+
I–
VCC_DIV
VCO_TANK+
VCO_TANK–
IREF
POT_IREF
31
30
29
28
27
26
25
24
23
22
21
VCC_CLK
VCC_VHF
VHF_CP
VCC_UHF
SYN_LO
UHF_LO
REF
LD_OUT
UHF_CP
40
39
38
34
33
32
37
36
35
VGA_CTRL
VGA_OUT+
VGA_OUT–
VCC_MIXER_2
POT_PCS
POT_CELL
IF_IN+
IF_IN–
VCC_MIXER_1
12
13
14
18
19
20
15
16
17
PCS_DRV_OUT_B
VCC_BIAS_SEC_DRV
PCS_DRV_OUT_A
VCC_PCS_DIFF_DRV
VCC_BIAS_DIFF_DRV
CDMA_DRV_OUT
VCC_CDMA_DRV
TX_PUNCTURE
DATA
LATCH_ENABLE
CLK
1
2
3
4
5
6
7
8
9
10
11
Figure 1. CX74002 Pinout – 40-Pin LGA Package (Top View)
The CX74002 device is a single-supply, monolithic integrated
circuit. It is designed for use in dual-mode and multi-band
CDMA/AMPS/PCS cellular voice/data applications including
extensions for Japanese (CDMA-Japan) and Korea (PCS-
Korea).
The CX74002 is a highly integrated superheterodyne
transmitter that incorporates the following components:
•
•
•
•
•
In-Phase and Quadrature (I/Q) modulator – accepts the
analog I and Q current outputs from the baseband analog
processor and converts them to Intermediate Frequency (IF)
signals
Voltage Controlled Oscillator (VCO) and VHF synthesizer –
generates the LO signal for the quadrature modulators for
the cellular and the PCS bands
UHF synthesizer – controls the UHF oscillator
Variable Gain Amplifier (VGA) – provides the variable output
power for CDMA systems
Image reject upconverter and power amplifier (PA) drivers
The signal enters the chip as a baseband I/Q signal, which is
upconverted by an I/Q Quadrature Modulator. The resulting
signal is fed through a VGA to provide variable output power.
After leaving the open collector output of the VGA, the signal
enters a switch matrix. This switch matrix allows the signal to
be routed through an external filter, or it can be filtered by the
collector load and passed directly to the UHF image reject
mixer. This feature allows for dual Tx IF frequencies without
any external switching components. The image reject mixer is
internally connected to the PA driver. The mixer driver
combination has a variable gain control, which can be used to
reduce the RF gain, which improves the in-band Signal-to-
Noise Ratio (SNR) at a lower output power. The PA driver
amplifies the RF signal to the appropriate level for the desired
output power. This is then filtered by a bandpass filter and sent
to an external PA to obtain the final rated output power at the
antenna.
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Data Sheet I CX74002
UHF_LO
VCC Bias
VCC_IF
VCC_ IQ_MOD
CDMA Driver Bias
VGA_CTRL
CDMA_DRV_OUT
PCS_DRV_O UT_B
PCS_DRV_O UT_
A
IREF
PCS Driver Bias
I+
I-
Q+
Q–
VCO_T ANK+
Mux
Control Sig
VHF PLL
REF
VHF_CP
Lock Detect
UHF PLL
UHF_CP
VCC_CLK
÷2
÷4
VC
C
VC
C
Enable
DATA
CLK
TX_PUNCTURE VCC_MIXER_1
VCC_MIXER_2
101253_002
÷2, 1
SYN_LO
POT_CELL
POT_PCS
VCO_T ANK–
Figure 2. CX74002 Tx ASIC Block Diagram
VCC_VHF
VCC_UHF
UHF_CP
REF
MUX
13-BIT
REFERENCE
COUNTER
PFD2 CHARGE
PUMP 2
12-BIT
PROGRAMMABLE
COUNTER
13-BIT
PROGRAMMABLE
COUNTER
13-BIT
REFERENCE
COUNTER
PFD1 CHARGE
PUMP 1
REF.
BUFFER
BUFFER
64/65
PRESCALER
8/9
PRESCALER BUFFER
6-BIT
SWALLOW
COUNTER
3-BIT
SWALLOW
COUNTER
IF
UHF_LO
VHF_CP
VCC_CLK
101253_003
Figure 3. UHF/VHF PLL Block Diagram
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Data Sheet I CX74002
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Technical Description
AC
B
VGA_OUT IF_IN
VGA MIXER
I/Q Modulator and VGA
The I/Q modulator converts the incoming I/Q signal to an IF
signal, then feeds it directly to the VGA. The LO for the I/Q
modulator is generated by the VHF VCO and is controlled by the
VHF PLL. The I/Q modulator has two input modes: voltage
mode and current mode. The voltage mode operates with
1.0 Vp-p differential I/Q inputs. In the current mode, a DC input
current of 1.0 mA is required with ±0.5 mA signal swing. The
modulator supports direct I/Q or direct VCO modulation in the
AMPS mode. The VGA has 90 dB of dynamic range. The open
collector output requires an inductor pull-up to VCC and filtered
to reject noise that falls in the receiver band.
Switch Modes
IFout1 IFout2 A B C
0 0 1 0 1
0 1 1 1 0
1 0 0 1 1
1 1 Not
used
Not
used
Not
used
0 = Logic low
1= Logic high
0 = Open
1 = Closed
VHF, VCO, and PLL
The VHF VCO has a frequency range of 200 to 700 MHz and
requires an external tank circuit. This tank circuit can be used
to provide the analog FM modulation in the AMPS mode. The
VHF VCO is connected to an on-chip VHF PLL. The frequency of
the VCO output is divided by 2 or 4 to derive the I/Q LO signals
for the I/Q modulator. Also, an additional divide by 2/4 is
derived from the tank frequency before input to the VHF PLL
buffer.
The VHF loop of the synthesizer has a 16-bit N divider and a
13-bit R divider (see Figure 3). The charge pump has four
programmable discreet levels from 100 to 400 µA. The VHF
PLL is supplied by the VCC_DIV and VCC_VHF pins, and the
VCO output follows an internal path to the I/Q modulator. As a
result, the VHF PLL must be used for proper operation of the
device. However, the VHF PLL and the VHF VCO may be
enabled and disabled independently through the serial bus.
Figure 4. VGA/Upconverter Switching Diagram
1100 MHz for the cellular band and 1600 to 2200 MHz for the
PCS band). The upconverter can be programmed for high side
(RF = LO – IF) or low side (RF = LO + IF) operation. Using an
image reject mixer eliminates the need for an image reject
SAW filter.
The output of the mixer may be routed to either the CDMA PA
driver or the PCS PA driver. At a low output power level, RF
gain is reduced to improve the SNR of the signal. The variable
gain function is controlled by VGA_CTRL signal, which also
controls IF VGA.
Switch Matrix
To provide the maximum flexibility for multiple IF frequency
plans, there is a switch matrix between the VGA output and the
upconverter input. This switch matrix allows a direct
connection between the VGA and the upconverter and provides
two external ports for the VGA’s open collector output. An LC
tank circuit can be used as the open collector load at the
VGA_OUT pins or the IF_IN pins, or both. This load provides
adequate Rx band noise filtering without an expensive external
SAW filter.
Synthesizer
A dual UHF/VHF synthesizer has been integrated into the
CX74002. This dual, multi-band frequency synthesizer has fully
programmable dividers and selected charge pump currents for
on-chip VHF VCO and external UHF VCO operation.
The UHF synthesizer operates from 600 to 2200 MHz. It takes
its reference signal from the REF pin. The programming of the
UHF synthesizer is provided through the serial bus (see
Figure 3). This synthesizer includes a 13-bit R divider and an
18-bit N divider. The charge pump current is adjustable and
has four discrete steps between 0.8 mA and 2.7 mA. The UHF
PLL has an independent power supply from the rest of the
device. As a result, the UHF PLL can remain operational when
the remainder of the CX74002 is disabled. The Rx LO can be
also supplied from the same synthesizer, minimizing the total
component count and minimizing the total current when only
the Rx portion of the radio is in operation. If an external PLL is
desired, the UHF PLL can be disabled without adversely
affecting the operation of the CX74002.
Dual Tx IF frequencies plan (single Rx IF [SIF] frequency plan)
can be easily implemented by using two separate LC tank
circuits on the VGA_OUT pin and the IF_IN pin: one set is tuned
to the cellular band, the other set is tuned to the PCS band. An
external dual-port filter can also be used between the
VGA_OUT pin and IF_IN pin for IF filtering before the signal
goes into the upconverter. The operation of this switch matrix
is programmed by using the serial bus interface (see Figure 4).
Variable RF Gain Image Reject Upconverter
The image reject upconverter receives the IF signal from the Tx
VGA after passing through the switch matrix. The upconverter
uses an external UHF VCO, controlled by the internal UHF PLL.
The UHF LO frequency can vary from 600 to 2.2 GHz (600 to
Data Sheet I CX74002
PA Drivers
Three PA drivers are included: the CDMA driver and two PCS
drivers. Each driver takes its input from the image reject
upconverter. The driver amplifies the signal and sends it to an
external PA. A SAW filter for noise rejection should be used
between the driver and the external PA. The primary purpose
of the SAW is to reduce the Rx band noise from the signal –
this Rx band noise can leak through the duplexer and reduce
the sensitivity of the receiver. Two outputs are provided in the
PCS band to facilitate the use of a split band filter at the PCS
output.
Serial Bus
A 3-wire serial bus is provided for mode control. The serial bus
is also used to program both the VHF and the UHF PLLs.
Electrical and Mechanical Specifications
Signal pin assignments and functional pin descriptions are
described in Table 1. The absolute maximum ratings of the
CX74002 are provided in Table 2. The recommended operating
conditions are specified in Table 3 and electrical specifications
are provided in Table 4. Tables 5 through 12 provide the
control logic and timing for the CX74002. Timing diagrams are
shown in Figures 5 and 6 for the synthesizer and serial data
word, respectively.
Typical performance characteristics of the CX74002 are
illustrated in Figures 7 through 28. Figure 29 shows an
application schematic diagram. The package dimensions for
the CX74002 40-pin RFLGA are shown in Figure 30, and the
tape and reel dimensions are provided in Figure 31.
Electrostatic Discharge (ESD) Sensitivity
The CX74002 is a static-sensitive electronic device. Do not
operate or store near strong electrostatic fields. Take proper
ESD precautions. The Human Body Model (HBM) ESD
withstand threshold value, with respect to ground, is ±1.5 kV.
The HBM ESD withstand threshold value, with respect to VCC
(the positive power supply terminal), is also 1.5 kV.
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Data Sheet I CX74002
Table 1. CX74002 Pin Assignments and Signal Descriptions (1 of 3)
Pin # Name Description Equivalent Circuit
1 VCC_IF VCC for the IF VGA and the mixer input buffer
2 Q+ Q+ input. High input impedance for voltage mode; low input
impedance for current mode.
3 Q– Q– input. High input impedance for voltage mode; low input
impedance for current mode.
4 VCC_IQ_MOD VCC for the I/Q modulator. Also shared by divide-by-2/4 last
stage, all the bias blocks (Note 1).
5 I+ I+ input. High input impedance for voltage mode; low input
impedance for current mode.
6 I– I– input. High input impedance for voltage mode; low input
impedance for current mode.
7 VCC_DIV VCC for the bias circuit of the VCO, VHF PLL buffer, divide-by-
2/4 first stage (Note 2).
8 VCO_TANK+ VCO tank
9 VCO_TANK– VCO tank
–
+
10 IREF Output to the baseband chip during the current I/Q mode.
This pin is not used and left open during the voltage I/Q
mode.
11 POT_IREF External resistor (120 k typical) is required to set the current
in the PLLs and the IREF.
12 VCC_CLK VCC supplies the TCXO buffers and related circuitry. Should
be kept separate from analog supply (Note 1) (Note 2).
13 VCC_VHF VCC for the VHF Prescalar, VHF, UHF counters, and the serial
bus (Note 1) (Note 2).
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Data Sheet I CX74002
Table 1. CX74002 Pin Assignments and Signal Descriptions (2 of 3)
Pin # Name Description Equivalent Circuit
14 VHF_CP VHF charge pump output Vcc
15 REF Reference clock input from TCXO. AC coupling is required.
16 LD_OUT Lock detector is a CMOS output.
17 UHF_CP UHF charge pump Vcc
18 VCC_UHF VCC for UHF prescalar and UHF charge pump. Should be kept
separate from Tx supply (Note 1).
19 SYN_LO RF input to the UHF PLL
20 UHF_LO UHF LO input for both cellular and PCS upconverter. AC
coupling is required.
21 CLK Clock input for the 3-wire bus
22 LATCH_ENABLE Latch input enable for the 3-wire bus
23 DATA Data input for the 3-wire bus
24 TX_PUNCTURE Use to turn on/off block function in gated mode. See Table 7
for details.
25 VCC_CDMA_DRV VCC for the CDMA differential driver.
26 CDMA_DRV_OUT CDMA driver output. AC coupling is required.
27 VCC_BIAS_DIFF_DRV VCC for the TX LO chain (Note 1).
28 VCC_PCS_DIFF_DRV VCC for the PCS differential driver.
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Data Sheet I CX74002
Table 1. CX74002 Pin Assignments and Signal Descriptions (3 of 3)
Pin # Name Description Equivalent Circuit
29 PCS_DRV_OUT_A PCS DRV A is an open collector output. VCC inductor pull-up
and external matching are required.
30 VCC_BIAS_SEC_DRV VCC for bias circuit of the second stage single-ended PCS
drivers (shared by A and B)
31 PCS_DRV_OUT_B PCS DRV B is an open collector output. VCC inductor pull-up
and external matching are required.
32 POT_CELL Resistor to set the Cellular driver bias current.
33 POT_PCS Resistor to set the PCS driver bias current.
34 VCC_MIXER_2 Open collector for external tank circuit for the differential UHF
mixer. Internally connected to driver amplifier input.
35 VCC_MIXER_1 Open collector for external tank circuit for the differential UHF
mixer. Internally connected to driver amplifier input.
36 IF_IN– IF input to the mixer is one of the dual VGA outputs. (See
Figure 4.)
37 IF_IN+ IF input to the Mixer is one of the dual VGA outputs. (See
Figure 4.)
38 VGA_OUT– VGA output is one of the dual VGA outputs.
39 VGA_OUT+ VGA output is one of the dual VGA outputs.
VGA_OUT IF_IN
40 VGA_CTRL VGA control input voltage.
Note 1: Required for UHF PLL On.
Note 2: Required for VHF PLL On.
Table 2. Absolute Maximum Ratings
Parameter Symbol Minimum Typical Maximum Units
Supply voltage –0.3 5.0 V
Input voltage range –0.3 VCC V
Ambient operating
temperature
–30 +80
°C
Storage temperature –40 +125 °C
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Data Sheet I CX74002
Table 3. Recommended Operating Conditions (@ +25 °C)
Parameter Symbol Minimum Typical Maximum Units
Supply voltage 2.7 2.85 3.3 V
Logic level high 1.9 V
Logic level low 0.6 V
Supply current in cellular mode: CDMA, 8 dBm
output
103 108 mA
Supply current in cellular mode: AMPS, 11 dBm
output
107 112 mA
Supply current in 1900 MHz: PCS, 9 dBm output 122 130 mA
Supply current in sleep mode 45 70 µA
Table 4. Electrical Characteristics (1 of 4)
(TA = +25 °C, VCC = 2.85 V, PLO = –5 dBm, IS95A Input Waveform)
Parameter Symbol Test
Conditions
Minimum Typical Maximum Units
IF VCO
Frequency range for VCO 200 260 700 MHz
2nd harmonic (measured @ tank circuit) –30 –20 dBc
3rd harmonic (measured @ tank circuit) –20 –10 dBc
Phase noise @ 100 kHz offset, Fc =
260 MHz, unloaded tank Q = 20
–117 –112 dBc/Hz
Supply current 4 4.3 mA
Divide by 2/4, I/Q Modulator, VGA
Current mode interface for IF block:
Input current
Input current swing (p-p differential)
Reference current sinking into the
device
(set by external resistor)
190
1
±1.0
200
±1.4
210
mA
mA
µA
Carrier suppression
@ CDMA
@ PCS
–40
–40
–35
-35
dBc
dBc
Residual sideband suppression:
@ CDMA
@ PCS
–40
–39
–35
–35
dBc
dBc
–1 dB bandwidth 3 5 MHz
VGA Pout (with 500 load resistor):
VGA_CTRL @ 2.5 V in AMPS mode
VGA_CTRL @ 2.5 V in CDMA mode
VGA_CTRL @ 2.5 V in PCS mode
–6.0
–6.0
– 6.0
–5.0
–5.0
–5.0
dBm
dBm
dBm
VGA frequency range (–1 dB
bandwidth)
50 600 MHz
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Data Sheet I CX74002
Table 4. Electrical Characteristics (2 of 4)
(TA = +25 °C, VCC = 2.85 V, PLO = –5 dBm, IS95A Input Waveform)
Parameter Symbol Test
Conditions
Minimum Typical Maximum Units
Divide by 2/4, I/Q Modulator, VGA (continued)
Gain control input impedance 30 40 kΩ
VGA gain slope (0.5 V to 2.5 V) 42 45 48 dB/V
Gain slope variation (over any 6 dB
segment)
–3 +3 dB
In CDMA mode:
ACPR in 30 kHz band @ 0.885 MHz
offset, VGA_CTRL = 2.5 V
ACPR in 30 kHz band @ 1.98 MHz
offset, VGA_CTRL = 2.5 V
–64
–68
–62
–64
dBc
dBc
In PCS mode:
ACPR in 30 kHz band @ 1.25 MHz
offset, VGA_CTRL = 2.5 V
ACPR in 30 kHz band @ 1.98 MHz
offset, VGA_CTRL = 2.5 V
–65
–68
–62
–64
dBc
dBc
Supply current @ maximum gain 29.0 30.0 mA
Supply current @ minimum gain 20.0 20.8 mA
Cellular Upconverter and Driver
LO frequency range 600 1100 MHz
Output frequency 824 924 MHz
RF gain dynamic range: @ CDMA mode 14.0 14.5 dB
Output power in AMPS mode 11 dBm
Output power in CDMA mode 8 dBm
ACPR in 30 kHz at 885 kHz offset
@ Po = 8 dBm
–54 –50 dBc
ACPR in 30 kHz at 1.98 MHz offset
@ Po = 8 dBm
–68 –64 dBc
RF input return loss (externally
matched)
–13.5 –10 dB
LO input return loss (externally
matched)
–13.5 –10 dB
Output return loss (externally matched) –13.5 –10 dB
Rx band noise @ maximum gain and
Po = 8.0 dBm. Input to mixer block is
thermal noise of –173.89 dBm/Hz
–138 –135 dBm/Hz
LO input level –8 –5 0 dBm
LO leakage power @ driver output 8
dBm
–21 –15 dBm
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Data Sheet I CX74002
Table 4. Electrical Characteristics (3 of 4)
(TA = +25 °C, VCC = 2.85 V, PLO = –5 dBm, IS95A Input Waveform)
Parameter Symbol Test
Conditions
Minimum Typical Maximum Units
Cellular Upconverter and Driver (continued)
Supply current @ 8.0 dBm 65 68 mA
Supply current FM @ 11 dBm 70 73 mA
RF image rejection @ Po = 8 dBm –33 –20 dBc
PCS Upconverter and Driver
LO frequency range 1600 2200 MHz
Output frequency 1700 1950 MHz
RF gain dynamic range 14 14.5 dB
Output power 9 dBm
ACPR in 30 kHz @ 1.25 MHz offset @
9 dBm
–52 –50 dBc
ACPR in 30 kHz @ 1.98 MHz offset @
9 dBm
–68 –66 dBc
LO input return loss (externally
matched)
–15 –10 dB
Output return loss (externally matched) –10 –8 dB
Rx band noise @ maximum gain,
Po = 9.0 dBm. Input to block is thermal
noise of –173.89 dBm/Hz
–134 –132 dBm/Hz
LO input level –8 –5 0 dBm
LO leakage power @ driver output
9 dBm
–15 –12 dBm
supply current @ Po = –10 dBm 60 63 mA
supply current @ Po = 9 dBm 81 84 mA
RF image rejection @ Po = 9 dBm –25 –15 dBc
Dual UHF/VHF Synthesizer
Input frequency minimum range RF
IF
600
200
2200
700
MHz
MHz
Reference range 1 25 MHz
Phase detector frequency minimum
range
10 1500 kHz
Reference input sensitivity 300 500 mVp-p
Prescalar input sensitivity @ 2.2 GHz –15 +6 dBm
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Data Sheet I CX74002
Table 4. Electrical Characteristics (4 of 4)
(TA = +25 °C, VCC = 2.85 V, PLO = –5 dBm, IS95A Input Waveform)
Parameter Symbol Test
Conditions
Minimum Typical Maximum Units
Dual UHF/VHF Synthesizer (continued)
Charge pump current, RF (sel 1) 0.7 0.8 0.9 mA
Charge pump current, RF (sel 2) 1.1 1.2 1.3 mA
Charge pump current, RF (sel 3) 1.5 1.8 2.0 mA
Charge pump current, RF (sel 4) 1.8 2.7 3.0 mA
Charge pump current, IF (sel 1) 0.09 0.1 0.11 mA
Charge pump current IF (sel 2) 0.18 0.2 0.22 mA
Charge pump current IF (sel 3) 0.27 0.3 0.33 mA
Charge pump current IF (sel 4) 0.36 0.4 0.44 mA
Charge pump output voltage
compliance minimum range
0.5 Vdd – 0.5 V
Supply current, RF 4.85 mA
Supply current, IF 1.65 mA
Supply current, total 6.5 6.8 mA
Cascaded Cellular Mode
CDMA output power 8 dBm
ACPR in 30 kHz at 885 kHz offset @ 8
dBm
–52 –50 dBc
ACPR in 30 kHz at 1.98 MHz offset
@ 8 dBm
–68 –64 dBc
AMPS mode output power 11 dBm
Rx band noise @ maximum gain and
Po = 8.0 dBm
–138 –135 dBm/Hz
Cascaded PCS Mode
Maximum output power 9 dBm
ACPR in 30 kHz @ 1.25 MHz offset
@ Po = 9 dBm
–52 –50 dBc
ACPR in 30 kHz @ 1.98 MHz offset
@ Po = 9 dBm
–68 –66 dBc
Rx band noise @ maximum gain and
Po = 9.0 dBm.
–134 –132 dBm/Hz
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Data Sheet I CX74002
Table 5. Serial Bus Interface for Synthesizer Control
Bit # Function Description
0 (LSB) Control (CO) Logic 1 selects the Mode/Feature Control Register .
Logic 0 selects the PLL Rregister
1 RF/IF or LD_UHF/VHF (Note
1)
Logic 1 selects the UHF PLL and Logic 0 selects the VHF PLL
2 R/N Logic 1 selects the R divider and Logic 0 selects the N divider for the respective synthesizer
(UHF or VHF)
Charge-pump polarity Logic 1 sets the charge pump output polarity inverted and Logic 0 sets it to normal polarity. 3
BUFF_CURR_SEL1
BUFF_CURR_SEL2
See Table 9 for details.
Power down Logic 1 selects power down.
Logic 0 sets the normal operation.
4
LD inih Logic 0 enables the LD test pin. Logic 1 disables it.
CP SEL1 CP SEL2 UHF CP CURRENT VHF CP CURRENT 5:6 CP Sel 1, CP Sel 2
Bit 5
0
1
0
1
Bit 6
0
0
1
1
0.8 mA
1.2mA
1.8 mA
2.7 mA
0.1 mA
0.2 mA
0.3 mA
0.4 mA
7 Three-state CP Logic 1 three-states the charge-pump output. Logic 0 sets it to normal.
LD MODE1
Bit 8
LD MODE2
Bit 9 LD MODE
0 0 Logic 00 muliplexes the ANDed lock detect of both PLL to
LD output
0 1 Logic 01 multiplexes the selected PLL Rdiv output to LD
output
1 0 Logic 10 multiplexes the selected PLL Ndiv output to LD
output
8:9 LD Mode 1, LD Mode 2
1 1 Logic 11 multiplexes the selected PLL lock det output to
LD output
21 DIV2_SW See Table 10 for details.
22 CDMA_BIAS See Table 11 for details.
5:22 N Divider This 18-bit word is loaded into N counter latch; 16-bit word for VHF N counter.
10:22 R Divider This 13-bit word is loaded into R counter latch
Key: 0 = low
1 = high
Note 1: Explained in Table 7.
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Data Sheet I CX74002
Table 6. Serial Bus Assignment
0 (LSB) CO 0 0 0 0 1
1 RF/IF 1 1 0 0 LD_UHF/VHF
2 R/N 0 1 0 1 X
3 Buf_curr_sel2 CP Polarity Buf_curr_sel1 CP Polarity PCS A/B
4 Power-down LD inih Power-down LD inih IFout1
5 CP Sel 1 CP Sel 1 VCO ON
6 CP Sel 2 CP Sel 2 IDLE
7 CP three-state CP three-state Cell/PCS
8 LD Mode 1 LD Mode 1 FM/CDMA
9 LD Mode 2 LD Mode 2 Divide 2/4
10 Both pcs_drv
11 FM Dig/Ana
12 Input Range b1
13 USB/LSB
14 Iref 1
15 IFout2
16 Bias Set 1
17 Bias Set 2
18 VGA Range
19 Block Control 1
20
16-Bit N Divider
(IF)
Block Control 2
21 DIV2_SW V/C Interface
22
18-Bit N Divider
(RF)
13-Bit R Divider
(RF)
CDMA_BIAS
13-Bit R Divider
(IF)
Rx_sif
Key: 0 = low
1 = high
X = N/A
Note: See Table 7 for Mode/Feature Logic
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Data Sheet I CX74002
Table 7. Mode/Feature Control Logic (1 of 2)
Mode Description
LD_UHF/VHF = 1, UHF
LD_UHF/VHF = 0, VHF
Selects the LD pin to be connected to the UHF or VHF LD functions
PCS A/B = 0, LOW Band Output (PCS Output B)
PCS A/B = 1, HIGH Band Output (PCS Output A)
PCS A/B controls the switching of the appropriate driver output for the lower
or higher part of the PCS band.
VCO_ON = 0, VCO = OFF
VCO_ON = 1, VCO = ON
VCO_ON controls the VHF VCO turn-on switching. VCO_ON acts
independently of IDLE bit
IDLE = 0, TX = OFF,
IDLE = 1, TX = ON
IDLE mode: When the handset is only receiving pages from the base station
and the transmitter is completely shut OFF
Cell/PCS = 0, CDMA Mode (Cellular)
Cell/PCS = 1, CDMA Mode (PCS)
Cell/PCS switches between cellular and PCS band.
FM/CDMA = 0, AMPS Mode
FM/CDMA = 1, CDMA Mode
FM/CDMA is used to select the operating mode of the transmitter in AMPS
and CDMA 800 MHz
Note: When FM/CDMA = 0, the device is in AMPS mode, independent of
Cell/PCS
Divby2/4 = 0, Divide by 2
Divby2/4 = 1, Divide by 4
Divby2/4 controls the divide ratio for the VHF oscillator
Both pcs_drv = 0, Only one PCS driver (either A or B) is ON,
Both pcs_drv = 1, Both PCS drivers are ON
Both pcs_drv controls the switching of one or both of the PCS drivers
FM Dig/Ana = 0, Analog IF VCO modulation
FM Dig/Ana = 1, FM Digital I/Q modulation
FM Dig/Ana to switch between FM Digital (I/Q) modulation and Analog (IF
VCO) modulation options in FM mode.
USB/LSB = 0, Lower Side-Band injection
USB/LSB = 1, Upper Side-Band Injection
USB/LSB controls either the upper sideband (USB) or lower sideband (LSB)
injection for the Local Oscillator (LO)
Iref 1 = 0, No Reference Current
Iref 1 = 1, Reference Current = 200 µA (Sink)
Iref 1 provides the reference bias current for the baseband device.
Note: Iref 2 is not used in this design. The 200 µA current can be adjusted
by external resistor value.
IFout1 = 0 and IFout2 = 0,
Provide a 2-port filter between VGA output and Mixer input
pins and VCC for VGA at VGA output pins,
IFout1 = 0 and IFout2 = 1,
Provide a 1-port tank and VCC for VGA at VGA output pins
IFout1 = 1 and IFout2 = 0,
Provide a 1-port tank and VCC for VGA at Mixer input pins
IFout1 = 1 and IFout2 = 1,
All switches disconnected
Refer to Figure 4.
IFout1 and IFout2 control the mode of operation between VGA output and
Mixer input.
Bias set 1 = 0 and Bias set 2 = 0, Highest current
Bias set 1 = 0 and Bias set 2 = 1, Decrease by 15%
Bias set 1 = 1 and Bias set 2 = 0, Decrease by 35%
Bias set 1 = 1 and Bias set 2 = 1, Decrease by 57%
Bias set 1 and Bias set 2 provide adjustment to the mixer core currents in
the particular mode of operation.
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Data Sheet I CX74002
Table 7. Mode/Feature Control Logic (2 of 2)
Mode Description
Block Control 1 = 0, Block Control 2 = 0,
VGA and Driver are punctured by TX puncture signal
Block Control 1 = 0, Block Control 2 = 1,
VGA, Mixer and Driver are punctured by TX puncture signal
Block Control 1 = 1, Block Control 2 = 0,
Iref, I/Q mod, VGA, Mixer, and Driver are puncture by TX
puncture signal
Block Control 1 = 1, Block Control 2 = 1
Driver is punctured by TX puncture signal
Block Control 1 and Block Control 2 configure the state of the
TX_PUNCTURE hardware pin. Depending on the combinations selected, the
different blocks are enabled/disabled in the TX chip.
Note: UHF PLL, IF VCO, and I/Q modulator are ON under all these conditions.
V/C Interface = 0, Current Interface
V/C Interface = 1, Voltage Interface
V/C Interface controls the voltage or current interface for the I/Q modulator.
Rx_sif = 0, 130 MHz IF for both Cellular and PCS bands.
Rx_sif = 1, 230 MHz IF for cellular and 260 MHz IF for PCS
bands
Rx_sif controls the IF polyphase network
Key: 0 = low
1 = high
X = N/A
Table 8. Voltage Regulator Programming
Input
Range_b1
VGA Range Voltage
Regulator Bias
0 0 1.8 V
0 1 2.0 V
1 0 2.2 V
1 1 2.4 V
Table 9. UHF LO Buffer Programming
Buf_curr_sel1 Buf_curr_sel2 UHF LO 1st
Buffer Bias
0 0 11% less current
0 1 Nominal current
1 0
11% more
current
1 1
22% more
current
Table 10. Divide by 2 Before the VHF Prescalar
Div2_sw Divider 2
on/off
0 Off
1 On
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101253B [978] 241-7000 I FAX [978] 241-7906 I SALES@SKYWORKSINC.COM I WWW.SKYWORKSINC.COM JANUARY 31, 2003
Data Sheet I CX74002
Table 11. Cellular Driver Biasing
CDMA_BIAS Cellular Bias
High/Low
0 High
1 Low
Table 12. Synthesizer Timing
Parameter Test
Conditions
Minimum Typical Maximum Units
High level digital I/O voltage 0.7 VDD V
Low level digital I/O voltage 0.3 VDD V
Serial clock HIGH time (tCkH) 40 ns
Serial clock LOW time (tCKL) 40 ns
Data setup time to clock rising edge
(tDSU)
40 ns
Data hold time to clock rising edge
(tDHD)
40 ns
LE pPulse width (tLEW) 40 ns
Clock falling edge to LE rising edge
(tCLE)
40 ns
LE falling edge to clock rising edge
(tLEC)
40 ns
D20 D19 D18
DATA
NOTE: LE MUST BE HELD HIGH WHEN THE BUS IS INACTIVE
t
LEC
t
CKL
t
CKH
CLOCK
LE
t
DSU
t
DHD
t
CLE
t
LEW
D0 R/N RF/IF C0 = 0
Figure 5. Synthesizer Timing Diagram
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Data Sheet I CX74002
DATA
NOTE: LE MUST BE HELD HIGH WHEN THE BUS IS INACTIVE
t
LEC
t
CKL
t
CKH
CLOCK
LE
t
DSU
WORD 1
t
DHD
t
CLE
t
LEW
Figure 6. Serial Data Word Format
-70
-65
-60
-55
-50
-45
-40
-35
012345678
Pout (dBm)
ACPR (dBc)
-30°C
25°C
80°C
-70
-65
-60
-55
-50
-45
-40
-35
012345678
Pout (dBm)
ACPR (dBc)
824.04MHz
836.52MHz
848.37MHz
Figure 7. CELLULAR ACPR vs. Pout Over Temperature.
Frequency = 836.52 MHz @ ± 885 kHz offset Vcc = 3.0
Figure 8. CELLULAR ACPR @ ± 885 kHz offset vs. Pout Over
Frequency. Vcc = 3.0 V Temp = +25 °C
-70
-65
-60
-55
-50
-45
-40
-35
0 123 45678
Pout ( dBm)
2.7V
3.0V
3.3V
-50
-45
-40
-35
-30
-25
012345678
Pout (dBm)
Image Reejction (dBc)
-30°C
25°C
80°C
Figure 9. CELLULAR ACPR @ ± 885 kHz offset vs. Pout Over Vcc.
Frequency = 836.5 MHz Temp = +25 °C
Figure 10. CELLULAR Image Rejection vs. Pout Over
Temperature. Frequency = 836.5 MHz and Vcc = 3.0 V
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101253B [978] 241-7000 I FAX [978] 241-7906 I SALES@SKYWORKSINC.COM I WWW.SKYWORKSINC.COM JANUARY 31, 2003
Data Sheet I CX74002
-50
-45
-40
-35
-30
-25
012345678
Pout (dBm)
Image Rejection(dBc)
2.7V
3.0V
3.3V
-35
-30
-25
-20
-15
-10
012345678
Pout (dBm)
LO Leakage (dBm)
-30°C
25°C
80°C
Figure 11. CELLULAR Image Rejection vs. Pout Over Vcc.
Frequency = 836.5 MHz and Temp = +25 °C
Figure 12. CELLULAR LO Leakage vs. Pout Over Temperature.
Frequency = 836.5 MHz Vcc = 3.0 V
-40
-35
-30
-25
-20
-15
-10
012345678
Pout (dBm)
LO Leakage (dBm)
2.7V
3.0V
3.3V
70
80
90
100
110
120
012345678
Pout (dBm)
Current (mA)
2.7V
3.0V
3.3V
Figure 13. CELLULAR LO Leakage vs. Pout Over Vcc.
Frequency = 836.5 MHz Temp +25 °C
Figure 14. CELLULAR Current vs. Pout Over Vcc.
Frequency = 836.5 MHz, Temp = +25 °C, and RFGC = 2.5 V
-70
-65
-60
-55
-50
-45
-40
-35
0123456789
Pout (dBm)
ACPR (dBc)
-30°C
25°C
80°C
-70
-65
-60
-55
-50
-45
-40
-35
-113579
Pout (dBm)
ACPR (dBc)
1.85GHz
1.88GHz
1.91GHz
Figure 15. PCS ACPR @ ± 1.25 MHz offset vs. Pout Over
Temperature. Frequency = 1.88 GHz and Vcc = 3.0 V
Figure 16. PCS ACPR @ ± 1.25 MHz offset vs. Pout Over
Frequency. Vcc = 3.0 V Temp +25 °C
18 Skyworks Solutions, Inc., Proprietary and Confidential
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Data Sheet I CX74002
-70
-65
-60
-55
-50
-45
-40
-35
0246810
Pout (dBm)
ACPR (dBc)
2.7V
3.0V
3.3V
-45
-40
-35
-30
-25
-20
0123456789
Pout (dBm)
Image Rejection (dBc)
-30°C
25°C
80°C
Figure 17. CS ACPR @ ± 1.25 MHz offset vs. Pout Over Vcc.
Frequency = 1.88 GHz Temp = +25 °C
Figure 18. PCS Image Rejection vs. Pout Over Temperature.
Frequency = 1.88 GHz and Vcc = 3.0 V
-45
-40
-35
-30
-25
-20
0246810
Pout (dBm)
Image Rejection (dBc)
2.7V
3.0V
3.3V
-25
-20
-15
-10
-5
0246810
Pout (dBm)
LO Leakage (dBm)
-30°C
25°C
80°C
Figure 19. PCS Image Rejection vs. Pout Over Vcc.
Frequency = 1.88 GHz Temp = +25 °C
Figure 20. PCS LO Leakage vs. Pout Over Temperature.
Frequency = 1.88 GHz Vcc = 3.0 V
-25
-20
-15
-10
-5
0246810
Pout (dBm)
LO Leakage (dBm)
2.7V
3.0V
3.3V
80
90
100
110
120
130
140
150
0246810
Pout (dBm)
Current (mA)
2.7V
3.0V
3.3V
Figure 21. PCS LO Leakage vs. Pout Over Vcc.
Frequency = 1.88 GHz Temp = +25 °C Figure 22. PCS Current vs. Pout Over Vcc.
Frequency = 1.88 GHz Vcc = 3.0 V Temp = +25 °C
Skyworks Solutions, Inc., Proprietary and Confidential 19
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Data Sheet I CX74002
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70
80
90
100
110
120
130
0.5 1.0 1.5 2.0 2.5
VGA Control Voltage (V)
Icc (mA)
2.7V
3.0V
3.3V
50
60
70
80
90
100
110
120
130
140
0.5 1.0 1.5 2.0 2.5
VGA Control Votlage (V)
Iccc (mA)
-30°C
25°C
80°C
Figure 23. AMPS Current vs. VGA Control Voltage over Vcc @
836.52 MHz +25°C RFGC = 2.5V
Figure 24. AMPS Current vs. VGA Control Voltage over Temp @
836.52 MHz 3V RFGC = 2.5V
70
75
80
85
90
95
100
105
110
0.5 1.0 1.5 2.0 2.5
VGA Control Voltage (V)
Icc (mA)
2.7V
3.0V
3.3V
70
75
80
85
90
95
100
105
110
0.5 1.0 1.5 2.0 2.5
VGA Control Voltage (V)
Icc (mA)
-30°C
25°C
80°C
Figure 25. CELLULAR Current vs. VGA Control Voltage over Vcc
@ 836.52 MHz +25°C
Figure 26. CELLULAR Current vs. VGA Control Voltage over Temp
@ 836.52 MHz 3V.
80
85
90
95
100
105
110
115
120
125
0.5 1.0 1.5 2.0 2.5
VGA Control Votlage (V)
Icc (mA)
2.7V
3.0V
3.3V
70
75
80
85
90
95
100
105
110
115
120
125
130
0.5 1.0 1.5 2.0 2.5
VGA Control Voltage (V)
Icc (mA)
-30°C
25°C
80°C
Figure 27. PCS Current vs. VGA Control Voltage over Vcc
@ 1.88 GHz +25°C
Figure 28. PCS Current vs. VGA Control Voltage over Temp
@ 1.88 GHz 3V
Data Sheet I CX74002
NOTES:
1.COMPO
NEN
TVAL
UESMAYCHAN
GE
2.DNI=DONOTINST
AL
L
PL
L_VC
C
C100
220pF
C101
1000pF
C102
1.0µF
R39
5.1
R53
10K
C
Cathode1An
ode1
Cathode2An
ode2
R52
10K
C107
1000pF
C108
1000pF
A2
A1
C2
C1
C109
33pF
C110
33pF
U6
BBY5
3-03W
VC
C_IF
Q+
Q–
PC
S_
DRV_
OUT_B
VC
C_BIAS_
SEC
_DRV
PC
S_
DRV_
OUT_A
VC
C_PC
S_
DIFF_
DRV
VC
C_BIAS_
DIFF_DRV
CDMA_
DRV_
OUT
R55120K
PO
T_IREF
U7
C105
DNI
VC
C_IQ_MO
D
I+
VC
C_DIV
VC
O_TAN
K+
VC
O_TAN
K–
IREF
I–
TCXO
R129
0.01µF
R67
1K
TX_
PU
NCTURE
DAT
A
LATCH_EN
ABL
E
CLK
VC
C_CDMA_
DRV
C136
33pF
C154
33pF
C144
33pF
C160
15pF
C168
33pF
C167
1.0µF
C177
8.2pF
C170
33pF
C138
33µF
R79
0TX_
VC
C
TX_
VC
C
R850
R970
TX_
VC
C
R940
TX_
VC
C
R720
C148
0.1µF
C147
8.2pF
L38
27nH
C145
0.1µF
C146
8.2pF
L37
27nH
L43
4.7nH
C173
33pF
C174
DNI
IN25OUT
16
34
U11
LA67F
L40
0
C16133pF
C164
DNI
L39
0
C15333pF
C156
DNI
IN_1
IN_2
OUT_1
1
3
7
5
2
46
8
U10
B4
214
TX_
VC
C
OUT_2
CEL
L_OUT
PC
S_
BAN
D_CNTL2
VC
ONT2
OUT2
OUT1
GND
VC
ONT1
IN
C163
33pF
C152
33pF
C15733pF
R811K
R841KPC
S_
BAN
D_CNTL
1
PC
S_
OUT
U9
UPG
152TA
R822K
R80500
R77500
R73500
SYN
_CLK
SYN
_EN
_TX
SYN
_DAT
A
PA_
ON
R740
C140
0.022µF
C139
1800µF
C142
0.027µF
R75
2.74K
C141
0.22µF
R5810
C117
1000pF
TX_
VC
C
TXQ
+
TXQ
–
R560
R570
R500
R510
C114
DNI
C113
DNI
R4810
C112
1000pF
PL
L_VC
C
R3810
C104
1000pF
TX_
VC
C
TXI
+
TXI
–
R460
R470
R400
R410
C106
DNI
C159
33pF
C155
33pF
1
34
6
25
CEL
LULAR
RFSAW
R49DNI
IREF
C125
220pF
C128
220pF
R64
4.7k
R634.7k
C126
6.2nF
+C127
560pF
C1161.0µF
C1194.7µF
+
C120
1000pF
R5410
PL
L_VC
C
R5910
PL
L_VC
C
PL
L_VC
C
C131
4.7µF
C130
33pF
IF_IN–
VG
A_
CTRL
IF_IN+
VC
C_MI
XER
_1
VC
C_MI
XER
_2
PO
T_PC
S
PO
T_CEL
L
VG
A_
OUT+
VG
A_
OUT–
1
9
2
3
4
5
6
7
8
10
11
+
VC
C_CLK
VC
C_VH
F
VH
F_CP
REF
LD
_OUT
UHF_CP
VC
C_UHF
SYN
_LO
UHF_LO
31
23
30
29
28
27
26
25
24
22
21
CX74002
C118
1.0µF
C1151000pF
R13
10K
BBY5
3-03W
C137
1.0µF
BAN
D_SEL
EC
T
R12
10K
R86
0
C135
33pF
R11
1K
PC
S
SPL
IT-BAN
D
FILTER
RFSW
ITCH
50ohms
C1588.2pF
L20
3.3
nH
PO
W
ER
R83
50
DNI
C149
4.7µF
+
CRL
GND1GND2
OUT
1
2
34
6
5
PL
L_VC
C
R7810
C143
1000pF
U8
VC
-3R0A2
3-0967/1750
BAN
D_SEL
UHFVC
O
R90
DNI
R87
100
RX_
LO
R89
DNI
C129
2.2 pF
BAN
D_SEL
EC
T
C109
1.5pF
C150
1.0µF
LOCK
C178
22pF
C108
6.2pF
C103
6.2pF
L30(0603)
7.5nH,2%
L31(0
603)
7.5nH,2%
R601K
TX_
AG
C_AD
J
C122
4700pF
TX_
VC
CR6110
L36
3.9nH
L34
3.9nH
L35
6.8nH
C133
33pF
C134
DNI
TX_
VC
C
R68
10
C132
1.2pF
C121
33pF
C182
33pF
TX_
VC
C
R70
1.4K
R69
1.8K
L32(0603)
0.15µH
L33 (0603)
27 nH, 2 %
C124
1.8 p
F
C123
22pF
L33 (0603)
27 nH, 2 %
C180
DNI
C181
18pF
C179
18pF
L32(0603)
0.15µH
PLL_VCC
12
15
16
17
18
19
20
13
14
37
36
35
34
33
32
39
38
40
1pF
L30
3.3 nH
101253_004
Figure 29. CX74002 Schematic Diagram
Skyworks Solutions, Inc., Proprietary and Confidential 21
101253B [978] 241-7000 I FAX [978] 241-7906 I SALES@SKYWORKSINC.COM I WWW.SKYWORKSINC.COM JANUARY 31, 2003
C1235
All dimensions are in millimeters
Pin #1
6.04 ± 0.05
0.500
To metal pad edge
1.20 ± 0.10
0.30 ± 0.05
2.980
2.980
To metal
pad edge
R1.500
Solder Mask
Pin #1
Downset Paddle
Detail A
Mold
Top View Bottom View Detail A
Substrate
6.04 ± 0.05
5.200
Solder Mask
Exposed Metal
0.38 ±0.05
0.300 ±0.020
0.400 ±0.050
Package Edge
0.040 REF
Figure 30. Package Dimensions – 40-Pin RFLGA (6 x 6 mm) Package
C1222
Notes:
1. Carrier tape: black conductive polycarbonate.
2. Cover tape material: transparent conductive PSA.
3. Cover tape size: 9.3 mm width
4. All dimensions are in millimeters
AB
8.00 ± 0.10
Pin #1
indicator
4.00 ± 0.10 1.50 ± 0.10
2.00 ± 0.10
1.75 ± 0.10
12.00 ± 0.10
1.50 ± 0.25
0.292 ± 0.02
1.59 ± 0.10
6.35 ± 0.10
8o Max 7o Max
6.35 ± 0.10
5.50 ± 0.10
A
B
B
A
Figure 31. Tape and Reel Dimensions – 40-Pin RFLGA (6 x 6) Package
Ordering Information
Model Name Manufacturing Part
Number
Product Revision
CX74002, Current Mode,
Dual Band – Tri-Mode CX74002-13
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