14-Bit, 210 MSPS TxDAC®
D/A Converter
Data Sheet
AD9744
Rev. C Document Feedback
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FEATURES
High performance member of pin-compatible
TxDAC product family
Excellent spurious-free dynamic range performance
SFDR to Nyquist
83 dBc at 5 MHz output
80 dBc at 10 MHz output
73 dBc at 20 MHz output
SNR at 5 MHz output, 125 MSPS: 77 dB
Twos complement or straight binary data format
Differential current outputs: 2 mA to 20 mA
Power dissipation: 135 mW at 3.3 V
Power-down mode: 15 mW at 3.3 V
On-chip 1.2 V reference
CMOS-compatible digital interface
28-lead SOIC, 28-lead TSSOP, and 32-lead LFCSP packages
Edge-triggered latches
APPLICATIONS
Wideband communication transmit channel
Direct IFs
Base stations
Wireless local loops
Digital radio links
Direct digital synthesis (DDS)
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
GENERAL DESCRIPTION
The AD97441 is a 14-bit resolution, wideband, third generation
member of the TxDAC series of high performance, low power
CMOS digital-to-analog converters (DACs). The TxDAC family,
consisting of pin-compatible 8-, 10-, 12-, and 14-bit DACs, is
specifically optimized for the transmit signal path of communi-
cation systems. All of the devices share the same interface options,
small outline package, and pinout, providing an upward or
downward component selection path based on performance,
resolution, and cost. The AD9744 offers exceptional ac and dc
performance while supporting update rates up to 210 MSPS.
The AD9744’s low power dissipation makes it well suited for
portable and low power applications. Its power dissipation can
be further reduced to a mere 60 mW with a slight degradation
in performance by lowering the full-scale current output. Also,
a power-down mode reduces the standby power dissipation to
approximately 15 mW. A segmented current source architecture
is combined with a proprietary switching technique to reduce
spurious components and enhance dynamic performance.
Edge-triggered input latches and a 1.2 V temperature compensated
band gap reference have been integrated to provide a complete
monolithic DAC solution. The digital inputs support 3 V
CMOS logic families.
PRODUCT HIGHLIGHTS
1. The AD9744 is the 14-bit member of the pin compatible TxDAC
family, which offers excellent INL and DNL performance.
2. Data input supports twos complement or straight binary data
coding.
3. High speed, single-ended CMOS clock input supports
210 MSPS conversion rate.
4. Low power: Complete CMOS DAC function operates on
135 mW from a 2.7 V to 3.6 V single supply. The DAC full-
scale current can be reduced for lower power operation, and a
sleep mode is provided for low power idle periods.
5. On-chip voltage reference: The AD9744 includes a 1.2 V
temperature compensated band gap voltage reference.
6. Industry-standard 28-lead SOIC, 28-lead TSSOP, and 32-lead
LFCSP packages.
1Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519.
1.2V REF
REFLO
3.3V
RSET
0.1µF
CLOCK
SLEEP
02913-001
REFIO
FS ADJ
DVDD
DCOM
CLOCK
DIGITAL DATA INPUTS (DB13–DB0)
150pF
3.3V
AVDD ACOM
AD9744
CURRENT
SOURCE
ARRAY
IOUTA
IOUTB
MODE
LSB
SWITCHES
SEGMENTED
SWITCHES
LATCHES
AD9744 Data Sheet
Rev. C | Page 2 of 32
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
DC Specifications ......................................................................... 3
Dynamic Specifications ............................................................... 4
Digital Specifications ................................................................... 5
Absolute Maximum Ratings ............................................................ 6
Thermal Characteristics .............................................................. 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Ter mi no lo g y .................................................................................... 12
Functional Description .................................................................. 13
Reference Operation .................................................................. 13
Reference Control Amplifier .................................................... 13
DAC Transfer Function ............................................................. 14
Analog Outputs .......................................................................... 14
Digital Inputs .............................................................................. 15
Clock Input .................................................................................. 15
DAC Timing ................................................................................ 16
Power Dissipation....................................................................... 16
Applying the AD9744 ................................................................ 17
Differential Coupling Using a Transformer ............................ 17
Differential Coupling Using an Op Amp ................................ 17
Single-Ended Unbuffered Voltage Output .............................. 18
Single-Ended, Buffered Voltage Output Configuration ........ 18
Power and Grounding Considerations, Power Supply
Rejection ...................................................................................... 18
Evaluation Board ............................................................................ 20
General Description ................................................................... 20
Outline Dimensions ....................................................................... 30
Ordering Guide ............................................................................... 31
REVISION HISTORY
12/13—Rev. B to Rev. C
Added Table 5; Renumbered Sequentially .................................... 6
Added Exposed Pad Note to Figure 4 and Table 6, Pin
Configurations and Function Descriptions Section .................... 7
Moved Terminology Section ......................................................... 12
Updated Outline Dimensions ....................................................... 30
Changes to Ordering Guide .......................................................... 31
4/05—Rev. A to Rev. B
Updated Format .................................................................. Universal
Changes to General Description .................................................... 1
Changes to Product Highlights ....................................................... 1
Changes to DC Specifications ......................................................... 3
Changes to Dynamic Specifications ............................................... 4
Changes to Pin Function Description ........................................... 7
Changes to Figure 6 and Figure 9 ................................................... 9
Inserted New Figure 10; Renumbered Sequentially .................... 9
Changes to Figure 12, Figure 13, Figure 14, and Figure 15 ...... 10
Changes to Figure 22 Caption ...................................................... 11
Inserted New Figure 23; Renumbered Sequentially .................. 11
Changes to Functional Description ............................................. 13
Changes to Reference Operation Section .................................... 13
Added Figure 25; Renumbered Sequentially .............................. 13
Changes to Digital Inputs Section ................................................ 15
Changes to Figure 31 and Figure 32............................................. 16
Updated Outline Dimensions ....................................................... 30
Changes to Ordering Guide .......................................................... 31
5/03—Rev. 0 to Re v. A
Added 32-Lead LFCSP Package ....................................... Universal
Edits to Features ................................................................................. 1
Edits to Product Highlights .............................................................. 1
Edits to DC Specifications ................................................................ 2
Edits to Dynamic Specifications ...................................................... 3
Edits to Digital Specifications .......................................................... 4
Edits to Absolute Maximum Ratings .............................................. 5
Edits to Thermal Characteristics ..................................................... 5
Edits to Ordering Guide ................................................................... 5
Edits to Pin Configuration ............................................................... 6
Edits to Pin Function Descriptions ................................................. 6
Edits to Figure 2 ................................................................................. 7
Replaced TPCs 1, 4, 7, and 8 ............................................................ 8
Edits to Figure 3 .............................................................................. 10
Edits to Functional Description ................................................... 10
Added Clock Input Section ........................................................... 12
Added Figure 7 ............................................................................... 12
Edits to DAC Timing Section ....................................................... 12
Edits to Sleep Mode Operation Section....................................... 13
Edits to Power Dissipation Section .............................................. 13
Renumbered Figures 8 to Figure 26 ............................................. 13
Added Figure 11 ............................................................................. 13
Added Figure 27 to Figure 35 ....................................................... 21
Updated Outline Dimensions ....................................................... 26
Data Sheet AD9744
Rev. C | Page 3 of 32
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit
RESOLUTION 14 Bits
DC ACCURACY1
Integral Linearity Error (INL) −5 ±0.8 +5 LSB
Differential Nonlinearity (DNL) −3 ±0.5 +3 LSB
ANALOG OUTPUT
Offset Error −0.02 +0.02 % of FSR
Gain Error (Without Internal Reference) −0.5 ±0.1 +0.5 % of FSR
Gain Error (With Internal Reference) −0.5 ±0.1 +0.5 % of FSR
Full-Scale Output Current2 2 20 mA
Output Compliance Range −1 +1.25 V
Output Resistance 100 kΩ
Output Capacitance 5 pF
REFERENCE OUTPUT
Reference Voltage 1.14 1.20 1.26 V
Reference Output Current3 100 nA
REFERENCE INPUT
Input Compliance Range 0.1 1.25 V
Reference Input Resistance (External Reference) 7 kΩ
Small Signal Bandwidth 0.5 MHz
TEMPERATURE COEFFICIENTS
Offset Drift 0 ppm of FSR/°C
Gain Drift (Without Internal Reference) ±50 ppm of FSR/°C
Gain Drift (With Internal Reference) ±100 ppm of FSR/°C
Reference Voltage Drift ±50 ppm/°C
POWER SUPPLY
Supply Voltages
AVDD 2.7 3.3 3.6 V
DVDD 2.7 3.3 3.6 V
CLKVDD 2.7 3.3 3.6 V
Analog Supply Current (IAVDD) 33 36 mA
Digital Supply Current (IDVDD)4 8 9 mA
Clock Supply Current (I
CLKVDD
)
5
6
Supply Current Sleep Mode (IAVDD) 5 6 mA
Power Dissipation4 135 145 mW
Power Dissipation5 145 mW
Power Supply Rejection Ratio—AVDD6 −1 +1 % of FSR/V
Power Supply Rejection Ratio—DVDD6 −0.04 +0.04 % of FSR/V
OPERATING RANGE −40 +85 °C
1 Measured at IOUTA, driving a virtual ground.
2 Nominal full-scale current, IOUTFS, is 32 times the IREF current.
3 An external buffer amplifier with input bias current <100 nA should be used to drive any external load.
4 Measured at fCLOCK = 25 MSPS and fOUT = 1 MHz.
5 Measured as unbuffered voltage output with IOUTFS = 20 mA and 50 Ω RLOAD at IOUTA and IOUTB, fCLOCK = 100 MSPS and fOUT = 40 MHz.
6 ±5% power supply variation.
AD9744 Data Sheet
Rev. C | Page 4 of 32
DYNAMIC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly
terminated, unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit
DYNAMIC PERFORMANCE
Maximum Output Update Rate (fCLOCK) 210 MSPS
Output Settling Time (tST) (to 0.1%)1 11 ns
Output Propagation Delay (tPD) 1 ns
Glitch Impulse
5
pV-s
Output Rise Time (10% to 90%)1 2.5 ns
Output Fall Time (10% to 90%)1 2.5 ns
Output Noise (IOUTFS = 20 mA)2 50 pA/√Hz
Output Noise (IOUTFS = 2 mA)2 30 pA/√Hz
Noise Spectral Density3 −155 dBm/Hz
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
fCLOCK = 25 MSPS; fOUT = 1.00 MHz
0 dBFS Output 77 90 dBc
−6 dBFS Output 87 dBc
−12 dBFS Output 82 dBc
−18 dBFS Output 82 dBc
fCLOCK = 65 MSPS; fOUT = 1.00 MHz 85 dBc
f
CLOCK
= 65 MSPS; f
OUT
= 2.51 MHz
84
dBc
fCLOCK = 65 MSPS; fOUT = 10 MHz 80 dBc
fCLOCK = 65 MSPS; fOUT = 15 MHz 75 dBc
fCLOCK = 65 MSPS; fOUT = 25 MHz 74 dBc
fCLOCK = 165 MSPS; fOUT = 21 MHz 73 dBc
fCLOCK = 165 MSPS; fOUT = 41 MHz 60 dBc
f
CLOCK
= 210 MSPS; f
OUT
= 41 MHz
68
dBc
fCLOCK = 210 MSPS; fOUT = 69 MHz 64 dBc
Spurious-Free Dynamic Range Within a Window
fCLOCK = 25 MSPS; fOUT = 1.00 MHz; 2 MHz Span 84 90 dBc
fCLOCK = 50 MSPS; fOUT = 5.02 MHz; 2 MHz Span 90 dBc
fCLOCK = 65 MSPS; fOUT = 5.03 MHz; 2.5 MHz Span 87 dBc
fCLOCK = 125 MSPS; fOUT = 5.04 MHz; 4 MHz Span 87 dBc
Total Harmonic Distortion
fCLOCK = 25 MSPS; fOUT = 1.00 MHz −86 −77 dBc
fCLOCK = 50 MSPS; fOUT = 2.00 MHz −77 dBc
fCLOCK = 65 MSPS; fOUT = 2.00 MHz −77 dBc
f
CLOCK
= 125 MSPS; f
OUT
= 2.00 MHz
−77
dBc
Signal-to-Noise Ratio
fCLOCK = 65 MSPS; fOUT = 5 MHz; IOUTFS = 20 mA 82 dB
fCLOCK = 65 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA 88 dB
fCLOCK = 125 MSPS; fOUT = 5 MHz; IOUTFS = 20 mA 77 dB
fCLOCK = 125 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA 78 dB
f
CLOCK
= 165 MSPS; f
OUT
= 5 MHz; I
OUTFS
= 20 mA
70
dB
fCLOCK = 165 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA 70 dB
fCLOCK = 210 MSPS; fOUT = 5 MHz; IOUTFS = 20 mA 74 dB
fCLOCK = 210 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA 67 dB
Data Sheet AD9744
Rev. C | Page 5 of 32
Parameter Min Typ Max Unit
Multitone Power Ratio (8 Tones at 400 kHz Spacing)
fCLOCK = 78 MSPS; fOUT = 15.0 MHz to 18.2 MHz
0 dBFS Output 66 dBc
−6 dBFS Output 68 dBc
−12 dBFS Output
62
dBc
−18 dBFS Output 61 dBc
1 Measured single-ended into 50 Ω load.
2 Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only.
3 Noise spectral density is the average noise power normalized to a 1 Hz bandwidth, with the DAC converting and producing an output tone.
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.
Table 3.
Parameter Min Typ Max Unit
DIGITAL INPUTS1
Logic 1 Voltage 2.1 3 V
Logic 0 Voltage 0 0.9 V
Logic 1 Current −10 +10 µA
Logic 0 Current −10 +10 µA
Input Capacitance
5
pF
Input Setup Time (tS) 2.0 ns
Input Hold Time (tH) 1.5 ns
Latch Pulse Width (tLPW) 1.5 ns
CLK INPUTS2
Input Voltage Range 0 3 V
Common-Mode Voltage 0.75 1.5 2.25 V
Differential Voltage 0.5 1.5 V
1 Includes CLOCK pin on SOIC/TSSOP packages and CLK+ pin on LFCSP package in single-ended clock input mode.
2 Applicable to CLK+ and CLK– inputs when configured for differential or PECL clock input mode.
Figure 2. Timing Diagram
0.1% 0.1%
t
S
t
H
t
PD
DB0–DB13
CLOCK
IOUTA
OR
IOUTB
02913-002
t
LPW
t
ST
AD9744 Data Sheet
Rev. C | Page 6 of 32
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
With
Respect to Min Max Unit
AVDD ACOM −0.3 +3.9 V
DVDD DCOM −0.3 +3.9 V
CLKVDD CLKCOM −0.3 +3.9 V
ACOM DCOM −0.3 +0.3 V
ACOM CLKCOM −0.3 +0.3 V
DCOM CLKCOM −0.3 +0.3 V
AVDD DVDD −3.9 +3.9 V
AVDD CLKVDD −3.9 +3.9 V
DVDD CLKVDD −3.9 +3.9 V
CLOCK, SLEEP DCOM −0.3 DVDD + 0.3 V
Digital Inputs,
MODE
DCOM −0.3 DVDD + 0.3 V
IOUTA, IOUTB ACOM −1.0 AVDD + 0.3 V
REFIO, REFLO, FS
ADJ
ACOM −0.3 AVDD + 0.3 V
CLK+, CLK−,
CMODE
CLKCOM −0.3 CLKVDD +
0.3
V
Junction
Temperature
150 °C
Storage
Temperature
−65 +150 °C
Lead Temperature
(10 sec)
300 °C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
Thermal impedance measurements were taken on a 4-layer
board in still air, in accordance with EIA/JESD51-7.
Table 5. Thermal Resistance
Package Type θJA Unit
28-Lead 300-Mil SOIC 55.9 °C/W
28-Lead TSSOP 67.7 °C/W
32-Lead LFCSP 32.5 °C/W
ESD CAUTION
Data Sheet AD9744
Rev. C | Page 7 of 32
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 3. 28-Lead SOIC and TSSOP
Figure 4. 32-Lead LFCSP
Table 6. Pin Function Descriptions
SOIC/TSSOP
Pin No.
LFCSP
Pin No. Mnemonic Description
1 27 DB13 Most Significant Data Bit (MSB).
2 to 13 28 to 32,
1, 2, 4 to 8
DB12 to
DB1
Data Bits 12 to 1.
14 9 DB0 Least Significant Data Bit (LSB).
15 25 SLEEP Power-Down Control Input. Active high. Contains active pull-down circuit; it may be left
unterminated if not used.
16 N/A REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to ACOM for both internal
and external reference operation modes.
17 23 REFIO Reference Input/Output. Serves as reference input when using external reference. Serves as
1.2 V reference output when using internal reference. Requires 0.1 µF capacitor to ACOM
when using internal reference.
18 24 FS ADJ Full-Scale Current Output Adjust.
19 N/A NC No Internal Connection.
20 19, 22 ACOM Analog Common.
21 20 IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s.
22 21 IOUTA DAC Current Output. Full-scale current when all data bits are 1s.
23
N/A
RESERVED
Reserved. Do not connect to common or supply.
24 17, 18 AVDD Analog Supply Voltage (3.3 V).
25 16 MODE Selects Input Data Format. Connect to DCOM for straight binary, DVDD for twos complement.
N/A 15 CMODE Clock Mode Selection. Connect to CLKCOM for single-ended clock receiver (drive CLK+ and
float CLK−). Connect to CLKVDD for differential receiver. Float for PECL receiver (terminations
on-chip).
26 10, 26 DCOM Digital Common.
27 3 DVDD Digital Supply Voltage (3.3 V).
28 N/A CLOCK Clock Input. Data latched on positive edge of clock.
N/A 12 CLK+ Differential Clock Input.
N/A 13 CLK− Differential Clock Input.
N/A
11
CLKVDD
Clock Supply Voltage (3.3 V).
N/A 14 CLKCOM Clock Common.
N/A EPAD EPAD Exposed Pad. Connect the exposed pad thermally to a copper ground plane for enhanced
electrical and thermal performance.
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
28
27
26
25
24
23
22
21
NC = NO CONNECT
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
(LSB) DB0
CLOCK
DVDD
DCOM
MODE
AVDD
RESERVED
IOUTA
IOUTB
ACOM
NC
FS ADJ
REFIO
REFLO
SLEEP
DB10
DB11
DB12
(MSB) DB13
02913-003
AD9744
TOP VIEW
(Not to Scale)
FS ADJ
REFIO
ACOM
IOUTA
DB7
NOTES
1. CONNECT THE E X P OSE D P AD THERM ALLY TO A COPP E R GRO UND P LANE
FOR ENHANCED E LECTRI CAL AND T HE RM AL PERFO RM ANCE .
DB6
DVDD
IOUTB
ACOM
AVDD
AVDD
DB5
DB4
DB3
DB2
DB1
(L S B) DB0
DCOM
CLKVDD
CLK+
CLK–
CLKCOM
CMODE
MODE
DB8
DB9
DB10
DB11
DB13 (MS B)
DCOM
SLEEP
DB12
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
AD9744
TOP VIEW
(No t t o Scal e)
02913-004
AD9744 Data Sheet
Rev. C | Page 8 of 32
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 5. SFDR vs. fOUT at 0 dBFS
Figure 6. SFDR vs. fOUT at 65 MSPS
Figure 7. SFDR vs. fOUT at 125 MSPS
Figure 8. SFDR vs. fOUT at 165 MSPS
Figure 9. SFDR vs. fOUT at 210 MSPS
Figure 10. SFDR vs. fOUT and IOUTFS at 65 MSPS and 0 dBFS
45
50
55
60
65
70
75
80
85
90
95
SFDR (dBc)
f
OUT (MHz)
1 10 100
02913-006
65MSPS
125MSPS
165MSPS
125MSPS (LFCSP)
165MSPS (LFCSP)
210MSPS
210MSPS (LFCSP)
45
50
55
60
65
70
75
80
85
90
95
SFDR (dBc)
0 5 10 15 20 25
fOUT (MHz)
02913-009
0dBFS
–6dBFS
–12dBFS
45
50
55
60
65
70
75
80
85
90
95
SFDR (dBc)
0 5 10 15
20 25 30 35 40 45
f
OUT
(MHz)
02913-012
0dBFS
–6dBFS
–12dBFS
45
50
55
60
65
70
75
80
85
90
95
SFDR (dBc)
20 300 10 40 50 60
fOUT
(MHz)
02913-007
0dBFS (LFCSP)
–6dBFS (LFCSP)
–12dBFS (LFCSP)
–6dBFS
0dBFS
–12dBFS
45
50
55
60
65
70
75
80
85
90
95
SFDR (dBc)
0 10 20 30 40 50 60 70 80
f
OUT
(MHz)
02913-055
–12dBFS (LFCSP)
–6dBFS
0dBFS
–12dBFS
0dBFS (LFCSP)
–6dBFS (LFCSP)
45
50
55
60
65
70
75
80
85
90
95
SFDR (dBc)
0 5 10 15 20 25
fOUT (MHz)
02913-010
20mA
10mA
5mA
Data Sheet AD9744
Rev. C | Page 9 of 32
Figure 11. Single-Tone SFDR vs. AOUT at fOUT = fCLOCK/11
Figure 12. Single-Tone SFDR vs. AOUT at fOUT = fCLOCK/5
Figure 13. SNR vs. fCLOCK and IOUTFS at fOUT = 5 MHz and 0 dBFS
Figure 14. Dual-Tone IMD vs. AOUT at fOUT = fCLOCK/7
Figure 15. Typical INL
Figure 16. Typical DNL
45
50
55
60
65
70
75
80
85
90
95
SFDR (dBc)
–25 –20 –15 –10 –5 0
A
OUT
(dBFS)
02913-013
65MSPS
125MSPS
210MSPS
165MSPS
210MSPS (LFCSP)
45
50
55
60
65
70
75
80
85
90
95
SFDR (dBc)
–25 –20 –15 –10 –5 0
A
OUT
(dBFS)
02913-008
65MSPS
125MSPS
125MSPS (LFCSP)
165MSPS
165MSPS (LFCSP)
210MSPS (LFCSP) 210MSPS
50
55
60
65
70
75
80
85
90
SNR (dB)
0 30 60 90 120 150 180 210
f
CLOCK
(MSPS)
02913-011
I
OUT
FS = 5mA I
OUT
FS = 5mA LFCSP
I
OUT
FS = 10mA
I
OUT
FS = 10mA LFCSP
I
OUT
FS = 20mA
I
OUT
FS = 20mA LFCSP
45
50
55
60
65
70
75
80
85
90
95
SFDR (dBc)
–25 –20 –15 –10 –5 0
A
OUT
(dBFS)
02913-014
65MSPS (8.3,10.3)
78MSPS (10.1, 12.1)
125MSPS (16.9, 18.9)
165MSPS (22.6, 24.6)
210MSPS (29,31)
210MSPS (29,31)
LFCSP
4096 8192 12288 16384
–1.0
–0.5
0
0.5
1.0
CODE
ERROR (LSB)
0
–1.5
1.5
02913-015
04096
1.0
0.8
–0.6
0.4
0.2
0
CODE
ERROR (LSB)
–0.2
–1.0
–0.8
–0.4
0.6
8192 12288 16384
02913-018
AD9744 Data Sheet
Rev. C | Page 10 of 32
Figure 17. SFDR vs. Temperature at 165 MSPS, 0 dBFS
Figure 18. Single-Tone SFDR
Figure 19. Dual-Tone SFDR
Figure 20. Four-Tone SFDR
Figure 21. Two-Carrier UMTS Spectrum,
fCLOCK = 122.88 MSPS (ACLR = 64 dB) LFCSP Package
Figure 22. Single-Carrier UMTS Spectrum,
fCLOCK = 61.44 MSPS (ACLR = 74 dB) LFCSP Package
45
50
55
60
65
70
75
80
85
90
95
SFDR (dBc)
020
–40 –20 40 60 80
TEMPERATURE (°C)
02913-020
4MHz
19MHz
34MHz
49MHz
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
MAGNITUDE (dBm)
1 6 11 16 21 26 31 36
FREQUENCY (MHz)
02913-016
f
CLOCK
= 78MSPS
f
OUT
= 15.0MHz
SFDR = 79dBc
AMPLITUDE = 0dBFS
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
MAGNITUDE (dBm)
1 6 11 16 21 26 31 36
FREQUENCY (MHz)
02913-019
f
CLOCK
= 78MSPS
f
OUT1
= 15.0MHz
f
OUT2
= 15.4MHz
SFDR = 77dBc
AMPLITUDE = 0dBFS
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
MAGNITUDE (dBm)
1 6 11 16 21 26 31 36
FREQUENCY (MHz)
02913-021
f
CLOCK
= 78MSPS
f
OUT1
= 15.0MHz
f
OUT2
= 15.4MHz
f
OUT3
= 15.8MHz
f
OUT4
= 16.2MHz
SFDR = 75dBc
AMPLITUDE = 0dBFS
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
MAGNITUDE (dBm)
FREQUENCY (MHz)
CENTER 33.22 MHz 3 MHz SPAN 30 MHz
02913-017
CU1
C0
C0
C11
C11
C12
C12
CU1
CU2 CU2
–39.01dBm
29.38000000MHz
CHPWR –19.26dBm
ACP UP –64.98dB
ACP LOW +0.55dB
ALT1 UP –66.26dB
ALT1 LOW –64.23dB
CENTER 10MHz
FREQ OFFSET
5.000MHz REF BW
3.840MHz
LOWER
dBc
–74.62 dBm
–84.12
UPPER
dBc
–75.04 dBm
–84.54
SPAN 18MHz
02913-056
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
MAGNITUDE (dBm)
RES BW = 30kHz
VBW = 300kHz
ATTEN = 8dB
AVG = 50
Data Sheet AD9744
Rev. C | Page 11 of 32
Figure 23. Simplified Block Diagram (SOIC/TSSOP Packages)
DIGITAL DATA INPUTS (DB13–DB0)
150pF
+1.2V REF
AVDD ACOM
REFLO
PMOS
CURRENT SOURCE
ARRAY
3.3V
SEGMENTED SWITCHES
FOR DB13–DB5 LSB
SWITCHES
REFIO
FS ADJ
DVDD
DCOM
CLOCK
3.3V
R
SET
2kΩ
0.1µF
IOUTA
IOUTB
AD9744
SLEEP LATCHES
I
REF
V
REFIO
CLOCK
IOUTB
IOUTA
R
LOAD
50Ω
V
OUTB
V
OUTA
R
LOAD
50Ω
MODE
V
DIFF
= V
OUTA
– V
OUTB
02913-022
AD9744 Data Sheet
Rev. C | Page 12 of 32
TERMINOLOGY
Linearity Error (Also Called Integral Nonlinearity or INL)
It is defined as the maximum deviation of the actual analog
output from the ideal output, determined by a straight line
drawn from zero to full scale.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called the offset error. For IOUTA, 0 mA output is expected
when the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Temperature Drift
It is specified as the maximum change from the ambient (25°C)
value to the value at either TMIN or TMAX. For offset and gain
drift, the drift is reported in ppm of full-scale range (FSR)
per °C. For reference drift, the drift is reported in ppm per °C.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified
bandwidth.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal. It is
expressed as a percentage or in decibels (dB).
Multitone Power Ratio
The spurious-free dynamic range containing multiple carrier
tones of equal amplitude. It is measured as the difference
between the rms amplitude of a carrier tone to the peak
spurious signal in the region of a removed tone.
Figure 24. Basic AC Characterization Test Set-Up (SOIC/TSSOP Packages)
150pF
1.2V REF
AVDD ACOM
REFLO
PMOS
CURRENT SOURCE
ARRAY
SEGMENTED SWITCHES
FOR DB13–DB5 LSB
SWITCHES
REFIO
FS ADJ
DVDD
DCOM
CLOCK
3.3V
R
SET
2kΩ
0.1µF
DVDD
DCOM
IOUTA
IOUTB
AD9744
SLEEP
50Ω
RETIMED
CLOCK
OUTPUT*
LATCHES
DIGITAL
DATA
TEKTRONIX AWG-2021
WITH OPTION 4
LECROY 9210
PULSE GENERATOR
CLOCK
OUTPUT
50Ω
RHODE & SCHWARZ
FSEA30
SPECTRUM
ANALYZER
MINI-CIRCUITS
T1-1T
*AWG2021 CLOCK RETIMED
SO THAT THE DIGITAL DATA
TRANSITIONS ON FALLING EDGE
OF 50% DUTY CYCLE CLOCK.
3.3V
MODE
50Ω
02913-005
Data Sheet AD9744
Rev. C | Page 13 of 32
FUNCTIONAL DESCRIPTION
Figure 23 shows a simplified block diagram of the AD9744. The
AD9744 consists of a DAC, digital control logic, and full-scale
output current control. The DAC contains a PMOS current
source array capable of providing up to 20 mA of full-scale
current (IOUTFS). The array is divided into 31 equal currents that
make up the five most significant bits (MSBs). The next four
bits, or middle bits, consist of 15 equal current sources whose
value is 1/16th of an MSB current source. The remaining LSBs
are binary weighted fractions of the middle bits current sources.
Implementing the middle and lower bits with current sources,
instead of an R-2R ladder, enhances its dynamic performance
for multitone or low amplitude signals and helps maintain the
DAC’s high output impedance (that is, >100 kΩ).
All of these current sources are switched to one or the other of
the two output nodes, that is, IOUTA or IOUTB, via PMOS
differential current switches. The switches are based on the
architecture that was pioneered in the AD9764 family, with
further refinements to reduce distortion contributed by the
switching transient. This switch architecture also reduces
various timing errors and provides matching complementary
drive signals to the inputs of the differential current switches.
The analog and digital sections of the AD9744 have separate
power supply inputs, that is, AVDD and DVDD, that can operate
independently over a 2.7 V to 3.6 V range. The digital section,
which is capable of operating at a rate of up to 210 MSPS,
consists of edge-triggered latches and segment decoding logic
circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.2 V band gap
voltage reference, and a reference control amplifier.
The DAC full-scale output current is regulated by the reference
control amplifier and can be set from 2 mA to 20 mA via an
external resistor, RSET, connected to the full-scale adjust
(FS ADJ) pin. The external resistor, in combination with both
the reference control amplifier and voltage reference VREFIO, sets
the reference current IREF, which is replicated to the segmented
current sources with the proper scaling factor. The full-scale
current, IOUTFS, is 32 times IREF.
REFERENCE OPERATION
The AD9744 contains an internal 1.2 V band gap reference. The
internal reference cannot be disabled, but can be easily overridden
by an external reference with no effect on performance. Figure 25
shows an equivalent circuit of the band gap reference. REFIO
serves as either an output or an input depending on whether the
internal or an external reference is used. To use the internal
reference, simply decouple the REFIO pin to ACOM with a
0.1 µF capacitor and connect REFLO to ACOM via a resistance
less than 5 Ω. The internal reference voltage will be present at
REFIO. If the voltage at REFIO is to be used anywhere else in
the circuit, an external buffer amplifier with an input bias
current of less than 100 nA should be used. An example of the
use of the internal reference is shown in Figure 26.
Figure 25. Equivalent Circuit of Internal Reference
Figure 26. Internal Reference Configuration
An external reference can be applied to REFIO, as shown in
Figure 27. The external reference may provide either a fixed
reference voltage to enhance accuracy and drift performance or
a varying reference voltage for gain control. Note that the 0.1 µF
compensation capacitor is not required since the internal reference
is overridden, and the relatively high input impedance of REFIO
minimizes any loading of the external reference.
Figure 27. External Reference Configuration
REFERENCE CONTROL AMPLIFIER
The AD9744 contains a control amplifier that is used to regulate
the full-scale output current, IOUTFS. The control amplifier is
configured as a V-I converter, as shown in Figure 26, so that its
current output, IREF, is determined by the ratio of the VREFIO and
an external resistor, RSET, as stated in Equation 4. IREF is copied
to the segmented current sources with the proper scale factor to
set IOUTFS, as stated in Equation 3.
AVDD
REFIO
REFLO
84µA
7kΩ
02913-057
150pF
+1.2V REF
AVDD
REFLO
CURRENT
SOURCE
ARRAY
3.3V
REFIO
FS ADJ
2kΩ
0.1µF
AD9744
ADDITIONAL
LOAD
OPTIONAL
EXTERNAL
REF BUFFER
02913-023
150pF
+1.2V REF
AVDDREFLO
CURRENT
SOURCE
ARRAY
3.3V
REFIO
FS ADJ
RSET
AD9744
EXTERNAL
REF
IREF =
VREFIO/RSET
AVDD
REFERENCE
CONTROL
AMPLIFIER
VREFIO
02913-024
AD9744 Data Sheet
Rev. C | Page 14 of 32
The control amplifier allows a wide (10:1) adjustment span of
IOUTFS over a 2 mA to 20 mA range by setting IREF between 62.5 µA
and 625 µA. The wide adjustment span of IOUTFS provides several
benefits. The first relates directly to the power dissipation of the
AD9744, which is proportional to IOUTFS (refer to the Power
Dissipation section). The second relates to the 20 dB adjustment,
which is useful for system gain control purposes.
The small signal bandwidth of the reference control amplifier is
approximately 500 kHz and can be used for low frequency small
signal multiplying applications.
DAC TRANSFER FUNCTION
Both DACs in the AD9744 provide complementary current
outputs, IOUTA and IOUTB. IOUTA provides a near full-scale
current output, IOUTFS, when all bits are high (that is, DAC
CODE = 16383), while IOUTB, the complementary output,
provides no current. The current output appearing at IOUTA
and IOUTB is a function of both the input code and IOUTFS and
can be expressed as
( )
OUTFS
ICODE
DACIOUTA ×= 16384/
(1)
( )
OUTFS
ICODEDACIOUTB ×−= /1638416383
(2)
where DAC CODE = 0 to 16383 (that is, decimal representation).
As mentioned previously, IOUTFS is a function of the reference
current IREF, which is nominally set by a reference voltage,
VREFIO, and external resistor, RSET. It can be expressed as
REF
OUTFS II ×= 32
(3)
where
SET
REFIO
REF RV
I/=
(4)
The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, IOUTA
and IOUTB should be directly connected to matching resistive
loads, RLOAD, that are tied to analog common, ACOM. Note that
RLOAD may represent the equivalent load resistance seen by
IOUTA or IOUTB as would be the case in a doubly terminated
50 Ω or 75 Ω cable. The single-ended voltage output appearing
at the IOUTA and IOUTB nodes is simply
LOAD
OUTA
RIOUTAV×=
(5)
LOAD
OUTB
RIOUTBV×=
(6)
Note that the full-scale value of VOUTA and VOUTB should not
exceed the specified output compliance range to maintain
specified distortion and linearity performance.
( )
LOAD
DIFF RIOUTBIOUTAV×−=
(7)
Substituting the values of IOUTA, IOUTB, IREF, and VDIFF can be
expressed as
( )
[ ]
( )
REFIO
SET
LOAD
DIFF
VRR
CODEDACV
××
−×=
/
16384/16383
32
2
(8)
Equation 7 and Equation 8 highlight some of the advantages of
operating the AD9744 differentially. First, the differential operation
helps cancel common-mode error sources associated with IOUTA
and IOUTB, such as noise, distortion, and dc offsets. Second, the
differential code dependent current and subsequent voltage, VDIFF,
is twice the value of the single-ended voltage output (that is, VOU TA
or VOUTB), thus providing twice the signal power to the load.
Note that the gain drift temperature performance for a single-
ended (VOUTA and VOUTB) or differential output (VDIFF) of the
AD9744 can be enhanced by selecting temperature tracking
resistors for RLOAD and RSET due to their ratiometric relationship,
as shown in Equation 8.
ANALOG OUTPUTS
The complementary current outputs in each DAC, IOUTA, and
IOUTB may be configured for single-ended or differential oper-
ation. IOUTA and IOUTB can be converted into complementary
single-ended voltage outputs, VOUTA and VOUTB, via a load resistor,
RLOAD, as described in the DAC Transfer Function section by
Equation 5 through Equation 8. The differential voltage, VDIFF,
existing between VOUTA and VOUTB, can also be converted to a
single-ended voltage via a transformer or differential amplifier
configuration. The ac performance of the AD9744 is optimum
and specified using a differential transformer-coupled output in
which the voltage swing at IOUTA and IOUTB is limited to ±0.5 V.
The distortion and noise performance of the AD9744 can be
enhanced when it is configured for differential operation. The
common-mode error sources of both IOUTA and IOUTB can
be significantly reduced by the common-mode rejection of a
transformer or differential amplifier. These common-mode
error sources include even-order distortion products and noise.
The enhancement in distortion performance becomes more
significant as the frequency content of the reconstructed
waveform increases and/or its amplitude decreases. This is due
to the first-order cancellation of various dynamic common-
mode distortion mechanisms, digital feedthrough, and noise.
Performing a differential-to-single-ended conversion via a
transformer also provides the ability to deliver twice the
reconstructed signal power to the load (assuming no source
termination). Since the output currents of IOUTA and IOUTB
are complementary, they become additive when processed
differentially. A properly selected transformer will allow the
AD9744 to provide the required power and voltage levels to
different loads.
The output impedance of IOUTA and IOUTB is determined by
the equivalent parallel combination of the PMOS switches
associated with the current sources and is typically 100 kΩ in
parallel with 5 pF. It is also slightly dependent on the output
voltage (that is, VOUTA and VOUTB) due to the nature of a PMOS
device. As a result, maintaining IOUTA and/or IOUTB at a
virtual ground via an I-V op amp configuration will result in
the optimum dc linearity. Note that the INL/DNL specifications
Data Sheet AD9744
Rev. C | Page 15 of 32
for the AD9744 are measured with IOUTA maintained at a
virtual ground via an op amp.
IOUTA and IOUTB also have a negative and positive voltage
compliance range that must be adhered to in order to achieve
optimum performance. The negative output compliance range
of −1 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a breakdown
of the output stage and affect the reliability of the AD9744.
The positive output compliance range is slightly dependent on
the full-scale output current, IOUTFS. It degrades slightly from its
nominal 1.2 V for an IOUTFS = 20 mA to 1 V for an IOUTFS = 2 mA.
The optimum distortion performance for a single-ended or
differential output is achieved when the maximum full-scale
signal at IOUTA and IOUTB does not exceed 0.5 V.
DIGITAL INPUTS
The AD9744 digital section consists of 14 input bit channels
and a clock input. The 14-bit parallel data inputs follow
standard positive binary coding, where DB13 is the most
significant bit (MSB) and DB0 is the least significant bit (LSB).
IOUTA produces a full-scale output current when all data bits
are at Logic 1. IOUTB produces a complementary output with
the full-scale current split between the two outputs as a
function of the input code.
Figure 28. Equivalent Digital Input
The digital interface is implemented using an edge-triggered
master/slave latch. The DAC output updates on the rising edge
of the clock and is designed to support a clock rate as high as
210 MSPS. The clock can be operated at any duty cycle that
meets the specified latch pulse width. The setup and hold
times can also be varied within the clock cycle as long as the
specified minimum times are met, although the location of
these transition edges may affect digital feedthrough and
distortion performance. Best performance is typically achieved
when the input data transitions on the falling edge of a 50%
duty cycle clock.
CLOCK INPUT
SOIC/TSSOP Packages
The 28-lead package options have a single-ended clock input
(CLOCK) that must be driven to rail-to-rail CMOS levels. The
quality of the DAC output is directly related to the clock quality,
and jitter is a key concern. Any noise or jitter in the clock will
translate directly into the DAC output. Optimal performance
will be achieved if the CLOCK input has a sharp rising edge,
since the DAC latches are positive edge triggered.
LFCSP Package
A configurable clock input is available in the LFCSP package,
which allows for one single-ended and two differential modes.
The mode selection is controlled by the CMODE input, as
summarized in Table 7. Connecting CMODE to CLKCOM
selects the single-ended clock input. In this mode, the CLK+
input is driven with rail-to-rail swings and the CLK– input is
left floating. If CMODE is connected to CLKVDD, the differential
receiver mode is selected. In this mode, both inputs are high
impedance. The final mode is selected by floating CMODE. This
mode is also differential, but internal terminations for positive
emitter-coupled logic (PECL) are activated. There is no significant
performance difference among any of the three clock input modes.
Table 7. Clock Mode Selection
CMODE Pin Clock Input Mode
CLKCOM Single-Ended
CLKVDD Differential
Float PECL
The single-ended input mode operates in the same way as the
CLOCK input in the 28-lead packages, as previously described.
In the differential input mode, the clock input functions as a
high impedance differential pair. The common-mode level of
the CLK+ and CLK− inputs can vary from 0.75 V to 2.25 V, and
the differential voltage can be as low as 0.5 V p-p. This mode
can be used to drive the clock with a differential sine wave since
the high gain bandwidth of the differential inputs will convert
the sine wave into a single-ended square wave internally.
The final clock mode allows for a reduced external component
count when the DAC clock is distributed on the board using
PECL logic. The internal termination configuration is shown in
Figure 29. These termination resistors are untrimmed and can
vary up to ±20%. However, matching between the resistors
should generally be better than ±1%.
DVDD
DIGITAL
INPUT
02913-025
AD9744 Data Sheet
Rev. C | Page 16 of 32
Figure 29. Clock Termination in PECL Mode
DAC TIMING
Input Clock and Data Timing Relationship
Dynamic performance in a DAC is dependent on the relationship
between the position of the clock edges and the time at which
the input data changes. The AD9744 is rising edge triggered,
and so exhibits dynamic performance sensitivity when the data
transition is close to this edge. In general, the goal when applying
the AD9744 is to make the data transition close to the falling
clock edge. This becomes more important as the sample rate
increases. Figure 30 shows the relationship of SFDR to clock
placement with different sample rates. Note that at the lower
sample rates, more tolerance is allowed in clock placement,
while at higher rates, more care must be taken.
Figure 30. SFDR vs. Clock Placement at fOUT = 20 MHz and 50 MHz
Sleep Mode Operation
The AD9744 has a power-down function that turns off the output
current and reduces the supply current to less than 6 mA over
the specified supply range of 2.7 V to 3.6 V and temperature
range. This mode can be activated by applying a logic level 1 to
the SLEEP pin. The SLEEP pin logic threshold is equal to 0.5 Ω
AVDD. This digital input also contains an active pull-down
circuit that ensures that the AD9744 remains enabled if this
input is left disconnected. The AD9744 takes less than 50 ns to
power down and approximately 5 µs to power back up.
POWER DISSIPATION
The power dissipation, PD, of the AD9744 is dependent on
several factors that include:
• The power supply voltages (AVDD, CLKVDD, and
DVDD)
• The full-scale current output IOUTFS
• The update rate fCLOCK
• The reconstructed digital input waveform
The power dissipation is directly proportional to the analog supply
current, IAVDD, and the digital supply current, IDVDD. IAVDD is
directly proportional to IOUTFS, as shown in Figure 31, and is
insensitive to fCLOCK. Conversely, IDVDD is dependent on both the
digital input waveform, fCLOCK, and digital supply DVDD. Figure 32
shows IDVDD as a function of full-scale sine wave output ratios
(fOUT/fCLOCK) for various update rates with DVDD = 3.3 V.
Figure 31. IAVDD vs. IOUTFS
Figure 32. IDVDD vs. Ratio at DVDD = 3.3 V
CLK+
TO DAC CORE
CLK–
V
TT
= 1.3V NOM
50Ω50Ω
AD9744
CLOCK
RECEIVER
02913-026
–3 –2 2–1 0 1
65
75
ns
dB
3
55
45
35
60
70
50
40 50MHz SFDR
20MHz SFDR
50MHz SFDR
02913-027
I
OUTFS
(mA)
35
02
I
AVDD
(mA)
30
25
20
15
10
4 6 8 10 12 14 16 18 20
02913-028
RATIO (fOUT/fCLOCK)
20
0.01 10.1
IDVDD (mA)
14
16
18
12
10
8
6
4
2
0
165MSPS
210MSPS
65MSPS
02913-029
125MSPS
Data Sheet AD9744
Rev. C | Page 17 of 32
Figure 33. ICLKVDD vs. fCLOCK and Clock Mode
APPLYING THE AD9744
Output Configurations
The following sections illustrate some typical output configurations
for the AD9744. Unless otherwise noted, it is assumed that IOUTFS
is set to a nominal 20 mA. For applications requiring the optimum
dynamic performance, a differential output configuration is
suggested. A differential output configuration may consist of
either an RF transformer or a differential op amp configuration.
The transformer configuration provides the optimum high
frequency performance and is recommended for any application
that allows ac coupling. The differential op amp configuration is
suitable for applications requiring dc coupling, a bipolar output,
signal gain, and/or level shifting within the bandwidth of the
chosen op amp.
A single-ended output is suitable for applications requiring a
unipolar voltage output. A positive unipolar output voltage
results if IOUTA and/or IOUTB are connected to an appro-
priately sized load resistor, RLOAD, referred to ACOM. This
configuration may be more suitable for a single-supply system
requiring a dc-coupled, ground referred output voltage. Alter-
natively, an amplifier could be configured as an I-V converter,
thus converting IOUTA or IOUTB into a negative unipolar
voltage. This configuration provides the best dc linearity since
IOUTA or IOUTB is maintained at a virtual ground.
DIFFERENTIAL COUPLING USING A
TRANSFORMER
An RF transformer can be used to perform a differential-to-single-
ended signal conversion, as shown in Figure 34. A differentially
coupled transformer output provides the optimum distortion
performance for output signals whose spectral content lies
within the transformer’s pass band. An RF transformer, such as
the Mini-Circuits T1–1T, provides excellent rejection of
common-mode distortion (that is, even-order harmonics) and
noise over a wide frequency range. It also provides electrical
isolation and the ability to deliver twice the power to the load.
Transformers with different impedance ratios may also be used
for impedance matching purposes. Note that the transformer
provides ac coupling only.
Figure 34. Differential Output Using a Transformer
The center tap on the primary side of the transformer must be
connected to ACOM to provide the necessary dc current path
for both IOUTA and IOUTB. The complementary voltages
appearing at IOUTA and IOUTB (that is, VOUTA and VOUTB)
swing symmetrically around ACOM and should be maintained
with the specified output compliance range of the AD9744. A
differential resistor, RDIFF, may be inserted in applications where
the output of the transformer is connected to the load, RLOAD,
via a passive reconstruction filter or cable. RDIFF is determined
by the transformer’s impedance ratio and provides the proper
source termination that results in a low VSWR. Note that approx-
imately half the signal power will be dissipated across RDIFF.
DIFFERENTIAL COUPLING USING AN OP AMP
An op amp can also be used to perform a differential-to-single-
ended conversion, as shown in Figure 35. The AD9744 is
configured with two equal load resistors, RLOAD, of 25 Ω. The
differential voltage developed across IOUTA and IOUTB is
converted to a single-ended signal via the differential op amp
configuration. An optional capacitor can be installed across
IOUTA and IOUTB, forming a real pole in a low-pass filter. The
addition of this capacitor also enhances the op amp’s distortion
performance by preventing the DAC’s high slewing output from
overloading the op amp’s input.
Figure 35. DC Differential Coupling Using an Op Amp
The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the differential
op amp circuit using the AD8047 is configured to provide some
additional signal gain. The op amp must operate off a dual supply
since its output is approximately ±1 V. A high speed amplifier
capable of preserving the differential performance of the AD9744
while meeting other system level objectives (such as cost or
power) should be selected. The op amp’s differential gain, gain
setting resistor values, and full-scale output swing capabilities
should all be considered when optimizing this circuit.
50 100 150
0
1
2
3
4
5
6
7
8
9
11
10
f
CLOCK
(MSPS)
I
CLKVDD
(mA)
2502000
SE
02913-030
PECL
DIFF
R
LOAD
AD9744
MINI-CIRCUITS
T1-1T
OPTIONAL R
DIFF
IOUTA
IOUTB
22
21
02913-031
AD9744
IOUTA
IOUTB C
OPT
500
225
225
500
2525
AD8047
02913-032
22
21
AD9744 Data Sheet
Rev. C | Page 18 of 32
The differential circuit shown in Figure 36 provides the necessary
level shifting required in a single-supply system. In this case,
AVDD, which is the positive analog supply for both the AD9744
and the op amp, is also used to level-shift the differential output
of the AD9744 to midsupply (that is, AVDD/2). The AD8041 is
a suitable op amp for this application.
Figure 36. Single-Supply DC Differential Coupled Circuit
SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT
Figure 37 shows the AD9744 configured to provide a unipolar
output range of approximately 0 V to 0.5 V for a doubly terminated
50 Ω cable since the nominal full-scale current, IOUTFS, of 20 mA
flows through the equivalent RLOAD of 25 Ω. In this case, RLOAD
represents the equivalent load resistance seen by IOUTA or
IOUTB. The unused output (IOUTA or IOUTB) can be connected
to ACOM directly or via a matching RLOAD. Different values of
IOUTFS and RLOAD can be selected as long as the positive compliance
range is adhered to. One additional consideration in this mode
is the integral nonlinearity (INL), discussed in the Analog
Outputs section. For optimum INL performance, the single-
ended, buffered voltage output configuration is suggested.
Figure 37. 0 V to 0.5 V Unbuffered Voltage Output
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT
CONFIGURATION
Figure 38 shows a buffered single-ended output configuration
in which the op amp U1 performs an I-V conversion on the
AD9744 output current. U1 maintains IOUTA (or IOUTB) at a
virtual ground, minimizing the nonlinear output impedance
effect on the DAC’s INL performance as described in the Analog
Outputs section. Although this single-ended configuration
typically provides the best dc linearity performance, its ac
distortion performance at higher DAC update rates may be
limited by U1’s slew rate capabilities. U1 provides a negative
unipolar output voltage, and its full-scale output voltage is
simply the product of RFB and IOUTFS. The full-scale output
should be set within U1’s voltage output swing capabilities by
scaling IOUTFS and/or RFB. An improvement in ac distortion
performance may result with a reduced IOUTFS since the signal
current U1 will be required to sink less signal current.
Figure 38. Unipolar Buffered Voltage Output
POWER AND GROUNDING CONSIDERATIONS,
POWER SUPPLY REJECTION
Many applications seek high speed and high performance under
less than ideal operating conditions. In these application circuits,
the implementation and construction of the printed circuit
board is as important as the circuit design. Proper RF techniques
must be used for device selection, placement, and routing as
well as power supply bypassing and grounding to ensure
optimum performance. Figure 43 to Figure 46 illustrate the
recommended printed circuit board ground, power, and signal
plane layouts implemented on the AD9744 evaluation board.
One factor that can measurably affect system performance is
the ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution.
This is referred to as the power supply rejection ratio (PSRR).
For dc variations of the power supply, the resulting performance
of the DAC directly corresponds to a gain error associated with
the DAC’s full-scale current, IOUTFS. AC noise on the dc supplies
is common in applications where the power distribution is
generated by a switching power supply. Typically, switching
power supply noise will occur over the spectrum from tens of
kHz to several MHz. The PSRR vs. frequency of the AD9744
AVDD supply over this frequency range is shown in Figure 39.
Figure 39. Power Supply Rejection Ratio (PSRR) vs. Frequency
Note that the ratio in Figure 39 is calculated as amps out/volts
in. Noise on the analog power supply has the effect of modulating
the internal switches, and therefore the output current. The
voltage noise on AVDD, therefore, will be added in a nonlinear
manner to the desired IOUT. Due to the relative different size of
AD9744
IOUTA
IOUTB C
OPT
500Ω
225Ω
225Ω
1kΩ
25Ω
25Ω
AD8041
1kΩAVDD
22
21
02913-033
AD9744
IOUTA
IOUTB
50Ω
25Ω
V
OUTA
= 0V TO 0.5V
I
OUTFS
= 20mA
50Ω
22
21
02913-034
AD9744
IOUTA
IOUTB
COPT
200Ω
U1 VOUT = IOUTFS × RFB
IOUTFS = 10mA
RFB
200Ω
22
21
02913-035
FREQUENCY (MHz)
85
40 126 8 100
PSRR (dB)
80
75
70
65
60
55
50
2 4
45
02913-036
Data Sheet AD9744
Rev. C | Page 19 of 32
these switches, the PSRR is very code dependent. This can produce
a mixing effect that can modulate low frequency power supply
noise to higher frequencies. Worst-case PSRR for either one of
the differential DAC outputs will occur when the full-scale current
is directed toward that output. As a result, the PSRR measurement
in Figure 39 represents a worst-case condition in which the
digital inputs remain static and the full-scale output current of
20 mA is directed to the DAC output being measured.
An example serves to illustrate the effect of supply noise on the
analog supply. Suppose a switching regulator with a switching
frequency of 250 kHz produces 10 mV of noise and, for
simplicity’s sake (ignoring harmonics), all of this noise is
concentrated at 250 kHz. To calculate how much of this
undesired noise will appear as current noise superimposed on
the DAC’s full-scale current, IOUTFS, one must determine the
PSRR in dB using Figure 39 at 250 kHz. To calculate the PSRR
for a given RLOAD, such that the units of PSRR are converted
from A/V to V/V, adjust the curve in Figure 39 by the scaling
factor 20 Ω log (RLOAD). For instance, if RLOAD is 50 Ω, the PSRR
is reduced by 34 dB (that is, PSRR of the DAC at 250 kHz,
which is 85 dB in Figure 39, becomes 51 dB VOUT/VIN).
Proper grounding and decoupling should be a primary
objective in any high speed, high resolution system. The
AD9744 features separate analog and digital supplies and
ground pins to optimize the management of analog and digital
ground currents in a system. In general, AVDD, the analog
supply, should be decoupled to ACOM, the analog common, as
close to the chip as physically possible. Similarly, DVDD, the
digital supply, should be decoupled to DCOM as close to the
chip as physically possible.
For those applications that require a single 3.3 V supply for both
the analog and digital supplies, a clean analog supply may be
generated using the circuit shown in Figure 40. The circuit
consists of a differential LC filter with separate power supply
and return lines. Lower noise can be attained by using low ESR
type electrolytic and tantalum capacitors.
Figure 40. Differential LC Filter for Single 3.3 V Applications
100µF
ELECT. 0.1µF
CER.
TTL/CMOS
LOGIC
CIRCUITS
3.3V
POWER SUPPLY
FERRITE
BEADS AVDD
ACOM
10µF–22µF
TANT.
02913-037
AD9744 Data Sheet
Rev. C | Page 20 of 32
EVALUATION BOARD
GENERAL DESCRIPTION
The TxDAC family evaluation boards allow for easy setup and
testing of any TxDAC product in the SOIC and LFCSP packages.
Careful attention to layout and circuit design, combined with a
prototyping area, allows the user to evaluate the AD9744 easily
and effectively in any application where high resolution, high
speed conversion is required.
This board allows the user the flexibility to operate the AD9744
in various configurations. Possible output configurations include
transformer coupled, resistor terminated, and single and
differential outputs. The digital inputs are designed to be driven
from various word generators, with the on-board option to add
a resistor network for proper load termination. Provisions are
also made to operate the AD9744 with either the internal or
external reference or to exercise the power-down feature.
Figure 41. SOIC Evaluation Board—Power Supply and Digital Inputs
2R1
3R2
4R3
5R4
6R5
7R6
8R7
9R8
10 R9
RP5
OPT
1DCOM
161 RP3 22ΩDB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB13X
DB12X
DB11X
DB10X
DB9X
DB8X
DB7X
DB6X
DB5X
DB4X
DB3X
DB2X
DB1X
DB0X
152 RP3 22Ω
14
3RP3 22Ω
13
4RP3 22Ω
12
5RP3 22Ω
11
6RP3 22Ω
10
7RP3 22Ω
9
8RP3 22Ω
16
1RP4 22Ω
15
2RP4 22Ω
14
3RP4 22Ω
13
4RP4 22Ω
12
5RP4 22Ω
11
6RP4 22Ω
9
8RP4 22Ω
10
7RP4 22Ω
CKEXT
CKEXTX
2
R1 3
R2 4
R3 5
R4 6
R5 7
R6 8
R7 9
R8 10
R9
RP6
OPT
1
DCOM
2R1
3R2
4R3
5R4
6R5
7R6
8R7
9R8
10 R9
RP1
OPT
1DCOM
2
R1 3
R2
4
R3 5
R4 6
R5 7
R6
8
R7
9
R810
R9
RP2
OPT
1
DCOM
2 1 DB13X
43DB12X
6 5 DB11X
8 7 DB10X
10 9 DB9X
12 11 DB8X
14 13 DB7X
16 15 DB6X
18 17 DB5X
20 19 DB4X
22 21 DB3X
24 23 DB2X
26 25 DB1X
28 27 DB0X
30 29
32 31
34 33 CKEXTX
36 35
38 37
40 39
JP3
J1
RIBBON
TB1 1
TB1 2
L2 BEAD
C7
0.1µFTP4
BLK +
DVDD
TP7
C6
0.1µF
C4
10µF
25V BLK BLKTP8
TP2
RED
TB1 3
TB1 4
L3 BEAD
C9
0.1µFTP6
BLK +
AVDD
TP10
C8
0.1µF
C5
10µF
25V BLK BLKTP9
TP5
RED
02913-038
Data Sheet AD9744
Rev. C | Page 21 of 32
Figure 42. SOIC Evaluation Board—Output Signal Conditioning
R6
OPT
S2
IOUTA
2
AB
JP10
13
IX
R11
50Ω
C13
OPT JP8 IOUT
S3
4
5
6
3
2
1
T1
T1-1T
JP9
C12
OPT
R10
50Ω
S1
IOUTB
123
A B
JP11
IY
1
EXT
23
INT
A B
JP5
REF
+
+
C14
10µF
16V
C16
0.1µFC17
0.1µF
AVDD
DVDD
CKEXT
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
AVDD
C15
10µF
16V
C18
0.1µFC19
0.1µF
CUT
UNDER DUT
JP6
JP4
R5
OPT
DVDD
R4
50Ω
CLOCK
S5
CLOCK
TP1
WHT
DVDD
AVDD
DVDD
R2
10kΩ
JP2
MODE
TP3
WHT
REF C2
0.1µF
C1
0.1µF
C11
0.1µF
R1
2kΩ
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
U1
AD9742
SLEEP
TP11
WHT
R3
10kΩ
CLOCK
DVDD
DCOM
MODE
AVDD
RESERVED
IOUTA
IOUTB
ACOM
NC
FS ADJ
REFIO
REFLO
SLEEP
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 AVDD
02913-039
AD9744 Data Sheet
Rev. C | Page 22 of 32
Figure 43. SOIC Evaluation Board—Primary Side
Figure 44. SOIC Evaluation Board—Secondary Side
02913-040
02913-041
Data Sheet AD9744
Rev. C | Page 23 of 32
Figure 45. SOIC Evaluation Board—Ground Plane
Figure 46. SOIC Evaluation Board—Power Plane
02913-042
02913-043
AD9744 Data Sheet
Rev. C | Page 24 of 32
Figure 47. SOIC Evaluation Board Assembly—Primary Side
Figure 48. SOIC Evaluation Board Assembly—Secondary Side
02913-044
02913-045
Data Sheet AD9744
Rev. C | Page 25 of 32
Figure 49. LFCSP Evaluation Board Schematic—Power Supply and Digital Inputs
CVDD
RED
TP12
BEAD
TB1 1
TB1 2
C7
0.1µF
C9
0.1µF
C3
0.1µF
BLK
TP2
TP4
TP6
BLK
BLK
C6
0.1µF
C8
0.1µF
C10
0.1µF
C2
10µF
6.3V
C4
10µF
6.3V
C5
10µF
6.3V
L1
DVDD
RED
TP13
BEAD
TB3 1
TB3 2
L2
AVDD
RED
TP5
BEAD
TB4 1
TB4 2
L3
J1
13
11
9
7
5
3
1
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
39
37
35
33
31
29
27
25
23
21
19
17
15
HEADER STRAIGHT UP MALE NO SHROUD
JP3 CKEXTX
CKEXT
CKEXTX
R21
100Ω
R24
100Ω
R25
100Ω
R26
100Ω
R27
100Ω
R28
100Ω
DB0X
DB1X
DB2X
DB3X
DB4X
DB5X
DB6X
DB7X
DB8X
DB9X
DB10X
DB11X
DB12X
DB13X
DB0X
DB1X
DB2X
DB3X
DB4X
DB5X
DB6X
DB7X
DB8X
DB9X
DB10X
DB11X
DB12X
DB13X
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
22Ω16
22Ω15
22Ω14
22Ω13
22Ω12
22Ω11
22Ω10
22Ω9
22Ω16
22Ω15
22Ω14
22Ω13
22Ω12
22Ω11
22Ω10
22Ω9
R20
100Ω
R19
100Ω
R18
100Ω
R17
100Ω
R16
100Ω
R15
100Ω
R4
100Ω
R3
100Ω
1 RP3
2 RP3
3 RP3
4 RP3
5 RP3
6 RP3
7 RP3
8 RP3
1 RP4
2 RP4
3 RP4
4 RP4
5 RP4
6 RP4
7 RP4
8 RP4
02913-046
AD9744 Data Sheet
Rev. C | Page 26 of 32
Figure 50. LFCSP Evaluation Board Schematic—Output Signal Conditioning
Figure 51. LFCSP Evaluation Board Schematic—Clock Input
C19
0.1
CVDD
CVDD
DB8
DB9
DB10
DB11
CLKB
DB5
DVDD
DB6
DB7
CLK
DB0
DB1
DB2
DB3
DB4 DB13
DB12
IOUT
AVDD
DVDD CVDDAVDD
DB8
DB9
DB10
DB11
IB
FS ADJ
CLKB
DB5
DVDD
DB6
DB7
CLK
CVDD
DCOM
DB0
DB1
DB2
DB3
DB4
DCOM1
DB13
ACOM1
AVDD
ACOM
IA
REFIO
AVDD1
SLEEP
DB12
CCOM
CMODE
MODE
CMODE
MODE
T1 – 1T
T1
JP8
JP9
4
3
2
1
5
6AGND: 3, 4, 5
S3
50Ω
R11
C13
28
25
17
23
21
22
18
19
27
26
24
20
29
30
31
32
DNP
DNP
C12
C11
0.1µF
C17
0.1µFC19
0.1µFC32
0.1µF
10kΩ
R30
10kΩ
R29
U1
AD9744LFCSP
14
5
6
7
8
9
10
11
12
1
2
3
4
13
15
16
WHT
TP1
WHT
TP11
JP1 0.1%
2kΩ
R1
R10
50Ω
WHT
TP3
TP7
WHT
SLEEP
02913-047
U4
U4
JP2
AGND: 5
CVDD: 8
4
3
6
CVDD: 8
C35
0.1µF
C20
10µF
16V
S5
AGND: 3, 4, 5
C34
0.1µF
CKEXT
CLK
CLKB
R5
120Ω
R2
120Ω
R6
50Ω
CVDD
AGND: 5
2
1
7
CVDD
02913-048
Data Sheet AD9744
Rev. C | Page 27 of 32
Figure 52. LFCSP Evaluation Board Layout—Primary Side
Figure 53. LFCSP Evaluation Board Layout—Secondary Side
02913-049
02913-050
AD9744 Data Sheet
Rev. C | Page 28 of 32
Figure 54. LFCSP Evaluation Board Layout—Ground Plane
Figure 55. LFCSP Evaluation Board Layout—Power Plane
02913-051
02913-052
Data Sheet AD9744
Rev. C | Page 29 of 32
Figure 56. LFCSP Evaluation Board Layout Assembly—Primary Side
Figure 57. LFCSP Evaluation Board Layout Assembly—Secondary Side
02913-053
02913-054
AD9744 Data Sheet
Rev. C | Page 30 of 32
OUTLINE DIMENSIONS
Figure 58. 28-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-28)
Dimensions shown in millimeters
Figure 59. 28-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-28)
Dimensions shown in millimeters and (inches)
COMPLIANT TO JEDEC STANDARDS MO-153-AE
28 15
141
8°
0°
SEATING
PLANE
COPLANARITY
0.10
1.20 MAX
6.40 BSC
0.65
BSC
PIN 1
0.30
0.19 0.20
0.09
4.50
4.40
4.30
0.75
0.60
0.45
9.80
9.70
9.60
0.15
0.05
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AE
18.10 (0.7126)
17.70 (0.6969)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75(0.0295)
0.25(0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
28 15
14
1
1.27 (0.0500)
BSC
06-07-2006-A
Data Sheet AD9744
Rev. C | Page 31 of 32
Figure 60. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 mm × 5 mm Body, Very Very Thin Quad
(CP-32-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Options
AD9744AR −40°C to +85°C 28-Lead, 300-Mil SOIC_W RW-28
AD9744ARZ −40°C to +85°C 28-Lead, 300-Mil SOIC_W RW-28
AD9744ARZRL −40°C to +85°C 28-Lead, 300-Mil SOIC_W RW-28
AD9744ARU
−40°C to +85°C
28-Lead TSSOP
RU-28
AD9744ARURL7 −40°C to +85°C 28-Lead TSSOP RU-28
AD9744ARUZ −40°C to +85°C 28-Lead TSSOP RU-28
AD9744ARUZRL7 −40°C to +85°C 28-Lead TSSOP RU-28
AD9744ACPZ −40°C to +85°C 32-Lead LFCSP_WQ CP-32-7
AD9744ACPZRL7 −40°C to +85°C 32-Lead LFCSP_WQ CP-32-7
AD9744-EBZ
Evaluation Board (SOIC)
AD9744ACP-PCBZ Evaluation Board (LFCSP)
1 Z = RoHS Compliant Part.
COM P LIANT T O JEDE C S TANDARDS M O-220- WHHD.
112408-A
1
0.50
BSC
BOTTOM VIEWTOP VI EW
PI N 1
INDICATOR
32
9
16
17
24
25
8
EXPOSED
PAD
PI N 1
INDICATOR
3.25
3.10 S Q
2.95
SEATING
PLANE
0.05 M AX
0.02 NOM
0.20 RE F
COPLANARITY
0.08
0.30
0.25
0.18
5.10
5.00 S Q
4.90
0.80
0.75
0.70
FOR PRO P E R CONNECTI ON O F
THE EXPOSED PAD, REFER TO
THE P IN CONFI GURAT IO N AND
FUNCTION DES CRIPTI ONS
SECTION OF THIS DATA SHEET.
0.50
0.40
0.30
0.25 M IN
AD9744 Data Sheet
Rev. C | Page 32 of 32
NOTES
©2003–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02913-0-12/13(C)