CCG1 Datasheet
USB Type-C Port Controller with Power
Delivery
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-93639 Rev. *K Revised May 3, 2017
General Description
CCG1 provides a complete USB Type-C and USB Power Delivery port control solution. The core architecture of CCG1 enables a
base Type-C solution that can scale to a complete 100-W USB Power Delivery with Alternate Mode multiplex support. CCG1 is also
a Type-C cable ID IC for active and passive cables. The CCG1 controller detects connector insert, plug orientation and VCONN
switching signals. CCG1 makes it easier to add USB Power Delivery to any architecture because it provides control signals to manage
external VBUS and VCONN power management solutions and external mux controls for most single cable-docking solutions.
The CCG1 family of devices are fixed-function parts that use a configuration table to control their operation in different applications.
The functionality is implemented in firmware and will be certified against USB Implementers Forum (USB-IF) compliance tests when
available. The programmability allows CCG1 devices to track any USB Specification changes. For information on accessing the source
code, contact Cypress support.
Applications
■Notebooks, tablets, monitors, docking stations
■Power adapters, USB Type-C cables
Features
32-bit MCU Subs ys te m
■48-MHz ARM Cortex-M0 CPU with 32-KB flash and 4-KB
SRAM
Integrated analog blocks
■12-bit, 1-Msps ADC for VBUS voltage and current monitoring
■Dynamic overcurrent and overvoltage protection
Integrated digital blocks
■Two configurable 16-bit TCPWM blocks
■One I2C master or slave
Type-C Support
■Integrated transceiver (BB PHY)
■Supports up to two USB ports with PD
■Supports routing of all protocols through an external mux
PD Support
■Supports Provider and Consumer roles
■Supports all power profiles
Low-Power Operation
■3.2 V to 5.5 V operation
■Sleep 1.3 mA, Deep Sleep 1.3 A[1]
Packages
■40-pin QFN
■16-pin SOIC
■35-ball wafer-level CSP (WLCSP)
Figure 1. CCG1 Block Diagram[2, 3, 4, 5, 6, 7]
Notes
1. Values measured for CCG1 silicon only. Application specific power numbers may be higher.
2. Timer, counter, pulse-width modulation block.
3. Serial communication block configurable as I2C.
4. Base band.
5. Termination resistor denoting a Downstream Facing Port (DFP).
6. Termination resistor denoting a Upstream Facing Port (UFP).
7. Termination resistor denoting an Electronically Marked Cable Assembly (EMCA).
Document Number: 001-93639 Rev. *K Page 2 of 31
CCG1 Datasheet
Contents
Functional Definitio n .............. ..........................................3
CPU and Memory Subsystem .....................................3
System Resources ......................................................3
GPIO ........................................................................... 3
Pin Definitions ..................................................................4
Pinouts ............................................................................10
Power ...............................................................................11
Electrical Specifications ................................................12
Absolute Maximum Ratings ....................................... 12
Device-Level Specifications ......................................12
Digital Peripherals ..................................................... 14
Memory .....................................................................15
System Resources ....................................................16
Applications in Detail .....................................................18
Ordering Information ......................................................23
Ordering Code Definitions ......................................... 23
Packaging ........................................................................24
Acronyms ........................................................................27
Document Conventions .................. ... ... .........................28
Units of Measure ....................................................... 28
Revision History .............................................................29
Sales, Solutions, and Legal Information ......................31
Worldwide Sales and Design Support ....................... 31
Products .................................................................... 31
PSoC® Solutions ...................................................... 31
Cypress Developer Community ................................. 31
Technical Support ..................................................... 31
Document Number: 001-93639 Rev. *K Page 3 of 31
CCG1 Datasheet
Functional Definition
CPU and Memory Subsystem
CPU
The Cortex-M0 CPU in the CCG1 is part of the 32-bit MCU
subsystem, which is optimized for low-power operation with
extensive clock gating. It mostly uses 16-bit instructions and
executes a subset of the Thumb-2 instruction set. This enables
fully compatible binary upward migration of the code to higher
performance processors such as the Cortex-M3 and M4, thus
enabling upward compatibility. The Cypress implementation
includes a hardware multiplier that provides a 32-bit result in one
cycle. It includes a nested vectored interrupt controller (NVIC)
block with 32 interrupt inputs and a Wakeup Interrupt Controller
(WIC). The WIC can wake the processor up from the Deep Sleep
mode, allowing power to be switched off to the main processor
when the chip is in the Deep Sleep mode. The Cortex-M0 CPU
provides a Non-Maskable Interrupt (NMI) input, which is made
available to the user when it is not in use for system functions
requested by the user.
The CPU also includes a debug interface, the serial wire debug
(SWD) interface, which is a 2-wire form of JTAG; the debug
configuration used for CCG1 has four break-point (address)
comparators and two watchpoint (data) comparators.
Flash
The CCG1 device has a flash module with a flash accelerator,
tightly coupled to the CPU to improve average access times from
the flash block. The flash block is designed to deliver 1 wait-state
(WS) access time at 48 MHz and 0-WS access time at 24 MHz.
The flash accelerator delivers 85% of single-cycle SRAM access
performance on average. Part of the flash module can be used
to emulate EEPROM operation if required.
SROM
A supervisory ROM that contains boot and configuration routines
is provided.
System Resources
Power System
The power system is described in detail in the section Power on
page 11. It provides assurance that voltage levels are as required
for each respective mode and either delay mode entry (on
power-on reset (POR), for example) until voltage levels are as
required for proper function or generate resets (Brown-Out
Detect (BOD)) or interrupts (Low Voltage Detect (LVD)). The
CCG1 operates with a single external supply over the range of
3.2 V to 5.5 V operation and has three different power modes:
Active, Sleep, and Deep Sleep; transitions between modes are
managed by the power system.
Serial Communication Blocks (SCB)
The CCG1 has one SCB, which can implement an I2C interface.
The hardware I2C block implements a full multi-master and slave
interface (it is capable of multimaster arbitration). This block is
capable of operating at speeds of up to 1 Mbps (Fast Mode Plus)
and has flexible buffering options to reduce interrupt overhead
and latency for the CPU. It also supports EZ-I2C that creates a
mailbox address range in the memory of the CCG1 and effec-
tively reduces I2C communication to reading from and writing to
an array in memory. In addition, the block supports an 8-deep
FIFO for receive and transmit which, by increasing the time given
for the CPU to read data, greatly reduces the need for clock
stretching caused by the CPU not having read data on time.
The I2C peripheral is compatible with the I2C Standard-mode,
Fast-mode, and Fast-mode Plus devices, as defined in the NXP
I2C-bus specification and user manual (UM10204). The I2C bus
I/O is implemented with GPIO in open-drain modes.
The CCG1 is not completely compliant with the I2C spec in the
following respects:
■GPIO cells are not overvoltage tolerant and, therefore, cannot
be hot-swapped or powered up independently of the rest of the
I2C system.
■Fast-mode Plus has an IOL specification of 20 mA at a VOL of
0.4 V. The GPIO cells can sink a maximum of 8 mA IOL with a
VOL maximum of 0.6 V.
■Fast-mode and Fast-mode Plus specify minimum Fall times,
which are not met with the GPIO cell; Slow strong mode can
help meet this spec depending on the Bus Load.
■When the SCB is an I2C Master, it interposes an IDLE state
between NACK and Repeated Start; the I2C spec defines Bus
free as following a Stop condition so other Active Masters do
not intervene but a Master that has just become activated may
start an Arbitration cycle.
■When the SCB is in the I2C Slave mode, and Address Match
on External Clock is enabled (EC_AM = 1) along with operation
in the internally clocked mode (EC_OP = 0), then its I2C
address must be even.
GPIO
The CCG1 has up to 30 GPIOs, which are configured for various
functions. Refer to the pinout tables for the definitions. The GPIO
block implements the following:
■Eight drive strength modes:
❐Analog input mode (input and output buffers disabled)
❐Input only
❐Weak pull-up with strong pull-down
❐Strong pull-up with weak pull-down
❐Open drain with strong pull-down
❐Open drain with strong pull-up
❐Strong pull-up with strong pull-down
❐Weak pull-up with weak pull-down
■Input threshold select (CMOS or LVTTL).
■Individual control of input and output buffer enabling/disabling
in addition to the drive strength modes.
■Hold mode for latching previous state (used for retaining I/O
state in Deep Sleep mode).
■Selectable slew rates for dV/dt related noise control to improve
EMI.
During power-on and reset, the I/O pins are forced to the disable
state so as not to crowbar any inputs and/or cause excess
turn-on current. A multiplexing network, known as a high-speed
I/O matrix, is used to multiplex between various signals that may
connect to an I/O pin.
Document Number: 001-93639 Rev. *K Page 4 of 31
CCG1 Datasheet
Pin Definitions
Tab l e 1 provides the pin definition for 35-Ball WLCSP for the Cable/EMCA application. Refer to Table 23 for part numbers to package
mapping.
Table 1. Pin Definitions for 35-b all WLCSP for EMCA Cable Application
Functional Pin Name CYPD1103-
35FNXIT
Balls Type Description
CC1_RX C4 I
CC1 control
0: TX enabled
z: RX sense
CC1_TX D7 O Configuration Channel 1
SWD_IO D1 I/O SWD I/O
SWD_CLK C1 I SWD clock
I2C_SCL B1 I/O I2C clock signal
I2C_SDA B2 I/O I2C data signal
XRES B6 I Reset
VCCD A7 POWER Regulated digital supply output. Connect a 1 to 1.6-µF capacitor. No
external source should be connected
VDDD C7 POWER Power supply for both analog and digital sections
VSSA B7 GND Analog ground
CC_VREF C5 I Data reference signal for CC lines
TX_U B3 O Signals for internal use only. The TX_U output signal should be
connected to the TX_M signal
TX_M B5 I –
TX_REF_IN D3 I Reference signal for internal use. Connect to TX_REF output via a
2.4K 1% resistor
TX_GND A3 I Connect to GND via 2K 1% resistor
TX_REF_OUT D4 O Reference signal generated by connecting internal current source to
two 1K external resistors
RA_DISCONNECT E4 O
Optional control signal to remove RA after assertion of VCONN
0: RA disconnected
1: RA connected
VCONN_DET C6 I
Local VCONN detection signal
0: VCONN is not locally applied
1: VCONN is locally applied
CC1_LPREF A5 I Reference signal for internal use. Connect to the output of resistor
divider from VDDD.
RA_FAR_DISCONNECT E5 O
Optional control signal to remove RA after assertion of VCONN (NC
for 2 chip/cable)
0: RA disconnected
1: RA connected
BYPASS D5 I Bypass capacitor for internal analog circuits
CC1_LPRX C3 I Configuration channel 1 RX signal for Low Power States
GPIO
A1, A2, A4, A6,
B4, C2, D2, D6,
E1, E2, E3, E6,
E7
– General-purpose I/Os
Document Number: 001-93639 Rev. *K Page 5 of 31
CCG1 Datasheet
Tab l e 2 provides the pin definitions for 40-pin QFN and 35-ball WLCSP for the notebook, tablet, smartphone, and monitor
applications. Refer to Table 23onpage23 for part numbers to package mapping.
Table 2. Pin Definitions for 4 0-QFN and 35-ball WLCSP for Notebook, Tablet, SmartPhone and Monitor Applications
Functional Pins CYPD
1122-40LQXI
Pins[8]
CYPD
1121-40LQXI
Pins[9]
CYPD
1131-35FNXIT
Balls[10] Type Description
MUXSEL_1 1 1D5 OExternal Data Mux Select signal 1
MUXSEL_2 2 2 D6 OExternal Data Mux Select signal 2
CC1_CTRL 33 D3 I/O
CC1 control
0: TX enabled
z: RX sense
CC2_CTRL 44 E4 I/O
CC2 control
0: TX enabled
z: RX sense
MUXSEL_3 55 E5 OExternal Data Mux Select signal 3
MUXSEL_4 6 6 E6 OExternal Data Mux Select signal 4
CS_P 7 7 E3 ICurrent Sensing Plus input
CS_M 8 8 E2 ICurrent Sensing Minus input I
VSS 9 9 – GND Ground
CC1 10 10 -I/O Configuration Channel 1
CC_SEL_REF_1 11 11 E1 OCC Reference Select signal
SWD_IO 12 12 D1 I/O SWD IO
SWD_CLK 13 13 C1 ISWD Clock
HOTPLUG_DET 14 14 C2 I/O HotPlug Detection for Display Port Alternate Mode
GPIO1 15 – – I/O General-purpose I/O
VSEL2 –15 – O Voltage Select signal 2 for selecting output voltage
GPIO2 16 – – I/O General-purpose I/O
GPIO3 17 – – I/O General-purpose I/O
IFAULT –17 – I
Current Fault Indication
0: No fault
1: Current fault
I2C_SCL 18 18 B1 I/O I2C Clock signal
I2C_SDA 19 19 B2 I/O I2C Data signal
I2C_INT 20 20 A2 OI2C Interrupt
CC_SEL_REF_2 21 21 A1 OCC Reference Select signal
CC1_RD 22 22 C3 O
Open Drain signal to connect RD to CC 1 line
z: RD not connected
0: RD connected for Monitor application
1: RD connected for Notebook application
CC1_RP 23 23 A5 O
Open Source signal to connect RP to CC 1 line
z: RP not connected
1: RP connected
Notes
8. Pinout for Notebook DRP application for 40-QFN.
9. Pinout for Monitor DRP application for 40-QFN.
10. Pinout for Notebook DRP application for 35-CSP.
Document Number: 001-93639 Rev. *K Page 6 of 31
CCG1 Datasheet
CC1_VCONN_CTRL 24 24 A4 O
Open Drain signal to control a PFET power switch
for VCONN on CC 1 line
0: VCONN switch closed
z: VCONN switch open
VBUS_DISCHARGE 25 25 A3 OSignal used for discharging VBUS line during
voltage change
CC2 26 26 B3 OConfiguration Channel 2
CC2_RD 27 27 A6 O
Open Drain signal to connect RD to CC 2 line
z: RD not connected
0: RD connected for Monitor application
1: RD connected for Notebook application
CC2_RP 28 28 B4 O
Open Source signal to connect RP to CC 2 line
z: RP not connected
1: RP connected
CC2_VCONN_CTRL 29 29 B5 O
Open Drain signal to control a PFET power switch
for VCONN on CC 2 line
0: VCONN switch closed
z: VCONN switch open
XRES 30 30 B6 IReset
VCCD 31 31 A7 POWER
Regulated digital supply output. Connect a 1 to
1.6-μF capacitor. No external source should be
connected
VDDD 32 32 C7 POWER Power supply for digital sections
VDDA 33 33 C7 POWER Power Supply for analog sections
VSSA 34 34 B7 GND Analog ground pin
VBUS_VMON 35 35 C4 IVBUS Overvoltage Protection monitoring signal
VBUS_VREF 36 36 C5 IVBUS reference signal for Overvoltage Protection
detection
VSEL1 –37 –OVoltage Select signal 1 for selecting the output
voltage
CC_SEL_REF_3 37 16 C6 OCC Reference Select signal
VBUS_C_CTRL 38 –D7
O
Full rail control signal for enabling/disabling
Consumer load FET
VBUS_OK –38 –VBUS_OK=1 - VBUS Voltage ok
VBUS_OK=0 - VBUS Overvoltage detected
CC_VREF 39 39 D4 IData reference signal for CC lines
VBUS_P_CTRL 40 40 E7 OFull rail control signal for enabling/disabling Provider
load FET
T able 2. Pin Definitions for 40-QFN and 35-ball WLCSP for Notebook, T ablet, SmartPhone and Monitor Applications (continued)
Functional Pins CYPD
1122-40LQXI
Pins[8]
CYPD
1121-40LQXI
Pins[9]
CYPD
1131-35FNXIT
Balls[10] Type Description
Notes
8. Pinout for Notebook DRP application for 40-QFN.
9. Pinout for Monitor DRP application for 40-QFN.
10. Pinout for Notebook DRP application for 35-CSP.
Document Number: 001-93639 Rev. *K Page 7 of 31
CCG1 Datasheet
Tab l e 3 provides the pin definition for 40-pin QFN for Notebook (DFP) application. Refer to Table 23 for part numbers to package
mapping.
Table 3. Pin Definitions for 40-Pin QFN for Notebook (DFP)
Functional Pin Name Active HIGH/
LOW Drive Mode CYPD
1134-40LQXI
Pins Type Description
MUXSEL_1 –Open drain, drives low 1OExternal Data Mux Select signal 1
MUXSEL_2 –Open drain, drives low 2OExternal Data Mux Select signal 2
CC1_CTRL –Analog input/Strong
drive (push pull) 3IO
CC1 control
0:Tx enabled
z: RX sense
CC2_CTRL –Analog input/Strong
drive (push pull) 4IO
CC2 control
0: TX enabled
z: RX sense
MUXSEL_3 –Open drain, drives low 5OExternal Data Mux Select signal 3
MUXSEL_4 –Open drain, drives low 6OExternal Data Mux Select signal 4
CS_P –Analog input 7 I Current Sensing Plus input
CS_M –Analog input 8 I Current Sensing Minus input
VSS –– 9 GND Ground
CC1 –Strong drive (push pull) 10 O Configuration Channel 1
CC1_RP_1.5 Active HIGH Open drain, drives high 11 O
Open Drain signal to connect RP to CC1
line (1.5A current)
z: RP not connected
1: RP connected
SWD_IO ––12IOSWD IO
SWD_CLK –– 13 I SWD Clock
CC1_RP_3.0 Active HIGH Open drain, drives high 14 O
Open Source signal to connect RP to
CC1 line (3A current)
z: RP not connected
1: RP connected
CC1_RP_DEF Active HIGH Open drain, drives high 15 O
Open Drain signal to connect RP to CC1
line (Default cu rrent )
z: RP not connected
1: RP connected
CC2_RP_DEF Active HIGH Open drain, drives high 16 O
Open Drain signal to connect RP to CC2
line (Default cu rrent )
z: RP not connected
1: RP connected
CC2_RP_1.5 Active HIGH Open drain, drives high 17 O
Open Drain signal to connect RP to CC2
line (1.5A current)
z: RP not connected
1: RP connected
I2C_SCL Active LOW Open drain, drives low 18 IO I2C Clock signal
I2C_SDA Active LOW Open drain, drives low 19 IO I2C Data signal
Document Number: 001-93639 Rev. *K Page 8 of 31
CCG1 Datasheet
I2C_INT Active LOW Open drain, drives low 20 O I2C Interrupt
CC2_RP_3.0 Active HIGH Open drain, drives high 21 O
Open Source signal to connect RP to
CC2 line (3A current)
z: RP not connected
1: RP connected
CC1_LPRX –Analog input 22 I Configuration channel 1 RX signal for
Low Power states
CC1_LPREF –Analog input 23 I Reference signal for internal use.
CC2_LPRX –Analog input 24 I Configuration channel 2 RX signal for
Low Power states
CC2_LPREF –Analog input 25 I Reference signal for internal use.
CC2 –Strong drive (push pull) 26 O Configuration Channel 2
CC1_VCONN_CTRL Active LOW Open drain, drives low 27 O
Open Drain signal to control a PFET
power switch for VCONN on CC1 line
0: VCONN switch closed
z: VCONN switch open
CC2_VCONN_CTRL Active LOW Open drain, drives low 28 O
Open Drain signal to control a PFET
power switch for VCONN on CC2 line
0: VCONN switch closed
z: VCONN switch open
IFAULT Active HIGH Digital input 29 I Current Fault Indication on VBUS
0: No fault
1: Over Current fault
XRES Active LOW Analog input 30 I Reset
VCCD ––31POWER
Connect 1uf Capacitor between VCCD
and Ground
VDDD –– 32 POWER 5-V Supply
VDDA –– 33 POWER 5-V Supply
VSSA –– 34 GND –
E-PAD –– E-PAD GND –
VBUS_VMON –Analog input 35 I VBUS Over-voltage Protection
monitoring signal
VBUS_VREF –Analog input 36 I VBUS reference signal for Over-voltage
Protection detection
VBUS_P_CTRL Active HIGH Strong drive (Push Pull) 37 O Full rail control signal for
enabling/disabling Provider load FET
HOTPLUG_DET Active HIGH Open drain, drives low 38 IO HotPlug Detection for Display Port
Alternate Mode
CC_VREF/
VBUS_DISCHARGE -/Active
HIGH
Analog input/Strong
drive (Push Pull) 39 IO Data reference signal for CC lines /
Signal used for discharging VBUS line
during voltage change
MUXSEL_5 –Open drain, drives low 40 O External Data Mux Select signal 5
Table 3. Pin Definitions for 40-Pin QFN for Notebook (DFP) (continued)
Functional Pin Name Active HIGH/
LOW Drive Mode CYPD
1134-40LQXI
Pins Type Description
Document Number: 001-93639 Rev. *K Page 9 of 31
CCG1 Datasheet
Tab l e 4 provides the pin definition for 16-pin SOIC for the Power Adapter application. Refer to Table 23 on page 23 for part numbers
to package mapping.
Table 4. Pin Definitions for 16-pin SOIC for Power Adap ter Application
Functional Pin Name CYPD
1132-16SXI
Pins Type Description
SWD_CLK 1 I SWD Clock
VBUS_P_CTRL 2 O Full rail control signal for enabling/disabling provider load FET
VBUS_VMON 3 I VBUS over-voltage protection monitoring signal
VBUS_VREF 4 I VBUS reference signal for over-voltage protection detection
XRES 5 – Active Low Reset
VCCD 6 – Connect 1 µF capacitor between VCCD and GROUND
VSSD 7 – Ground
VDDD 8 – Power 3.3 V/5 V
VSSA 9 – Ground
CC_VREF/VBUS_DISCHARGE 10 I/O Data reference signal for CC line (0.55 Volt) / Signal used for
discharging VBUS line during voltage decrease
CC_CTRL 11 I/O
CC1 control
0: TX enabled
z: RX sense
CS 12 I Low Side Current Sense
VSEL1 13 O Voltage select signal for selecting the output voltage 5/12/20 V
VSEL2 14 O Voltage select signal for selecting the output voltage 5/12/20 V
CC 15 I/O Configuration Channel TX/RX
SWD_IO 16 I/O SWD I/O
Document Number: 001-93639 Rev. *K Page 10 of 31
CCG1 Datasheet
Pinouts
Figure 2. Pinout for CYPD1122-40LQXI/CYPD1121-40LQXI
Figure 3. Pinout for CYPD1134-40LQXI
Figure 4. Pinout for CYPD1132-16SXI
QFN
(To p View)
10
30
29
28
27
26
25
24
23
22
21
2
3
4
5
6
7
8
9
SWD_CLK
MUXSEL_2
CC2_CTRL
MUXSEL_3
CS _P
CS_M
VSS
CC_SEL_REF_1
SWD_IO
GPIO1/VSEL2
GPIO2/CC_SEL_REF_3
GPIO3/iFAULT
I2C_SCL
I2C_SDA
I2C_INT
CC_SEL_REF_2
CC1_RD
VDDD
CC1_RP
CC1_VCONN _CTRL
VBUS _DISCHARGE
CC2
CC2_RD
CC2_VCONN _CTRL
XRES
HOTPLUG_DET
VDDA
VSSA
1
VBUS_VMON
VBUS_VREF
CC_SEL_REF_3/VSEL1
VBUS_C_CTRL/VBUS_OK
CC_VREF
VBUS_P_CTRL
VCCD
CC1
MUXSEL_1
CC1_CTRL CC2_RP
MUXSEL_4
20
19
18
17
16
15
14
13
12
11
31
32
33
34
35
36
37
38
39
40
QFN
(Top View)
10
30
29
28
27
26
25
24
23
22
21
2
3
4
5
6
7
8
9
SWD_CLK
MUXSEL_2
CC2_CTRL
MUXSEL_3
CS _P
CS_M
VSS
CC1_RP_1.5
SWD_IO
CC1_RP_DEF
CC2_RP_DEF
CC2_RP_1.5
I2C _SCL
I2C _SDA
I2C _IN T
CC2_RP_3.0
CC1_LPRX
VDDD
CC1_LPREF
CC2_LPRX
CC2_LPREF
CC2
CC1_VCONN _CTRL
IFAULT
XRES
CC1_RP_3.0
VDDA
VSSA
1
VBUS_VMON
VBUS_VREF
VBUS_P_CTRL
HOT PLUG_D ET
CC_VREF/VBUS_DISCHARGE
MUXSEL_5
VCCD
CC1
MUXSEL_1
CC1_CTRL CC2_VCONN _CTRL
MUXSEL_4
20
19
18
17
16
15
14
13
12
11
31
32
33
34
35
36
37
38
39
40
SOIC
(Top View)
16 SWD_IO
15 CC
VSEL2
14
13 VSEL1
CS
12
11 CC_CTRL
CC_VREF/VBUS_DISCHARGE
10
VSSA
9
8
VDDD
1SWD_CLK
VBUS_P_CTRL 2
3
VBUS_VMON
4
VBUS_VREF
5
XRES
6
VCCD
7
VSSD
Document Number: 001-93639 Rev. *K Page 11 of 31
CCG1 Datasheet
Figure 5. Pinout for CYPD1103-35FNXIT/CYPD1131-FNXIT
Power
The following power system diagram shows the minimum set of
power supply pins as implemented for the CCG1. The system
has one regulator in Active mode for the digital circuitry. There is
no analog regulator; the analog circuits run directly from the
VDDA input. There is a separate regulator for the Deep Sleep
mode. There is a separate low-noise regulator for the bandgap.
The supply voltage range is 3.2 V to 5.5 V with all functions and
circuits operating over that range.
VDDA and VDDD must be shorted together; the grounds, VSSA
and VSS must also be shorted together. Bypass capacitors must
be used from VDDD to ground. The typical practice for systems
in this frequency range is to use a capacitor in the 1-µF range in
parallel with a smaller capacitor (0.1 µF, for example). Note that
these are simply rules of thumb and that, for critical applications,
the PCB layout, lead inductance, and the bypass capacitor
parasitic should be simulated to design and obtain optimal
bypassing.
Refer to Application Diagrams for bypassing schemes.
GPIO/
CC2_RD
XRES
654321
A
B
C
D
E
VCCD
VSSA
7
GPIO/
CC1_VCO
NN_CTRL
GPIO/
CC2_RP
CC1_LPRE
F/CC1_RP
TX_M/
CC2_VCON
N_CTRL
VCONN_D
ET/
CC_SEL_R
EF_3
GPIO/
MUXSEL_2
VDDD/
VDDA
CC1_TX/
VBUS_C_C
TRL
CC1_RX/
VBUS_VMO
N
TX_REF_O
UT/
CC_VREF
CC_VREF/
VBUS_VRE
F
BYPASS/
MUXSEL_1
GPIO/
MUXSEL_4
GPIO/
VBUS_P_C
TRL
RA_DISCO
NNECT/
CC2_CTRL
RA_FAR_D
ISCONNEC
T/
MUXSEL_3
GPIO/
I2C_INT
I2C_SDA
TX_GND/
VBUS_DIS
CHARGE
TX_U/
CC2
GPIO/
HOTPLUG_
DET
GPIO
CC1_LPRX/
CC1_RD
TX_REF_IN
/CC1_CTRL
GPIO/
CS_M
GPIO/
CS_P
GPIO/
CC_SEL_R
EF_2
I2C_SCL
SWD_CLK
SWD_IO
GPIO/
CC_SEL_R
EF_1
Document Number: 001-93639 Rev. *K Page 12 of 31
CCG1 Datasheet
Electrical Specifications
Absolute Maximum Ratings
Device-Level Specifications
All specifications are valid for –40 °C TA 85 °C and TJ 100 °C for 35-CSP and 40-QFN package options. Specifications are valid
for –40 °C TA 105 °C and TJ 120 °C for 16-SOIC package options. Specifications are valid for 3.2 V to VDD’s maximum value,
depending on the type of application.
Note
11. Usage above the absolute maximum conditions listed in Tab le 5 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended
periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification.
Table 5. Absolute Maximum Ra tings[11]
Spec ID Parameter Description Min Typ Max Units Details/
Conditions
SID1 VDDD_ABS Digital supply relative to VSSD –0.50 – 6.00 V Absolute max
SID2 VCCD_ABS
Direct digital core voltage input
relative to VSSD
–0.50 – 1.95 V Absolute max
SID3 VGPIO_ABS GPIO voltage –0.50 – VDDD+0.50 V Absolute max
SID4 IGPIO_ABS Maximum current per GPIO –25.00 – 25.00 mA Absolute max
SID5 IGPIO_injection
GPIO injection current, Max for VIH >
VDDD, and Min for VIL < VSS
–0.50 – 0.50 mA Absolute max, current
injected per pin
BID44 ESD_HBM Electrostatic discharge human body
model 2200.00 – – V –
BID45 ESD_CDM Electrostatic discharge charged
device model 500.00 – – V –
BID46 LU Pin current for latch-up –200.00 – 200.00 mA –
Table 6. DC Specifications
Spec ID Parameter Description Min Typ Max Units Details/
Conditions
SID53 VDDD Power supply input voltage 3.20 – 5.20 V Notebook, tablet, monitor and
power adapter applications
SID53_A VDDD Power supply input voltage 3.20 – 5.50 V EMCA applications
SID54 VCCD Output voltage (for core logic) – 1.80 – V –
SID55 CEFC External regulator voltage bypass 1.00 1.30 1.60 μF X5R ceramic or better
SID56 CEXC Power supply decoupling capacitor – 1.00 – μF X5R ceramic or better
Active Mode, VDDD = 3.2 to 5.5 V. Typical values measured at VDD = 3.3 V.
SID19 IDD14 Execute from flash; CPU at 48 MHz – 12.80 – mA T = 25 °C
SID20 IDD15 Execute from flash; CPU at 48 MHz – – 13.80 mA –
Sleep Mode, VDDD = 3.2 to 5.5 V –
SID25A IDD20A I2C wakeup and comparators on – 1.70 2.2 0 mA –
Deep Sleep Mode, VDDD = 3.2 to 3.6 V (Regulator on)
SID31 IDD26 I2C wakeup on – 1.30 – μA T = 25 °C, 3.6 V
SID32 IDD27 I2C wakeup on – – 50.00 μA T = 85 °C
Deep Sleep Mode, VDDD = 3.6 to 5.5 V
SID34 IDD29 I2C wakeup – 15.00 – μA T = 25 °C, 5 V
XRES Current
SID307 IDD_XR Supply current while XRES asserted – 2.00 5.00 mA –
Document Number: 001-93639 Rev. *K Page 13 of 31
CCG1 Datasheet
I/O
Table 7. AC Specifications
Spec ID Parameter Description Min Typ Max Units Details/
Conditions
SID48 FCPU CPU frequency DC – 48.00 MHz 3.2 VDD 5.5
SID49 TSLEEP Wakeup from sleep mode – 0.00 – µs Guaranteed by
characterization
SID50 TDEEPSLEEP Wakeup from Deep Sleep mode – – 25.00 µs
24-MHz IMO.
Guaranteed by
characterization
SID52 TRESETWIDTH External reset pulse width 1.00 – – µs Guaranteed by
characterization
Note
12. VIH must not exceed VDDD + 0.2 V.
Table 8. I/O DC Specifications
Spec ID Parameter Description Min Typ Max Units Details/
Conditions
SID57 VIH[12] Input voltage high threshold 0.70 ×
VDDD
– – V CMOS Input
SID58 VIL Input voltage low threshold – – 0.30 ×
VDDD
V CMOS Input
SID243 VIH[12] LVTTL input 2.00 – – V –
SID244 VIL LVTTL input – – 0.80 V –
SID59 VOH Output voltage high level VDDD
–0.60 –– VI
OH = 4mA at 3V V
DDD
SID62 VOL Output voltage low level – – 0.60 V IOL = 8mA at 3V V
DDD
SID62A VOL Output voltage low level – – 0.40 V IOL = 3mA at 3V V
DDD
SID63 RPULLUP Pull-up resistor 3.50 5.60 8.50 kΩ–
SID64 RPULLDOWN Pull-down resistor 3.50 5.60 8.50 kΩ–
SID65 IIL Input leakage current (absolute value) – – 2.00 nA 25 °C, VDDD = 3.0 V
SID65A IIL_CTBM
Input leakage current (absolute value)
for analog pins – – 4.00 nA –
SID66 CIN Input capacitance – – 7.00 pF –
SID67 VHYSTTL Input hysteresis LVTTL 15.00 40.00 – mV
VDDD 2.7 V.
Guaranteed by charac-
terization
SID68 VHYSCMOS Input hysteresis CMOS 200.00 – – mV
VDDD 4.5 V.
Guaranteed by charac-
terization
SID69 IDIODE
Current through protection diode to
VDD/VSS
– – 100.00 μAGuaranteed by charac-
terization
SID69A ITOT_GPIO
Maximum Total Source or Sink Chip
Current – – 200.00 mA Guaranteed by charac-
terization
Table 9. I/O AC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/
Conditions
SID70 TRISEF Rise time 2.00 – 12.00 ns 3.3-V VDDD, Cload = 25 pF
SID71 TFALLF Fall time 2.00 – 12.00 ns 3.3-V VDDD, Cload = 25 pF
Document Number: 001-93639 Rev. *K Page 14 of 31
CCG1 Datasheet
XRES
Digital Peripherals
The following specifications apply to the Timer/Counter/PWM peripherals in the Timer mode.
Pulse Width Modulation (PWM) for VSEL and CUR_LIM Pins
Table 10. XRES DC Specifications
Spec ID Parameter Description Min Typ Max Units Details/
Conditions
SID77 VIH Input voltage high threshold 0.70 × VDDD –– VCMOS input
SID78 VIL Input voltage low threshold – – 0.30 × VDDD VCMOS input
SID79 RPULLUP Pull-up resistor 3.50 5.60 8.50 kΩ–
SID80 CIN Input capacitance – 3.00 – pF –
SID81 VHYSXRES Input voltage hysteresis – 100.00 – mV Guaranteed by
characterization
SID82 IDIODE
Current through protection diode to
VDDD/VSS
– – 100.00 µA Guaranteed by
characterization
Table 11. PWM AC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/
Conditions
SID140 TPWMFREQ Operating frequency – – 48.00 MHz –
SID141 TPWMPWINT Pulse width (internal) 42.00 – – ns –
SID142 TPWMEXT Pulse width (external) 42.00 – – ns –
SID143 TPWMKILLINT Kill pulse width (internal) 42.00 – – ns –
SID144 TPWMKILLEXT Kill pulse width (external) 42.00 – – ns –
SID145 TPWMEINT Enable pulse width (internal) 42.00 – – ns –
SID146 TPWMENEXT Enable pulse width (external) 42.00 – – ns –
SID147 TPWMRESWINT Reset pulse width (internal) 42.00 – – ns –
SID148 TPWMRESWEXT Reset pulse width (external) 42.00 – – ns –
Document Number: 001-93639 Rev. *K Page 15 of 31
CCG1 Datasheet
I2C
Memory
Table 12. Fixed I2C DC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID149 II2C1 Block current consumption at 100 kHz – – 50 µA–
SID150 II2C2 Block current consumption at 400 kHz – – 135.00 µA–
SID151 II2C3 Block current consumption at 1 Mbps – – 310.00 µA–
SID152 II2C4 I2C enabled in Deep Sleep mode – – 1.40 µA–
Table 13. Fixed I2C AC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID153 FI2C1 Bit rate – – 1.00 Mbps –
Table 14. Flash DC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID173 VPE Erase and program voltage 3.20 – 5.50 V –
Notes
13. It can take as much as 20 milliseconds to write to flash. During this time the device should not be Reset, or flash operations will be interrupted and cannot be relied
on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.
Make certain that these are not inadvertently activated.
14. Cypress provides a retention calculator to calculate the retention lifetime based on customers' individual temperature profiles for operation over the –40 °C to +105 °C
ambient temperature range. Contact customercare@cypress.com.
Table 15. Flash AC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID174 TROWWRITE[13] Row (block) write time (erase and
program) – – 20.00 ms Row (block) =
128 bytes
SID175 TROWERASE[13] Row erase time – – 13.00 ms –
SID176 TROWPROGRAM[13] Row program time after erase – – 7.00 ms –
SID178 TBULKERASE[13] Bulk erase time (32 KB) – – 35.00 ms –
SID180 TDEVPROG[13] Total device program time – – 7.00 seconds Guaranteed by
characterization
SID181 FEND Flash endurance 100 K – – cycles Guaranteed by
characterization
SID182 FRET[14] Flash retention. TA 55 °C, 100 K P/E
cycles 20 – – years Guaranteed by
characterization
SID182A – Flash retention. TA 85 °C, 10 K P/E
cycles 10 – – years Guaranteed by
characterization
SID182B – Flash retention. 85 °C < TA < 105 °C,
10K P/E cycles 3– –years
Guaranteed by
characterization
Document Number: 001-93639 Rev. *K Page 16 of 31
CCG1 Datasheet
System Resources
Power-on-Reset (POR) with Brown Out
SWD Interface
Internal Main Oscillator
Table 16. Imprecise Power On Reset (PRES)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID185 VRISEIPOR Rising trip voltage 0.80 – 1.45 V Guaranteed by characterization
SID186 VFALLIPOR Falling trip voltage 0.75 – 1.40 V Guaranteed by characterization
SID187 VIPORHYST Hysteresis 15.0 – 200.0 mV Guaranteed by characterization
Table 17. Precise Power On Reset (POR)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID190 VFALLPPOR
BOD trip voltage in active and
sleep modes 1.64 – – V Guaranteed by characterization
SID192 VFALLDPSLP BOD trip voltage in Deep Sleep 1.40 – – V Guaranteed by characterization
Table 18. SWD Interfa ce Specification s
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID213 F_SWDCLK1 3.2 V VDDD 5.5 V – – 14.00 MHz SWDCLK ≤1/3 CPU clock
frequency
SID215 T_SWDI_SETUP T = 1/f SWDCLK 0.25 × T – – ns Guaranteed by characterization
SID216 T_SWDI_HOLD T = 1/f SWDCLK 0.25 × T – – ns Guaranteed by characterization
SID217 T_SWDO_VALID T = 1/f SWDCLK – – 0.50*T ns Guaranteed by characterization
SID217A T_SWDO_HOLD T = 1/f SWDCLK 1 – – ns Guaranteed by characterization
Table 19. IMO DC Specifications
(Guaranteed by Design)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID218 IIMO1 IMO operating current at 48 MHz – – 1000.00 µA–
Table 20. IMO AC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID223 FIMOTOL1 Frequency variation – – ±2.00 % With API-called calibration
SID226 TSTARTIMO IMO startup time – – 12.00 µs –
SID229 TJITRMSIMO3 RMS Jitter at 48 MHz – 139.00 – ps –
Document Number: 001-93639 Rev. *K Page 17 of 31
CCG1 Datasheet
Internal Low-Speed Oscillator
Table 21. ILO DC Specifications
(Guaranteed by Design)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID231 IILO1 ILO operating current at 32 kHz – 0.30 1.05 µA Guaranteed by characterization
SID233 IILOLEAK ILO leakage current – 2.00 15.00 nA Guaranteed by design
Table 22. ILO AC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID234 TSTARTILO1 ILO startup time – – 2.00 ms Guaranteed by characterization
SID236 TILODUTY ILO duty cycle 40.00 50.00 60.00 % Guaranteed by characterization
SID237 FILOTRIM1 32-kHz trimmed frequency 15.00 32.00 50.00 kHz ±60% with trim
Document Number: 001-93639 Rev. *K Page 18 of 31
CCG1 Datasheet
Applications in Detail
Figure 6. Single Chip/Cable, Component Count = 19
Document Number: 001-93639 Rev. *K Page 19 of 31
CCG1 Datasheet
Figure 7. Two Chip/Cable, Component Count = 15/paddle
Figure 8. 16-pin SOIC Power Adapter Application Diagram
CYPD1103-35FNXI
35CSP
VCONN 1
VBUS
CC
VDDD
Type-C Plug
1uF
VCCD
VSSA
CC_VREF
XRES
SWD_
IO
SWD_
CLK
I2C_
SCL
I2C_
SDA
TX_REF_OUT
2k1%
TX_GND
TX_REF_IN
CC1_RX

TX_M
TX_U
CC1_TX
221%
Type-C Plug
VCONN 2

1% Ra
VCONN_DET
1uF
CC1_LPRX
100k1%12.4k1%
CC1_LPREF
TF412S
100k
10%
D
G
S
RA_DISCONNECT
806
1% Ra
TF412S
100k
10%
D
G
S
2.4k1%2.2nf
2k1%
BYPASS
47pF
CYPD1103-35FNXI
35CSP
VDDD
1uF
VCCD
VSSA
CC_VREF
XRES
SWD_
IO
SWD_
CLK
I2C_
SCL
I2 C_
SDA
TX_REF_OUT
2k1%
TX_GND
TX_REF_IN
CC1_RX

TX_M
TX_U
CC1_TX
221%
VCONN_DET
1uF
CC1_LPRX
100k1%12.4k1%
CC1_L PREF
RA_DISCONNECT
2.4k1%
2.2n f
2k1%
BYPASS
47pF
VBUS
CC
GND GND
SuperSpeed and HighSpeed Lines SuperSpeed and HighSpeed Lines
C5
C4
D7
B3
B5
D3
A3
D4
C3
C5
C4
D7
B3
B5
D3
A3
D4
C3
C7
A5
C7A5
A7
B7
B6
C6
E4
D5
A7
B7
B6
C6
E4
D5
D1 C1
B1 B2 D1 C1B1 B2
GG
NTNS31 64NZ NTNS3164NZ
RA_FAR_DISCONNECT
E5 RA_FAR_DISCONNECT
E5
D
S
D
S
GPIO
A1, A2, A4, A6, B4, C2, D2,
D6, E1, E2, E3, E6, E7 GPIO
A1, A2, A4, A6, B4, C2, D2,
D6, E1, E2, E3, E6, E7
CYPD1132-16SXI
16SOIC
VBUS_P_CTRL
CC
1uF
VCCD
CC_CTRL
VDDD
SWD_IO
84.51%
51.11% 4.7nF
16
SWD_CLK
1
VSEL1
13
68
XRES
5
15
11
2
5-20 Volts
From
Secondary
Side
VSSA
9
5.6K 1%
VBUS_VMON
VBUS_VREF
34
VBUS
VBUS_DISCHARGE/
CC_VREF
10
100k1%
10k1%
21.5k1%
3.3V
VBUS_DISCHARGE
MGSF1N03L
3.3v
1uF
To
Primary
Side
49.9k
1% G
S
PFET
DMG7401SFG-7
D
D
S
G
0.1uF
0.1uF
VSSD
7
CS
12
VSEL2
14
3.9k1%
MGSF1N03LT1G
NFET
100
1%
VBUS_DISCHARGE
10uF
MGSF1N03L
NFET
1k1%
100k
VBUS VSEL1 VSEL2
5V 0 0
12V 0 1
19.6V 1 0
0.1uF
Rsense
10 m
Sense Resistor on the
return path of Secondary Select
NFET
with Vth
> 1V
Rp
CC
4.7k 1%
3.3v
330pF
3.3v
NTS3164NZ
CCG1 supports up to 2.2kV ESD
protection. If higher protection is
required, add external ESD.
Document Number: 001-93639 Rev. *K Page 20 of 31
CCG1 Datasheet
Figure 9. Notebook (DRP) Application Diagram
CYPD1122-40LQXI
40QFN
Rp Rd
NFET
PFET
CC1
CC2
CC1_VCONN_ CTRL
CC1_RP
CC1_RD
CC2_RP
CC2_RD
CC2_VCONN_CTRL
VBUS_P_CTRL
I2C_SCL
CC1
CC2
1uF
VC CD
Type C
Receptacle
HS/SS/
DP/SBU
Lines
CC1_CTRL
VDDD
VDD A
20
10k1%
5.1k
10%
SWD_IO
2871%
80.61% 2.2nF
CC2_CTRL
1M, 5%
I2C_SDA
19
12
SWD_CLK
13
MUXSEL_3
MUXSEL_1
5
1
MUXSEL_2
2
31 3233
10
3
26
4
22
23
24
40
29
27
28
CS_P
7
GPIO2
16
CS_M
8
VBUS_DISCHARGE
25
VSS
VSS A
349
VBUS_VMON
VBUS_VREF
10k1%
3.9k1%
35 36
VBUS
XRES
30
0.1 uF
I2C_INT
18
VB US _C _CTR L/ VBU S_ OK
38
100k1%
10k1%
To System
From
System
MUXSEL_4
6
Embedded
Controller
HS/SS/DP
Mux
HS
SS/DP0/1
DP2/3
AUX+/-
MUXSEL_x
5V
D
G
S
G
S
PFET
D
NFET
D
S
G
D
G
S
G
S
PFET
D
D
S
G
5 Volts
0.2 1%
CS_P
CS_M
CC_VREF
39
21.5k1%
5 Volts
D
G
S
VDDD = 5V
VDDD
NFET
1001% 1W
VBUS_DISCHARGE
D
S
G
D
S
G
PFET
10k1%
2871%
80.61% 2.2n F
D
S
G
Rp 10k
1%
Rd
1M, 5%
D
G
S
VDDD 5.1k
10%
S
D
G
S
D
G
NFET
330pF
HOTPLUG_DET
14
GPIO1
15
GPIO3
17
DisplayPort
Chipset
HPD
DP0/1/2/3
AUX+/-
HPD
USB
Chipset
HS
SS
VBUS_DISCHARGE
CS_P
CS_M
1uF0.1 uF
NFET
NFET
D
G
S
VDDD
330pF
NFET
D
G
S
VDDD
NFET
50k
5%
50k
5%
CC_SEL_REF_3
37
CC_SEL_REF_1
11
CC_SEL_REF_2
21
4.1 k
1%
3.16k
1%
2.3 2k
1%
Select
NFET
with Vth
> 1V
Document Number: 001-93639 Rev. *K Page 21 of 31
CCG1 Datasheet
Figure 10. Notebook (DFP) Applic a t io n Diag ram
CYPD1134-40LQXI
40QFN
22k1%
PFET
CC1
CC2
CC1_VCONN_CTRL
CC1_RP_1.5
CC2_VCONN_CTRL
VB US _P_C TRL
0.0 21%
I2C_SCL
CC1
CC2
1uF
VCCD
Type C
Recep tacle
HS/SS/
DP/SBU
Lines
CC1_CTRL
VDD D
VDDA
20
10k1%
SWD_IO
2871%
80.61% 2.2nF
CC2_CTRL
I2C_SDA
19
12
SWD_CLK
13
MUXSEL_3
MUXSEL_1
5
1
MUXSEL_2
2
31 3233
10
3
26
4
15
11
2737
28
CS_P
7
CS_M
8
VSS
VSSA
349
VB US _VM ON
VBUS_VREF
3.9k1%
35 36
VBUS
XRES
30
0.1uF
I2C_INT
18
100k1%
10k1%
Current Monitor
+ Comparator
iFAULT
From
System
MUXSEL_4
6
Embedded
Controller
HS/SS/DP
Mux
HS
SS/DP0/1
DP2/3
AUX+/-
MUXSEL_x
5V
NFET
D
S
G
D
G
S
G
S
PFET
D
5 Volts
0.2 1%
CS_P
CS_M
CC_VREF/
VB US_DISCHARGE
39
21.5k1%
3.42k1%
5 Volts
VDDD = 5V
NFET
1001% 1W
VB US_DISCHA RGE
D
S
G
D
S
G
PFET
10k1%
2871%
80.61% 2.2nF
D
S
G
D
G
S
VDDD
390pF
MUXSEL_5
40
HOTPLUG_DET
38
iFAULT
29
DisplayPort
Chipset
HPD
DP0/1/2/3
AUX+/-
HPD
USB
Chipset
HS
SS
iFAULT
CS_P
CS_M
1uF0.1u F
NFET
D
G
S
VDDD
390pF
NFET
50k
5%
CC 1_ RP _DE F
10k1%
56k1%
CC1_RP_3.0 14
22k1%
CC2_RP_1.5
16
17
CC2_RP_DEF
10k1%
56k1%
CC2_RP_3.0 21
VB US_DISCHARGE
CC1_LPREF
CC2_LPREF
2523
CC2_LPRX 24
CC1_LPRX 22
Select
NFET
with Vth
> 1V
Document Number: 001-93639 Rev. *K Page 22 of 31
CCG1 Datasheet
Figure 11. Monitor Application Block Diagram
CYPD1121-40LQXI
40QFN
Rp
Rd
PFET
CC1
CC2
CC1_VCONN_CTRL
CC1_RP
CC1_RD
CC2_RP
CC2_RD
CC2_VCONN_CTRL
VBUS_P_CTRL
I2C_ SCL
CC1
CC2
1uF
VCCD
Type C
Recep tacle
HS/SS/
DP/SBU
Lines
CC1_CTRL
VDDD
VDD A
20
10k1%
5.1k
1%
SWD_IO
2871%
80.61% 2.2nF
CC2_CTRL
I2C_ SDA
19
12
SWD_CLK
13
MUXSEL_3
MUXSEL_1
5
1
MUXSEL_2
2
31 3233
10
3
26
4
22
23
24
40
29
27
28
CS_ P
7
CS_M
8
VBUS_DISCHARGE
25
VSS
VSS A
349
VB US _ VM ON
VBUS_VREF
10k
1%
3.9k1%
35 36
VBUS
XRES
30
0.1uF
I2C_ INT
18
VBUS_C_CTRL/VBUS_OK
38
100k1%
10k1%
MUXSEL_4
6
VSEL1
37
Embedded
Controller
HS/SS/DP
Mux
HS
SS/DP0/1
DP2/3
AUX+/-
MUXSEL_x
5/12/20V
NFET
D
S
G
D
G
S
G
S
PFET
D
5 Volts
0.21%
CS_P
CS_ M
CC_VREF
39
21.50k1%
5 Volts
D
G
S
VDDD = 5V
VDDD
NFET
1001% , 1W
VBUS_DISCHARGE
D
S
G
D
S
G
PFET
10k
2871%
80.61% 2.2nF
D
S
G
Rp 10k
1%
Rd
D
G
S
VDDD
5.1k
1%
330pF
330pF
HOTPLUG_DET
14
VSEL2
15
iFAULT
17
DC/DC
REG
DC In p ut
VBUS VSEL1 VSEL2
5V 00
12V 01
19.6V 10
0V 11
DisplayPort
Chipset
HPD
DP0 /1/2/3
AUX+/-
USB
Chipset
HS
SS
HPD
1uF0.1u F
CS_P
CS_M
VBUS_
DISCHA RGE
NFET
NFET
50k
5%
C C_S E L_R EF _3
16
C C_S E L_R EF _1
11
C C_S E L_R EF _2
21
4.1k
1%
3.16k
1%
2.32k
1%
Select
NFET
with Vth
> 1V
Document Number: 001-93639 Rev. *K Page 23 of 31
CCG1 Datasheet
Ordering Information
The CCG1 part numbers and features are listed in the following table.
Ordering Code Definitions
Table 23. CCG1 Ordering Information
Part Number[15] Application Type-C
Ports[16] Overcurrent
Protection Overvoltage
Protection Termination
Resistor[17] Role[18] Package Si ID
CYPD1103-35FNXIT Cable, EMCA 1 No No Ra[19] Cable 35-WLCSP[20] 0490
CYPD1131-35FNXIT
Notebook,
Ta b le t,
Smartphone
1Yes YesR
p[23], Rd[21] DRP[24] 35-WLCSP[22] 0491
CYPD1121-40LQXI Monitor 1 Yes Yes Rp[23], Rd[21] DRP[24] 40-QFN 0489
CYPD1122-40LQXI Notebook 1 Yes Yes Rp[23], Rd[21] DRP[24] 40-QFN 048A
CYPD1134-40LQXI Notebook,
Desktop 1Yes YesR
p[23] DFP 40-QFN 048B
CYPD1132-16SXI Power Adapter 1 Yes Yes Rp[23] DFP 16-SOIC 0498
CYPD1132-16SXQ Power Adapter 1 Yes Yes Rp[23] DFP 16-SOIC 0498
CY
Marketing Code: PD = Power delivery product family
PD
Number of Type-C Ports: 1 = 1 Port, 2 = 2 Port
Product Type: 1 = First-generation product family, CCG1
Company ID: CY = Cypress
X
Number of pins in the package
Package Type: LQ = QFN, FN = CSP, S = SOIC
XX
XX XX
Lead: X = Pb-free
-X
XX
0X: OCP and OVP not supported, 1X: reserved,
2X, 3X: OCP and OVP supported
Temperature Range: I = Industrial, Q = Extended industrial
X
T = Tape and reel for CSP, N/A for other packages
Notes
15. All part numbers support: Input voltage range from 3.2 V to 5.5 V. Industrial parts support -40 °C to +85 °C, Extended Industrial parts support -40 °C to 105 °C.
16. Number of USB Type-C Ports supported .
17. Default VCONN termination.
18. PD Role.
19. Type-C Cable Termination.
20. 35-WLCSP #1 pinout.
21. USB Device Termination.
22. 35-WLCSP #2 pinout.
23. USB Host Termination.
24. Dual Role Port.
Document Number: 001-93639 Rev. *K Page 24 of 31
CCG1 Datasheet
Packaging
Table 24. Package Characteristics
Parameter Description Conditions Min Typ Max Units
TA (40-QFN, 35-CSP) Operating ambient temperature – –40 25.00 85.00 °C
TJ (40-QFN, 35-CSP) Operating junction temperature – –40 – 100.00 °C
TA (16-SOIC) Operating ambient temperature – –40 25.00 105.00 °C
TJ (16-SOIC) Operating junction temperature – –40 – 120.00 °C
TJA Package JA (40-pin QFN) – – 15.34 – °C/Watt
TJA Package JA (35-CSP) – – 28.00 – °C/Watt
TJA Package JA (16-SOIC) – – 85.00 – °C/Watt
TJC Package JC (40-pin QFN) – – 02.50 – °C/Watt
TJC Package JC (35-CSP) – – 00.40 – °C/Watt
TJC Package JC (16-SOIC) – – 49.00 – °C/Watt
Table 25. Solder Reflow Pea k Temperature
Package Maximum Peak Temperature Maximum Time at Peak Temperatu re
16-pin SOIC 260 °C 30 seconds
40-pin QFN 260 °C 30 seconds
35-ball WLCSP 260 °C 30 seconds
Table 26. Package Moisture Sen sitivity Le vel (MSL), IPC/JEDEC J-STD-2
Package MSL
16-pin SOIC MSL 3
40-pin QFN MSL 3
35-ball WLCSP MSL 1
Document Number: 001-93639 Rev. *K Page 25 of 31
CCG1 Datasheet
Figure 12. 40-pin QFN Package Outline, 001-80659
The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and electrical performance.
If not connected to ground, it should be electrically floating and not connected to any other signal.
Figure 13. 35-Ball WLCSP Package Outline, 001-93741
001-80659 *A
D
C
B
A
1234
1234
D
C
B
A
TOP VIEW BOTTOM VIEW
SIDE VIEW
NOTES:
1. REFERENCE JEDEC PUBLICATION 95, DESIGN GUIDE 4.18
2. ALL DIMENSIONS ARE IN MILLIMETERS
E
56 7 567
E
001-93741 **
Document Number: 001-93639 Rev. *K Page 26 of 31
CCG1 Datasheet
Figure 14. 16-pin SOIC (150 Mils) S16.15/SZ16.15 Package Outline, 51-85068
51-85068 *E
Document Number: 001-93639 Rev. *K Page 27 of 31
CCG1 Datasheet
Acronyms
Table 27. Acrony ms Used in this Document
Acronym Description
ADC analog-to-digital converter
API application programming interface
ARM®advanced RISC machine, a CPU architecture
CC Configuration Channel
CPU central processing unit
CRC cyclic redundancy check, an error-checking
protocol
CS Current Sense
DFP downstream facing port
DIO digital input/output, GPIO with only digital
capabilities, no analog. See GPIO.
EEPROM electrically erasable programmable read-only
memory
EMI electromagnetic interference
ESD electrostatic discharge
FPB flash patch and breakpoint
FS full-speed
GPIO general-purpose input/output, applies to a PSoC
pin
IC integrated circuit
IDE integrated development environment
I2C, or IIC Inter-Integrated Circuit, a communications
protocol
ILO internal low-speed oscillator, see also IMO
IMO internal main oscillator, see also ILO
I/O input/output, see also GPIO, DIO, SIO, USBIO
LVD low-voltage detect
LVTTL low-voltage transistor-transistor logic
MCU microcontroller unit
NC no connect
NMI nonmaskable interrupt
NVIC nested vectored interrupt controller
opamp operational amplifier
OCP Overcurrent protection
OVP Overvoltage protection
PCB printed circuit board
PGA programmable gain amplifier
PHY physical layer
POR power-on reset
PRES precise power-on reset
PSoC®Programmable System-on-Chip™
PWM pulse-width modulator
RAM random-access memory
RISC reduced-instruction-set computing
RMS root-mean-square
RTC real-time clock
RX receive
SAR successive approximation register
SCL I2C serial clock
SDA I2C serial data
S/H sample and hold
SPI Serial Peripheral Interface, a communications
protocol
SRAM static random access memory
SWD serial wire debug, a test protocol
TX transmit
UART Universal Asynchronous Transmitter Receiver, a
communications protocol
UFP upstream facing port
USB Universal Serial Bus
USBIO USB input/output, PSoC pins used to connect to
a USB port
XRES external reset I/O pin
Table 27. Acronyms Used in this Document (continued)
Acronym Description
Document Number: 001-93639 Rev. *K Page 28 of 31
CCG1 Datasheet
Document Conventions
Units of Measure
Table 28. Units of Measure
Symbol Unit of Measure
°C degrees Celsius
Hz hertz
KB 1024 bytes
kHz kilohertz
kkilo ohm
Mbps megabits per second
MHz megahertz
Mmega-ohm
Msps megasamples per second
µA microampere
µF microfarad
µs microsecond
µV microvolt
µW microwatt
mA milliampere
ms millisecond
mV millivolt
nA nanoampere
ns nanosecond
ohm
pF picofarad
ppm parts per million
ps picosecond
s second
sps samples per second
Vvolt
Document Number: 001-93639 Rev. *K Page 29 of 31
CCG1 Datasheet
Revision History
Description Title: CCG1 Datasheet USB Type-C Port Controller with Power Delivery
Document Number: 001-93639
Revision ECN Orig. of
Change Submission
Date Description of Change
** 4520316 MSMI 09/30/2014 New datasheet
*A 4531795 SJH 10/13/2014
Updated Functional Definition.
Updated Figure 8, Figure , Figure 7, Figure , Figure 14, Figure 9.
Added Figure 11.
Updated Pinouts.
Updated Power.
Updated Figure , Figure 8.
Updated Ordering Information
Added Note 24 and referred the same note in 40-pin QFN corresponding to
CYPD1122-40LQXI.
Added Note 27 and referred the same note in 40-pin QFN corresponding to
CYPD1134-40LQXI.
*B 4569912 SJH 11/21/2014
Updated Features.
Added 16-pin SOIC related information.
Updated Functional Definition.
Updated Pin Definitions.
Added Table 2.
Updated Pinouts.
Updated Figure 2, Figure 5.
Added Figure 4.
Updated Power.
Updated Figure , Figure 8.
Added Figure 6.
Updated Electrical Specifications.
Updated Device-Level Specifications.
Updated Memory.
Added Note 14 and referred the same note in FRET parameter.
Added details corresponding to spec ID SID182B under FRET parameter.
Updated Figure 14, Figure 9, Figure 11. Added Figure 8 and Figure 10.
Updated Ordering Information.
Updated part numbers.
Added a column “Si ID”.
Updated Packaging.
Updated Ta b le 24 .
Updated details in maximum value column corresponding to TA and TJ
parameters.
Added 16-pin SOIC related information.
Updated Ta b le 25 .
*C 4596141 SJH 12/14/2014 Updated Figure 6, Figure 14, Figure 16.
Updated Ta b le 8, Ta b l e 2 3 .
*D 4646123 SJH 02/04/2015
Updated pin definitions for 40-pin QFN and 35-ball WLCSP.
Updated Pinout for CYPD1122-40LQXI/CYPD1121-40LQXI and Ordering
Information.
Updated conditions for Device-Level Specifications.
Updated diagrams in Applications in Detail section.
*E 4686050 VGT 03/13/2015
Removed information about 28-pin SSOP.
Updated Ta b le 3, Ta b l e 2 3 , Tab l e 24, Ta b l e 2 5 , Tab l e 26, Ta b l e 2 7 .
Updated Figure 2, Figure .
*F 4747272 VGT 05/13//2015
Updated General Description.
Added Note 1 and referenced it in Features.
Updated Figure 6, Figure 8 through Figure 11.
Removed Figure 9. Single Chip/Cable, Component Count = 13.
Removed Figure 11. Two Chip/Cable, Component Count = 11/paddle.
Document Number: 001-93639 Rev. *K Page 30 of 31
CCG1 Datasheet
*G 4800534 VGT 07/02/2015
Updated Low-Power Operation.
Updated the number of GPIOs to “up to 30” in GPIO.
Updated “1.8 to 5.5 V” to “3.2 V to 5.5 V” in Low-Power Operation, Power
System, Power, Device-Level Specifications and Note 15.
Updated Ta b le 2, Ta b l e 4 , Table 5, Table 6, Tab le 7, Tab l e 8, Table 14 and
Tab l e 18.
Added table footnotes 8, 9 and 10.
Deleted footnotes 25 through 28.
Updated Figure 2 and Figure 8 through Figure 11.
Added Figure 3.
Updated the following in Power: Removed Figures 5 through 8. Updated the
section.
*H 4939764 VGT 09/29/2015 Removed specs SID241 and 242.
Updated 40-pin QFN package to current revision.
*I 5179365 KISB 03/17/2016 Updated max value of II2C1 from 10.50 µA to 50 µA.
Updated copyright information and sales links at the end of the document.
*J 5459633 VGT 10/03/2016
Added compliance information regarding the USB Specification.
Updated copyright notice to include WICED.
Added IoT link in Sales, Solutions, and Legal Information.
*K 5725038 VGT 05/03/2017 Updated Cypress logo.
Updated Copyright information.
Revision History (continued)
Description Title: CCG1 Datasheet USB Type-C Port Controller with Power Delivery
Document Number: 001-93639
Revision ECN Orig. of
Change Submission
Date Description of Change
Document Number: 001-93639 Rev. *K Revised May 3, 2017 Page 31 of 31
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CCG1 Datasheet
Notice regarding compliance with Universal Serial Bus specification: Cypress offers firmware and hardware solutions that are certified to comply with the Universal Serial Bus specification, USB Type-C™
Cable and Connector Specification, and other specifications of USB Implementers Forum, Inc (USB-IF). You may use Cypress or third-party software tools, including sample code, to modify the firmware
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