ADSP-21365KSQZ-1AA - Analog Devices, Inc.

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

SHARC

Processor

ADSP-21365

Rev. 0

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However, no responsibility is assumed by Analog Devices for its use, nor for any

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SUMMARY

High performance 32-bit/40-bit floating-point processor

optimized for high performance automotive audio

processing

Audio decoder and post processor-algorithm support with

32-bit floating-point implementations

Nonvolatile memory may be configured to support audio

decoders and post processor-algorithms like PCM, Dolby®

Digital EX, Dolby Prologic IIx, DTS 96/24, Neo:6, DTS ES

MPEG2 AAC, MPEG2 2-channel, MP3, and functions like

bass management, delay, speaker equalization, graphic

equalization, and more. Decoder/post-processor algo-

rithm combination support will vary depending upon the

chip version and the system configurations. Please visit

www.analog.com/SHARC.

Single-instruction, multiple-data (SIMD) computational

architecture

On-chip memory—3M bit of on-chip SRAM and a dedicated

4M bit of on-chip mask-programmable ROM

Code compatible with all other members of the SHARC family

The ADSP-21365 is available with a 333 MHz core instruction

rate and unique audiocentric peripherals such as the digi-

tal audio interface, S/PDIF transceiver, DTCP (digital

transmission content protocol), serial ports, 8-channel

asynchronous sample rate converter, precision clock gen-

erators and more. For complete ordering information, see

Ordering Guide 53.

Figure 1. Functional Block Diagram—Processor Core

ADDR DATA

IOD

ADDR DATA

IOA

ADDR DATA

IOA

SRAM

1M BIT ROM

2M BIT

SRAM

0.5M BIT

BLOCK 0 BLOCK 1 BLOCK 2 BLOCK 3

ADDR DATA

IOA

IOP REGISTERS

(MEMORY MAPPED)

SEE ADSP-21365 MEMORY

AND I/O INTERFACE FEATURES

SECTION FOR DETAILS

I/O PROCESSOR

AND PERIPHERALS

JTAG TEST AND EMULATION

PM ADDRESS BUS

DM ADDRESS BUS 32

PM DATA BUS

DM DATA BUS

PX REGISTER

PROCESSING

ELEMENT

(PEY)

PROCESSING

ELEMENT

(PEX)

TIMER

INSTRUCTION

CACHE

32 X 48-BIT

DAG1

8X4X32

DAG2

8X4X32

CORE PROCESSOR

PROGRAM

SEQUENCER

SRAM

1M BIT ROM

2M BIT

SIGNAL

ROUTING

UNIT

SRAM

0.5M BIT

4 BLOCKS OF ON-CHIP MEMORY

IOD IOA IOD IOD

SPI

SPORTS

IDP

PCG

TIMERS

SRC

SPDIF

DTCP

Rev. 0 | Page 2 of 56 | October 2005

ADSP-21365

KEY FEATURES—PROCESSOR CORE

At 333 MHz (3.0 ns) core instruction rate, the ADSP-21365

performs 2 GFLOPS/666 MMACS

3M bit on-chip SRAM (1M bit in blocks 0 and 1, and 0.50M bit

in blocks 2 and 3) for simultaneous access by the core pro-

cessor and DMA

4M bit on-chip mask-programmable ROM (2M bit in block 0

and 2M bit in block 1)

Dual data address generators (DAGs) with modulo and bit-

reverse addressing

Zero-overhead looping with single-cycle loop setup, provid-

ing efficient program sequencing

Single-instruction, multiple-data (SIMD) architecture

provides:

Two computational processing elements

Concurrent execution

Code compatibility with other SHARC family members at

the assembly level

Parallelism in buses and computational units allows single

cycle execution (with or without SIMD) of a multiply opera-

tion, an ALU operation, a dual memory read or write, and

an instruction fetch

Transfers between memory and core at a sustained 5.4G

bytes/s bandwidth at 333 MHz core instruction rate

INPUT/OUTPUT FEATURES

DMA controller supports:

25 DMA channels for transfers between

ADSP-21365 internal memory and a variety of peripherals

32-bit DMA transfers at peripheral clock speed, in parallel

with full-speed processor execution

Asynchronous parallel port provides access to asynchronous

external memory

16 multiplexed address/data lines support 24-bit address

external address range with 8-bit data or 16-bit address

external address range with 16-bit data

55M bytes/s transfer rate

External memory access in a dedicated DMA channel

8-bit to 32-bit and 16-bit to 32-bit packing options

Programmable data cycle duration: 2 to 31 CCLK

Digital audio interface (DAI) includes six serial ports, two pre-

cision clock generators, an input data port, three timers, an

S/PDIF transceiver, a DTCP cipher, an 8-channel asynchro-

nous sample rate converter, an SPI port, and a signal

routing unit

Six dual data line serial ports that operate at up to 50M bits/s

on each data line—each has a clock, frame sync, and two

data lines that can be configured as either a receiver or

transmitter pair

Left-justified sample pair and I

S support, programmable

direction for up to 24 simultaneous receive or transmit

channels using two I

S-compatible stereo devices per

serial port

TDM support for telecommunications interfaces including

128 TDM channel support for newer telephony interfaces

such as H.100/H.110

Up to 12 TDM stream support, each with 128 channels per

frame

Companding selection on a per channel basis in TDM mode

Input data port provides an additional input path to the pro-

cessor core, configurable as eight channels of serial data or

seven channels of serial data and up to a 20-bit wide paral-

lel data channel

Signal routing unit provides configurable and flexible con-

nections between all DAI components–six serial ports, one

SPI port, eight channels of asynchronous sample rate con-

verters, an S/PDIF receiver/transmitter, DTCP (digital

transmission content protocol, three timers, an SPI port,10

interrupts, six flag inputs, six flag outputs, and 20 SRU I/O

pins (DAI_Px)

Two serial peripheral interfaces (SPI): primary on dedicated

pins, secondary on DAI pins provide:

master or slave serial boot through primary SPI, full-

duplex operation, master-slave mode multimaster sup-

port, open-drain outputs, programmable baud rates, clock

polarities, and phases

3 muxed flag/IRQ lines

1 muxed flag/timer expired line

DEDICATED AUDIO COMPONENTS

S/PDIF-compatible digital audio receiver/transmitter sup-

ports EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards

left-justified, I

S, or right-justified serial data input with

16-, 18-, 20-, or 24-bit word widths (transmitter)

Two channel mode and single channel double frequency

(SCDF) mode

Digital transmission content protection (DTCP)—a crypto-

graphic protocol for protecting audio content from

unauthorized copying, intercepting, and tampering

Sample rate converter (SRC) contains a serial input port, de-

emphasis filter, sample rate converter (SRC) and serial out-

put port providing up to -128 dB SNR performance

Supports left-justified, I

S, TDM, and right-justified 24-,

20-, 18-, and 16-bit serial formats (input)

Pulse-width modulation provides:

16 PWM outputs configured as four groups of four outputs

Supports center-aligned or edge-aligned PWM waveforms

Can generate complementary signals on two outputs in

paired mode or independent signals in nonpaired mode

ROM-based security features include:

JTAG access to memory permitted with a 64-bit key

Protected memory regions that can be assigned to limit

access under program control to sensitive code

PLL has a wide variety of software and hardware multi-

plier/divider ratios

Dual voltage: 3.3 V I/O, 1.2 V, or 1.0 V core

Available in 136-ball BGA and 144-lead LQFP packages (see

Ordering Guide 53)

ADSP-21365

Rev. 0 | Page 3 of 56 | October 2005

CONTENTS

Summary ................................................................1

Key Features—Processor Core ..................................2

Input/Output Features ............................................2

Dedicated Audio Components ..................................2

General Description ..................................................4

ADSP-21365 Family Core Architecture .......................4

ADSP-21365 Memory and I/O Interface Features ..........6

Development Tools ................................................9

Additional Information ......................................... 11

Pin Function Descriptions ........................................ 12

Address Data Pins as Flags ..................................... 15

Address/Data Modes ............................................15

Boot Modes ........................................................15

Core Instruction Rate to CLKIN Ratio Modes .............15

ADSP-21365 Specifications ....................................... 16

Recommended Operating Conditions .......................16

Electrical Characteristics ........................................16

Maximum Power Dissipation .................................17

Absolute Maximum Ratings ...................................17

ESD Sensitivity .................................................... 17

Timing Specifications ........................................... 18

Output Drive Currents ..........................................45

Test Conditions ................................................... 45

Capacitive Loading ...............................................45

Thermal Characteristics ........................................ 46

136-Ball BGA Pin Configurations ...............................47

144-Lead LQFP Pin Configurations ............................. 50

Outline Dimensions ................................................51

Surface Mount Design .......................................... 52

Ordering Guide ...................................................... 53

REVISION HISTORY

9/05—Revision 0: Initial Version

Rev. 0 | Page 4 of 56 | October 2005

ADSP-21365

GENERAL DESCRIPTION

The ADSP-21365 SHARC processor is a member of the SIMD

SHARC family of DSPs that feature Analog Devices’ Super

Harvard Architecture. The processors are source code-compati-

ble with the ADSP-2126x, and ADSP-2116x, DSPs as well as

with first generation ADSP-2106x SHARC processors in SISD

(single-instruction, single-data) mode. The ADSP-21365 is a

32-bit/40-bit floating-point processor optimized for high per-

formance automotive audio applications with their large

on-chip SRAM and mask-programmable ROM, multiple

internal buses to eliminate I/O bottlenecks, and an innovative

digital audio interface (DAI).

As shown in the functional block diagram on Page 1, the

ADSP-21365 uses two computational units to deliver a signifi-

cant performance increase over the previous SHARC processors

on a range of signal processing algorithms. Fabricated in a state-

of-the-art, high speed, CMOS process, the ADSP-21365 proces-

sor achieves an instruction cycle time of 3.0 ns at 333 MHz.

With its SIMD computational hardware, the ADSP-21365 can

perform two GFLOPS running at 333 MHz.

Table 1 shows performance benchmarks for the processors run-

ning at 333 MHz.

The ADSP-21365 continues SHARC’s industry-leading stan-

dards of integration for DSPs, combining a high performance

32-bit DSP core with integrated, on-chip system features.

The block diagram of the ADSP-21365 on Page 1 illustrates the

following architectural features:

• Two processing elements, each of which comprises an

ALU, multiplier, shifter, and data register file

• Data address generators (DAG1, DAG2)

• Program sequencer with instruction cache

• PM and DM buses capable of supporting four 32-bit data

transfers between memory and the core at every core pro-

cessor cycle

• Three programmable interval timers with PWM genera-

tion, PWM capture/pulse width measurement, and

external event counter capabilities

•On-chip SRAM (3M bit)

•On-chip mask-programmable ROM (4M bit)

• 8-bit or 16-bit parallel port that supports interfaces to off-

chip memory peripherals

• JTAG test access port

The block diagram of the ADSP-21365 on Page 7 illustrates the

following architectural features:

• DMA controller

• Six full duplex serial ports

• Two SPI-compatible interface ports—primary on dedi-

cated pins, secondary on DAI pins

• Digital audio interface that includes two precision clock

generators (PCG), an input data port (IDP), an S/PDIF

receiver/transmitter, eight channels asynchronous sample

rate converters, DTCP cipher, six serial ports, eight serial

interfaces, a 20-bit parallel input port, 10 interrupts, six flag

outputs, six flag inputs, three timers, and a flexible signal

routing unit (SRU)

Figure 2 on Page 5 shows one sample configuration of a SPORT

using the precision clock generators to interface with an I

ADC and an I

S DAC with a much lower jitter clock than the

serial port would generate itself. Many other SRU configura-

tions are possible.

ADSP-21365 FAMILY CORE ARCHITECTURE

The ADSP-21365 is code-compatible at the assembly level with

the ADSP-2126x, ADSP-21160 and ADSP-21161 and with the

first generation ADSP-2106x SHARC processors. The ADSP-

21365 shares architectural features with the ADSP-2126x and

ADSP-2116x SIMD SHARC processors, as detailed in the fol-

lowing sections.

SIMD Computational Engine

The ADSP-21365 contains two computational processing ele-

ments that operate as a single-instruction, multiple-data

(SIMD) engine. The processing elements are referred to as PEX

and PEY and each contains an ALU, multiplier, shifter, and reg-

ister file. PEX is always active, and PEY may be enabled by

setting the PEYEN mode bit in the MODE1 register. When this

mode is enabled, the same instruction is executed in both pro-

cessing elements, but each processing element operates on

different data. This architecture is efficient at executing math

intensive signal processing algorithms.

Entering SIMD mode also has an effect on the way data is trans-

ferred between memory and the processing elements. When in

SIMD mode, twice the data bandwidth is required to sustain

computational operation in the processing elements. Because of

this requirement, entering SIMD mode also doubles the band-

width between memory and the processing elements. When

using the DAGs to transfer data in SIMD mode, two data values

are transferred with each access of memory or the register file.

Table 1. Benchmarks (at 333 MHz)

Benchmark Algorithm

Speed

(at 333 MHz)

1024 Point Complex FFT (Radix 4, with reversal) 27.9 μs

FIR Filter (per tap)

Assumes two files in multichannel SIMD mode

1.5 ns

IIR Filter (per biquad)

6.0 ns

Matrix Multiply (pipelined)

[3×3] × [3×1]

[4×4] × [4×1]

13.5 ns

23.9 ns

Divide (y/x) 10.5 ns

Inverse Square Root 16.3 ns

ADSP-21365

Rev. 0 | Page 5 of 56 | October 2005

Independent, Parallel Computation Units

Within each processing element is a set of computational units.

The computational units consist of an arithmetic/logic unit

(ALU), multiplier, and shifter. These units perform all opera-

tions in a single cycle. The three units within each processing

element are arranged in parallel, maximizing computational

throughput. Single multifunction instructions execute parallel

ALU and multiplier operations. In SIMD mode, the parallel

ALU and multiplier operations occur in both processing ele-

ments. These computation units support IEEE 32-bit single-

precision floating-point, 40-bit extended-precision floating-

point, and 32-bit fixed-point data formats.

Data Register File

A general-purpose data register file is contained in each pro-

cessing element. The register files transfer data between the

computation units and the data buses, and store intermediate

results. These 10-port, 32-register (16 primary, 16 secondary)

vard architecture, allow unconstrained data flow between

computation units and internal memory. The registers in PEX

are referred to as R0–R15 and in PEY as S0–S15.

Single-Cycle Fetch of Instruction and Four Operands

The ADSP-21365 features an enhanced Harvard architecture in

which the data memory (DM) bus transfers data and the pro-

gram memory (PM) bus transfers both instructions and data

(see Figure 1 on Page 1). With the processor’s separate program

and data memory buses and on-chip instruction cache, the pro-

cessor can simultaneously fetch four operands (two over each

data bus) and one instruction (from the cache), all in a single

cycle.

Instruction Cache

The ADSP-21365 includes an on-chip instruction cache that

enables three-bus operation for fetching an instruction and four

data values. The cache is selective—only the instructions whose

fetches conflict with PM bus data accesses are cached. This

cache allows full-speed execution of core, looped operations

such as digital filter multiply-accumulates, and FFT butterfly

processing.

Data Address Generators With Zero-Overhead Hardware

Circular Buffer Support

The ADSP-21365’s two data address generators (DAGs) are

used for indirect addressing and implementing circular data

buffers in hardware. Circular buffers allow efficient program-

ming of delay lines and other data structures required in digital

Figure 2. ADSP-21365 System Sample Configuration

DAI

SPI

IDP

SRC

SPDIF

SPORT0-5

SCLK0

SD0A

SFS0

SD0B

SRU

DAI_P1

DA I_ P2

DA I_ P3

DAI_P18

DAI_P19

DA I_ P2 0

DAC

(OPTIONAL)

ADC

(OPTIONAL)

CLK

SDAT

CLK

SDAT

CLOCK

FLAG3-1

CLKIN

XTAL

CLK_CFG1-0

BOOTCFG1-0

ADDR PARALLEL

PORT

RAM, ROM

BOO T ROM

I/O DEVICE

DATA

CLKOUT

ALE

AD 1 5-0 LATCH

RESET JTAG

ADSP-21365

ADDRESS

DATA

CONTROL

FLAG0

PCGB

PCGA

CLK

TIMERS

Rev. 0 | Page 6 of 56 | October 2005

ADSP-21365

signal processing, and are commonly used in digital filters and

Fourier transforms. The two DAGs contain sufficient registers

to allow the creation of up to 32 circular buffers (16 primary

address pointer wraparound, reduce overhead, increase perfor-

mance, and simplify implementation. Circular buffers can start

and end at any memory location.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel

operations, for concise programming. For example, the

ADSP-21365 can conditionally execute a multiply, an add, and a

subtract in both processing elements while branching and fetch-

ing up to four 32-bit values from memory—all in a single

instruction.

ADSP-21365 MEMORY AND I/O INTERFACE

FEATURES

The ADSP-21365 adds the following architectural features to

the SIMD SHARC family core.

On-Chip Memory

The ADSP-21365 contains three megabits of internal SRAM

and four megabits of internal mask-programmable ROM. Each

block can be configured for different combinations of code and

data storage (see Table 2). Each memory block supports single-

cycle, independent accesses by the core processor and I/O pro-

cessor. The processor’s memory architecture, in combination

with its separate on-chip buses, allows two data transfers from

the core and one from the I/O processor, in a single cycle.

The ADSP-21365’s SRAM can be configured as a maximum of

96K words of 32-bit data, 192K words of 16-bit data, 64K words

of 48-bit instructions (or 40-bit data), or combinations of differ-

ent word sizes up to three megabits. All of the memory can be

accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit float-

ing-point storage format is supported that effectively doubles

the amount of data that may be stored on-chip. Conversion

between the 32-bit floating-point and 16-bit floating-point for-

mats is performed in a single instruction. While each memory

block can store combinations of code and data, accesses are

most efficient when one block stores data using the DM bus for

transfers, and the other block stores instructions and data using

the PM bus for transfers.

Table 2. ADSP-21365 Internal Memory Space

IOP Registers 0x0000 0000–0003 FFFF

Long Word (64 bits)

Extended Precision Normal or

Instruction Word (48 bits) Normal Word (32 bits) Short Word (16 bits)

BLOCK 0 ROM

0x0004 0000–0x0004 7FFF

BLOCK 0 ROM

0x0008 0000–0x0008 AAA9

BLOCK 0 ROM

0x0008 0000–0x0008 FFFF

BLOCK 0 ROM

0x0010 0000–0x0011 FFFF

Reserved

0x0004 8000–0x0004 BFFF

Reserved

0x0009 0000–0x0009 7FFF

Reserved

0x0012 0000–0x0012 FFFF

BLOCK 0 RAM

0x0004 C000–0x0004 FFFF

BLOCK 0 RAM

0x0009 0000–0x0009 5554

BLOCK 0 RAM

0x0009 8000–0x0009 FFFF

BLOCK 0 RAM

0x0013 0000–0x0013 FFFF

BLOCK 1 ROM

0x0005 0000–0x0005 7FFF

BLOCK 1 ROM

0x000A 0000–0x000A AAA9

BLOCK 1 ROM

0x000A 0000–0x000A FFFF

BLOCK 1 ROM

0x0014 0000–0x0015 FFFF

Reserved

0x0005 8000–0x0005 BFFF

Reserved

0x000B 0000–0x000B 7FFF

Reserved

0x0016 0000–0x0016 FFFF

BLOCK 1 RAM

0x0005 C000–0x0005 FFFF

BLOCK 1 RAM

0x000B 0000–0x000B 5554

BLOCK 1 RAM

0x000B 8000–0x000B FFFF

BLOCK 1 RAM

0x0017 0000–0x0017 FFFF

BLOCK 2 RAM

0x0006 0000–0x0006 1FFF

BLOCK 2 RAM

0x000C 0000–0x000C 2AA9

BLOCK 2 RAM

0x000C 0000–0x000C 3FFF

BLOCK 2 RAM

0x0018 0000–0x0018 7FFF

Reserved

0x0006 2000–0x0006 FFFF

Reserved

0x000C 4000–0x000D FFFF

Reserved

0x0018 8000–0x001B FFFF

BLOCK 3 RAM

0x0007 0000–0x0007 1FFF

BLOCK 3 RAM

0x000E 0000–0x000E 2AA9

BLOCK 3 RAM

0x000E 0000–0x000E 3FFF

BLOCK 3 RAM

0x001C 0000–0x001C 7FFF

Reserved

0x0007 2000–0x0007 FFFF

Reserved

0x000E 4000–0x000F FFFF

Reserved

0x001C 8000–0x001F FFFF

Reserved

0x0020 0000–0xFFFF FFFF

ADSP-21365

Rev. 0 | Page 7 of 56 | October 2005

Using the DM bus and PM buses, with one bus dedicated to

each memory block, assures single-cycle execution with two

data transfers. In this case, the instruction must be available in

the cache.

DMA Controller

The ADSP-21365’s on-chip DMA controllers allow data trans-

fers without processor intervention. The DMA controller

operates independently and invisibly to the processor core,

allowing DMA operations to occur while the core is simulta-

neously executing its program instructions. DMA transfers can

occur between the ADSP-21365’s internal memory and its serial

ports, the SPI-compatible (serial peripheral interface) ports, the

IDP (input data port), the parallel data acquisition port (PDAP)

or the parallel port. Twenty-five channels of DMA are available

on the processors—two for the SPI interface, 12 via the serial

ports, eight via the input data port, two for DTCP (or memory-

to-memory data transfer when DTCP is not used), and one via

the processor’s parallel port. Programs can be downloaded to

the processors using DMA transfers. Other DMA features

include interrupt generation upon completion of DMA trans-

fers, and DMA chaining for automatic linked DMA transfers.

Digital Audio Interface (DAI)

The digital audio interface (DAI) provides the ability to connect

various peripherals to any of the DSP’s DAI pins (DAI_P20–1).

Programs make these connections using the signal routing unit

(SRU, shown in Figure 3).

The SRU is a matrix routing unit (or group of multiplexers) that

enables the peripherals provided by the DAI to be intercon-

nected under software control. This allows easy use of the DAI-

associated peripherals for a much wider variety of applications

by using a larger set of algorithms than is possible with noncon-

figurable signal paths.

The DAI also includes six serial ports, an S/PDIF receiver/trans-

mitter, a DTCP cipher, a precision clock generator (PCG), eight

channels of asynchronous sample rate converters, an input data

port (IDP), an SPI port, six flag outputs and six flag inputs, and

three timers. The IDP provides an additional input path to the

ADSP-21365 core, configurable as either eight channels of I

serial data or as seven channels plus a single 20-bit wide syn-

chronous parallel data acquisition port. Each data channel has

its own DMA channel that is independent from the processor’s

serial ports.

For complete information on using the DAI, see the

ADSP-2136x SHARC Processor Hardware Reference.

Serial Ports

The ADSP-21365 features six synchronous serial ports that pro-

vide an inexpensive interface to a wide variety of digital and

mixed-signal peripheral devices such as Analog Devices’

AD183x family of audio codecs, ADCs, and DACs. The serial

ports are made up of two data lines, a clock, and a frame sync.

The data lines can be programmed to either transmit or receive

and each data line has a dedicated DMA channel.

Serial ports are enabled via 12 programmable and simultaneous

receive or transmit pins that support up to 24 transmit or 24

receive channels of audio data when all six SPORTS are enabled,

or six full duplex TDM streams of 128 channels per frame.

The serial ports operate at a maximum data rate of 50M bits/s.

Serial port data can be automatically transferred to and from

on-chip memory via dedicated DMA channels. Each of the

serial ports can work in conjunction with another serial port to

provide TDM support. One SPORT provides two transmit sig-

nals while the other SPORT provides the two receive signals.

The frame sync and clock are shared.

Serial ports operate in four modes:

• Standard DSP serial mode

•Multichannel (TDM) mode

•I

S mode

• Left-justified sample pair mode

Figure 3. ADSP-21365 I/O Processor and

Peripherals Block Diagram

PRECISION CLOCK

GENERATORS (2)

SPI PORT (1)

SERIAL PORTS (6)

INPUT

DATA PORTS (8)

TIMERS (3)

DMA CONTROLLER

IOPREGISTERS

(MEMORYMAPPED)

CONTROL,STATUS,ANDDATABUFFERS

PARALLEL PORT

GPIO FLAGS/IRQ/TIMEXP

SIGNAL ROUTING UNIT

ADDRESS/DATA BUS/GPIO

CONTROL/GPIO

DIGITAL AUDIO INTERFACE

25 CHANNELS

TO PROCESSOR BUSES AND

SYSTEM MEMORY

IO ADDRESS

BUS (18)

SRC (8 CHANNELS)

SPDIF (Rx/Tx)

DTCP CIPHER

PWM (16)

IO DATA

BUS (32)

SPI PORT (1)

I/O PROCESSOR

Rev. 0 | Page 8 of 56 | October 2005

ADSP-21365

Left-justified sample pair mode is a mode where in each frame

sync cycle two samples of data are transmitted/received—one

sample on the high segment of the frame sync, the other on the

low segment of the frame sync. Programs have control over var-

ious attributes of this mode.

Each of the serial ports supports the left-justified sample pair

and I

S protocols (I

S is an industry-standard interface com-

monly used by audio codecs, ADCs and DACs such as the

Analog Devices AD183x family), with two data pins, allowing

four left-justified sample pair or I

S channels (using two stereo

devices) per serial port, with a maximum of up to 24 I

S chan-

nels. The serial ports permit little-endian or big-endian

transmission formats and word lengths selectable from 3 bits to

32 bits. For the left-justified sample pair and I

S modes, data-

word lengths are selectable between 8 bits and 32 bits. Serial

ports offer selectable synchronization and transmit modes as

well as optional μ-law or A-law companding selection on a per

channel basis. Serial port clocks and frame syncs can be inter-

nally or externally generated.

Parallel Port

The parallel port provides interfaces to SRAM and peripheral

devices. The multiplexed address and data pins (AD15–0) can

access 8-bit devices with up to 24 bits of address, or 16-bit

devices with up to 16 bits of address. In either mode, 8-bit, or

16-bit, the maximum data transfer rate is 55M bytes/sec.

DMA transfers are used to move data to and from internal

memory. Access to the core is also facilitated through the paral-

lel port register read/write functions. The RD, WR, and ALE

(address latch enable) pins are the control pins for the parallel

port.

Serial Peripheral (Compatible) Interface

The processors contain two serial peripheral interface ports

(SPIs). The SPI is an industry-standard synchronous serial link,

enabling the ADSP-21365 SPI-compatible port to communicate

with other SPI-compatible devices. The SPI consists of two data

pins, one device select pin, and one clock pin. It is a full-duplex

synchronous serial interface, supporting both master and slave

modes. The SPI port can operate in a multimaster environment

by interfacing with up to four other SPI-compatible devices,

either acting as a master or slave device. The ADSP-21365 SPI-

compatible peripheral implementation also features program-

mable baud rate and clock-phase and polarities. The SPI-

compatible port uses open-drain drivers to support a multimas-

ter configuration and to avoid data contention.

S/PDIF-Compatible Digital Audio Receiver/Transmitter

and Synchronous/Asynchronous Sample Rate Converter

The S/PDIF transmitter has no separate DMA channels. It

receives audio data in serial format and converts it into a

biphase encoded signal. The serial data input to the transmitter

can be formatted as left-justified, I

S, or right-justified with

word widths of 16, 18, 20, or 24 bits.

The serial data, clock, and frame sync inputs to the S/PDIF

transmitter are routed through the signal routing unit (SRU).

They can come from a variety of sources such as the SPORTs,

external pins, the precision clock generators (PCGs), or the

sample rate converters (SRC) and are controlled by the SRU

control registers.

The sample rate converter (SRC) contains four SRC blocks and

is the same core as that used in the AD1896 192 kHz stereo

asynchronous sample rate converter and provides up to 128 dB

SNR. The SRC block is used to perform synchronous or asyn-

chronous sample rate conversion across independent stereo

channels, without using internal processor resources. The four

SRC blocks can also be configured to operate together to con-

vert multichannel audio data without phase mismatches.

Finally, the SRC is used to clean up audio data from jittery clock

sources such as the S/PDIF receiver.

Digital Transmission Content Protection

The DTCP specification defines a cryptographic protocol for

protecting audio entertainment content from illegal copying,

intercepting, and tampering as it traverses high performance

digital buses, such as the IEEE 1394 standard. Only legitimate

entertainment content delivered to a source device via another

approved copy protection system (such as the DVD content

scrambling system) will be protected by this copy protection

system.

Pulse-Width Modulation

The PWM module is a flexible, programmable, PWM waveform

generator that can be programmed to generate the required

switching patterns for various applications related to motor and

engine control or audio power control. The PWM generator can

generate either center-aligned or edge-aligned PWM wave-

forms. In addition, it can generate complementary signals on

two outputs in paired mode or independent signals in non-

paired mode (applicable to a single group of four PWM

waveforms).

The entire PWM module has four groups of four PWM outputs

each. Therefore, this module generates 16 PWM outputs in

total. Each PWM group produces two pairs of PWM signals on

the four PWM outputs.

The PWM generator is capable of operating in two distinct

modes while generating center-aligned PWM waveforms: single

update mode or double update mode. In single update mode the

duty cycle values are programmable only once per PWM period.

This results in PWM patterns that are symmetrical about the

midpoint of the PWM period. In double update mode, a second

updating of the PWM registers is implemented at the midpoint

of the PWM period. In this mode, it is possible to produce

asymmetrical PWM patterns that produce lower harmonic dis-

tortion in three-phase PWM inverters.

ADSP-21365

Rev. 0 | Page 9 of 56 | October 2005

Timers

The ADSP-21365 has a total of four timers: a core timer that can

generate periodic software interrupts and three general-purpose

timers that can generate periodic interrupts and be indepen-

dently set to operate in one of three modes:

• Pulse waveform generation mode

• Pulse width count/capture mode

• External event watchdog mode

The core timer can be configured to use FLAG3 as a timer

expired signal, and each general-purpose timer has one bidirec-

tional pin and four registers that implement its mode of

operation: a 6-bit configuration register, a 32-bit count register,

a 32-bit period register, and a 32-bit pulse width register. A sin-

gle control and status register enables or disables all three

general-purpose timers independently.

ROM-Based Security

The ADSP-21365 has a ROM security feature that provides

hardware support for securing user software code by preventing

unauthorized reading from the internal code when enabled.

When using this feature, the processor does not boot-load any

external code, executing exclusively from internal SRAM/ROM.

Additionally, the processor is not freely accessible via the JTAG

port. Instead, a unique 64-bit key, which must be scanned in

through the JTAG or test access port will be assigned to each

customer. The device will ignore a wrong key. Emulation fea-

tures and external boot modes are only available after the

correct key is scanned.

Program Booting

The internal memory of the ADSP-21365 boots at system

power-up from an 8-bit EPROM via the parallel port, an SPI

master, an SPI slave, or an internal boot. Booting is determined

by the boot configuration (BOOTCFG1–0) pins (see Table 6 on

Page 15). Selection of the boot source is controlled via the SPI as

either a master or slave device, or it can immediately begin exe-

cuting from ROM.

Phase-Locked Loop

The processors use an on-chip phase-locked loop (PLL) to gen-

erate the internal clock for the core. On power up, the

CLKCFG1–0 pins are used to select ratios of 32:1, 16:1, and 6:1

(see Table 7 on Page 15). After booting, numerous other ratios

can be selected via software control.

The ratios are made up of software configurable numerator val-

ues from 1 to 64 and software configurable divisor values of 1, 2,

4, and 8.

Power Supplies

The ADSP-21365 has separate power supply connections for the

internal (V

DDINT

), external (V

DDEXT

), and analog (A

VDD

VSS

)

power supplies. The internal and analog supplies must meet the

1.2 V requirement for K and B grade models, and the 1.0 V

requirement for W grade models. The external supply must

meet the 3.3 V requirement. All external supply pins must be

connected to the same power supply.

Note that the analog supply pin (A

VDD

) powers the processor’s

internal clock generator PLL. To produce a stable clock, it is rec-

ommended that PCB designs use an external filter circuit for the

VDD

pin. Place the filter components as close as possible to the

VDD

VSS

pins. For an example circuit, see Figure 4. (A recom-

mended ferrite chip is the muRata BLM18AG102SN1D). To

reduce noise coupling, the PCB should use a parallel pair of

power and ground planes for V

DDINT

and GND. Use wide traces

to connect the bypass capacitors to the analog power (A

VDD

)

and ground (A

VSS

) pins. Note that the A

VDD

and A

VSS

pins

specified in Figure 4 are inputs to the processor and not the ana-

log ground plane on the board—the A

VSS

pin should connect

directly to digital ground (GND) at the chip.

Target Board JTAG Emulator Connector

Analog Devices DSP Tools product line of JTAG emulators uses

the IEEE 1149.1 JTAG test access port of the processor to moni-

tor and control the target board processor during emulation.

Analog Devices’ DSP Tools product line of JTAG emulators

provides emulation at full processor speed, allowing inspection

and modification of memory, registers, and processor stacks.

The processor’s JTAG interface ensures that the emulator will

not affect target system loading or timing.

For complete information on Analog Devices’ SHARC DSP

Tools product line of JTAG emulator operation, see the appro-

priate “Emulator Hardware User’s Guide.”

DEVELOPMENT TOOLS

The ADSP-21365 is supported with a complete set of CROSS-

CORE

software and hardware development tools, including

Analog Devices emulators and VisualDSP++

development

environment. The same emulator hardware that supports other

SHARC processors also fully emulates the ADSP-21365.

The VisualDSP++ project management environment lets pro-

grammers develop and debug an application. This environment

includes an easy to use assembler (which is based on an alge-

braic syntax), an archiver (librarian/library builder), a linker, a

loader, a cycle-accurate instruction-level simulator, a C/C++

compiler, and a C/C++ run-time library that includes DSP and

mathematical functions. A key point for these tools is C/C++

code efficiency. The compiler has been developed for efficient

translation of C/C++ code to DSP assembly. The SHARC has

architectural features that improve the efficiency of compiled

C/C++ code.

Figure 4. Analog Power (A

VDD

) Filter Circuit

HI Z FERRITE

BEAD CHIP

LOCATE ALL COMPONENTS

CLOSE TO AVDD AND AVSS PINS

AVDD

AVSS

100nF 10nF 1nF ADSP-213xx

VDDINT

Rev. 0 | Page 10 of 56 | October 2005

ADSP-21365

The VisualDSP++ debugger has a number of important fea-

tures. Data visualization is enhanced by a plotting package that

offers a significant level of flexibility. This graphical representa-

tion of user data enables the programmer to quickly determine

the performance of an algorithm. As algorithms grow in com-

plexity, this capability can have increasing significance on the

designer’s development schedule, increasing productivity. Sta-

tistical profiling enables the programmer to nonintrusively poll

the processor as it is running the program. This feature, unique

to VisualDSP++, enables the software developer to passively

gather important code execution metrics without interrupting

the real-time characteristics of the program. Essentially, the

developer can identify bottlenecks in software quickly and effi-

ciently. By using the profiler, the programmer can focus on

those areas in the program that impact performance and take

corrective action.

Debugging both C/C++ and assembly programs with the

VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved source

and object information)

• Insert breakpoints

• Set conditional breakpoints on registers, memory,

and stacks

• Trace instruction execution

• Perform linear or statistical profiling of program execution

• Fill, dump, and graphically plot the contents of memory

• Perform source level debugging

• Create custom debugger windows

The VisualDSP++ IDDE lets programmers define and manage

DSP software development. Its dialog boxes and property pages

let programmers configure and manage all of the SHARC devel-

opment tools, including the color syntax highlighting in the

VisualDSP++ editor. This capability permits programmers to:

• Control how the development tools process inputs and

generate outputs

• Maintain a one-to-one correspondence with the tool’s

command line switches

The VisualDSP++ Kernel (VDK) incorporates scheduling and

resource management tailored specifically to address the mem-

ory and timing constraints of DSP programming. These

capabilities enable engineers to develop code more effectively,

eliminating the need to start from the very beginning, when

developing new application code. The VDK features include

threads, critical and unscheduled regions, semaphores, events,

and device flags. The VDK also supports priority-based, pre-

emptive, cooperative, and time-sliced scheduling approaches. In

addition, the VDK was designed to be scalable. If the application

does not use a specific feature, the support code for that feature

is excluded from the target system.

Because the VDK is a library, a developer can decide whether to

use it or not. The VDK is integrated into the VisualDSP++

development environment, but can also be used via standard

command line tools. When the VDK is used, the development

environment assists the developer with many error-prone tasks

and assists in managing system resources, automating the gen-

eration of various VDK-based objects, and visualizing the

system state, when debugging an application that uses the VDK.

VisualDSP++ component software engineering (VCSE) is Ana-

log Devices’ technology for creating, using, and reusing software

components (independent modules of substantial functionality)

to quickly and reliably assemble software applications. It allows

downloading components from the Web, dropping them into

the application, and publishing component archives from

within VisualDSP++. VCSE supports component implementa-

tion in C/C++ or assembly language.

Use the expert linker to visually manipulate the placement of

code and data on the embedded system; view memory use in a

color-coded graphical form, easily move code and data to differ-

ent areas of the processor or external memory with a drag of the

mouse, and examine run-time stack and heap usage. The expert

linker is fully compatible with the existing linker definition file

(LDF), allowing the developer to move between the graphical

and textual environments.

In addition to the software and hardware development tools

available from Analog Devices, third parties provide a wide

range of tools supporting the SHARC processor family. Hard-

ware tools include SHARC processor PC plug-in cards. Third

party software tools include DSP libraries, real-time operating

systems, and block diagram design tools.

Designing an Emulator-Compatible DSP Board (Target)

The Analog Devices family of emulators are tools that every

DSP developer needs to test and debug hardware and software

systems. Analog Devices has supplied an IEEE 1149.1 JTAG test

access port (TAP) on each JTAG processor. Nonintrusive in-

circuit emulation is assured by the use of the processor’s JTAG

interface—the emulator does not affect target system loading or

timing. The emulator uses the TAP to access the internal fea-

tures of the processor, allowing the developer to load code, set

breakpoints, observe variables, observe memory, and examine

registers. The processor must be halted to send data and com-

mands, but once an operation has been completed by the

emulator, the DSP system is set running at full speed with no

impact on system timing.

To use these emulators, the target board must include a header

that connects the DSP’s JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, multiprocessor scan

chains, signal buffering, signal termination, and emulator pod

logic, see the EE-68: Analog Devices JTAG Emulation Technical

Reference on the Analog Devices website (www.analog.com)—

use site search on “EE-68.” This document is updated regularly

to keep pace with improvements to emulator support.

Evaluation Kit

Analog Devices offers a range of EZ-KIT Lite evaluation plat-

forms to use as a cost-effective method to learn more about

developing or prototyping applications with Analog Devices

processors, platforms, and software tools. Each EZ-KIT Lite

includes an evaluation board along with an evaluation suite of

ADSP-21365

Rev. 0 | Page 11 of 56 | October 2005

the VisualDSP++ development and debugging environment

with the C/C++ compiler, assembler, and linker. Also included

are sample application programs, power supply, and a USB

cable. All evaluation versions of the software tools are limited

for use only with the EZ-KIT Lite product.

The USB controller on the EZ-KIT Lite board connects the

board to the USB port of the user’s PC, enabling the

VisualDSP++ evaluation suite to emulate the on-board proces-

sor in-circuit. This permits the customer to download, execute,

and debug programs for the EZ-KIT Lite system. It also allows

in-circuit programming of the on-board flash device to store

user-specific boot code, enabling the board to run as a

standalone unit without being connected to the PC.

With a full version of VisualDSP++ installed (sold separately),

engineers can develop software for the EZ-KIT Lite or any cus-

tom defined system. Connecting one of Analog Devices’ JTAG

emulators to the EZ-KIT Lite board enables high speed, non-

intrusive emulation.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the

ADSP-21365 architecture and functionality. For detailed infor-

mation on the ADSP-2136x family core architecture and

instruction set, refer to the ADSP-2136x SHARC Processor

Hardware Reference and the ADSP-2136x SHARC Processor

Programming Reference.

Rev. 0 | Page 12 of 56 | October 2005

ADSP-21365

PIN FUNCTION DESCRIPTIONS

ADSP-21365 pin definitions are listed below. Inputs identified

as synchronous (S) must meet timing requirements with respect

to CLKIN (or with respect to TCK for TMS and TDI). Inputs

identified as asynchronous (A) can be asserted asynchronously

to CLKIN (or to TCK for TRST). Tie or pull unused inputs to

DDEXT

or GND, except for the following:

• DAI_Px, SPICLK, MISO, MOSI, EMU, TMS, TRST, TDI,

and AD15–0 (NOTE: These pins have pull-up resistors.)

The following symbols appear in the Type column of Table 3:

A = asynchronous, G = ground, I = input, O = output,

P = power supply, S = synchronous, (A/D) = active drive,

(O/D) = open-drain, and T = three-state, (pd) = pull-down

resistor, (pu) = pull-up resistor.

Table 3. Pin Descriptions

Pin Type

State During and

After Reset Function

AD15–0 I/O/T

(pu)

Three-state with

pull-up enabled

Parallel Port Address/Data. The ADSP-21365 parallel port and its corresponding

DMA unit output addresses and data for peripherals on these multiplexed pins. The

multiplex state is determined by the ALE pin. The parallel port can operate in either

8-bit or 16-bit mode. Each AD pin has a 22.5 kΩ internal pull-up resistor. See

Address/Data Modes 15 for details of the AD pin operation.

For 8-bit mode: ALE is automatically asserted whenever a change occurs in the upper

16 external address bits, A23–8; ALE is used in conjunction with an external latch to

retain the values of the A23–8.

For detailed information on I/O operations and pin multiplexing, see the ADSP-2136x

SHARC Processor Hardware Reference.

RD O

(pu)

Three-state, driven

high

Parallel Port Read Enable. RD is asserted low whenever the processor reads 8-bit or

16-bit data from an external memory device. When AD15–0 are flags, this pin remains

deasserted. RD has a 22.5 kΩ internal pull-up resistor.

WR O

(pu)

Three-state, driven

high

Parallel Port Write Enable. WR is asserted low whenever the processor writes 8-bit or

16-bit data to an external memory device. When AD15–0 are flags, this pin remains

deasserted. WR has a 22.5 kΩ internal pull-up resistor.

ALE O

(pd)

Three-state, driven

low

Parallel Port Address Latch Enable. ALE is asserted whenever the processor drives

a new address on the parallel port address pins. On reset, ALE is active high. However,

it can be reconfigured using software to be active low. When AD15–0 are flags, this

pin remains deasserted. ALE has a 20 kΩ internal pull-down resistor.

FLAG3–0 I/O/A Three-state Flag Pins. Each flag pin is configured via control bits as either an input or output. As

an input, it can be tested as a condition. As an output, it can be used to signal external

peripherals. These pins can be used as an SPI interface slave select output during SPI

mastering. These pins are also multiplexed with the IRQx and the TIMEXP signals. For

detailed information on I/O operations and pin multiplexing, see the ADSP-2136x

SHARC Processor Hardware Reference

DAI_P20–1 I/O/T

(pu)

Three-state with

programmable

pull-up

Digital Audio Interface Pins. These pins provide the physical interface to the SRU.

The SRU configuration registers define the combination of on-chip peripheral inputs

or outputs connected to the pin and to the pin’s output enable. The configuration

registers of these peripherals then determines the exact behavior of the pin. Any input

or output signal present in the SRU may be routed to any of these pins. The SRU

provides the connection from the serial ports, input data port, precision clock gener-

ators and timers, sample rate converters and SPI to the DAI_P20–1 pins. These pins

have internal 22.5 kΩ pull-up resistors which are enabled on reset. These pull-ups can

be disabled in the DAI_PIN_PULLUP register.

ADSP-21365

Rev. 0 | Page 13 of 56 | October 2005

SPICLK I/O

(pu)

Three-state with

pull-up enabled

Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls

the rate at which data is transferred. The master may transmit data at a variety of baud

rates. SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that is active

during data transfers, only for the length of the transferred word. Slave devices ignore

the serial clock if the slave select input is driven inactive (HIGH). SPICLK is used to shift

out and shift in the data driven on the MISO and MOSI lines. The data is always shifted

out on one clock edge and sampled on the opposite edge of the clock. Clock polarity

and clock phase relative to data are programmable into the SPICTL control register

and define the transfer format. SPICLK has a 22.5 kΩ internal pull-up resistor.

SPIDS I Input only Serial Peripheral Interface Slave Device Select. An active low signal used to select

the processor as an SPI slave device. This input signal behaves like a chip select, and

is provided by the master device for the slave devices. In multimaster mode the

processor’s SPIDS signal can be driven by a slave device to signal to the processor (as

SPI master) that an error has occurred, as some other device is also trying to be the

master device. If asserted low when the device is in master mode, it is considered a

multimaster error. For a single-master, multiple-slave configuration where flag pins

are used, this pin must be tied or pulled high to V

DDEXT

on the master device. For

processor to processor SPI interaction, any of the master processor’s flag pins can be

used to drive the SPIDS signal on the SPI slave device.

MOSI I/O (O/D)

(pu)

Three-state with

pull-up enabled

SPI Master Out Slave In. If the ADSP-21365 is configured as a master, the MOSI pin

becomes a data transmit (output) pin, transmitting output data. If the processor is

configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input

data. In a SPI interconnection, the data is shifted out from the MOSI output pin of the

master and shifted into the MOSI input(s) of the slave(s). MOSI has a 22.5 kΩ internal

pull-up resistor.

MISO I/O (O/D)

(pu)

Three-state with

pull-up enabled

SPI Master In Slave Out. If the ADSP-21365 is configured as a master, the MISO pin

becomes a data receive (input) pin, receiving input data. If the processor is configured

as a slave, the MISO pin becomes a data transmit (output) pin, transmitting output

data. In an SPI interconnection, the data is shifted out from the MISO output pin of the

slave and shifted into the MISO input pin of the master. MISO has a 22.5 kΩ internal

pull-up resistor. MISO can be configured as O/D by setting the OPD bit in the SPICTL

Note: Only one slave is allowed to transmit data at any given time. To enable broadcast

transmission to multiple SPI-slaves, the processor’s MISO pin may be disabled by

setting (=1) Bit 5 (DMISO) of the SPICTL register.

BOOTCFG1–0 I Input only Boot Configuration Select. This pin is used to select the boot mode for the processor.

The BOOTCFG pins must be valid before reset is asserted. See Table 6 for a description

of the boot modes.

CLKIN I Input only Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21365 clock input.

It configures the ADSP-21365 to use either its internal clock generator or an external

clock source. Connecting the necessary components to CLKIN and XTAL enables the

internal clock generator. Connecting the external clock to CLKIN while leaving XTAL

unconnected configures the processors to use the external clock source such as an

external clock oscillator. The core is clocked either by the PLL output or this clock input

depending on the CLKCFG1–0 pin settings. CLKIN may not be halted, changed, or

operated below the specified frequency.

XTAL O Output only

Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external

crystal.

CLKCFG1–0 I Input only Core/CLKIN Ratio Control. These pins set the start up clock frequency. See Table 7

for a description of the clock configuration modes. Note that the operating frequency

can be changed by programming the PLL multiplier and divider in the PMCTL register

at any time after the core comes out of reset.

Table 3. Pin Descriptions (Continued)

Pin Type

State During and

After Reset Function

Rev. 0 | Page 14 of 56 | October 2005

ADSP-21365

RSTOUT/CLKOUT O Output only Local Clock Out/Reset Out. Drives out the core reset signal to an external device.

CLKOUT can also be configured as a reset out pin. The functionality can be switched

between the PLL output clock and reset out by setting Bit 12 of the PMCTREG register.

The default is reset out.

RESET I/A Input only Processor Reset. Resets the ADSP-21365 to a known state. Upon deassertion, there

is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins

program execution from the hardware reset vector address. The RESET input must be

asserted (low) at power-up.

TCK I Input only

Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted

(pulsed low) after power-up or held low for proper operation of the processors.

TMS I/S

(pu)

Three-state with

pull-up enabled

Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 kΩ

internal pull-up resistor.

TDI I/S

(pu)

Three-state with

pull-up enabled

Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a

22.5 kΩ internal pull-up resistor.

TDO O Three-state

Test Data Output (JTAG). Serial scan output of the boundary scan path.

TRST I/A

(pu)

Three-state with

pull-up enabled

Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)

after power-up or held low for proper operation of the ADSP-21365. TRST has a

22.5 kΩ internal pull-up resistor.

EMU O (O/D)

(pu)

Three-state with

pull-up enabled

Emulation Status. Must be connected to the processor’s JTAG emulators target board

connector only. EMU has a 22.5 kΩ internal pull-up resistor.

DDINT

PCore Power Supply. Nominally +1.2 V dc for the K and B grade models, and 1.0 V dc

for the W grade models, and supplies the processor’s core (13 pins on the BGA

package, 32 pins on the LQFP package).

DDEXT

PI/O Power Supply. Nominally +3.3 V dc. (6 pins on the BGA package, 10 pins on the

LQFP package).

VDD

PAnalog Power Supply. Nominally +1.2 V dc for the K and B grade models, and 1.0 V

dc for the W grade models, and supplies the processor’s internal PLL (clock generator).

This pin has the same specifications as V

DDINT

, except that added filtering circuitry is

required. For more information, see Power Supplies on Page 9.

VSS

GAnalog Power Supply Return.

GND G Power Supply Return. (54 pins on the BGA package, 39 pins on the LQFP package).

RD, WR, and ALE are three-stated (and not driven) only when RESET is active.

Output only is a three-state driver with its output path always enabled.

Input only is a three-state driver with both output path and pull-up disabled.

Three-state is a three-state driver with pull-up disabled.

Table 3. Pin Descriptions (Continued)

Pin Type

State During and

After Reset Function

ADSP-21365

Rev. 0 | Page 15 of 56 | October 2005

ADDRESS DATA PINS AS FLAGS

To use these pins as flags (FLAGS15–0) set (=1) Bit 20 of the

SYSCTL register to disable the parallel port. Then set (=1) Bits

22 to 25 in the SYSCTL register accordingly.

ADDRESS/DATA MODES

The following table shows the functionality of the AD pins for

8-bit and 16-bit transfers to the parallel port. For 8-bit data

transfers, ALE latches address bits A23–A8 when asserted, fol-

lowed by address bits A7–A0 and data bits D7–D0 when

deasserted. For 16-bit data transfers, ALE latches address bits

A15–A0 when asserted, followed by data bits D15–D0 when

deasserted.

BOOT MODES

CORE INSTRUCTION RATE TO CLKIN RATIO MODES

For details on processor timing, see Timing Specifications and

Figure 5 on Page 18.

Table 4. AD15–0 to Flag Pin Mapping

AD Pin Flag Pin AD Pin Flag Pin

AD0 FLAG8 AD8 FLAG0

AD1 FLAG9 AD9 FLAG1

AD2 FLAG10 AD10 FLAG2

AD3 FLAG11 AD11 FLAG3

AD4 FLAG12 AD12 FLAG4

AD5 FLAG13 AD13 FLAG5

AD6 FLAG14 AD14 FLAG6

AD7 FLAG15 AD15 FLAG7

Table 5. Address/Data Mode Selection

PP Data

Mode ALE

AD7–0

Function

AD15–8

Function

8-Bit Asserted A15–8 A23–16

8-Bit Deasserted D7–0 A7–0

16-Bit Asserted A7–0 A15–8

16-Bit Deasserted D7–0 D15–8

Table 6. Boot Mode Selection

BOOTCFG1–0 Booting Mode

00 SPI Slave Boot

01 SPI Master Boot

10 Parallel Port Boot via EPROM

Table 7. Core Instruction Rate/CLKIN Ratio Selection

CLKCFG1–0 Core to CLKIN Ratio

00 6:1

01 32:1

10 16:1

Rev. 0 | Page 16 of 56 | October 2005

ADSP-21365

ADSP-21365 SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

Parameter

Specifications subject to change without notice.

K Grade B Grade W Grade

Min Max Min Max Min Max Unit

DDINT

Internal (Core) Supply Voltage 1.14 1.26 1.14 1.26 0.95 1.05 V

VDD

Analog (PLL) Supply Voltage 1.14 1.26 1.14 1.26 0.95 1.05 V

DDEXT

External (I/O) Supply Voltage 3.13 3.47 3.13 3.47 3.13 3.47 V

Applies to input and bidirectional pins: AD15–0, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOTCFGx, CLKCFGx, RESET, TCK, TMS, TDI, TRST.

High Level Input Voltage @ V

DDEXT

= max 2.0 V

DDEXT

+ 0.5 2.0 V

DDEXT

+ 0.5 2.0 V

DDEXT

+ 0.5 V

Low Level Input Voltage @ V

DDEXT

= min –0.5 +0.8 –0.5 +0.8 –0.5 +0.8 V

IH_CLKIN

Applies to input pin CLKIN.

High Level Input Voltage @ V

DDEXT

= max 1.74 V

DDEXT

+ 0.5 1.74 V

DDEXT

+ 0.5 1.74 V

DDEXT

+ 0.5 V

IL_CLKIN

Low Level Input Voltage @ V

DDEXT

= min –0.5 +1.19 –0.5 +1.19 –0.5 +1.19 V

AMB

See Thermal Characteristics 46 for information on thermal specifications.

See Engineer-to-Engineer Note (No. EE-277) for further information.

Ambient Operating Temperature 0 +70 –40 +85 –40 +105 °C

Parameter

Test Conditions Min Max Unit

High Level Output Voltage @ V

DDEXT

= min, I

= –1.0 mA

2.4 V

Low Level Output Voltage @ V

DDEXT

= min, I

= 1.0 mA

0.4 V

4, 5

High Level Input Current @ V

DDEXT

= max, V

= V

DDEXT

max 10 μA

Low Level Input Current @ V

DDEXT

= max, V

= 0 V 10 μA

ILPU

Low Level Input Current Pull-Up @ V

DDEXT

= max, V

= 0 V 200 μA

OZH

6, 7

Three-State Leakage Current @ V

DDEXT

= max, V

= V

DDEXT

max 10 μA

OZL

Three-State Leakage Current @ V

DDEXT

= max, V

= 0 V 10 μA

OZLPU

Three-State Leakage Current Pull-Up @ V

DDEXT

= max, V

= 0 V 200 μA

DD-INTYP

8, 9

Supply Current (Internal) t

CCLK

= min, V

DDINT

= nom 800 mA

Supply Current (Analog) A

VDD

= max 10 mA

11,

Input Capacitance f

= 1 MHz, T

CASE

= 25°C, V

= 1.2V 4.7 pF

Specifications subject to change without notice.

Applies to output and bidirectional pins: AD15–0, RD, WR, ALE, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, CLKOUT, XTAL.

See Output Drive Currents 45 for typical drive current capabilities.

Applies to input pins: SPIDS, BOOTCFGx, CLKCFGx, TCK, RESET, CLKIN.

Applies to input pins with 22.5 kΩ internal pull-ups: TRST, TMS, TDI.

Applies to three-stateable pins: FLAG3–0.

Applies to three-stateable pins with 22.5 kΩ pull-ups: AD15–0, DAI_Px, SPICLK, EMU, MISO, MOSI.

Typical internal current data reflects nominal operating conditions.

See Engineer-to-Engineer Note (No. EE-277) for further information.

Characterized, but not tested.

Applies to all signal pins.

Guaranteed, but not tested.

ADSP-21365

Rev. 0 | Page 17 of 56 | October 2005

MAXIMUM POWER DISSIPATION

See Engineer-to-Engineer Note (EE-277) for detailed thermal

and power information regarding maximum power dissipation.

For information on package thermal specifications, see Thermal

Characteristics 46.

ABSOLUTE MAXIMUM RATINGS

ESD SENSITIVITY

Parameter Rating

Internal (Core) Supply Voltage (V

DDINT

)

Stresses greater than those listed above may cause permanent damage to the device.

These are stress ratings only; functional operation of the device at these or any other

conditions greater than those indicated in the operational sections of this specification

is not implied. Exposure to absolute maximum rating conditions for extended periods

may affect device reliability.

–0.3 V to +1.5 V

Analog (PLL) Supply Voltage (A

VDD

)

–0.3 V to +1.5 V

External (I/O) Supply Voltage (V

DDEXT

)

–0.3 V to +4.6 V

Input Voltage –0.5 V to V

DDEXT

+0.5 V

Output Voltage Swing –0.5 V to V

DDEXT

+0.5 V

Load Capacitance

200 pF

Storage Temperature Range

–65°C to +150°C

Junction Temperature Under Bias

125°C

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the ADSP-21365 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 18 of 56 | October 2005

ADSP-21365

TIMING SPECIFICATIONS

The ADSP-21365’s internal clock (a multiple of CLKIN) pro-

vides the clock signal for timing internal memory, processor

core, serial ports, and parallel port (as required for read/write

strobes in asynchronous access mode). During reset, program

the ratio between the processor’s internal clock frequency and

external (CLKIN) clock frequency with the CLKCFG1–0 pins

(see Table 7 on Page 15). To determine switching frequencies

for the serial ports, divide down the internal clock, using the

programmable divider control of each port (DIVx for the serial

ports).

The ADSP-21365’s internal clock switches at higher frequencies

than the system input clock (CLKIN). To generate the internal

clock, the processor uses an internal phase-locked loop (PLL).

This PLL-based clocking minimizes the skew between the sys-

tem clock (CLKIN) signal and the processor’s internal clock (the

clock source for the parallel port logic and I/O pads).

Note the definitions of various clock periods that are a function

of CLKIN and the appropriate ratio control shown in Table 8.

Figure 5 shows core to CLKIN ratios of 6:1, 16:1, and 32:1 with

external oscillator or crystal. Note that more ratios are possible

and can be set through software using the power management

control register (PMCTL). For more information, see the

ADSP-2136x SHARC Processor Programming Reference.

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results

for an individual device, the values given in this data sheet

reflect statistical variations and worst cases. Consequently, it is

not meaningful to add parameters to derive longer times. See

Figure 38 on Page 45 under Test Conditions for voltage refer-

ence levels.

Switching Characteristics specify how the processor changes its

signals. Circuitry external to the processor must be designed for

compatibility with these signal characteristics. Switching char-

acteristics describe what the processor will do in a given

circumstance. Use switching characteristics to ensure that any

timing requirement of a device connected to the processor (such

as memory) is satisfied.

Timing Requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation. Timing requirements guarantee that the processor

operates correctly with other devices.

Table 8. ADSP-21365 CLKOUT and CCLK Clock Genera-

tion Operation

Timing

Requirements Description Calculation

CLKIN Input Clock 1/t

CCLK Core Clock 1/t

CCLK

Table 9. Clock Periods

Timing

Requirements Description

CLKIN Clock Period

CCLK

(Processor) Core Clock Period

PCLK

(Peripheral) Clock Period = 2 × t

CCLK

SCLK

Serial Port Clock Period = (t

PCLK

) × SR

SPICLK

SPI Clock Period = (t

PCLK

) × SPIR

where:

SR = serial port-to-peripheral clock ratio (wide range, determined by SPORT

CLKDIV)

SPIR = SPI-to-peripheral clock ratio (wide range, determined by SPIBAUD

DAI_Px = serial port clock

SPICLK = SPI clock

Figure 5. Core Clock and System Clock Relationship to CLKIN

PLLM

CLKIN

CCLK

(CORE CLOCK)

PLLICLK

XTAL

OSC

CLKOUT

CLK-CFG [1:0]

(6:1, 16:1, 32:1)

PCLK, MCLK

(PERIPHERAL CLOCK,

MASTER CLOCK)

INDIV

÷1, 2

DIVEN

÷2,4,8,16

ADSP-21365

Rev. 0 | Page 19 of 56 | October 2005

Power-Up Sequencing

The timing requirements for processor startup are given in

Table 10.

Table 10. Power-Up Sequencing Timing Requirements (Processor Startup)

Parameter Min Max Unit

Timing Requirements

RSTVDD

RESET Low Before V

DDINT

DDEXT

On 0 ns

IVDDEVDD

DDINT

On Before V

DDEXT

–50 200 ms

CLKVDD

CLKIN Valid After V

DDINT

DDEXT

Valid 0 200 ms

CLKRST

CLKIN Valid Before RESET Deasserted 10

μs

PLLRST

PLL Control Setup Before RESET Deasserted 20 μs

Switching Characteristic

CORERST

Core Reset Deasserted After RESET Deasserted 4096t

+ 2 t

CCLK

3, 4

Valid V

DDINT

DDEXT

assumes that the supplies are fully ramped to their 1.2 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds

depending on the design of the power supply subsystem.

Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to your crystal oscillator manufacturer’s data sheet for start-up time.

Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly initialize and

propagate default states at all I/O pins.

The 4096 cycle count depends on t

SRST

specification in Table 12. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097

cycles maximum.

Figure 6. Power-Up Sequencing

CLKIN

RESET

tRSTVDD

RSTOUT

VDDEXT

VDDINT

tPLLRST

tCLKRST

tCLKVDD

tIVDDEVDD

CLK_CFG1-0

tCORERST

Rev. 0 | Page 20 of 56 | October 2005

ADSP-21365

Clock Input

Clock Signals

The ADSP-21365 can use an external clock or a crystal. See the

CLKIN pin description in Table 3 on Page 12. The user applica-

tion program can configure the ADSP-21365 to use its internal

clock generator by connecting the necessary components to the

CLKIN and XTAL pins. Figure 8 shows the component connec-

tions used for a fundamental frequency crystal operating in

parallel mode.

Note that the clock rate is achieved using a 16.67 MHz crystal

and a PLL multiplier ratio 16:1 (CCLK:CLKIN achieves a clock

speed of 266.72 MHz). To achieve the full core clock rate, pro-

grams need to configure the multiplier bits in the PMCTL

Table 11. Clock Input

Parameter

333 MHz

Unit

Min Max

Timing Requirements

CLKIN Period 18

Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL.

100 ns

CKL

CLKIN Width Low 7.5

CKH

CLKIN Width High 7.5

CKRF

CLKIN Rise/Fall (0.4 V–2.0 V) 3 ns

CCLK

Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t

CCLK

CCLK Period 3.0

10 ns

CKJ

3,4

Actual input jitter should be combined with ac specifications for accurate timing analysis.

Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.

CLKIN Jitter Tolerance –250 +250 ps

Figure 7. Clock Input

CLKIN

tCK

tCKH tCKL

tCKJ

Figure 8. 333 MHz Operation (Fundamental Mode Crystal)

CLKIN XTAL

C1 C2

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.

CONTACT CRYSTAL MANUFACTURER FOR DETAILS. CRYSTAL

SELECTION MUST COMPLY WITH CLKCFG1-0 = 10 OR = 01.

1M⍀

ADSP-21365

Rev. 0 | Page 21 of 56 | October 2005

Reset

Interrupts

The following timing specification applies to the FLAG0,

FLAG1, and FLAG2 pins when they are configured as IRQ0,

IRQ1, and IRQ2 interrupts.

Table 12. Reset

Parameter Min Max Unit

Timing Requirements

WRST

RESET Pulse Width Low 4t

SRST

RESET Setup Before CLKIN Low 8 ns

Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming

stable VDD and CLKIN (not including start-up time of external clock oscillator).

Figure 9. Reset

CLKIN

RESET

tWRST tSRST

Table 13. Interrupts

Parameter Min Max Unit

Timing Requirement

IPW

IRQx Pulse Width 2 × t

PCLK

+2 ns

Figure 10. Interrupts

DAI_P20-1

FLAG2-0

(IRQ2-0)

tIPW

Rev. 0 | Page 22 of 56 | October 2005

ADSP-21365

Core Timer

The following timing specification applies to FLAG3 when it is

configured as the core timer (CTIMER).

Timer PWM_OUT Cycle Timing

The following timing specification applies to Timer0, Timer1,

and Timer2 in PWM_OUT (pulse-width modulation) mode.

Timer signals are routed to the DAI_P20–1 pins through the

SRU. Therefore, the timing specifications provided below are

valid at the DAI_P20–1 pins.

Table 14. Core Timer

Parameter Min Max Unit

Switching Characteristic

WCTIM

CTIMER Pulse Width 2 × t

PCLK

– 1 ns

Figure 11. Core Timer

FLAG3

(CTIMER)

tWCTIM

Table 15. Timer PWM_OUT Timing

Parameter Min Max Unit

Switching Characteristic

PWMO

Timer Pulse Width Output 2 t

PCLK

– 2 2(2

– 1) t

PCLK

Figure 12. Timer PWM_OUT Timing

DAI_P20-1

(TIMER2-0)

tPWMO

ADSP-21365

Rev. 0 | Page 23 of 56 | October 2005

Timer WDTH_CAP Timing

The following timing specification applies to Timer0, Timer1,

and Timer2 in WDTH_CAP (pulse width count and capture)

mode. Timer signals are routed to the DAI_P20–1 pins through

the SRU. Therefore, the timing specification provided below are

valid at the DAI_P20–1 pins.

DAI Pin to Pin Direct Routing

For direct pin connections only (for example, DAI_PB01_I to

DAI_PB02_O).

Table 16. Timer Width Capture Timing

Parameter Min Max Unit

Timing Requirement

PWI

Timer Pulse Width 2 t

PCLK

2(2

– 1) t

PCLK

Figure 13. Timer Width Capture Timing

DAI_P20-1

(TIMER2-0)

tPWI

Table 17. DAI Pin to Pin Routing

Parameter Min Max Unit

Timing Requirement

DPIO

Delay DAI Pin Input Valid to DAI Output Valid 1.5 10 ns

Figure 14. DAI Pin to Pin Direct Routing

DAI_Pn

tDPIO

DAI_Pm

Rev. 0 | Page 24 of 56 | October 2005

ADSP-21365

Precision Clock Generator (Direct Pin Routing)

This timing is only valid when the SRU is configured such that

the precision clock generator (PCG) takes its inputs directly

from the DAI pins (via pin buffers) and sends its outputs

directly to the DAI pins. For the other cases, where the PCG’s

inputs and outputs are not directly routed to/from DAI pins (via

pin buffers) there is no timing data available. All timing param-

eters and switching characteristics apply to external DAI pins

(DAI_P01 – DAI_P20).

Table 18. Precision Clock Generator (Direct Pin Routing)

K and B Grade W Grade

Parameter Min Max Max Unit

Timing Requirements

PCGIP

Input Clock Period 20 ns

STRIG

PCG Trigger Setup Before Falling

Edge of PCG Input Clock

4.5 ns

HTRIG

PCG Trigger Hold After Falling

Edge of PCG Input Clock

3ns

Switching Characteristics

DPCGIO

PCG Output Clock and Frame Sync

Active Edge Delay After PCG Input

Clock

2.5 10 10 ns

DTRIGCLK

PCG Output Clock Delay After PCG

Trigger

2.5 + ((2.5 + D) × t

PCGIP

) 10 + ((2.5 + D) × t

PCGIP

) 12 + ((2.5 + D) × t

PCGIP

)ns

DTRIGFS

PCG Frame Sync Delay After PCG

Trigger

2.5 + ((2.5 + D – PH) × t

PCGIP

) 10 + ((2.5 + D – PH) × t

PCGIP

) 12 + ((2.5 + D – PH) × t

PCGIP

)ns

PCGOP

Output Clock Period 2 × t

PCGIP

D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-2136x SHARC Processor Hardware Reference, “Precision Clock Generators” chapter.

In normal mode, t

PCGOP

(min) = 2 x t

PCGIP

Figure 15. Precision Clock Generator (Direct Pin Routing)

DAI_Pn

PCG_TRIGx_I

tSTRIG

DAI_Pm

PCG_EXTx_I

(CLKIN)

DAI_Py

PCG_CLKx_O

DAI_Pz

PCG_FSx_O

tHTRIG

tDPCGIO

tDTRIGFS

tPCGIP

tPCGOP

tDTRIGCLK tDPCGIO

ADSP-21365

Rev. 0 | Page 25 of 56 | October 2005

Flags

The timing specifications provided below apply to the FLAG3–0

and DAI_P20–1 pins, the parallel port, and the serial peripheral

interface (SPI). See Table 3, “Pin Descriptions,” on Page 12 for

more information on flag use.

Table 19. Flags

Parameter Min Max Unit

Timing Requirement

FIPW

FLAG3–0 IN Pulse Width 2 × t

PCLK

+ 3 ns

Switching Characteristic

FOPW

FLAG3–0 OUT Pulse Width 2 × t

PCLK

– 1 ns

Figure 16. Flags

DAI_P20-1

(FLAG3-0IN)

(DATA31-0)

tFIPW

DAI_P20-1

(FLAG3-0OUT)

(DATA31-0)

tFOPW

Rev. 0 | Page 26 of 56 | October 2005

ADSP-21365

Memory Read—Parallel Port

Use these specifications for asynchronous interfacing to memo-

ries (and memory-mapped peripherals) when the ADSP-21365

is accessing external memory space.

Table 20. 8-Bit Memory Read Cycle

Parameter

K and B Grade W Grade

Min Max Min Max Unit

Timing Requirements

DRS

AD7–0 Data Setup Before RD High 3.3 4.5 ns

DRH

AD7–0 Data Hold After RD High 0 0 ns

DAD

AD15–8 Address to AD7–0 Data Valid D + t

PCLK

– 5.0 D + t

PCLK

– 5.0 ns

Switching Characteristics

ALEW

ALE Pulse Width 2 × t

PCLK

– 2.0 2 × t

PCLK

– 2.0 ns

ADAS

AD15–0 Address Setup Before ALE Deasserted t

PCLK

– 2.5 t

PCLK

– 2.5 ns

RRH

Delay Between RD Rising Edge to Next

Falling Edge

H + t

PCLK

– 1.4 H + t

PCLK

– 1.4 ns

ALERW

ALE Deasserted to Read Asserted 2 × t

PCLK

– 3.8 2 × t

PCLK

– 3.8 ns

RWALE

Read Deasserted to ALE Asserted F + H + 0.5 F + H + 0.5 ns

ADAH

AD15–0 Address Hold After ALE Deasserted t

PCLK

– 2.3 t

PCLK

– 2.3 ns

ALEHZ

ALE Deasserted to AD7–0 Address in High Z t

PCLK

+ 3.0 t

PCLK

+ 3.8 ns

RD Pulse Width D – 2.0 D – 2.0 ns

RDDRV

AD7–0 ALE Address Drive After Read High F + H + t

PCLK

– 2.3 F + H + t

PCLK

– 2.3 ns

ADRH

AD15–8 Address Hold After RD High H H ns

DAWH

AD15–8 Address to RD High D + t

PCLK

– 4.0 D + t

PCLK

– 4.0 ns

D = (data cycle duration = the value set by the PPDUR bits (5–1) in the PPCTL register) × t

PCLK

H = t

PCLK

(if a hold cycle is specified, else H = 0)

F = 7 x t

PCLK

(if FLASH_MODE is set, else F = 0)

PCLK

= (peripheral) clock period = 2 × t

CCLK

The timing specified here is sufficient to satisfy either t

DAD

or t

DRS

as they are independent.

On reset, ALE is an active high cycle. However, it can be configured by software to be active low.

Figure 17. Read Cycle for 8-Bit Memory Timing

VALID

ADDRESS

AD15-8

tADAS

AD7-0

tALEW

ALE

RD tRW

tADAH

tADRH

tDRS tDRH

tDAD

tALERW

tRWALE

VALID

DATA

VALID

ADDRESS

tRDDRV

tALEHZ

VALID ADDRESS

VALID

DATA

tRRH

tDAWH

NOTE: MEMORY READS ALWAYS OCCUR IN GROUPS OF FOUR

BETWEEN ALE CYCLES. THIS FIGURE ONLY SHOWS TWO MEMORY

READS IN ORDER TO PROVIDE THE NECESSAR

TIMING INFORMATION.

VALID ADDRESS

ADSP-21365

Rev. 0 | Page 27 of 56 | October 2005

Table 21. 16-Bit Memory Read Cycle

Parameter

K and B Grade W Grade

Min Max Min Max Unit

Timing Requirements

DRS

AD15–0 Data Setup Before RD High 3.3 4.5 ns

DRH

AD15–0 Data Hold After RD High 0 0 ns

Switching Characteristics ns

ALEW

ALE Pulse Width 2 × t

PCLK

– 2.0 2 × t

PCLK

– 2.0 ns

ADAS

AD15–0 Address Setup Before ALE Deasserted t

PCLK

– 2.5 t

PCLK

– 2.5 ns

ALERW

ALE Deasserted to Read Asserted 2 × t

PCLK

– 3.8 2 × t

PCLK

– 3.8 ns

RRH

Delay Between RD Rising Edge to Next Falling

Edge

H + t

PCLK

– 1.4 H + t

PCLK

– 1.4 ns

RWALE

Read Deasserted to ALE Asserted F + H + 0.5 F + H + 0.5 ns

RDDRV

ALE Address Drive After Read High F + H + t

PCLK

– 2.3 F + H + t

PCLK

– 2.3 ns

ADAH

AD15–0 Address Hold After ALE Deasserted t

PCLK

– 2.3 t

PCLK

– 2.3 ns

ALEHZ

ALE Deasserted to Address/Data15–0 in High Z t

PCLK

+ 3.0 t

PCLK

+ 3.8 ns

RD Pulse Width D – 2.0 D – 2.0 ns

D = (data cycle duration = the value set by the PPDUR bits (5–1) in the PPCTL register) × t

PCLK

H = t

PCLK

(if a hold cycle is specified, else H = 0)

F = 7 x t

PCLK

(if FLASH_MODE is set, else F = 0)

PCLK

= (peripheral) clock period = 2 × t

CCLK

On reset, ALE is an active high cycle. However, it can be configured by software to be active low.

This parameter is only available when in EMPP = 0 mode.

Figure 18. Read Cycle for 16-Bit Memory Timing

AD15-0

tDRS tDRH

tALEHZ

tADAH

tADAS

VALID ADDRESS VALID DATA VALID DATA

tALEW

tRW

tALERW

tRRH

ALE

tRWALE

tRDDRV

VALID

ADDRESS

NOTE: FOR 16-BIT MEMORY READS, WHEN EMPP ⫽0, ONLY ONE RD PULSE OCCURS BETWEEN ALE CYCLES.

WHEN EMPP = 0, MULTIPLE RD PULSES OCCUR BETWEEN ALE CYCLES. FOR COMPLETE INFORMATION,

SEE THE ADSP-2136X SHARC PROCESSOR HARDWARE REFERENCE.

Rev. 0 | Page 28 of 56 | October 2005

ADSP-21365

Memory Write—Parallel Port

Use these specifications for asynchronous interfacing to memo-

ries (and memory-mapped peripherals) when the

ADSP-21365 is accessing external memory space.

Table 22. 8-Bit Memory Write Cycle

Parameter

K and B Grade W Grade

Min Max Min Max Unit

Switching Characteristics:

ALEW

ALE Pulse Width 2 × t

PCLK

– 2.0 2 × t

PCLK

– 2.0 ns

ADAS

AD15–0 Address Setup Before ALE Deasserted t

PCLK

– 2.8 t

PCLK

– 2.8 ns

ALERW

ALE Deasserted to Write Asserted 2 × t

PCLK

– 3.8 2 × t

PCLK

– 3.8 ns

RWALE

Write Deasserted to ALE Asserted H + 0.5 H + 0.5 ns

WRH

Delay Between WR Rising Edge to Next WR Falling Edge F + H + t

PCLK

– 2.3 F + H + t

PCLK

– 2.3 ns

ADAH

AD15–0 Address Hold After ALE Deasserted t

PCLK

– 0.5 t

PCLK

– 0.5 ns

WR Pulse Width D – F – 2.0 D – F – 2.0 ns

ADWL

AD15–8 Address to WR Low t

PCLK

– 2.8 t

PCLK

– 3.5 ns

ADWH

AD15–8 Address Hold After WR High H H ns

DWS

AD7–0 Data Setup Before WR High D – F + t

PCLK

– 4.0 D – F + t

PCLK

– 4.0 ns

DWH

AD7–0 Data Hold After WR High H H ns

DAWH

AD15–8 Address to WR High D – F + t

PCLK

– 4.0 D – F + t

PCLK

– 4.0 ns

D = (data cycle duration = the value set by the PPDUR bits (5–1) in the PPCTL register) × t

PCLK

H = t

PCLK

(if a hold cycle is specified, else H = 0)

F = 7 x t

PCLK

(if FLASH_MODE is set, else F = 0). If FLASH_MODE is set, D must be ≥ 9 x t

PCLK

= (peripheral) clock period = 2 × t

CCLK

On reset, ALE is an active high cycle. However, it can be configured by software to be active low.

Figure 19. Write Cycle for 8-Bit Memory Timing

AD15-8 VALID

ADDRESS VALID ADDRESS

tADAS

AD7-0

ALE

tADAH tADWH

tADWL

VALID DATA

tDAWH

tWRH

tRWALE

VALID

ADDRESS VALID DATA

tALEW

tALERW

tWW

tDWS

tDWH

VALID ADDRESS

NOTE: MEMORY WRITES ALWAYS OCCUR IN GROUPS OF FOUR

BETWEEN ALE CYCLES. THIS FIGURE ONLY SHOWS TWO MEMORY

WRITES IN ORDER TO PROVIDE THE NECESSARY TIMING INFORMATION.

ADSP-21365

Rev. 0 | Page 29 of 56 | October 2005

Table 23. 16-Bit Memory Write Cycle

Parameter

K and B Grade W Grade

Min Min Unit

Switching Characteristics

ALEW

ALE Pulse Width 2 × t

PCLK

– 2.0 2 × t

PCLK

– 2.0 ns

ADAS

AD15–0 Address Setup Before ALE Deasserted t

PCLK

– 2.5 t

PCLK

– 2.5 ns

ALERW

ALE Deasserted to Write Asserted 2 × t

PCLK

– 3.8 2 × t

PCLK

– 3.8 ns

RWALE

Write Deasserted to ALE Asserted H + 0.5 H + 0.5 ns

WRH

Delay Between WR Rising Edge to Next WR Falling Edge F + H + t

PCLK

– 2.3 F + H + t

PCLK

– 2.3 ns

ADAH

AD15–0 Address Hold After ALE Deasserted t

PCLK

– 2.3 t

PCLK

– 2.3 ns

WR Pulse Width D – F – 2.0 D – F – 2.0 ns

DWS

AD15–0 Data Setup Before WR High D – F + t

PCLK

– 4.0 D – F + t

PCLK

– 4.0 ns

DWH

AD15–0 Data Hold After WR High H H ns

D = (data cycle duration = the value set by the PPDUR bits (5–1) in the PPCTL register) × t

PCLK

H = t

PCLK

(if a hold cycle is specified, else H = 0)

F = 7 x t

PCLK

(if FLASH_MODE is set, else F = 0). If FLASH_MODE is set, D must be ≥ 9 x t

PCLK

= (peripheral) clock period = 2 × t

CCLK

On reset, ALE is an active high cycle. However, it can be configured by software to be active low.

This parameter is only available when in EMPP = 0 mode.

Figure 20. Write Cycle for 16-Bit Memory Timing

AD15-0 VALID

ADDRESS VALID DATA

tADAS

ALE

tADAH

tWRH

tRWALE

tALEW tALERW

tWW

tDWS

tDWH

VALID DATA VALID

ADDRESS

NOTE: FOR 16-BIT MEMORY WRITES, WHEN EMPP Þ0, ONLY ONE WR PULSE OCCURS BETWEEN ALE CYCLES.

WHEN EMPP = 0, MULTIPLE WR PULSES OCCUR BETWEEN ALE CYCLES. FOR COMPLETE INFORMATION,

SEE THE ADSP-2136X SHARC PROCESSOR HARDWARE REFERENCE.

Rev. 0 | Page 30 of 56 | October 2005

ADSP-21365

Serial Ports

To determine whether communication is possible between two

devices at clock speed n, the following specifications must be

confirmed: 1) frame sync delay and frame sync setup and hold,

2) data delay and data setup and hold, and 3) SCLK width.

Serial port signals (SCLK, FS, data channel A, data channel B)

are routed to the DAI_P20–1 pins using the SRU. Therefore, the

timing specifications provided below are valid at the

DAI_P20–1 pins.

Table 24. Serial Ports—External Clock

K and B Grade W Grade

Parameter Min Max Max Unit

Timing Requirements

SFSE

FS Setup Before SCLK

(Externally Generated FS in Either Transmit or Receive Mode) 2.5 ns

HFSE

FS Hold After SCLK

(Externally Generated FS in Either Transmit or Receive Mode) 2.5 ns

SDRE

Receive Data Setup Before Receive SCLK 2.5 ns

HDRE

Receive Data Hold After SCLK 2.5 ns

SCLKW

SCLK Width 12 ns

SCLK

SCLK Period 24 ns

Switching Characteristics

DFSE

FS Delay After SCLK

(Internally Generated FS in Either Transmit or Receive Mode) 9.5 11 ns

HOFSE

FS Hold After SCLK

(Internally Generated FS in Either Transmit or Receive Mode) 2 ns

DDTE

Transmit Data Delay After Transmit SCLK 9.5 11 ns

HDTE

Transmit Data Hold After Transmit SCLK 2 ns

Referenced to sample edge.

Referenced to drive edge.

Table 25. Serial Ports—Internal Clock

K and B Grade W Grade

Parameter Min Max Max Unit

Timing Requirements

SFSI

FS Setup Before SCLK

(Externally Generated FS in Either Transmit or Receive Mode) 7 ns

HFSI

FS Hold After SCLK

(Externally Generated FS in Either Transmit or Receive Mode) 2.5 ns

SDRI

Receive Data Setup Before SCLK 7 ns

HDRI

Receive Data Hold After SCLK 2.5 ns

Switching Characteristics

DFSI

FS Delay After SCLK (Internally Generated FS in Transmit Mode) 3 3.5 ns

HOFSI

FS Hold After SCLK (Internally Generated FS in Transmit Mode) –1.0 ns

DFSIR

FS Delay After SCLK (Internally Generated FS in Receive Mode) 8 9.5 ns

HOFSIR

FS Hold After SCLK (Internally Generated FS in Receive Mode) –1.0 ns

DDTI

Transmit Data Delay After SCLK 3 4.0 ns

HDTI

Transmit Data Hold After SCLK –1.0 ns

SCLKIW

Transmit or Receive SCLK Width 0.5t

SCLK

– 2 0.5t

SCLK

+ 2 0.5t

SCLK

+ 2 ns

Referenced to the sample edge.

Referenced to drive edge.

ADSP-21365

Rev. 0 | Page 31 of 56 | October 2005

Table 26. Serial Ports—Enable and Three-State

K and B Grade W Grade

Parameter Min Max Max Unit

Switching Characteristics

DDTEN

Data Enable from External Transmit SCLK 2 ns

DDTTE

Data Disable from External Transmit SCLK 7 8.5 ns

DDTIN

Data Enable from Internal Transmit SCLK –1 ns

Referenced to drive edge.

Table 27. Serial Ports—External Late Frame Sync

K and B Grade W Grade

Parameter Min Max Max Unit

Switching Characteristics

DDTLFSE

Data Delay from Late External Transmit FS or

External Receive FS with MCE = 1, MFD = 0 9 10.5 ns

DDTENFS

Data Enable for MCE = 1, MFD = 0 0.5 ns

The t

DDTLFSE

and t

DDTENFS

parameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0.

Figure 21. External Late Frame Sync

This figure reflects changes made to support left-justified sample pair mode.

DRIVE SAMPLE DRIVE

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

DAI_P20-1

(DATA CHANNEL A/B)

DRIVE SAMPLE DRIVE

LATE EXTERNAL TRANSMIT FS

EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0

1ST BIT 2ND BIT

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

1ST BIT 2ND BIT

tHFSE/I

tSFSE/I

tDDTE/I

tDDTENFS

tDDTLFSE

tHDTE/I

tSFSE/I

tDDTE/I

tDDTENFS

tDDTLFSE

tHDTE/I

DAI_P20-1

(DATA CHANNEL A/B)

NOTE: SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20-1 PINS

USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20-1 PINS.

tHFSE/I

Rev. 0 | Page 32 of 56 | October 2005

ADSP-21365

Figure 22. Serial Ports

DRIVE EDGE

DAI_P20-1

SCLK (INT)

DRIVE EDGE DRIVE EDGE

SCLKDAI_P20-1

SCLK (EXT)

tDDTTE

tDDTEN

tDDTIN

DAI_P20-1

(DATA CHANNEL A/B)

DAI_P20-1

(DATA CHANNEL A/B)

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

DRIVE EDGE SAMPLE EDGE

DATA RECEIVE—INTERNAL CLOCK DATA RECEIVE

—

TERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

tSDRI tHDRI

tSFSI tHFSI

tDFSI

tHOFSI

tSCLKIW

tSDRE tHDRE

tSFSE tHFSE

tDFSE

tSCLKW

tHOFSE

DAI_P20-1

(DATA CHANNEL A/B)

tDDTI

DRIVE EDGE SAMPLE EDGE

DATA TRANSMIT—INTERNAL CLOCK

tSFSI tHFSI

tDFSI

tHOFSI

tSCLKIW

tHDTI

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

tDDTE

DRIVE EDGE SAMPLE EDGE

DATA TRANSMIT—EXTERNAL CLOCK

tSFSE tHFSE

tDFSE

tHOFSE

tSCLKW

tHDTE

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

DAI_P20-1

(DATA CHANNEL A/B)

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

DAI_P20-1

(DATA CHANNEL A/B)

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

DAI_P20-1

(DATA CHANNEL A/B)

ADSP-21365

Rev. 0 | Page 33 of 56 | October 2005

Input Data Port (IDP)

The timing requirements for the IDP are given in Table 28. IDP

signals (SCLK, FS, SDATA) are routed to the DAI_P20–1 pins

using the SRU. Therefore, the timing specifications provided

below are valid at the DAI_P20–1 pins.

Table 28. IDP

Parameter Min Max Unit

Timing Requirements

SISFS

FS Setup Before SCLK Rising Edge 3 ns

SIHFS

FS Hold After SCLK Rising Edge 3 ns

SISD

SData Setup Before SCLK Rising Edge 3 ns

SIHD

SData Hold After SCLK Rising Edge 3 ns

IDPCLKW

Clock Width 9 ns

IDPCLK

Clock Period 24 ns

DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

Figure 23. IDP Master Timing

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

SAMPLE EDGE

tSISFS tSIHFS

tIPDCLK

DAI_P20-1

(SDATA)

tIPDCLKW

tSISD tSIHD

Rev. 0 | Page 34 of 56 | October 2005

ADSP-21365

Parallel Data Acquisition Port (PDAP)

The timing requirements for the PDAP are provided in

Table 29. PDAP is the parallel mode operation of channel 0 of

the IDP. For details on the operation of the IDP, see the IDP

chapter of the ADSP-2136x SHARC Processor Hardware Refer-

ence. Note that the most significant 16 bits of external PDAP

data can be provided through either the parallel port AD15–0 or

the DAI_P20–5 pins. The remaining 4 bits can only be sourced

through DAI_P4–1. The timing below is valid at the

DAI_P20–1 pins or at the AD15–0 pins.

Table 29. Parallel Data Acquisition Port (PDAP)

Parameter Min Max Unit

Timing Requirements

SPCLKEN

PDAP_CLKEN Setup Before PDAP_CLK Sample Edge 2.5 ns

HPCLKEN

PDAP_CLKEN Hold After PDAP_CLK Sample Edge 2.5 ns

PDSD

PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge 3.0 ns

PDHD

PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge 2.5 ns

PDCLKW

Clock Width 7.0 ns

PDCLK

Clock Period 24 ns

Switching Characteristics

PDHLDD

Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word 2 × t

PCLK

– 1 ns

PDSTRB

PDAP Strobe Pulse Width 2 × t

PCLK

– 1.5 ns

Source pins of DATA are ADDR7–0, DATA7–0, or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.

Figure 24. PDAP Timing

DAI_P20-1

(PDAP_CLK)

SAMPLE EDGE

tPDSD tPDHD

tSPCLKEN tHPCLKEN

tPDCLKW

DATA

DAI_P20-1

(PDAP_CLKEN)

tPDSTRB

tPDHLDD

DAI_P20-1

(PDAP_STROBE)

tPDCLK

ADSP-21365

Rev. 0 | Page 35 of 56 | October 2005

Pulse-Width Modulation Generators

Sample Rate Converter—Serial Input Port

The SRC input signals (SCLK, FS, and SDATA) are routed from

the DAI_P20–1 pins using the SRU. Therefore, the timing spec-

ifications provided in Table 31 are valid at the DAI_P20–1 pins.

Table 30. PWM Timing

Parameter Min Max Unit

Switching Characteristics

PWMW

PWM Output Pulse Width t

PCLK

– 2 (2

– 2) x t

PCLK

– 2 ns

PWMP

PWM Output Period 2 × t

PCLK

– 1.5 (2

– 1) x t

PCLK

Figure 25. PWM Timing

PWM

OUTPUTS

tPWMW

tPWMP

Table 31. SRC, Serial Input Port

Parameter Min Max Unit

Timing Requirements

SRCSFS

FS Setup Before SCLK Rising Edge 3 ns

SRCHFS

FS Hold After SCLK Rising Edge 3 ns

SRCSD

SData Setup Before SCLK Rising Edge 3 ns

SRCHD

SData Hold After SCLK Rising Edge 3 ns

SRCCLKW

Clock Width 36 ns

SRCCLK

Clock Period 80 ns

DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

Figure 26. SRC Serial Input Port Timing

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

SAMPLE EDGE

tSRCSFS tSRCHFS

tSRCCLK

DAI_P20-1

(SDATA)

tSRCCLKW

tSRCSD tSRCHD

Rev. 0 | Page 36 of 56 | October 2005

ADSP-21365

Sample Rate Converter—Serial Output Port

For the serial output port, the frame-sync is an input and should

meet setup and hold times with regard to SCLK on the output

port. The serial data output, SDATA, has a hold time and delay

specification with regard to SCLK. Note that SCLK rising edge is

the sampling edge and the falling edge is the drive edge.

Table 32. SRC, Serial Output Port

K and B Grade W Grade

Parameter Min Max Max Unit

Timing Requirements

SRCSFS

FS Setup Before SCLK Rising Edge 3 ns

SRCHFS

FS Hold After SCLK Rising Edge 3 ns

Switching Characteristics

SRCTDD

Transmit Data Delay After SCLK Falling Edge 10.5 12.5 ns

SRCTDH

Transmit Data Hold After SCLK Falling Edge 2 ns

DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

Figure 27. SRC Serial Output Port Timing

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

tSRCSFS tSRCHFS

DAI_P20-1

(SDATA)

tSRCTDD

tSRCTDH

SAMPLE EDGE

tSRCCLK

tSRCCLKW

ADSP-21365

Rev. 0 | Page 37 of 56 | October 2005

SPDIF Transmitter

Serial data input to the SPDIF transmitter can be formatted as

left-justified, I

S, or right-justified with word widths of 16, 18,

20, or 24 bits. The following sections provide timing for the

transmitter.

SPDIF Transmitter—Serial Input Waveforms

Figure 28 shows the right-justified mode. LRCLK is HI for the

left channel and LO for the right channel. Data is valid on the

rising edge of SCLK. The MSB is delayed 12-bit clock periods

(in 20-bit output mode) or 16-bit clock periods (in 16-bit output

mode) from an LRCLK transition, so that when there are 64

SCLK periods per LRCLK period, the LSB of the data will be

right-justified to the next LRCLK transition.

Figure 29 shows the default I

S-justified mode. LRCLK is LO for

the left channel and HI for the right channel. Data is valid on the

rising edge of SCLK. The MSB is left-justified to an LRCLK

transition but with a single SCLK period delay.

Figure 30 shows the left-justified mode. LRCLK is HI for the left

channel and LO for the right channel. Data is valid on the rising

edge of SCLK. The MSB is left-justified to an LRCLK transition

with no MSB delay.

Figure 28. Right -Justified Mode

LRCLK

SCLK

SDATA

LEFT CHANNEL RIGHT CHANNEL

MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB MSB-1 MSB-2 LSB+2 LSB+1 LSBLSB MSB

Figure 29. I

S-Justified Mode

MSB-1 MSB-2 LSB+2 LSB+1 LSB

LRCLK

SCLK

SDATA

LEFT CHANNEL

RIGHT CHANNEL

MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB MSBMSB

Figure 30. Left-Justified Mode

LRCLK

SCLK

SDATA

LEFT CHANNEL RIGHT CHANNEL

MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB MSB+1

MSB

Rev. 0 | Page 38 of 56 | October 2005

ADSP-21365

SPDIF Transmitter Input Data Timing

The timing requirements for the input port are given in

Table 33. Input signals (SCLK, FS, SDATA) are routed to the

DAI_P20–1 pins using the SRU. Therefore, the timing specifica-

tions provided below are valid at the DAI_P20–1 pins.

Oversampling Clock (TXCLK) Switching Characteristics

The SPDIF transmitter has an oversampling clock. This TXCLK

input is divided down to generate the biphase clock.

Table 33. SPDIF Transmitter Input Data Timing

K and B Grade W Grade

Parameter Min Min Max Unit

Timing Requirements

SISFS

FS Setup Before SCLK Rising Edge 3 3 ns

SIHFS

FS Hold After SCLK Rising Edge 3 3 ns

SISD

SData Setup Before SCLK Rising Edge 3 3 ns

SIHD

SData Hold After SCLK Rising Edge 3 3 ns

SISCLKW

Clock Width 36 36 ns

SISCLK

Clock Period 80 80 ns

SITXCLKW

Transmit Clock Width 9 9.5 ns

SITXCLK

Transmit Clock Period 20 20 ns

DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

Figure 31. SPDIF Transmitter Input Timing

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

SAMPLE EDGE

tSISD

tSISFS

tSISCLKW

DAI_P20-1

(SDATA)

DAI_P20-1

(TXCLK)

tSIHD

tSIHFS

tSITXCLKW tSITXCLK

Table 34. Over Sampling Clock (TXCLK) Switching Characteristics

Parameter Min Max Unit

TXCLK Frequency for TXCLK = 768 × FS 147.5 MHz

TXCLK Frequency for TXCLK = 512 × FS 98.4 MHz

TXCLK Frequency for TXCLK = 384 × FS 73.8 MHz

TXCLK Frequency for TXCLK = 256 × FS 49.2 MHz

Frame Rate 192.0 kHz

ADSP-21365

Rev. 0 | Page 39 of 56 | October 2005

SPDIF Receiver

The following section describes timing as it relates to the SPDIF

receiver.

Internal Digital PLL Mode

In the internal digital phase-locked loop mode the internal PLL

(digital PLL) generates the 512 × FS clock.

Table 35. SPDIF Receiver Output Timing (Internal Digital PLL Mode)

Parameter Min Max Unit

Switching Characteristics

DFSI

LRCLK Delay After SCLK 5 ns

HOFSI

LRCLK Hold After SCLK –2 ns

DDTI

Transmit Data Delay After SCLK 5 ns

HDTI

Transmit Data Hold After SCLK –2 ns

SCLKIW

Transmit SCLK Width 38 ns

CCLK

Core Clock Period 5 ns

SCLK frequency is 64 × FS where FS = the frequency of LRCLK.

Figure 32. SPDIF Receiver Internal Digital PLL Mode Timing

DRIVE EDGE SAMPLE EDGE

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

DAI_P20-1

(DATA CHANNEL A/B)

tSCLKIW

tDFSI

tDDTI

tHOFSI

tHDTI

Rev. 0 | Page 40 of 56 | October 2005

ADSP-21365

SPI Interface—Master

The ADSP-21365 contains two SPI ports. The primary has dedi-

cated pins and the secondary is available through the DAI. The

timing provided in Table 36 and Table 37 applies to both.

Table 36. SPI Interface Protocol—Master Switching and Timing Specifications

Parameter

K Grade W Grade

Min Max Min Max Unit

Timing Requirements

SSPIDM

Data Input Valid to SPICLK Edge (Data Input

Setup Time)

5.2 6.2 ns

SSPIDM

Data Input Valid to SPICLK Edge (Data Input

Setup Time) (SPI2)

8.2 9.5 ns

HSPIDM

SPICLK Last Sampling Edge to Data

Input Not Valid

22ns

Switching Characteristics

SPICLKM

Serial Clock Cycle 8 × t

PCLK

– 2 8 × t

PCLK

– 2 ns

SPICHM

Serial Clock High Period 4 × t

PCLK

– 2 4 × t

PCLK

– 2 ns

SPICLM

Serial Clock Low Period 4 × t

PCLK

– 2 4 × t

PCLK

– 2 ns

DDSPIDM

SPICLK Edge to Data Out Valid

(Data Out Delay Time)

3.0 3.0 ns

DDSPIDM

SPICLK Edge to Data Out Valid

(Data Out Delay Time) (SPI2)

8.0 9.5 ns

HDSPIDM

SPICLK Edge to Data Out Not Valid

(Data Out Hold Time)

22ns

SDSCIM

FLAG3–0IN (SPI Device Select) Low to First

SPICLK Edge

4 × t

PCLK

– 2.5 4 × t

PCLK

– 3.0 ns

SDSCIM

FLAG3–0IN (SPI Device Select) Low to First

SPICLK Edge (SPI2)

4 × t

PCLK

– 2.5 4 × t

PCLK

– 3.0 ns

HDSM

Last SPICLK Edge to FLAG3–0IN High 4 × t

PCLK

– 2 4 × t

PCLK

– 2 ns

SPITDM

Sequential Transfer Delay 4 × t

PCLK

– 1 4 × t

PCLK

– 1 ns

ADSP-21365

Rev. 0 | Page 41 of 56 | October 2005

Figure 33. SPI Master Timing

LSB

VALID

MSB

VALID

tSSPIDM tHSPIDM

tHDSPIDM

LSBMSB

tHSPIDM

tDDSPIDM

MOSI

(OUTPUT)

MISO

(INPUT)

FLAG3-0

(OUTPUT)

SPICLK

(CP = 0)

(OUTPUT)

SPICLK

(CP = 1)

(OUTPUT)

tSPICHM tSPICLM

tSPICLM

tSPICLKM

tSPICHM

tHDSM tSPITDM

tHDSPIDM

LSB

VALID

LSBMSB

MSB

VALID

tHSPIDM

tDDSPIDM

MOSI

(OUTPUT)

MISO

(INPUT)

tSSPIDM

CPHASE = 1

CPHASE = 0

tSDSCIM

tSSPIDM

Rev. 0 | Page 42 of 56 | October 2005

ADSP-21365

SPI Interface—Slave

Table 37. SPI Interface Protocol—Slave Switching and Timing Specifications

K and B Grade W Grade

Parameter Min Max Max Unit

Timing Requirements

SPICLKS

Serial Clock Cycle 4 × t

PCLK

– 2 ns

SPICHS

Serial Clock High Period 2 × t

PCLK

– 2 ns

SPICLS

Serial Clock Low Period 2 × t

PCLK

– 2 ns

SDSCO

SPIDS Assertion to First SPICLK Edge

CPHASE = 0

CPHASE = 1

2 × t

PCLK

2 × t

PCLK

HDS

Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0 2 × t

PCLK

SSPIDS

Data Input Valid to SPICLK Edge (Data Input Setup Time) 2 ns

HSPIDS

SPICLK Last Sampling Edge to Data Input Not Valid 2 ns

SDPPW

SPIDS Deassertion Pulse Width (CPHASE = 0) 2 × t

PCLK

Switching Characteristics

DSOE

SPIDS Assertion to Data Out Active 0 5 5 ns

DSOE

SPIDS Assertion to Data Out Active (SPI2) 0 8 9 ns

DSDHI

SPIDS Deassertion to Data High Impedance 0 5 5.5 ns

DSDHI

SPIDS Deassertion to Data High Impedance (SPI2) 0 8.6 10 ns

DDSPIDS

SPICLK Edge to Data Out Valid (Data Out Delay Time) 9.5 11.0 ns

HDSPIDS

SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 2 × t

PCLK

DSOV

SPIDS Assertion to Data Out Valid (CPHASE = 0) 5 × t

PCLK

5 × t

PCLK

The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, see the ADSP-2136x SHARC Processor Hardware

Reference, “Serial Peripheral Interface Port” chapter.

ADSP-21365

Rev. 0 | Page 43 of 56 | October 2005

Figure 34. SPI Slave Timing

tHSPIDS

tDDSPIDS

tDSDHI

LSBMSB

MSB VALID

tDSOE tDDSPIDS

tHDSPIDS

MISO

(OUTPUT)

MOSI

(INPUT)

tSSPIDS

SPIDS

(INPUT)

SPICLK

(CP = 0)

(INPUT)

SPICLK

(CP = 1)

(INPUT)

tSDSCO

tSPICHS tSPICLS

tSPICLS

tSPICLKS tHDS

tSPICHS

tSSPIDS tHSPIDS

tDSDHI

LSB VALID

MSB

MSB VALID

tDSOE

tDDSPIDS

MISO

(OUTPUT)

MOSI

(INPUT)

tSSPIDS

LSB VALID

LSB

CPHASE = 1

CPHASE = 0

tSDPPW

tDSOV tHDSPIDS

Rev. 0 | Page 44 of 56 | October 2005

ADSP-21365

JTAG Test Access Port and Emulation

Table 38. JTAG Test Access Port and Emulation

Parameter Min Max Unit

Timing Requirements

TCK

TCK Period t

STAP

TDI, TMS Setup Before TCK High 5 ns

HTAP

TDI, TMS Hold After TCK High 6 ns

SSYS

System Inputs Setup Before TCK High 7 ns

HSYS

System Inputs Hold After TCK High 18 ns

TRSTW

TRST Pulse Width 4t

Switching Characteristics

DTDO

TDO Delay from TCK Low 7 ns

DSYS

System Outputs Delay After TCK Low t

÷ 2 + 7 ns

System Inputs = AD15–0, SPIDS, CLKCFG1–0, RESET, BOOTCFG1–0, MISO, MOSI, SPICLK, DAI_Px, FLAG3–0.

System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15–0, RD, WR, FLAG3–0, CLKOUT, EMU, ALE.

Figure 35. IEEE 1149.1 JTAG Test Access Port

TCK

TMS

TDI

TDO

SYSTEM

INPUTS

SYSTEM

OUTPUTS

tSTAP

tTCK

tHTAP

tDTDO

tSSYS tHSYS

tDSYS

ADSP-21365

Rev. 0 | Page 45 of 56 | October 2005

OUTPUT DRIVE CURRENTS

Figure 36 shows typical I-V characteristics for the output driv-

ers of the ADSP-21365. The curves represent the current drive

capability of the output drivers as a function of output voltage.

TEST CONDITIONS

The ac signal specifications (timing parameters) appear in

Table 12 on Page 21 through Table 38 on Page 44. These include

output disable time, output enable time, and capacitive loading.

The timing specifications for the SHARC apply for the voltage

reference levels in Figure 37.

Timing is measured on signals when they cross the 1.5 V level as

described in Figure 38. All delays (in nanoseconds) are mea-

sured between the point that the first signal reaches 1.5 V and

the point that the second signal reaches 1.5 V.

CAPACITIVE LOADING

Output delays and holds are based on standard capacitive

loads—30 pF on all pins (see Figure 37). Figure 41 shows graph-

ically how output delays and holds vary with load capacitance.

The graphs of Figure 39, Figure 40, and Figure 41 may not be

linear outside the ranges shown for Typical Output Delay vs.

Load Capacitance and Typical Output Rise Time (20%–80%, V

= Min) vs. Load Capacitance.

Figure 36. ADSP-21365 Typical Drive

Figure 37. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

Figure 38. Voltage Reference Levels for AC Measurements

SWEEP (VDDEXT) VOLTAGE (V)

-20

03.50.5 1 1.5 2 2.5 3

-40

-30

-10

SOURCE(VDDEXT)CURRENT(mA)

VOL

3.11V, 125°C

3.3V, 25°C

3.47V, -45°C

VOH

3.11V, 125°C

3.3V, 25°C

3.47V, -45°C

1.5V

30pF

OUTPUT

50⍀

INPUT

OUTPUT

1.5V 1.5V

Figure 39. Typical Output Rise/Fall Time

(20% to 80%, V

DDEXT

= Max)

Figure 40. Typical Output Rise/Fall Time

(20% to 80%, V

DDEXT

= Min)

LOAD CAPACITANCE (pF)

0100 250

RISEANDFALLTIMES(ns)

20015050

FALL

y = 0.0467x + 1.6323

y = 0.045x + 1.524

RISE

LOAD CAPACITANCE (pF)

0 50 100 150 200 250

RISEANDFALLTIMES(ns)

RISE

FALL

y = 0.049x + 1.5105

y = 0.0482x + 1.4604

ADSP-21365

Rev. 0 | Page 46 of 56 | October 2005

THERMAL CHARACTERISTICS

The ADSP-21365 processor is rated for performance over the

temperature range specified in Recommended Operating Con-

ditions 16.

Table 39 through Table 42 airflow measurements comply with

JEDEC standards JESD51-2 and JESD51-6 and the junction-to-

board measurement complies with JESD51-8. Test board and

thermal via design comply with JEDEC standards JESD51-9

(BGA) and JESD51-5 (integrated heat sink LQFP). The junc-

tion-to-case measurement complies with MIL-STD-883. All

measurements use a 2S2P JEDEC test board.

Industrial applications using the BGA package require thermal

vias, to an embedded ground plane, in the PCB. Refer to JEDEC

standard JESD51-9 for printed circuit board thermal ball land

and thermal via design information. Industrial applications

using the LQFP package require thermal trace squares and ther-

mal vias, to an embedded ground plane, in the PCB. The bottom

side heat slug must be soldered to the thermal trace squares.

Refer to JEDEC standard JESD51-5 for more information.

To determine the junction temperature of the device while on

the application PCB, use:

where:

= junction temperature (°C)

= case temperature (°C) measured at the top center of the

package

= junction-to-top (of package) characterization parameter

is the typical value from Table 39 and Table 41.

= power dissipation (see EE Note No. EE-277 for more

information).

Values of θ

are provided for package comparison and PCB

design considerations.

Values of θ

are provided for package comparison and PCB

design considerations when an external heat sink is required.

Note that the thermal characteristics values provided in

Table 39 through Table 42 are modeled values.

Figure 41. Typical Output Delay or Hold vs. Load Capacitance

(at Ambient Temperature)

LOAD CAPACITANCE (pF)

0 20050 100 150

OUTPUTDELAYORHOLD(ns)

-4

-2

Y = 0.0488X

1.5923

TJTT

JT PD

×()+=

Table 39. Thermal Characteristics for BGA (no thermal vias

in PCB)

Parameter Condition Typical Unit

Airflow = 0 m/s 25.40 °C/W

JMA

Airflow = 1 m/s 21.90 °C/W

JMA

Airflow = 2 m/s 20.90 °C/W

5.07 °C/W

Airflow = 0 m/s 0.140 °C/W

JMT

Airflow = 1 m/s 0.330 °C/W

JMT

Airflow = 2 m/s 0.410 °C/W

Table 40. Thermal Characteristics for BGA (thermal vias in

PCB)

Parameter Condition Typical Unit

Airflow = 0 m/s 23.40 °C/W

JMA

Airflow = 1 m/s 20.00 °C/W

JMA

Airflow = 2 m/s 19.20 °C/W

5.00 °C/W

Airflow = 0 m/s 0.130 °C/W

JMT

Airflow = 1 m/s 0.300 °C/W

JMT

Airflow = 2 m/s 0.360 °C/W

Table 41. Thermal Characteristics for LQFP (with heat slug

not soldered to PCB)

Parameter Condition Typical Unit

Airflow = 0 m/s 26.08 °C/W

JMA

Airflow = 1 m/s 24.59 °C/W

JMA

Airflow = 2 m/s 23.77 °C/W

6.83 °C/W

Airflow = 0 m/s 0.236 °C/W

JMT

Airflow = 1 m/s 0.427 °C/W

JMT

Airflow = 2 m/s 0.441 °C/W

Table 42. Thermal Characteristics for LQFP (with heat slug

soldered to PCB)

Parameter Condition Typical Unit

Airflow = 0 m/s 16.50 °C/W

JMA

Airflow = 1 m/s 15.14 °C/W

JMA

Airflow = 2 m/s 14.35 °C/W

6.83 °C/W

Airflow = 0 m/s 0.129 °C/W

JMT

Airflow = 1 m/s 0.255 °C/W

JMT

Airflow = 2 m/s 0.261 °C/W

ADSP-21365

Rev. 0 | Page 47 of 56 | October 2005

136-BALL BGA PIN CONFIGURATIONS

The following table shows the ADSP-21365’s pin names and

their default function after reset (in parentheses).

Table 43. Ball Grid Array Pin Assignments

Ball Name Ball No. Ball Name Ball No. Pin Name Ball No. Pin Name Ball No.

CLKCFG0 A01 CLKCFG1 B01 BOOTCFG1 C01 V

DDINT

D01

XTAL A02 GND B02 BOOTCFG0 C02 GND D02

TMS A03 V

DDEXT

B03 GND C03 GND D04

TCK A04 CLKIN B04 GND C12 GND D05

TDI A05 TRST B05 GND C13 GND D06

CLKOUT A06 A

VSS

B06 V

DDINT

C14 GND D09

TDO A07 A

VDD

B07 GND D10

EMU A08 V

DDEXT

B08 GND D11

MOSI A09 SPICLK B09 GND D13

MISO A10 RESET B10 V

DDINT

D14

SPIDS A11 V

DDINT

B11

DDINT

A12 GND B12

GND A13 GND B13

GND A14 GND B14

DDINT

E01 FLAG1 F01 AD7 G01 AD6 H01

GND E02 FLAG0 F02 V

DDINT

G02 V

DDEXT

H02

GND E04 GND F04 V

DDEXT

G13 DAI_P18 (SD5B) H13

GND E05 GND F05 DAI_P19 (SCLK45) G14 DAI_P17 (SD5A) H14

GND E06 GND F06

GND E09 GND F09

GND E10 GND F10

GND E11 GND F11

GND E13 FLAG2 F13

FLAG3 E14 DAI_P20 (SFS45) F14

Rev. 0 | Page 48 of 56 | October 2005

ADSP-21365

AD5 J01 AD3 K01 AD2 L01 AD0 M01

AD4 J02 V

DDINT

K02 AD1 L02 WR M02

GND J04 GND K04 GND L04 GND M03

GND J05 GND K05 GND L05 GND M12

GND J06 GND K06 GND L06 DAI_P12 (SD3B) M13

GND J09 GND K09 GND L09 DAI_P13 (SCLK23) M14

GND J10 GND K10 GND L10

GND J11 GND K11 GND L11

DDINT

J13 GND K13 GND L13

DAI_P16 (SD4B) J14 DAI_P15 (SD4A) K14 DAI_P14 (SFS23) L14

AD15 N01 AD14 P01

ALE N02 AD13 P02

RD N03 AD12 P03

DDINT

N04 AD11 P04

DDEXT

N05 AD10 P05

AD8 N06 AD9 P06

DDINT

N07 DAI_P1 (SD0A) P07

DAI_P2 (SD0B) N08 DAI_P3 (SCLK0) P08

DDEXT

N09 DAI_P5 (SD1A) P09

DAI_P4 (SFS0) N10 DAI_P6 (SD1B) P10

DDINT

N11 DAI_P7 (SCLK1) P11

DDINT

N12 DAI_P8 (SFS1) P12

GND N13 DAI_P9 (SD2A) P13

DAI_P10 (SD2B) N14 DAI_P11 (SD3A) P14

Table 43. Ball Grid Array Pin Assignments (Continued)

Ball Name Ball No. Ball Name Ball No. Pin Name Ball No. Pin Name Ball No.

ADSP-21365

Rev. 0 | Page 49 of 56 | October 2005

Figure 42. Ball Grid Array Pin Assignments (Bottom View, Summary)

AVSS

VDDINT

VDDEXT I/O SIGNALS

AVDD

GND*

*USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE

THERMAL PATHWAYS TO YOUR PRINTED

CIRCUIT BOARD’S GROUND PLANE.

KEY

12345678910111214 13

ADSP-21365

Rev. 0 | Page 50 of 56 | October 2005

144-LEAD LQFP PIN CONFIGURATIONS

The following table shows the ADSP-21365’s pin names and

their default function after reset (in parentheses).

Table 44. LQFP Pin Assignments

Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.

DDINT

37 V

DDEXT

73 GND 109

CLKCFG0 2 GND 38 GND 74 V

DDINT

110

CLKCFG1 3 RD 39 V

DDINT

75 GND 111

BOOTCFG0 4 ALE 40 GND 76 V

DDINT

112

BOOTCFG1 5 AD15 41 DAI_P10 (SD2B) 77 GND 113

GND 6 AD14 42 DAI_P11 (SD3A) 78 V

DDINT

114

DDEXT

7 AD13 43 DAI_P12 (SD3B) 79 GND 115

GND 8 GND 44 DAI_P13 (SCLK23) 80 V

DDEXT

116

DDINT

DDEXT

45 DAI_P14 (SFS23) 81 GND 117

GND 10 AD12 46 DAI_P15 (SD4A) 82 V

DDINT

118

DDINT

11 V

DDINT

47 V

DDINT

83 GND 119

GND 12 GND 48 GND 84 V

DDINT

120

DDINT

13 AD11 49 GND 85 RESET 121

GND 14 AD10 50 DAI_P16 (SD4B) 86 SPIDS 122

FLAG0 15 AD9 51 DAI_P17 (SD5A) 87 GND 123

FLAG1 16 AD8 52 DAI_P18 (SD5B) 88 V

DDINT

124

AD7 17 DAI_P1 (SD0A) 53 DAI_P19 (SCLK45) 89 SPICLK 125

GND 18 V

DDINT

54 V

DDINT

90 MISO 126

DDINT

19 GND 55 GND 91 MOSI 127

GND 20 DAI_P2 (SD0B) 56 GND 92 GND 128

DDEXT

21 DAI_P3 (SCLK0) 57 V

DDEXT

93 V

DDINT

129

GND 22 GND 58 DAI_P20 (SFS45) 94 V

DDEXT

130

DDINT

23 V

DDEXT

59 GND 95 A

VDD

131

AD6 24 V

DDINT

60 V

DDINT

96 A

VSS

132

AD5 25 GND 61 FLAG2 97 GND 133

AD4 26 DAI_P4 (SFS0) 62 FLAG3 98 CLKOUT 134

DDINT

27 DAI_P5 (SD1A) 63 V

DDINT

99 EMU 135

GND 28 DAI_P6 (SD1B) 64 GND 100 TDO 136

AD3 29 DAI_P7 (SCLK1) 65 V

DDINT

101 TDI 137

AD2 30 V

DDINT

66 GND 102 TRST 138

DDEXT

31 GND 67 V

DDINT

103 TCK 139

GND 32 V

DDINT

68 GND 104 TMS 140

AD1 33 GND 69 V

DDINT

105 GND 141

AD0 34 DAI_P8 (SFS1) 70 GND 106 CLKIN 142

WR 35 DAI_P9 (SD2A) 71 V

DDINT

107 XTAL 143

DDINT

36 V

DDINT

72 V

DDINT

108 V

DDEXT

144

ADSP-21365

Rev. 0 | Page 51 of 56 | October 2005

OUTLINE DIMENSIONS

The ADSP-21365 is available in a 144-lead integrated heat sink

LQFP package and a 136-ball BGA package.

Figure 43. 144-Lead Low Profile Quad Flat Package, with Integrated Heatsink [LQFP_INT_HS] (SQ-144-3)

SEATING

PLANE

1.6 0 MAX

0.15

0.05

0. 08 MAX (LEAD

COPLANARITY)

1. 45

1. 40

1. 35

0.27

0.22

0.17 TYP 0.50

BSC

TYP

(LEAD

PI TCH)

DETAIL A

DE TAI L A

0.75

0.60TYP

0.45

37 72

108

144 10 9

TOP VIEW (PINS DOWN)

22.00BSC SQ

20.00 BSC SQ

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS AND COMPLY WITH

JEDEC STANDARD MS-026-BFB-HD.

2. ACTUAL POSITION OF EACH LEAD ISWITHIN 0.08 OF ITS

IDEAL POSITION, WHEN MEASURED IN THE LATERAL DIRECTION.

3. CENTER DIMENSIONS ARE NOMINAL.

4. HEAT SLUG IS COINCIDENT WITH BOTTOM SURFACE AND DOES

NOT PROTRUDE BEYOND IT.

PIN 1 INDI CA TOR

HEAT SLUG ON BOTTOM

(NOTE 4)

DIA

12.71

13.21

13.71

Rev. 0 | Page 52 of 56 | October 2005

ADSP-21365

SURFACE MOUNT DESIGN

The following table is provided as an aide to PCB design. The

numbers listed in the table are for reference purposes and

should not supersede the PCB design rules. Please reference

IPC-7351, Surface Mount Design and Land Pattern Standard,

for PCB design recommendations.

Figure 44. 136-Lead Chip Scale Package Ball Grid Array [CSP_BGA](BC-136-2)

SEATING

PLANE

0.25

MIN

DETAIL A

0.50

0.45

0.40

(BALL

DIAMETER)

DETAIL A

1.70

MAX

1. DIMENSIONS ARE IN MILIMETERS (MM).

2. THE ACTUAL POSITION OF THE BALL GRID IS

WITHIN 0.15 MM OF ITS IDEAL POSITION RELATIVE

TO THE PACKAGE EDGES.

3. COMPLIANT TO JEDEC STANDARD MO-205-AE, EXCEPT FOR

THE BALL DIAMETER.

4. CENTER DIMENSIONS ARE NOMINAL.

109876543211314 1112

0.80

BSC

TYP

10.40 BSC SQ

PIN A1 INDICATOR

BOTTOM VIEW

TOP VIEW

12.00 BSC SQ

0.12 MAX (BALL

COPLANARITY)

0.80

BSC

TYP

0.80

BSC

TYP

Package Ball Attach Type

Solder Mask

Opening Ball Pad Size

136-Lead Ball Grid

Array (BC-136-2)

Solder Mask

Defined (SMD)

0.40 0.53

ADSP-21365

Rev. 0 | Page 53 of 56 | October 2005

ORDERING GUIDE

Analog Devices offers a wide variety of audio algorithms and

combinations to run on the ADSP-21365 processor. These

products are sold as part of a chipset, bundled with necessary

application software under special part numbers. For a complete

list, visit our website at www.analog.com/SHARC.

These products also may contain 3rd party IPs that may require

users to have authorization from the respective IP holders to

receive them. Royalty for use of the 3rd party IPs may also be

payable by users.

Model

Temperature

Range

Instruction

Rate

On-Chip

SRAM ROM

Operating

Voltage

Internal/External Package Description

Package

Option

ADSP-21365KBC–1AA 0 to 70°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-ball CSP-BGA BC-136-2

ADSP-21365KBCZ–1AA

0 to 70°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-ball CSP-BGA BC-136-2

ADSP-21365KSQZ–1AA

0 to 70°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 144-lead LQFP_INT_HS SQ-144-3

ADSP-21365BBC–1AA –40 to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-ball CSP-BGA BC-136-2

ADSP-21365BBCZ–1AA

–40 to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-ball CSP-BGA BC-136-2

ADSP-21365BSQZ–1AA

–40 to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 144-lead LQFP_INT_HS SQ-144-3

ADSP-21365WSQZ–2AA

–40 to +105°C 200 MHz 3M Bit 4M Bit 1.0 V/3.3 V 144-lead LQFP_INT_HS SQ-144-3

Referenced temperature is ambient temperature.

Z = Pb-free package.

Rev. 0 | Page 54 of 56 | October 2005

ADSP-21365

Rev. 0 | Page 55 of 56 | October 2005

Rev. 0 | Page 56 of 56 | October 2005

registered trademarks are the property of their respective owners.

D04625-0-10/05(0)

ADSP-21365