CM8870PI - California Micro Devices

12/18/2001

1

215 Topaz Street, Milpitas, Califor nia 95035  Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com

CM8870/70C

CALIFORNIA MICRO DEVICES

CMOS Integrated DTMF Receiver

Features

• Full DTMF receiver

• Less than 35mW power consumption

• Industrial temperature range

• Uses quar tz cr ystal or ceramic resonators

• Adjustable acquisition and release times

• 18-pin DIP, 18-pin DIP EIAJ, 18-pin SOIC, 20-pin

PLCC

• CM8870C

— Power down mode

— Inhibit mode

— Buffered OSC3 output (PLCC package only)

• CM8870C is fully compatible with CM8870 for 18-pin

devices by grounding pin 5 and pin 6.

Product Description

The CAMD CM8870/70C provides full DTMF receiver

capability by integrating both the band-split filter and

digital decoder functions into a single 18-pin DIP, SOIC,

or 20-pin PLCC package. The CM8870/70C is manufac-

tured using state-of-the-art CMOS process technology

for low power consumption (35mW, MAX) and precise

data handling. The filter section uses a switched capaci-

tor technique for both high and low group filters and dial

Applications

• PABX

• Central office

• Mobile radio

• Remote control

• Remote data entry

• Call limiting

• Telephone answer ing systems

• Paging systems

C1581000

tone rejection. The CM8870/70C decoder uses digital

counting techniques for the detection and decoding of all

16 DTMF tone pairs into a 4-bit code. This DTMF

receiver minimizes external component count by provid-

ing an on-chip differential input amplifier, clock genera-

tor, and a latched three-state interface bus. The on-chip

clock generator requires only a low cost TV crystal or

ceramic resonator as an external component.

Block Dia

g

ra

m

DIGITAL

DETECTION

ALGORITHM

ZERO

CROSSING DETECTORS

CODE

CONVERTER

AND

LATCH

+

–

V

DD

IN+

IN–

BIAS

CIRCUIT

V

SS

CHIP

REF

CHP

BIAS

CHP

POWER

V

REF

StD

STEERING

LOGIC

PD

DIAL

TONE

FILTER

HIGH

GROUP

FILTER

LOW

GROUP

FILTER

+

–

INH

TOE

Q1

ESt

St

GT

OSC 1 OSC 2 OSC 3

TO ALL

CHIP

CLOCKS

St/GT

Q2

Q3

Q4

GS

12/18/2001

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2

CM8870/70C

CALIFORNIA MICRO DEVICES

Absolute Maximum Ratin

gs

S

y

mbol P

a

r

a

m

e

t

e

rV

a

l

ue

V

DD

Power Supply Volta

g

e

(V

DD

/V

SS

)

6

V MA

X

Vdc Voltage on any Pin VSS – 0.3V to VDD + 0.3V

IDD Current on any Pin 10mA MAX

T

A Operating Temperature –40

˚

C to 85

˚

C

T

S Storage Temperature –65

˚

C to 150

˚

C

Absolute Maximum Ratings: (Note 1) This device contains input protection

against damage due to high static

voltages or electric fields; however,

precautions should be taken to avoid

application of voltages higher than the

maximum rating.

Notes:

1. Exceeding these ratings may cause

permanent damage, functional

operation under these conditions is

not implied.

D

C

haracteristic

s

S

y

mbol P

a

r

a

m

e

t

e

r Test

C

onditions

MIN

TYP

MAX

U

NI

T

V

DD

Operatin

g

Supply Volta

g

e 4.7

5

.2

5

V

I

DD Operating Supply Current 3.0 7.0 mA

I

DDQ Standby Supply Current PD = VDD 25 µA

P

O Power Consumption f = 3.579 MHz; VDD = 5V 15 35 mW

V

IL Low Level Input Voltage VDD = 5V 1.5 V

V

IH High Level Input Voltage VDD = 5V 3.5 V

I

IH/LIL Input Leakage Current VIN = VSS = VDD (Note 1) 0.1 µA

I

SO Pull Up (Source) Current on TOE TOE = 0V, VDD = 5V 6.5 20 µA

R

IN Input Impedance, (IN+, IN–) @ 1KHz 8 10 MΩ

V

Tst Steering Threshold V oltage VDD = 5V 2.2 2.5 V

V

OL Low Level Output Voltage VDD = 5V, No Load 0.03 V

V

OH High Level Output Voltage VDD = 5V, No Load 4.97 V

I

OL Output Low (Sink) Current VOUT = 0.4V 1.0 2.5 mA

I

OH Output High (Source) Current VOUT = 4.6V 0.4 0.8 mA

V

REF Output Voltage VREF VDD = 5.0V, No Load 2.4 2.7 V

R

OR Output Resistance 10 kΩ

DC Characteristics: All voltages referenced to VSS, VDD = 5V ±5%, TA = –40°C to 85°C unless otherwise noted.

Operatin

g

Characteristic

s

S

y

mbol P

a

r

a

m

e

t

e

r Test

C

onditions

MIN

TYP

MAX

U

NI

T

I

IN

Input Leaka

g

e Current

V

SS

<

V

IN

<

V

DD

±

1

00

nA

R

IN

Input Resistance 10 MΩ

V

OS

Input Offset Voltage ±25 mV

PSRR Power Supply Rejection 1 KHz (Note 12) 50 dB

CMRR Common Mode Rejection –3V < V

IN

< 3V 40 dB

A

VOL

DC Open Loop Voltage Gain 32 dB

fc Open Loop Unity Gain Bandwidth 0.3 MHz

V

O

Output Voltage Swing R

L

≥ 100

KW to V

SS

4 V

P-P

C

L

Maximum Capacitive Load (GS) 100 pF

R

L

Maximum Resistive Load (GS) 50 KΩ

Vcm Common Mode Range (No Load) No Load 2.5 V

P-P

Operating Characteristics: All voltages referenced to VSS, VDD = 5V ±5%, T A = –40°C to 85°C unless otherwise noted.

Gain Setting Amplifier

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CM8870/70C

CALIFORNIA MICRO DEVICES

A

C

haracteristic

s

Symbol P

a

r

a

m

e

t

e

rN

o

t

es

MIN

TYP

MAX

U

NI

T

Valid Input Si

g

nal Levels 1, 2, 3, 4, 5, 8

–

2

9

1

d

B

m

(each tone of composite signal) 27.5 869 mVRMS

P ositive Twist Accept 2, 3, 4, 8 10 dB

Negative Twist Accept 10 dB

Freq. Deviation Aceept Limit 2, 3, 5, 8, 10 1.5%±2Hz Norm.

Freq. Deviation Reject Limit 2, 3, 5 ±3.5% Norm.

Third Tone Tolerance 2, 3, 4, 5, 8, 9, 13, 14 –16 dB

Noise Tolerance 2, 3, 4, 5, 6, 8, 9 –12 dB

Dial Tone Tolerance 2, 3, 4,5, 7, 8, 9 22 dB

t

DP Tone Present Detection Time Refer to Timing Diagram 5 8 14 ms

t

DA Tone Absent Dectection Time Refer to Timing Diagram 0.5 3 8.5 ms

tREC MIN Tone Duration Accept 15 40 ms

MAX Tone Duration Reject 15 20 ms

t

ID MIN Interdigit Pause Accept 15 40 ms

t

DO MAX Interdigit Pause Reject 15 20 µs

t

PQ Propagation Delay (St to Q) TOE = VDD 6 11 µs

t

PStD Propagation Delay (St to StD) TOE = VDD 9 16 µs

t

QStD Output Data Set Up (Q to StD) TOE = VDD 3.4 µs

t

PTE Propagation Delay (TOE to Q) Enable RL = 10KΩ 50 ns

tPTD Disable CL = 50pf 300 ns

f

CLK Crystal/Clock Frequency 3.5759 3.5795 3.5831 MHz

C

LO Clock Ouput (OSC 2) Capacitive Load 30 pF

AC Characteristics: All voltages referenced to V SS, VDD = 5.0V ±5%, TA = –40°C to +85°C, fCLK = 3.579545 MHz

using test circuit in Figure 1 unless otherwise noted.

Notes: 1. dBm = decibels above or below a reference power

of 1mW into a 600Ω load.

2. Digit sequence consists of all 16 DTMF tones.

3. Tone duration = 40ms. Tone pause = 40ms.

4. Nominal DTMF frequencies are used.

5. Both tones in the composite signal have

an equal amplitude.

6. Bandwidth limited (0 to 3KHz) Gaussian Noise.

7. The precise dial tone frequencies are

(350Hz and 440Hz) ±2%.

8. For an error rate of better than 1 in 10,000

9. Referenced to lowest level frequency component

in DTMF signal.

10. Minimum signal acceptance level is measured with

specified maximum frequency deviation.

11. Input pins defined as IN+, IN–, and TOE.

12. External voltage source used to bias VREF.

13. This parameter also applies to a third tone injected onto

the power supply.

14. Referenced to Figure 1. Input DTMF tone level

at –28dBm.

15.Times shown are obtained with circuit in

Figure 1 (User adjustable).

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4

CM8870/70C

CALIFORNIA MICRO DEVICES

EVENTS

INTERDIGIT PAUSE

A

TOE

St/Gt

ESt

VIN

DECODED TONE # N+1

TONE # N TONE # N+1 TONE # N+1

DECODED T ONE # N HIGH IMPEDANCE DECODED TONE # n+1

VTSt

tPTE

StD

OUTPUT

DATA

OUTPUTS

Q1-Q4

tPTD

tQStD

tPStD

tGTA

tGTP

tPQ

tDP

tREC tREC tDO TONE DROPOUTtID

tDA

B C E F G

D

Explanation of Events

A. Tone bursts detected, tone duration invalid, outputs

not updated.

B. Tone #n detected, tone dur ation valid, tone decoded

and latched in outputs.

C. End of tone #n detected, tone absent duration valid,

outputs remain latched until next valid tone.

D. Outputs switched to high impedance state.

E. Tone #n + 1 detected, tone duration valid, tone

decoded and latched in outputs (currently high

impedance).

F. Acceptable dropout of tone #n + 1, tone absent

duration invalid, outputs remain latched.

G. End of tone #n + 1 detected, tone absent duration

valid, outputs remain latched until next valid tone.

Explanation of Symbols

VIN DTMF composite input signal.

ESt Early Steering Output. Indicates detection

of valid tone frequencies.

St/GT Steering input/guard time output. Drives

exter nal RC timing circuit.

Q1-Q4 4-bit decoded tone output.

StD Delayed Steer ing Output. Indicates that

valid frequencies have been present/absent

for the required guard time, thus constituting

a valid signal.

TOE Tone Output Enable (input). A low level

shifts Q1-Q4 to its high impedance state.

tREC Maximum DTMF signal duration not

detected as valid.

tREC Minimum DTMF signal duration required

for valid recognition.

tID Minimum time between valid DTMF signals.

tDO Maximum allowable drop-out during valid

DTMF signal.

tDP Time to detect the presence of valid

DTMF signals.

tDA Time to detect the absence of valid

DTMF signals.

tGTP Guard time, tone present.

tGTA Guard time, tone absent.

Timing Diagram

12/18/2001

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CM8870/70C

CALIFORNIA MICRO DEVICES

Functional Description

The CAMD CM8870/70C DTMF Integrated Receiver

provides the design engineer with not only low power

consumption, but high performance in a small 18-pin

DIP, SOIC, or 20-pin PLCC package configuration. The

CM8870/70C’s internal architecture consists of a

band-split filter section which separates the high and low

tones of the received pair, followed by a digital decode

(counting) section which verifies both the frequency and

duration of the received tones before passing the

resultant 4-bit code to the output bus.

Filter Section

Separation of the low-group and high-group tones is

achieved by applying the dual-tone signal to the inputs of

two 9th-order switched capacitor bandpass filters. The

bandwidths of these filters correspond to the bands

enclosing the low-group and high-group tones (See

Figure 3). The filter section also incor porates notches at

350Hz and 440Hz which provides excellent dial tone

rejection. Each filter output is followed by a single order

switched capacitor section which smooths the signals

prior to limiting. Signal limiting is perfor m ed by high-gain

comparators. These comparators are provided with a

hysteresis to prevent detection of unwanted low-level

signals and noise. The outputs of the comparators

provide full-rail logic swings at the frequencies of the

incoming tones.

Decoder Section

The CM8870/70C decoder uses a digital counting

technique to deter mine the frequencies of the limited

tones and to verify that these tones correspond to

standard DTMF frequencies. A complex averaging

algorithm is used to protect against tone simulation by

extraneous signals (such as voice) while providing

tolerance to small frequency va riations. The averaging

algorithm has been developed to ensure an optimum

combination of immunity to “talk-off” and tolerance to the

presence of interfering signals (third tones) and noise.

When the detector recognizes the simultaneous pres-

ence of two valid tones (known as “signal condition”), it

raises the “Early Steering” flag (ESt). Any subsequent

loss of signal condition will cause ESt to fall.

Steering Circuit

Before the registration of a decoded tone pair, the

receiver checks for a valid signal duration (referred to as

“character-recognition-condition”). This check is per-

formed by an external RC time constant driven by ESt. A

logic high on ESt causes VC (See Figure 4) to r ise as the

capacitor discharges. Providing signal condition is

maintained (ESt remains high) for the validation per iod

(tGTP), VC reaches the threshold (VTSt) of the steering logic

to register the tone pair, thus latching its corresponding

4-bit code (See Figure 2) into the output latch. At this

point, the GT output is activated and drives VC to VDD.

GT continues to drive high as long as ESt remains high,

signaling that a received tone pair has been registered.

The contents of the output latch are made available on

the 4-bit output bus by raising the three-state control

input (TOE) to a logic high. The steering circuit works in

reverse to validate the interdigit pause between signals.

Thus, as well as rejecting signals too shor t to be consid-

ered valid, the receiver will tolerate signal interruptions

(drop outs) too short to be considered a valid pause.

This capability together with the capability of selecting

the steering time constants externally, allows the de-

signer to tailor performance to meet a wide variety of

system requirements.

Guard Time Adjustment

In situations which do not require independent selection

of receive and pause, the simple steering circuit of

Figure 4 is applicable. Component values are chosen

according to the following for mula:

tREC = tDP + tGTP

tGTP = 0.67 RC

The value of tDP is a parameter of the device and tREC is

the minimum signal duration to be recognized by the

receiver. A value for C of 0.1µF is recommended for

most applications, leaving R to be selected by the

designer. For example, a suitable value of R for a tREC of

40ms would be 300K. A typical circuit using this steering

configuration is shown in Figure 1. The timing require-

ments for most telecommunication applications are

satisfied with this circuit. Different steering arrange-

ments may be used to select independently the

guard-times f or tone-present (t GTP) and tone absent (tGTA).

This may be necessar y to meet system specifications

which place both accept and reject limits on both tone

duration and interdigit pause.

Guard time adjustment also allows the designer to tailor

system parameters such as talk-off and noise immunity.

Increasing tREC improves talk-off performance, since it

reduces the probability that tones simulated by speech

will maintain signal condition for long enough to be

registered. On the other hand, a relatively shor t tREC with

a long tDO would be appropriate for extremely noisy

environments where fast acquisition time and immunity

to drop-outs would be requirements. Design infor mation

for guard time adjustment is shown in Figure 5.

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6

CM8870/70C

CALIFORNIA MICRO DEVICES

Input Configuration

The input arrangement of the CM8870/70C provides a

differential input operational amplifier as well as a bias

source (VREF) which is used to bias the inputs at mid-rail.

Provision is made for connection of a feedback resistor to

the op-amp output (GS) for adjustment of gain.

In a single-ended configuration, the input pins are con-

nected as shown in Figure 1, with the op-amp connected

for unity gain and VREF biasing the input at ½ VDD. Figure

6 shows the differential configuration, which per mits the

adjustment of gain with the feedback resistor R5.

Clock Cir cuit

The inter nal clock circuit is completed with the addition

of a standard television color burst crystal or ceramic

resonator having a resonant frequency of

3.579545MHz. The CM8870C in a PLCC package has a

buffered oscillator output (OSC3) that can be used to

drive clock inputs of other devices such as a micropro-

cessor or other CM887X’s as shown in Figure 7. Mul-

tiple CM8870/70Cs can be connected as shown in figure

8 such that only one crystal or resonator is required.

Pin F

u

n

c

ti

on

N

a

m

e

F

u

n

c

ti

o

n Discri

p

tio

n

IN+

Non-invertin

g

input Connection to the front-end differential amplifier

IN– Inverting input Connection to the front-end differential amplifier

GS Gain select Gives access to output of front-end differential amplifier for connection

of feedback resistor.

V

REF

Reference output Voltage May be used to bias the inputs at mid-rail.

(nominally V

DD

/2)

INH Inhibits detection of tones Represents keys A, B, C, and D

OSC3 Digital buffered oscillator output

PD Power down Logic high powers down the device and inhibits the oscillator.

OSC1 Clock input 3.579545MHz crystal connected between these pins

completes internal oscillator

OSC2 Clock output 3.579545MHz crystal connected between these pins

completes internal oscillator

V

SS

Negative power supply Normally connected to OV

TOE Three-state output enable (Input) Logic high enables the outputs Q1-Q4. Internal pull-up.

Q

1

Three-state ouputs When enabled by TOE, provides the code corresponding to the last valid

Q

2

tone pair received. (See Figure 2).

Q

3

Q

4

StD Delayed Steering output Presents a logic high when a received tone pair has been registered and the

output latch is updated. Returns to logic low shen the voltage on St/GT

falls below V

TSt

.

ESt Early steering output Presents logic high immediately when the digital algorithm detects a

recongnizable tone pair (signal condition). Any momentary loss of signal

condition will cause ESt to return to a logic low.

St/Gt Steering input/guard A voltage greater than V

TSt

detected at St causes the device to register

time output (bidirectional) the dectected tone pair. The GT output acts to reset the external steering

time constrant, and its state is a function of ESt and the voltage on St.

(See Figure 2).

V

DD

Positve power supply

IC Internal connection Must be tied to V

SS

(for 8870 configuration only).

12/18/2001

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CM8870/70C

CALIFORNIA MICRO DEVICES

Figure 1. Single Ended Input Configuration

F

u

n

c

ti

o

n

a

l Di

ode

T

ab

l

e

F

L

OW

F

HI

GH

KEY

T

O

W

Q

4

Q

3

Q

2

Q

1

69

712

09

1

H

0

1

697 1336 2 H 0 0 1 0

697

1477 3 H 0 0 1 1

770 1209 4 H 0 1 0 0

770 1336 5 H 0 1 0 1

770 1477 6 H 0 1 1 0

852 1209 7 H 0 1 1 1

852 1336 8

H 1 0 0 0

852 1477 9 H 1 0 0 1

941 1336 0 H 1 0 1 0

941 1209 * H 1 0 1 1

941 1477 # H 1 1 0 0

697 1633 A H 1 1 0 1

770 1633 B H 1 1 1 0

852 1633 C H 1 1 1 1

941 1633 D H 0 0 0 0

- - ANY L Z Z Z Z

L Logic Low, H = Logic, Z = High Impedance

Figure 2. Functional Decode T able

IN+

1

3

4

5

6

7

8

9

2

18

16

15

14

13

12

11

10

17

0.1µF

5V

3.58

MHz

100KΩ

300KΩ

V

DD

CM8870

IN–St/GT

GS ESt

V

REF

StD

INH Q4

PD Q3

OSC 1 Q2

OSC 2 Q1

V

SS

TOE

IN+

1

3

4

5

6

7

8

9

2

18

16

15

14

13

12

11

10

17

0.1µF

All resistors are ±1% tolerance.

All capacitors are ±5% tolerance.

5V

3.58

MHz

100KΩ

300KΩ

V

DD

CM8870C

IN–St/GT

GS ESt

V

REF

StD

INH Q4

PD Q3

OSC 1 Q2

OSC 2 Q1

V

SS

TOE

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8

CM8870/70C

CALIFORNIA MICRO DEVICES

VDD

VTST

VDD

C

RVC

tGTA = (RC) In

St/GT

ESt

StD

VDD

VDD – VTST

tGTP = (RC) In

Figure 4. Basic Steering Cir cuit

VDD

VTST

tGTA = (RPC) In

RP = R1R2

R1 + R2

VDD

VDD – VTST

tGTP = (R

1

C) In

(A.) Decreasing tGTA (tGTP > tGTA)

St/GT

ESt

C

R1

R2

VDD

VTST

tGTA = (R1C) In

RP = R1R2

R1 + R2

VDD

VDD – VTST

tGTP = (R

P

C) In

(B.) Decreasing tGTP (tGTP < tGTA)

St/GT

ESt

C

R1

R2

Figure 5. Guar d Time Adjustment

50 0

XY ABC D

FREQUENCY Hz

PRECISE DIAL T ONES DTMF T ONES

ATTENUATION dB

1K EF G H

2K

40

30

20

10

0

X = 350Hz

y = 440Hz A = 607Hz E = 1209Hz

B = 770Hz F = 1336Hz

C = 852Hz G = 1477Hz

D = 841Hz H = 1633Hz

Figure 3. T ypical Filter Characteristic

C1

+

–

R1

R2

R5

R3

IN+

IN–

C2 R4 CM8870

C1 = C2 = 10nF

R1 = R4 = R4 =100 KΩ

R2 = 60KΩ, R3 = 37.5KΩ

All resistors are –1% tolerance.

All capacitors are –5% tolerance.

(Xxxx) = 2 R2 + 2

VOLTAGE GAIN (Av diff) =

IMPUT IMPEDANCE

R3 = R2R5

R2 + R5

DIFFERENTIAL INPUT AMPLIFIER

V

REF

GS

R5

R1

1

wC

Figure 6. Differential Input Configuration

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CM8870/70C

CALIFORNIA MICRO DEVICES

Figure 7. CM8870C Crystal Connection

(PLCC P acka ge Only)

OSC1 OSC2 OSC3

Clock input of other devices

30pF

OSC1 of other CM887X's

OSC1 OSC2

3.58MHz 30pF 30pF

OSC1 OSC2 OSC1 OSC2

Figure 8. CM8870/70C Crystal Connection

Pin Assignments

IN+

IN–

GS

V

REF

IC*

OSC 1

OSC 2

V

SS

V

DD

St/GT

ESt

StD

Q4

Q3

Q2

Q1

TOE

1

2

3

4

5

6

7

8

9

18

17

16

15

14

13

12

11

10

CM8870

IN+

IN–

GS

V

REF

INH

IC*

OSC 1

OSC 2

V

SS

V

DD

St/GT

ESt

StD

Q4

Q3

Q2

Q1

TOE

1

2

3

4

5

6

7

8

9

18

17

16

15

14

13

12

11

10

CM8870C

IN-

NC

IN+

GS

V

REF

IC*

OSC 1

OSC 2

V

SS

V

DD

St/GT

ESt

StD

NC

Q4

Q3

Q2

Q1

TOE

CM8870

4

5

6

7

8

9

10

11

12

13

18

17

16

15

14

3

2

1

20

19

IN-

GS

IN+

GS

V

REF

PD

OSC 3

OSC 1

OSC 2

V

SS

V

DD

St/GT

ESt

StD

NC

Q4

Q3

Q2

Q1

TOE

CM8870C

4

5

6

7

8

9

10

11

12

13

18

17

16

15

14

3

2

1

20

19

P –Plastic DIP (18)

F –Plastic SOP

EIAJ (18)

S –SPIC (18)

P –Plastic DIP (18)

F –Plastic SOP

EIAJ (18)

S –SOIC (18)

PE –PLCC (20)

* –Connected to VSS

PE –PLCC (20)

Ordering Information

IP

CM8870

CM8870C

Product Identification Number

Example:

Pa ckage

P — Plastic Dip (18)

F — Plastic SOP EIAJ (18)

PE — PLCC (20)

S — SOIC (18)

Temperature/Processing

None — 0˚C to 70˚C, ±5% P.S. Tol.

I — –40˚C to 85˚C, ±5% P.S. Tol.