FST16292MTDX_NL - Fairchild Semiconductor

July 1997

Revised November 2000

FST16292 12-Bit to 24-Bit Multiplexer /Demultiplexer Bus Switch

FST16292

12-Bit to 24-Bit Mult iplexer/Demultiplexer Bus Switch

General Description

The Fairchild Switch FST16292 provides twelve 2:1 high-

speed CMOS TTL-compatible multiplexer/demultiplexer

bus switches. The low on resistance of the switch allows

inputs t o be connect ed to output s with out ad ding prop aga-

tion delay or generating additional ground bounce noise.

The select pin connects the A Port to the selected B Port

output. The A2 Ports are not externally connected, thus

have a 500Ω pull-down resistor to ground.

Features

■4Ω switch connection between two ports.

■Minimal propagation delay through the switch.

■Low lCC.

■Zero bounce in flow-through mode.

■Control inputs compatible with TTL level.

■Internal 500Ω pull-down resistor on A2 Por t.

Ordering Code:

Devices also available in Tape and R eel. Speci fy by append ing the suffix let t er “X” to the orderin g c ode.

Logic Diagram

Pin Descriptions

Connection Diagram

Truth Table

Order Number Package Number Package Description

FST16292MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide

FST16292MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Pin Name Description

S Data-select input

A1Bus A

B1, B2Bus B

SA1A2Function

1B2A1 = B1, A2 = B2

2B1A1 = B2, A2 = B1

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FST16292

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: The “Absolute Maximum Ratings” are thos e values bey ond which

the saf ety of the device cannot be gu aranteed. Th e device shoul d not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the absolute maximum rating.

The “R ecomm ended Oper ating Co ndition s” table will def ine the condit ions

for actu al device operation.

Note 2: The inpu t and outpu t negati ve voltag e ratings m ay be ex ceede d if

the input and output diode current ratings are observed.

DC Electrical Characteristi cs

Note 3: Typical v alues are at VCC = 5.0V and TA =+25°C

Note 4: Measured by the v olt age drop between A and B pins at th e indica te d c urrent thro ugh the swit c h. On resistance is determi ned by the lower of the

voltages on the two (A or B) pi ns .

Supply Voltage (VCC)−0.5V to +7.0V

DC Switch Voltage (VS)−0.5V to +7.0V

DC Input Voltage (VIN) (Note 2) −0.5V to +7.0V

DC Input Diode Current (lIK) VIN < 0V −50mA

DC Output (IOUT) Sink Current 128mA

DC VCC/GND Current (ICC/IGND)+/− 100mA

Storage Temperature Range (T STG)−65°C to +150 °C

Power Supply Operating (VCC) 4.0V to 5.5V

Input Voltage (VIN)0V to 5.5V

Output Voltage (VOUT)0V to 5.5V

Input Rise and Fall Time (tr, tf)

Switch Control Input 0ns/V to 5ns/V

Switch I/O 0ns/V to DC

Free Air Operating Temperature (TA)−40 °C to +85 °C

Symbol Parameter VCC

(V)

TA = −40 °C to +85 °CUnits Conditions

Min Typ

(Note 3) Max

VIK Clamp Diode Voltage 4.5 −1.2 V IIN = −18mA

VIH HIGH Level Input Voltage 4.0–5.5 2.0 V

VIL LOW Level Input Voltage 4.0–5.5 0.8 V

IIInput Leakage Current 5.5 ±1.0 µA0≤ VIN ≤ 5.5V

010µAV

IN = 5.5 V

IOZ OFF-STATE Leakage Current 5.5 ±1.0 µA0 ≤A, B ≤ VCC

RON Switch On Resistance 4.5 4 7 ΩVIN = 0V, IIN = 64mA

(Note 4) 4.5 4 7 ΩVIN = 0V, IIN = 30mA

4.5 8 12 ΩVIN = 2.4V, IIN = 15mA

4.0 14 20 ΩVIN = 2.4V, IIN = 15mA

ICC Quiescent Supply Current 5.5 3 µAV

IN = VCC or GND, IOUT = 0

∆ ICC Increase in ICC per Input 5.5 2.5 mA One input at 3.4V

Other inputs at VCC or GND

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FST16292

AC Electrical Characteristics

Note 5: T his paramet er is gu aranteed by design but is not te s t ed. Th e bus switch contri butes no propagation del ay other than t he RC del a y of the typical On

resistan c e of t he s witch a nd t he 50pF load capac it ance, w hen driven by an ideal v oltage so urce (zero output im pedance).

Capacitance (Note 6)

Note 6: TA = +25°C, f = 1 MHz, Ca pacitance is characterized but not te s te d.

AC Loading and Waveforms

Note: Input driven by 50 Ω source terminated in 50 Ω

Note: CL includes load and stray capacitance

Note: Input PRR = 1.0 MHz, t W = 500 ns

FIGURE 1. AC Test Circuit

FIGURE 2. AC Waveforms

Symbol Parameter

TA = −40 °C to +85 °C,

Units Conditions Figure

No.

CL = 50pF, RU = RD = 500Ω

VCC = 4.5 – 5.5V VCC = 4.0V

MinMaxMinMax

tPHL, tPLH Prop Delay Bus to Bus (Note 5) 0.25 0.25 ns VI = OPEN Figures

1, 2

tPHL, tPLH Prop Delay S to A11.5 7.0 7.4 ns VI = OPEN Figures

1, 2

tPZL, tPZH Output Enable Time 1.0 6.7 7.0 ns VI = 7V for tPZL Figures

1, 2

S to B1 or B2VI = OPEN for tPZH

tPLZ, tPHZ Output Disable Time 1.0 7.5 7.8 ns VI = 7V for tPLZ Figures

1, 2

S to B1 or B2VI = OPEN for tPHZ

Symbol Parameter Typ Max Units Conditions

CIN Control Pin Input Capacitance 3 pF VCC = 5.0V

CI/O Input/Output Capacitance 10 pF VCC = 5.0V, S0 =GND

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FST16292

Physical Dimensions inches (millimeters) unless otherwise noted

56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide

Packag e Num b er MS56A

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

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FST16292 12-Bit to 24-Bit Multiplexer /Demultiplexer Bus Switch

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

56-Lea d Th in S hri n k Small Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 6.1mm Wide

Package Number MTD56

Technology Description

The Fairchild Switch family derives fro m and embodies Fairchild’s proven switch t echnology used for several years in its

74LVX3L384 (FST3384) bus switch product.

Fairchild does not assume an y responsibility fo r use of any circu itry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are dev ic es or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use pr ovi de d in the l abe ling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A crit ical componen t in any com ponen t of a life s uppor t

device or system whose failure to perform can be rea-

sonabl y e xpec ted to cause th e fa i lure of the l ife s upport

device or system, or to affect its safety or effectiveness.