Integrated Silicon Solution, Inc. — 1-800-379-4774 1
Rev. 00B
08/09/2010
IS41C44052C
IS41LV44052C
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-
pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon
Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
FEATURES
• Fast Page Mode Access Cycle
• TTLcompatibleinputsandoutputs
• RefreshInterval:
2,048 cycles/32 ms
• RefreshMode:RAS-Only,
CAS-before-RAS(CBR),andHidden
• Singlepowersupply:
5V±10% (IS41C44052C)
3.3V±10%(IS41LV44052C)
• ByteWriteandByteReadoperationviatwoCAS
• Industrialtemperaturerange-40°Cto+85°C
• RoHScompliant
DESCRIPTION
TheISSIIS41C/41LV44052Cisa4,194,304x4-bithigh-perfor-
mance
CMOSDynamicRandomAccessMemory.The
Fast Page Mode allows 2,048 or 4096 random accesses
within a single row with access cycle time as short as 20
ns per 4-bit word.
Thesefeaturesmakethe
IS41C/41LV44052C
ideally suited
for high-bandwidth graphics, digital signal processing,
high-performance computing systems, and peripheral
applications.
The
IS41C/41LV44052C
is packaged in a 24/26-pin 300-mil
TSOP2withJEDECstandardpinout.
4Mx4
16Mb DRAM WITH FAST PAGE MODE
ADVANCED INFORMATION
AUGUST 2010
KEY TIMING PARAMETERS
Parameter -50 -60 Unit
RAS AccessTime(tr a c ) 50 60 ns
CASAccessTime(tc a c ) 13 15 ns
ColumnAddressAccessTime(ta a )
25 30 ns
FastPageModeCycleTime(tp c )
20 25 ns
Read/WriteCycleTime(tr c ) 84 104 ns
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDD
I/O0
I/O1
WE
RAS
NC
A10
A0
A1
A2
A3
VDD
GND
I/O3
I/O2
CAS
OE
A9
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A10 Address Inputs (2KRefresh)
I/O0-3 Data Inputs/Outputs
WE WriteEnable
OE OutputEnable
RAS RowAddressStrobe
CAS Column Address Strobe
Vd d Power
GND Ground
NC No Connection
PIN CONFIGURATION
24 (26) Pin TSOP 2
2 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00B
08/09/2010
IS41C44052C
IS41LV44052C
FUNCTIONAL BLOCK DIAGRAM
OE
WE
CAS CAS WE
OE
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
MEMORY ARRAY
4,194,304 x 4
ROW DECODER
DATA I/O BUFFERS
CAS
CONTROL
LOGIC
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
I/O0-I/O3
RAS
RAS
A0-A10
RAS
CLOCK
GENERATOR
REFRESH
COUNTER
ADDRESS
BUFFERS
TRUTH TABLE
Function RAS CAS WE OE Address tR/tC I/O
Standby H H X X X High-Z
Read L L H L ROW/COL Do u t
Write:Word(EarlyWrite) L L L X ROW/COL Di n
Read-Write L L H→L L→H ROW/COL Do u t , Di n
HiddenRefresh Read L→H→L L H L ROW/COL Do u t
Write(1)L→H→L L L X ROW/COL Do u t
RAS-OnlyRefresh H→L H X X ROW/NA High-Z
CBRRefresh H→L L X X X High-Z
Note:
1. EARLYWRITEonly.
Integrated Silicon Solution, Inc. — 1-800-379-4774 3
Rev. 00B
08/09/2010
IS41C44052C
IS41LV44052C
Functional Description
The IS41C/41LV44052C are CMOS DRAMs
optimized
for high-speed
bandwidth, low power applications. During
READorWRITEcycles,eachbitisuniquelyaddressed
throughthe11addressbit.Theseareentered11bits(A0-
A10)atatime.TherowaddressislatchedbytheRow
Address Strobe (RAS).Thecolumnaddressislatchedby
the Column Address Strobe (CAS). RAS is used to latch
the first nine bits and CAS is used the latter ten bits.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it
is terminated by returning both RAS and CAS HIGH.
To ensures proper device operation and data integrity
any memory cycle, once initiated, must not be ended or
aborted before the minimum tr a s time has expired. A new
cycle must not be initiated until the minimum precharge
time tr p , tc p has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or
OE, whichever occurs last, while holding WEHIGH.The
column address must be held for a minimum time speci-
fied by ta r . Data Out becomes valid only when tr a c , ta a ,
tc a c and to e a are all satisfied. As a result, the access time
is dependent on the timing relationships between these
parameters.
Write Cycle
A write cycle is initiated by the falling edge of CAS and
WE,whicheveroccurslast.Theinputdatamustbevalid
at or before the falling edge of CAS or WE, whichever
occurs last.
Auto Refresh Cycle
Toretaindata,2,048refreshcyclesarerequiredineach
32msperiod.Therearetwowaystorefreshthemem-
ory:
1. By clocking each of the 2,048 row addresses (A0 through
A10)withRASatleastonceevery32ms.Anyread,
write,read-modify-writeorRAS-onlycyclerefreshes
the addressed row.
2.
Using a CAS-before-RAS refresh cycle. CAS-before-RAS
refresh is activated by the falling edge of RAS, while
holding CASLOW.InCAS-before-RAS refresh cycle,
an internal 9-bit counter provides the row addresses
and the external address inputs are ignored.
CAS-before-RAS is a refresh-only mode and no data
accessordeviceselectionisallowed.Thus,theoutput
remainsintheHigh-Zstateduringthecycle.
Power-On
After application of the Vd d supply, an initial pause of
200 µs is required followed by a minimum of eight ini-
tialization cycles (any combination of cycles containing a
RAS signal).
During power-on, it is recommended that RAS track with
Vd d or be held at a valid Vi h to avoid current surges.
4 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00B
08/09/2010
IS41C44052C
IS41LV44052C
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameters Rating Unit
Vt VoltageonAnyPinRelativetoGND 5V –1.0to+7.0 V
3.3V –0.5to+4.6
Vd d SupplyVoltage 5V –1.0to+7.0 V
3.3V –0.5to+4.6
Io u t Output Current 50 mA
Pd PowerDissipation 1 W
Ta CommercialOperationTemperature 0to+70 °C
IndustrialOperationTemperature -40to+85
Ts t g StorageTemperature –55to+125 °C
Note:
1. StressgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGSmaycausepermanentdamagetothedevice.
Thisisastressratingonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethoseindi-
catedintheoperationalsectionsofthisspecicationisnotimplied.Exposuretoabsolutemaximumratingconditions
for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol Parameter Test Condition Min. Typ. Max. Unit
Vd d Supply Voltage 5V 4.5 5.0 5.5 V
3.3V 3.0 3.3 3.6
Vi h InputHighVoltage 5V 2.0 — Vd d +1.0 V
3.3V 2.0 — Vd d +0.3
Vi l InputLowVoltage 5V –1.0 — 0.8 V
3.3V –0.3 — 0.8
ii l InputLeakageCurrent Anyinput0V≤ Vi n ≤ Vd d –5 5 µA
Other inputs not under test = 0V
ii o OutputLeakageCurrent Outputisdisabled(Hi-Z) –5 5 µA
0V ≤ Vo u t ≤ Vd d
Vo h
OutputHighVoltageLevel
io h =–5.0mA 5V 2.4 — V
io h =–2.0mA 3.3V 2.4 —
Vo l
OutputLowVoltageLevel
io l =4.2mA 5V — 0.4 V
io l =2mA 3.3V — 0.4
Ta CommercialAmbientTemperature 0 — +70 °C
IndustrialAmbientTemperature -40 — +85
CAPACITANCE(1,2)
Symbol Parameter Max. Unit
Ci n 1 Input Capacitance: A0-A10 5 pF
Ci n 2 Input Capacitance: RAS, CAS, WE, OE 7 pF
Ci o DataInput/OutputCapacitance:I/O0-I/O3 7 pF
Notes:
1. Testedinitiallyandafteranydesignorprocesschangesthatmayaffecttheseparameters.
2. Testconditions:T
a=25°C,f=1MHz.
Integrated Silicon Solution, Inc. — 1-800-379-4774 5
Rev. 00B
08/09/2010
IS41C44052C
IS41LV44052C
ELECTRICAL CHARACTERISTICS(1)
(RecommendedOperatingConditionsunlessotherwisenoted.)
Symbol Parameter Test Condition VD D /Speed Min. Max. Unit
id d 1 StandbyCurrent:TTL RAS, CAS ≥ Vi h
Commercial
5V 2 mA
3.3V — 0.5
Industrial
5V — 3
3.3V — 2
id d 2 Standby Current: CMOS RAS, CAS ≥ Vd d –0.2V 5V — 1 mA
3.3V — 0.5
id d 3 Operating Current: RAS, CAS, -50 — 120 mA
RandomRead/Write(2,3)
Address Cycling, tr c = tr c (min.)
-60 — 110
Average Power Supply Current
id d 4 Operating Current: RAS= Vi l , CAS ≥ Vi h -50 — 90 mA
Fast Page Mode(2,3,4) tr c = tr c (min.) -60 — 80
Average Power Supply Current
id d 5 Refresh Current: RAS Cycling, CAS ≥ Vi h -50 — 120 mA
RAS-Only(2,3) tr c = tr c (min.) -60 — 110
Average Power Supply Current
id d 6 Refresh Current: RAS, CAS Cycling -50 — 120 mA
CBR(2,3,5) tr c = tr c (min.) -60 — 110
Average Power Supply Current
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-OnlyorCBR)beforeproperdevice
operationisassured.TheeightRAS cycles wake-up should be repeated any time the tr e f refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each Fast Page cycle.
5. Enableson-chiprefreshandaddresscounters.
6 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00B
08/09/2010
IS41C44052C
IS41LV44052C
AC CHARACTERISTICS(1,2,3,4,5,6)
(RecommendedOperatingConditionsunlessotherwisenoted.)
-50 -60
Symbol Parameter Min. Max. Min. Max. Units
tr c RandomREADorWRITECycleTime 84 — 104 — ns
tr a c AccessTimefromRAS(6,7) — 50 — 60 ns
tc a c AccessTimefromCAS(6, 8, 15) — 13 — 15 ns
ta a AccessTimefromColumn-Address(6) — 25 — 30 ns
tr a s RASPulseWidth 50 10K 60 10K ns
tr p RASPrechargeTime 30 — 40 — ns
tc a s CASPulseWidth(23) 8 10K 10 10K ns
tc p CASPrechargeTime(9) 9 — 9 — ns
tc s h CASHoldTime(21) 38 — 40 — ns
tr c d RAS to CASDelayTime(10, 20) 12 37 14 45 ns
ta s r Row-AddressSetupTime 0 — 0 — ns
tr a h Row-AddressHoldTime 8 — 10 — ns
ta s c Column-AddressSetupTime(20) 0 — 0 — ns
tc a h Column-AddressHoldTime(20) 8 — 10 — ns
ta r Column-AddressHoldTime 30 — 40 — ns
(referenced to RAS)
tr a d RAStoColumn-AddressDelayTime(11) 10 25 12 30 ns
tr a l Column-Address to RASLeadTime 25 — 30 — ns
tr p c RAS to CASPrechargeTime 5 — 5 — ns
tr s h RASHoldTime 8 — 10 — ns
tr h c p RASHoldTimefromCASPrecharge 30 — 35 — ns
tc l z CAStoOutputinLow-Z(15, 24) 0 — 0 — ns
tc r p CAS to RASPrechargeTime(21) 5 — 5 — ns
to d OutputDisableTime(19, 24) 3 15 3 15 ns
to e OutputEnableTime(15, 16) — 12 — 15 ns
to e d OutputEnableDataDelay(Write) 12 — 15 — ns
to e h c OEHIGHHoldTimefromCASHIGH 5 — 5 — ns
to e p OEHIGHPulseWidth 10 — 10 — ns
to e s OELOWtoCASHIGHSetupTime 5 — 5 — ns
tr c s ReadCommandSetupTime(17,20) 0 — 0 — ns
tr r h ReadCommandHoldTime 0 — 0 — ns
(referenced to RAS)(12)
tr c h ReadCommandHoldTime 0 — 0 — ns
(referenced to CAS)(12,17,21)
tw c h WriteCommandHoldTime(17) 8 — 10 — ns
tw c r WriteCommandHoldTime 40 — 50 — ns
(referenced to RAS)(17)
tw p WriteCommandPulseWidth(17) 8 — 10 — ns
tw p z WEPulseWidthstoDisableOutputs 7 — 7 — ns
Integrated Silicon Solution, Inc. — 1-800-379-47747
Rev. 00B
08/09/2010
IS41C44052C
IS41LV44052C
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(RecommendedOperatingConditionsunlessotherwisenoted.)
-50 -60
Symbol Parameter Min. Max. Min. Max. Units
tr w l WriteCommandtoRASLeadTime(17) 13 — 15 — ns
tc w l WriteCommandtoCASLeadTime(17,21) 8 — 10 — ns
tw c s WriteCommandSetupTime(14,17,20) 0 — 0 — ns
td h r Data-inHoldTime(referencedtoRAS) 39 — 39 — ns
ta c h Column-AddressSetupTimetoCAS 15 — 15 — ns
PrechargeduringWRITECycle
to e h OEHoldTimefromWEduring 8 — 10 — ns
READ-MODIFY-WRITEcycle(18)
td s Data-InSetupTime(15, 22) 0 — 0 — ns
td h Data-InHoldTime(15, 22) 8 — 10 — ns
tr w c READ-MODIFY-WRITECycleTime 108 — 133 — ns
tr w d RAS to WEDelayTimeduring 64 — 77 — ns
READ-MODIFY-WRITECycle(14)
tc w d CAS to WEDelayTime(14, 20) 26 — 32 — ns
ta w d Column-Address to WEDelayTime(14) 39 — 47 — ns
tp c FastPageModeREADorWRITE 20 — 25 — ns
CycleTime
tr a s p RASPulseWidth 50 100K 60 100K ns
tc p a AccessTimefromCAS Precharge(15) — 30 — 35 ns
tp r w c READ-WRITECycleTime(24) 56 — 68 — ns
tc o h DataOutputHoldafterCASLOW 5 — 5 — ns
to f f OutputBufferTurn-OffDelayfrom 0 12 0 15 ns
CAS or RAS(13,15,19, 24)
tw h z Output Disable Delay from WE 3 10 3 10 ns
tc s r CASSetupTime(CBRREFRESH)(20, 25) 5 — 5 — ns
tc h r CASHoldTime(CBRREFRESH)( 21, 25) 8 — 10 — ns
to r d OESetupTimepriortoRASduring 0 — 0 — ns
HIDDENREFRESHCycle
tr e f AutoRefreshPeriod 2,048Cycles — 32 — 32 ms
tt TransitionTime(RiseorFall)(2, 3) 1 50 1 50 ns
AC TEST CONDITIONS
Outputload: TwoTTLLoadsand50pF(Vd d = 5.0V ±10%)
OneTTLLoadand50pF(Vd d = 3.3V ±10%)
Input timing reference levels: Vi h = 2.0V, Vi l = 0.8V (Vd d = 5.0V ±10%);
Vi h = 2.0V, Vi l = 0.8V (Vd d = 3.3V ±10%)
Output timing reference levels: Vo h = 2.4V, Vo l = 0.4V (Vd d = 5V ±10%, 3.3V ±10%)
8 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00B
08/09/2010
IS41C44052C
IS41LV44052C
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-OnlyorCBR)beforeproperdevice
operationisassured.TheeightRAS cycles wake-up should be repeated any time the tr e f refresh requirement is exceeded.
2. Vi h (MIN) and Vi l (MAX)arereferencelevelsformeasuringtimingofinputsignals.Transitiontimes,aremeasuredbetweenVi h
and Vi l (or between Vi l and Vi h ) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between Vi h and Vi l (or between Vi l and Vi h )
in a monotonic manner.
4. If CAS and RAS = Vi h ,dataoutputisHigh-Z.
5. If CAS = Vi l ,dataoutputmaycontaindatafromthelastvalidREADcycle.
6.MeasuredwithaloadequivalenttooneTTLgateand50pF.
7.Assumesthattr c d tr c d (MAX).Iftr c d is greater than the maximum recommended value shown in this table, tr a c will increase by
the amount that tr c d exceeds the value shown.
8. Assumes that tr c d ž tr c d (MAX).
9. If CASisLOWatthefallingedgeofRAS,dataoutwillbemaintainedfromthepreviouscycle.Toinitiateanewcycleandclearthe
data output buffer, CAS and RAS must be pulsed for tc p .
10. Operation with the tr c d (MAX)limitensuresthattr a c (MAX)canbemet.tr c d (MAX)isspeciedasareferencepointonly;iftr c d
is greater than the specified tr c d (MAX)limit,accesstimeiscontrolledexclusivelybytc a c .
11. Operation within the tr a d (MAX)limitensuresthattr c d (MAX)canbemet.tr a d (MAX)isspeciedasareferencepointonly;iftr a d
is greater than the specified tr a d (MAX)limit,accesstimeiscontrolledexclusivelybyta a .
12.Eithertr c h or tr r h mustbesatisedforaREADcycle.
13. to f f (MAX)denesthetimeatwhichtheoutputachievestheopencircuitcondition;itisnotareferencetoVo h or Vo l .
14. tw c s , tr w d , ta w d and tc w d arerestrictiveoperatingparametersinLATEWRITEandREAD-MODIFY-WRITEcycleonly.Iftw c s ž
tw c s (MIN),thecycleisanEARLYWRITEcycleandthedataoutputwillremainopencircuitthroughouttheentirecycle.Iftr w d ž
tr w d (MIN), ta w d ž ta w d (MIN) and tc w d ž tc w d (MIN),thecycleisaREAD-WRITEcycleandthedataoutputwillcontaindataread
from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go
back to Vi h ) is indeterminate. OEheldHIGHandWEtakenLOWafterCASgoesLOWresultinaLATEWRITE(OE-controlled)
cycle.
15. Output parameter (I/O) is referenced to corresponding CAS input.
16.DuringaREADcycle,ifOEisLOWthentakenHIGHbeforeCASgoesHIGH,I/Ogoesopen.IfOEistiedpermanentlyLOW,a
LATEWRITEorREAD-MODIFY-WRITEisnotpossible.
17.WritecommandisdenedasWE going low.
18.LATEWRITEandREAD-MODIFY-WRITEcyclesmusthavebothto d and to e h met (OEHIGHduringWRITEcycle)inorderto
ensurethattheoutputbufferswillbeopenduringtheWRITEcycle.TheI/OswillprovidethepreviouslywrittendataifCAS remains
LOWandOEistakenbacktoLOWafterto e h is met.
19.TheI/OsareinopenduringREADcyclesonceto d or to f f occur.
20. Determined by falling edge of CAS.
21. Determined by rising edge of CAS.
22.TheseparametersarereferencedtoCASleadingedgeinEARLYWRITEcyclesandWEleadingedgeinLATEWRITEorREAD-
MODIFY-WRITEcycles.
23. CAS must meet minimum pulse width.
24.The3nsminimumisaparameterguaranteedbydesign.
25.Enableson-chiprefreshandaddresscounters.
Integrated Silicon Solution, Inc. — 1-800-379-4774 9
Rev. 00B
08/09/2010
IS41C44052C
IS41LV44052C
FAST-PAGE-MODE READ CYCLE
tRAS
tRC
tRP
tAR
tCAH
tASC
tRAD tRAL
OE
I/O
WE
ADDRESS
CAS
RAS
Row Column Row
Open Open
Valid Data
tCSH
tCAS
tRSH
tCRP tCLCH
tRCD
tRAHtASR
tRRH
tRCHtRCS
tAA
tCAC tOFF(1)
tRAC
tCLC
tOES
tOE tOD
Don’t Care
10 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00B
08/09/2010
IS41C44052C
IS41LV44052C
FAST PAGE MODE READ-MODIFY-WRITE CYCLE
OUT
t
AR
t
RWD
t
AWD
I/O
WE
OE
ADDRESS
CAS
RAS
Row Column Column Column
t
AR
t
CSH
t
CAS
t
CAS
t
CAS
t
RASP
t
RSH
t
PRWC
t
RCD
t
CWD
t
CWD
t
CWD
t
CRP
t
ASR
t
RAD
t
RCS
t
ASC
t
ASC
t
ASC
t
RAL
t
CAH
t
CP
t
CP
t
RP
t
CAH
t
AWD
t
AWD
t
CAC
t
AA
t
DH
t
CLZ
t
RAC
t
DH
t
DH
t
OEA
t
CLZ
t
CAC
t
OEA
t
CAC
t
OEA
OUT
OUT ININ IN
t
OEZ
t
OEZ
t
OED
t
OED
t
DS
t
OEZ
t
OED
t
DS
t
CLZ
t
AA
t
AA
t
WP
t
RAH
t
WP
t
WP
t
CWL
t
CWL
t
CWL
t
RWL
t
CPWD
t
CPWD
t
CAH
t
CRP
t
DS
Don’t Care
Integrated Silicon Solution, Inc. — 1-800-379-4774 11
Rev. 00B
08/09/2010
IS41C44052C
IS41LV44052C
FAST-PAGE-MODE EARLY WRITE CYCLE (OE=DON'TCARE)
tRAS
tRC
tRP
tAR
tCAH
tASC
tRAD tRAL
tACH
I/O
WE
ADDRESS
CAS
RAS
Row Column Row
tCSH
tCAS
tRSH
tCRP tCLCH
tRCD
tRAHtASR
tCWL
tWCR
tWCH
tRWL
tWP
tWCS
tDH
tDS
tDHR
Valid Data
Don’t Care
12 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00B
08/09/2010
IS41C44052C
IS41LV44052C
FAST-PAGE-MODE READ WRITE CYCLE (LATEWRITEandREAD-MODIFY-WRITECycles)
t
RAS
t
RWC
t
RP
t
AR
t
CAH
t
ASC
t
RAD
t
RAL
t
ACH
WE
OE
ADDRESS
CAS
RAS
Row Column Row
t
CSH
t
CAS
t
RSH
t
CRP
t
CLCH
t
RCD
t
RAH
t
ASR
t
RWD
t
CWL
t
CWD
t
RWL
t
AWD
t
WP
t
RCS
t
CAC
t
CLZ
t
DS
t
DH
t
OEH
t
OD
t
OE
t
RAC
t
AA
I/O Open Open
Valid D
OUT
Valid D
IN
Don’t Care
Integrated Silicon Solution, Inc. — 1-800-379-4774 13
Rev. 00B
08/09/2010
IS41C44052C
IS41LV44052C
FAST PAGE MODE EARLY WRITE CYCLE
t
AR
I/O
WE
OE
ADDRESS
CAS
RAS
Row Column Column Column
t
AR
t
CWL
t
WCR
t
DHR
t
CSH
t
CAS
t
CAS
t
CAS
t
RASP
t
RSH
t
RHCP
t
PC
t
RCD
t
CRP
t
ASR
t
WCS
t
DS
t
RAD
t
ASC
t
ASC
t
ASC
t
RAL
t
CAH
t
WCH
t
DH
t
DS
t
DS
t
DH
t
DH
t
CP
t
CP
t
RP
t
CAH
t
RAH
t
CAH
t
CRP
t
CWL
t
WCS
t
WCS
t
WCH
t
WP
t
WP
t
CWL
t
WCH
t
WP
Valid DIN Valid DIN
Valid DIN
Don’t Care
14 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00B
08/09/2010
IS41C44052C
IS41LV44052C
AC WAVEFORMS
READ CYCLE (WithWE-Controlled Disable)
RAS-ONLY REFRESH CYCLE (OE, WE=DON'TCARE)
tAR
tCAH tASC
tASC
tRAD
OE
I/O
WE
ADDRESS
CAS
RAS
Row Column
Open Open
Valid Data
tCSH
tCAS
tCRP tRCD tCP
tRAHtASR
tRCH tRCStRCS
tAA
tCAC
tWHZ
tRAC
tCLZ
tCLZ
tOE tOD
Column
t
RAS
t
RC
t
RP
I/O
ADDRESS
CAS
RAS
Row Row
Open
t
CRP
t
RAH
t
ASR
t
RPC
Don’t Care
Don’t Care
Integrated Silicon Solution, Inc. — 1-800-379-4774 15
Rev. 00B
08/09/2010
IS41C44052C
IS41LV44052C
HIDDEN REFRESH CYCLE(1) (WE=HIGH;OE=LOW)
CBR REFRESH CYCLE (Addresses; WE, OE=DON'TCARE)
t
RAS
t
RAS
t
RP
t
RP
I/O
CAS
RAS
Open
t
CP
t
RPC
t
CSR
t
CHR
t
RPC
t
CSR
t
CHR
t
RAS
t
RAS
t
RP
CAS
RAS
t
CRP
t
RCD
t
RSH
t
CHR
t
AR
t
ASC
t
RAD
ADDRESS Row Column
t
RAH
t
ASR
t
RAL
t
CAH
I/O Open Open
Valid Data
t
AA
t
CAC
t
RAC
t
CLZ
t
OFF
(2)
OE
t
OE
t
ORD
t
OD
Don’t Care
Don’t Care
16 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00B
08/09/2010
IS41C44052C
IS41LV44052C
ORDERING INFORMATION: 5V
Industrial Range: -40°C to +85°C
Speed (ns) Order Part No. Refresh Package
50 IS41C44052C-50CTGI 2K 300-milTSOP-II,CuleadframeplatedwithmatteSnBi
ORDERING INFORMATION: 3.3V
Industrial Range: -40°C to +85°C
Speed (ns) Order Part No. Refresh Package
50 IS41LV44052C-50CTGI 2K 300-milTSOP-II,CuleadframeplatedwithmatteSnBi
Note:
The -50 speed option supports 50ns and 60ns timing specications.
Integrated Silicon Solution, Inc. — 1-800-379-4774 17
Rev. 00B
08/09/2010
IS41C44052C
IS41LV44052C
Θ
Θ
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION.
4. REFERENCE DOCUMENT : JEDEC SPEC. MS-025 , A
1. CONTROLLING DIMENSION : MM
2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION.
NOTE :
07/07/2008
Package Outline
