This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.07 /Jan.99 Hyundai Semiconductor
HY62V16100-(I)/HY62U16100-(I) Series
64Kx16bit CMOS SRAM
DESCRIPTION
The HY62V16100-(I)/HY62U16100-(I) is a high-
speed, low power and 1M bits CMOS SRAM
organized as 65,536 words by 16 bits. The
HY62V16100-(I)/ HY62U16100-(I) uses sixteen
common input and output lines and has an output
enable pin which operates faster than address
access time at a read cycle. The device is
fabricated using HYUNDAI's advanced CMOS
process and designed with high-speed low power
circuit technology. It is particulary well suited for
being used in high-density and low power system
applications.
FEATURES
• Fully static operation and Tri-state output
• TTL compatible inputs and outputs
• Data Byte Control
- LB : I/O1 ~ I/O8, UB : I/O9 ~ I/O16
• Battery backup(L/LL-part)
- 2.0V(min) data retention
• Standard pin configuration
- 44pin 400mil TSOP-II
(Standard and Reversed)
Product Supply Speed Operation Standby Current(uA) Temperature.
No. Voltage(V) (ns) Current(mA) L LL (°C)
HY62V16100 3.3 85/100/120 5 50 10 0~70(Normal)
HY62V16100-I 3.3 85/100/120 5 50 15 -40~85(E.T.)
HY62U16100 3.0 100/120/150 5 50 10 0~70(Normal)
HY62U16100-I 3.0 100/120/150 5 50 10 -40~85(E.T.)
Note 1. E.T. : Extended Temperature, Normal : Normal Temperature
2. Current value is max.
PIN CONNECTION BLOCK DIAGRAM
A5
A6
/OE
/UB
/LB
I/O16
I/O15
I/O14
I/O13
GND
Vcc
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
NC
A7
A4
A3
A2
A1
A0
/CS
I/O1
I/O2
I/O3
I/O4
Vcc
GND
I/O5
I/O6
I/O7
I/O8
/WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
A11
A9
A8
NC
I/O9
I/O10
I/O11
I/O12
Vcc
GND
I/O13
I/O14
I/O15
I/O16
/LB
/UB
/OE
A7
A6
A5
A10
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
NC
A12
A13
A14
A15
/WE
I/O8
I/O7
I/O6
I/O5
GND
Vcc
I/O4
I/O3
I/O2
I/O1
/CS
A0
A1
A2
A3
A4
TSOP-II(Standard) TSOP-II(Reversed)
PIN DESCRIPTION
Pin Name Pin Funtion Pin Name Pin Funtion
/CS Chip Select I/O1~I/O16 Data Input/Output
/WE Write Enable A0~A15 Address Input
/OE Output Enable Vcc Power(3.3V/3.0V)
/LB Low Byte Control(I/O1~I/O8) Vss Ground
/UB Upper Byte Control(I/O9~I/O16) NC No Connection
A12
A13
ROW
DECODER
COLUMN
DECODER
BLOCK
DECODER
MEMORY ARRAY
512x128x16
SENSE AMP
WRITE DRIVER
OUTPUT
BUFFER
I/O1
I/O8
I/O9
I/O16
PRE-DECODER
ADD INPUT
BUFFER
ADD INPUT
BUFFER
ADD INPUT
BUFFER
A1~A7
A14
A15
A8
A9
A10
A11
A0
/CS
/OE
/LB
/UB
/WE
HY62V16100-(I)/HY62U16100-(I) Series
Rev.07 /Jan.99 2
ORDERING INFORMATION
Part No. Speed Power Temp. Package
HY62V16100LT2 85/100/120 L-part TSOP-II Standard
HY62V16100LLT2 85/100/120 LL-part TSOP-II Standard
HY62V16100LR2 85/100/120 L-part TSOP-II Reversed
HY62V16100LLR2 85/100/120 LL-part TSOP-II Reversed
HY62V16100LT2-I 85/100/120 L-part E.T. TSOP-II Standard
HY62V16100LLT2-I 85/100/120 LL-part E.T. TSOP-II Standard
HY62V16100LR2-I 85/100/120 L-part E.T. TSOP-II Reversed
HY62V16100LLR2-I 85/100/120 LL-part E.T. TSOP-II Reversed
HY62U16100LT2 100/120/150 L-part TSOP-II Standard
HY62U16100LLT2 100/120/150 LL-part TSOP-II Standard
HY62U16100LR2 100/120/150 L-part TSOP-II Reversed
HY62U16100LLR2 100/120/150 LL-part TSOP-II Reversed
HY62U16100LT2-I 100/120/150 L-part E.T. TSOP-II Standard
HY62U16100LLT2-I 100/120/150 LL-part E.T. TSOP-II Standard
HY62U16100LR2-I 100/120/150 L-part E.T. TSOP-II Reversed
HY62U16100LLR2-I 100/120/150 LL-part E.T. TSOP-II Reversed
Note 1. E.T. : Extended Temperature, Blank : Normal Temperature
ABSOLUTE MAXIMUM RATING (1)
Symbol Parameter Rating Unit Remark
Vcc, VIN, VOUT Power Supply, Input/Output Voltage -0.3 to 4.6 V
TAOperating Temperature 0 to 70 °CHY62V16100
HY62U16100
-40 to 85 °CHY62V16100-I
HY62U16100-I
TSTG Storage Temperature -65 to 125 °C
PDPower Dissipation 1.0 W
IOUT Data Output Current 50 mA
TSOLDER Lead Soldering Temperature & Time 260 • 10 °C•sec
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliablity.
RECOMMENDED DC OPERATING CONDITION
TA = 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.)
Symbol Parameter Product Min. Typ. Max. Unit
Vcc Supply Voltage HY62V16100-(I) 3.0 3.3 3.6 V
HY62U16100-(I) 2.7 3.0 3.3 V
Vss Ground HY62V16100-(I) 0 0 0 V
HY62U16100-(I)
VIH Input High Voltage HY62V16100-(I) 2.2 -Vcc+0.3 V
HY62U16100-(I)
VIL Input Low Voltage HY62V16100-(I) -0.3 -0.4 V
HY62U16100-(I)
HY62V16100-(I)/HY62U16100-(I) Series
Rev.07 /Jan.99 3
TRUTH TABLE
I/O Pin
I/O1~I/O8 I/O9~I/O16
HX X X X Not Selected Hi-Z Hi-Z ISB, ISB1
LH H X X Output Disabled Hi-Z Hi-Z Icc
LX X H H Hi-Z Hi-Z
LHL L HRead DOUT Hi-Z
HLHi-Z DOUT Icc
L L DOUT DOUT
LLXLHWrite DIN Hi-Z
HLHi-Z DIN Icc
L L DIN DIN
Note:
1. H=VIH, L=VIL, X=don't care
2. UB, LB(Upper, Lower Byte enable)
These active LOW inputs allow indiviual bytes to be written or read.
When LB is LOW, data is written or read to the lower byte, I/O1 -I/O8.
When UB is LOW, data is written or read to the Upper byte, I/O9 -I/O16.
DC ELECTRICAL CHARACTERISTICS
Vcc = 3.3V ± 10%/3.0V ±10%, TA = 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.), unless otherwise specified
Symbol Parameter Test Condition Min Typ Max Unit
ILI Input Leakage Current Vss < VIN < Vcc -1 -1uA
ILO Output Leakage Current Vss < VOUT < Vcc,
/CS = VIH or /OE = VIH or /WE = VIL
or /UB = VIH or /LB = VIH
-1 -1uA
Icc Operating Power Supply
Current /CS = VIL, VIN = VIH or VIL
II/O = 0mA - - 5mA
ICC1 Average Operating Current /CS = VIL, Min Duty Cycle = 100%
II/O = 0mA - - 50 mA
ISB TTL Standby Current
(TTL Input) /CS = VIH - - 0.5 mA
ISB1 Standby HY62V16100 /CS = Vcc – 0.2V L- - 50 uA
Current LL - - 10 uA
(CMOS HY62V16100-I L 50 uA
Input) LL - - 15 uA
HY62U16100 L- - 50 uA
LL - - 10 uA
HY62U16100-I L- - 50 uA
LL - - 10 uA
VOL Output Low Voltage IOL = 2.1mA - - 0.4 V
VOH Output High Voltage IOH = -1mA 2.2 - - V
Note : Typical values are at Vcc = 3.3V/3.0V, TA = 25°C
/CS
/WE
/OE
/LB
/UB
Mode
Supply Current
HY62V16100-(I)/HY62U16100-(I) Series
Rev.07 /Jan.99 4
AC CHARACTERISTICS(I)
Vcc = 3.3V ± 10%, TA = 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.), unless otherwise specified
-85 -10 -12
Min. Max. Min. Max. Min Max.
1tRC Read Cycle Time 85 -100 -120 -ns
2tAA Address Access Time -85 -100 -120 ns
3tACS Chip Select Access Time -85 -100 -120 ns
4tOE Output Enable to Output Valid -45 -50 -60 ns
5tBA /LB, /UB Access Time -45 -50 -60 ns
6tCLZ Chip Select to Output in Low Z 10 -10 -10 -ns
7tOLZ Output Enable to Output in Low Z 10 -10 -10 -ns
8tBLZ /LB. /UB Enable to Output in Low Z 10 -10 -10 -ns
9tCHZ Chip Deselection to Output in High Z 0 30 0 30 0 40 ns
10 tOHZ Out Disable to Output in High Z 0 30 0 30 0 40 ns
11 tBHZ /LB, /UB Disable to Output in High Z 0 30 0 30 0 40 ns
12 tOH Output Hold from Address Change 20 -20 -20 -ns
13 tWC Write Cycle Time 85 -100 -120 -ns
14 tCW Chip Selection to End of Write 70 -80 -100 -ns
15 tAW Address Valid to End of Write 70 -80 -100 -ns
16 tBW /LB, /UB Valid to End of Write 70 -80 -100 -ns
17 tAS Address Set-up Time 0-0-0-ns
18 tWP Write Pulse Width 55 -70 -85 -ns
19 tWR Write Recovery Time 0-0-0-ns
20 tWHZ Write to Output in High Z 0 30 0 30 0 40 ns
21 tDW Data to Write Time Overlap 35 -40 -50 -ns
22 tDH Data Hold from Write Time 0-0-0-ns
23 tOW Output Active from End of Write 10 -10 -10 -ns
Symbol Parameter
#Unit
HY62V16100-(I)/HY62U16100-(I) Series
Rev.07 /Jan.99 5
AC CHARACTERISTICS(II)
Vcc = 3.0V ± 10%, TA = 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.), unless otherwise specified
-10 -12 -15
Min. Max. Min. Max. Min Max.
1TRC Read Cycle Time 100 -120 -150 -ns
2TAA Address Access Time -100 -120 -150 ns
3TACS Chip Select Access Time -100 -120 -150 ns
4tOE Output Enable to Output Valid -50 -60 -75 ns
5tBA /LB, /UB Access Time -50 -60 -75 ns
6tCLZ Chip Select to Output in Low Z 10 -10 -10 -ns
7tOLZ Output Enable to Output in Low Z 10 -10 -10 -ns
8tBLZ /LB. /UB Enable to Output in Low Z 10 -10 -10 -ns
9tCHZ Chip Deselection to Output in High Z 0 30 0 40 0 50 ns
10 tOHZ Out Disable to Output in High Z 0 30 0 40 0 50 ns
11 tBHZ /LB, /UB Disable to Output in High Z 0 30 0 40 0 50 ns
12 tOH Output Hold from Address Change 20 -20 -20 -ns
13 tWC Write Cycle Time 100 -120 -150 -ns
14 tCW Chip Selection to End of Write 80 -100 -120 -ns
15 tAW Address Valid to End of Write 80 -100 -120 -ns
16 tBW /LB, /UB Valid to End of Write 80 -100 -120 -ns
17 tAS Address Set-up Time 0-0-0-ns
18 tWP Write Pulse Width 70 -85 -100 -ns
19 tWR Write Recovery Time 0-0-0-ns
20 tWHZ Write to Output in High Z 0 30 0 40 0 50 ns
21 tDW Data to Write Time Overlap 40 -50 -60 -ns
22 tDH Data Hold from Write Time 0-0-0-ns
23 tOW Output Active from End of Write 10 -10 -10 -ns
AC TEST CONDITIONS
TA = 0°C to 70°C (Normal) / -40°C to 85°C (E.T.), unless otherwise specified
PARAMETER Value
Input Pulse Level 0.4V to 2.2V
Input Rise and Fall Time 5ns
Input and Output Timing Reference Level 1.5V
Output Load CL = 100pF + 1TTL Load
AC TEST LOADS
CL(1)
TTL
Note : Including jig and scope capacitance
Symbol Parameter
#
Unit
HY62V16100-(I)/HY62U16100-(I) Series
Rev.07 /Jan.99 6
CAPACITANCE
Temp = 25°C, f= 1.0MHz
Symbol Parameter Condition Max. Unit
CIN Input Capacitance(ADD, /CS, /WE, /OE, /LB, /UB) VIN = 0V 6pF
COUT Output Capacitance(I/O) VI/O = 0V 8pF
Note : This parameter is sampled and not 100% not tested
TIMING DIAGRAM
READ CYCLE 1(Note 1)
ADDR
OE
CS
UB,LB
Data
Out
Data Valid
tRC
tACS
tCLZ
tOE
tOLZ(5)
tAA
tOH
tBHZ(5)
High-Z
tBA
tBLZ(5)
tOHZ(5)
tCHZ(5)
READ CYCLE 2(Note 1,2,4)
tRC
tAA
Data ValidPrevious Data
tOH tOH
ADDR
Data
Out
HY62V16100-(I)/HY62U16100-(I) Series
Rev.07 /Jan.99 7
READ CYCLE 3(Note 1,3,4)
CS
tACS
Data Valid
tCLZ(5)
tCHZ(5)
Data
Out
Notes:
1. /WE is high for the Read Cycle.
2. Device is continuously selected. /CS = VIL
3. Address valid is prior to or coincident with /CS transition low
4. /OE = VIL
5. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
WRITE CYCLE 1
ADDR
CS
Data
Out
tWC
tDW
tOHZ(3,9)
WE
Data Valid
tDH
tWP(1)
tAS
Data In
tCW
tWR(2)
tBW
tAS
tAW
UB,LB
HY62V16100-(I)/HY62U16100-(I) Series
Rev.07 /Jan.99 8
WRITE CYCLE 2 (Note 5)
tDW
tWHZ
WE
Data Valid
tDH
tWP
tAS
Data In
tWR
tCW
tAW
(6)
(7)
tWHZ
ADDR
CS
Data
Out
tWC
Notes:
1. A write occurs during the overlap(tWP) of a low /CS and low /WE .
2. tWR is measured from the earlier of /CS, /LB, /UB, or /WE going high to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the /CS, /LB and /UB low transition occur simultaneously with the /WE low transition or after the /WE
transition, outputs remain in a high impedance state.
5. /OE is continuously low(/OE=VIL)
6. Q(data out) is the same phase with the write data of this write cycle.
7. Q(data out) is the read data of the next address.
8. If /CS is low during this period, I/O pins are in the output state.
Then the data input signals of opposite phase to the outputs must not be applied to them.
9. Transition is measured +200mV from steady state.
This parameter is sampled and not 100% tested.
HY62V16100-(I)/HY62U16100-(I) Series
Rev.07 /Jan.99 9
DATA RETENTION ELECTRIC CHARATERISTIC
TA = 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.)
Symbol Parameter Test Condition Min Typ Max Unit
VDR Vcc for Data Retention 2--V
ICCDR Data Retention HY62V16100 Vcc = 3.0V, L- - 30 uA
Current /CS > Vcc - 0.2V LL - - 10 uA
HY62V16100-I Vss<VIN<Vcc L- - 30 uA
LL - - 15 uA
HY62U16100 L- - 30 uA
LL - - 10 uA
HY62U16100-I L- - 30 uA
LL - - 15 uA
tCDR Chip Deselect to Data Retention Time 0- - ns
tR Operating Recovery Time 5- - ms
DATA RETENTION TIMING DIAGRAM
CS
VDR
CS>VCC-0.2V
tCDR tR
VSS
VCC
3.0/2.7V
2.2V
DATA RETENTION MODE
Note :
1. 3.0V : HY62V16100 and HY62V16100-I
2. 2.7V : HY62U16100 and HY62U16100-I
RELIABILITY SPEC.
TEST MODE TEST SPEC.
ESD HBM > 2000V
MM > 250V
LATCH - UP < -100mA
> 100mA
HY62V16100-(I)/HY62U16100-(I) Series
Rev.07 /Jan.99 10
PACKAGE INFORMATION
44pin 400mil Thin Small Outline Package
#22
#23
#44
#1
0.016(0.4)
0.012(0.3) 0.0315(0.800)
BSC
0.0059(0.150)
0.002(0.050)
0.047(1.194)
0.039(0.991)
0.721(18.313)
0.729(18.517)
0.10MAX
0.004MAX
0.404(10.262)
0.396(10.058)
0.0235(0.597)
0.0160(0.406)
0.0083(0.21)
0.0047(0.120)
0~5
UNIT : INCH(mm)
0.462(11.735)
0.470(11.938)
Min.
Max.