ISL8013 - Intersil Corporation

FN6309.1

ISL8013

3A Low Quiescent Current 1MHz High

Efficiency Synchronous Buck Regulator

The ISL8013 is a high efficiency, monolithic, synchronous

step-down DC/DC converter that can deliver up to 3A

continuous output current from a 2.7V to 5.5V input supply . It

uses a current control architecture to deliver very low duty

cycle operation at high frequency with fast transient

response and excellent loop stability.

The ISL8013 integrates a pair of low ON-resistance

P-Channel and N-Channel inte rnal MOSFETs to maximize

efficiency and minimize external component count. The

100% duty-cycle operation allows less than 400mV dropout

voltage at 3A output current. High 1MHz pulse-width

modulation (PWM) switching frequency allows the use of

small external components and SYNC input enables multiple

ICs to synchronize out of phase to reduce ripple and

eliminate beat frequencies.

The ISL8013 can be configured for discontinuous or forced

continuous operation at light load. Forced continuous

operation reduces noise and RF interference while

discontinuous mode provides high efficiency by reducing

switching losses at light loads.

Fault protection is provided by internal hiccup mode current

limiting during short circuit and overcurrent conditions, an

output over voltage comparator and over-temperature

monitor circuit. A power good output voltage monitor

indicates when the output is in regulation.

The ISL8013 is offered in a space saving 4x4 QFN lead free

package with exposed pad lead frames for low thermal

resistance.

The ISL8013 includes a pair of low ON-resistance

P-Channel and N-Channel inte rnal MOSFETs to maximize

efficiency and minimize external component count. The

100% duty-cycle operation allows less than 300mV dropout

voltage at 3A.

The ISL8013 offers a 1ms Power Good (PG) timer at

power-up. When shutdown, ISL8013 discharges the output

capacitor. Other features include internal soft-start, internal

compensation, overcurrent protection, and thermal

shutdown.

The ISL8013 is offered in a 4mmx4mm 16 Ld QFN package

with 1mm maximum height. The complete converter

occupies less than 0.4in2 area.

Features

• High Efficiency Synchronous Buck Regulator with up to

97% Efficiency

• Power-Good (PG) Output with a 1ms Delay

• 2.7V to 5.5V Supply Voltage

• 3% Output Accuracy Over-Temperature/Load/Line

• 3A Output Current

• Start-up with Pre-Biased Output

• Internal Soft-Start - 1ms

• Soft-Stop Output Discharge During Disabled

• 35µA Quiescent Supply Current in PFM Mode

• Selectable Forced PWM Mode and PFM Mode

• External Synchronization up to 4MHz

• Less than 1µA Logic Controlled Shutdown Current

• 100% Maximum Duty Cycle

• Internal Current Mode Compensation

• Peak Current Limiting and Hiccup Mode Short Circuit

Protection

• Over-Temperature Protection

• Small 16 Ld 4mmx4mm QFN

• Pb-Free (RoHS Compliant)

Applications

• DC/DC POL Modules

• µC/µP, FPGA and DSP Power

• Plug-in DC/DC Modules for Routers and Switch ers

• Portable Instruments

• Test and Measurement Systems

• Li-ion Battery Powered Device s

• Small Form Factor (SFP) Modules

• Bar Code Readers

Data Sheet December 27, 2007

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

2FN6309.1

December 27, 2007

Pinout

ISL8013

(16 LD QFN)

TOP VIEW

Typical Application

Ordering Information

PART

NUMBER

(Note) PART

MARKING

TEMP.

RANGE

(°C) PACKAGE

(Pb-Free) PKG.

DWG. #

ISL8013IRZ* 8013IRZ -40 to +85 16 Ld 4x4 QFN L16.4x4

*Add “-T” suffix for tape and reel. Please refer to TB347 for details

on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ

special Pb-free material sets; molding compounds/die attach

materials and 100% matte tin plate PLUS ANNEAL - e3 termination

finish, which is RoHS compliant and compatible with both SnPb and

Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed

the Pb-free requirements of IPC/JEDEC J STD-020.

VIN

VDD

SYNCH

16 14 13

6578

PGND

SGND

VFB

1.5µH

PGND

VFB

VIN

SYNCH

INPUT 2.7V TO 5.5V OUTPUT

1.8V

2 x 22µF

ISL8013

124k

100k

2 x 22µF

VDD

SGND

47pF

100k

FIGURE 1. TYPICAL APPLICATION DIAGRAM

ISL8013

3FN6309.1

December 27, 2007

Block Diagram

FIGURE 2. FUNCTIONAL BLOCK DIAGRAM

CSA

OCP 1.4V

0.5V

SKIP

Slope

COMP

SLOPE

Soft

START

SOFT

0.8V EAMP COMP PWM/PFM

LOGIC

CONTROLLER

PROTECTION

DRIVER

VFB

0.736V

0.864V

SYNCH

SHUTDOWN

VIN

PGND

OSCILLATOR

ZERO-CROSS

SENSING

BANDGAP

SCP

0.2V

SHUTDOWN

1ms

DELAY

27pF

390k

SGND

3pF

ISL8013

4FN6309.1

December 27, 2007

Absolute Maximum Ratings (Reference to GND) Thermal Information

VIN, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to 6V

EN, SYNCH, PG . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN+0.3V

LX. . . . . . . . . . . . . . . . . . . . . . . . . .-1.5V (100ns)/-0.3V (DC) to 6.5V

VFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V

Recommended Operating Conditions

VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . .2.7V to 5.5V

Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 3A

Ambient Temperature Range. . . . . . . . . . . . . . . . . . .-40°C to +85°C

Thermal Resistance (Typical, Notes 1, 2) θJA (°C/W) θJC (°C/W)

16 Ld 4x4 QFN Package . . . . . . . . . 37 6

Junction Temperature Range. . . . . . . . . . . . . . . . . .-55°C to +125°C

Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product relia bility and

result in failures not covered by warranty.

NOTES:

1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

Tech Brief TB379.

2. θJC, “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379.

Electrical Specifications Unless otherwise noted, all parameter limits are established over the recommended operating conditions and

the typical specification are measured at the following conditions: TA = -40°C to +85°C, VIN = 3.6V, EN = VDD,

unless otherwise noted. Typical values are at TA= +25°C.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

INPUT SUPPLY

VIN Undervoltage Lockout Threshold VUVLO Rising, no load - 2.5 2.7 V

Falling, no load 2.2 2.4 - V

Quiescent Supply Current IVIN SYNCH = GND, no load at the output - 35 - µA

SYNCH = GND, no load at the output and no

switches switching -3045µA

SYNCH = VDD, FS = 1MHz, no load at the

output -6.510mA

Shut Down Supply Current ISD VIN = 5.5V, EN = low - 0.1 2 µA

OUTPUT REGULATION

Reference Voltage VREF 0.790 0.8 0.810 V

VFB Bias Current IVFB VFB = 0.75V - 0.1 - µA

Line Regulation VIN = VO + 0.5V to 5.5V (minimal 2.7V) - 0.2 - %/V

Soft-Start Ramp Time Cycle -1-ms

OVERCURRENT PROTECTION

Current Limit Blanking Time tOCON -17-Clock

pulses

Overcurrent and Auto Restart Period tOCOFF - 4 - SS cycle

Switch Current Limit ILIMIT (Note 3) 4.0 4.8 5.9 A

Peak Skip Limit ISKIP (Note 3) - 1.2 - A

COMPENSATION

Error Amplifier Trans-Conductance -20-µA/V

Trans-Resistance RT 0.213 0.25 0.287 Ω

P-Channel MOSFET ON-Resistance VIN = 5V, IO = 200mA - 50 75 mΩ

VIN = 2.7V, IO = 200mA - 70 100 mΩ

ISL8013

5FN6309.1

December 27, 2007

N-Channel MOSFET ON-Resistance VIN = 5V, IO = 200mA - 50 75 mΩ

VIN = 2.7V, IO = 200mA - 70 100 mΩ

LX Maximum Duty Cycle - 100 - %

PWM Switching Frequency fS0.80 1.00 1.20 MHz

LX Minimum On-Time SYNCH = High - - 140 ns

Output Low Voltage Sinking 1mA - - 0.3 V

Delay Time (Rising Edge) 0.65 1 1.35 ms

PG Pin Leakage Current PG = VIN = 3.6V - 0.01 0.1 µA

PGOOD Rising Threshold Percentage of regulation voltage 89 92 95 %

PGOOD Falling Threshold Percentage of regulation voltage 85 88 91.5 %

PGOOD Delay Time (Falling Edge) -15-µs

EN, SYNCH

Logic Input Low --0.4V

Logic Input High 1.4 - - V

Synch Logic Input Leakage Current ISYNCH Pulled up to 5.5V - 0.1 1 μA

Enable Logic Input Leakage Current IEN -0.11μA

Thermal Shutdown - 140 - °C

Thermal Shutdown Hysteresis -25-°C

NOTE:

3. Limits established by characterization and are not production tested.

Electrical Specifications Unless otherwise noted, all parameter limits are established over the recommended operating conditions and

the typical specification are measured at the following conditions: TA = -40°C to +85°C, VIN = 3.6V, EN = VDD,

unless otherwise noted. Typical values are at TA= +25°C. (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

ISL8013

6FN6309.1

December 27, 2007

Pin Descriptions

VIN

Input supply voltage. Connect a 10µF ceramic capacitor to

power ground.

VDD

Input supply vol tage for the analog circuitry. Connect to VIN

pin.

Regulator enable pin. Enable the output when driven to high.

Shut down the chip and discharge output capacitor when

driven to low. Do not leave this pin floating.

1ms timer output. At power-up or EN HI, this output is a 1ms

delayed Power-Good signal for the output voltage.

SYNCH

Mode Selection pin. Connect to logic high or input voltage

VDD for PWM mode. Connect to logic low or ground for PFM

mode. Connect to an external function generator for

synchronization with the negative edge trigger. Do not leave

this pin floating.

Switching node connection. Connect to one terminal of the

inductor.

PGND

Power ground.

SGND

Signal ground.

VFB

Buck regulator output feedback. Connect to the output

through a resistor divider for adjustable outpu t voltage. For

0.8V output voltage, connect this pin to the output.

No connect.

Exposed Pad

The exposed pad must be connected to the SGND pin for

proper electrical performance. Place as much vias as

possible under the pad connecting to SGND plane for

optimal thermal performance.

ISL8013

7FN6309.1

December 27, 2007

ISL8013

Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 2.5V to 5.5V, EN = VIN,

SYNCH = 0V, L = 1.5µH, C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 3A).

FIGURE 3. EFFICIENCY vs LOAD (1MHz 3.3 VIN PWM) FIGURE 4. EFFICIENCY vs LOAD (1MHz 3.3 VIN PFM)

FIGURE 5. EFFICIENCY vs LOAD (

1MHz 5V

PWM)

FIGURE 6. EFFICIENCY vs LOAD (

1MHz 5V

PFM

)

FIGURE 7. POWER DISSIPATION vs LOAD (1MHz, VOUT = 1.8V) FIGURE 8. POWER DISSIPATION WITH NO LOAD vs VIN

(PWM VOUT = 1.8V)

100

OUTPUT LOAD (A)

EFFICIENCY (%)

2.5VOUT-PWM 1.8VOUT-PWM 1.5VOUT-PWM

1.2VOUT-PWM

0.0 0.5 1.0 1.5 2.0 2.5 3.0 40

100

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

OUTPUT LOAD (A)

EFFICIENCY (%)

2.5VOUT-PFM 1.8VOUT-PFM 1.5VOUT-PFM 1.2VOUT-PFM

0.0 0.5 1.0 1.5 2.0 2.5 3.0

100

OUTPUT LOAD (A)

EFFICIENCY (%)

2.5VOUT-PWM 1.8VOUT-PWM 1.5VOUT-PWM

1.2VOUT-PWM

3.3VOUT-PWM

100

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

OUTPUT LOAD (A)

EFFICIENCY (%)

2.5VOUT-PFM 1.8VOUT-PFM 1.5VOUT-PFM

1.2VOUT-PFM

3.3VOUT-PFM

0.0 0.5 1.0 1.5 2.0 2.5 3.0

0.00

0.25

0.50

0.75

1.00

1.25

1.50

1.75

2.00

OUTPUT LOAD (A)

POWER DISSIPATION (W)

5VIN-PWM

3.3V

IN-PFM

3.3VIN-PWM

5VIN-PFM

100

125

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

(V)

POWER DISSIPATION (mW)

8FN6309.1

December 27, 2007

FIGURE 9. POWER DISSIP ATION WITH NO LOAD vs VIN

(PFM VOUT = 1.8V) FIGURE 10. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.2V)

FIGURE 11. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.5V) FIGURE 12. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.8V)

FIGURE 13. VOUT REGULATION vs LOAD (1MHz, VOUT = 2.5V) FIGURE 14. VOUT REGULATION vs LOAD (1MHz, VOUT = 3.3V)

Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 2.5V to 5.5V, EN = VIN,

SYNCH = 0V, L = 1.5µH, C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 3A). (Conti nued)

0.05

0.10

0.15

0.20

0.25

POWER DISSIPATION (mW)

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

(V)

0.0 0.5 1.0 1.5 2.0 2.5 3.0

1.16

1.17

1.18

1.19

1.20

1.21

1.22

1.23

1.24

OUTPUT LOAD (A)

OUTPUT VOLTAGE (V)

5VIN-PWM

5VIN-PFM

3.3VIN-PFM

3.3VIN-PWM

0.0 0.5 1.0 1.5 2.0 2.5 3.0

1.47

1.48

1.49

1.50

1.51

1.52

1.53

1.54

1.55

OUTPUT LOAD (A)

OUTPUT VOLTAGE (V)

5VIN-PWM

5VIN-PFM

3.3VIN-PFM

3.3VIN-PWM

0.0 0.5 1.0 1.5 2.0 2.5 3.0

1.75

1.76

1.77

1.78

1.79

1.80

1.81

1.82

1.83

OUTPUT LOAD (A)

OUTPUT VOLTAGE (V)

5VIN-PWM

5VIN-PFM 3.3VIN-PWM

3.3VIN-PFM

0.0 0.5 1.0 1.5 2.0 2.5 3.

2.44

2.45

2.46

2.47

2.48

2.49

2.50

2.51

2.52

OUTPUT LOAD (A)

OUTPUT VOLTAGE (V)

5VIN-PWM

5VIN-PFM

3.3VIN-PWM

3.3VIN-PFM

0.0 0.5 1.0 1.5 2.0 2.5 3.0

3.28

3.29

3.30

3.31

3.32

3.33

3.34

3.35

3.36

OUTPUT LOAD (A)

OUTPUT VOLTAGE (V)

5VIN-PWM

5VIN-PFM

4.5VIN-PWM

4.5VIN-PFM

ISL8013

9FN6309.1

December 27, 2007

FIGURE 15. OUTPUT VOLTAGE REGULATION vs VIN

(PWM VOUT = 1.8 ) FIGURE 16. OUTPUT VOLTAGE REGULATION vs VIN

(PFM VOUT = 1.8V)

FIGURE 17. STEADY STATE OPERATION AT NO LOAD (PWM) FIGURE 18. STEADY STATE OPERATION AT NO LOAD (PFM)

FIGURE 19. STEADY STATE OPERATION WITH FULL LOAD FIGURE 20. MODE TRANSITION CCM TO DCM

Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 2.5V to 5.5V, EN = VIN,

SYNCH = 0V, L = 1.5µH, C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 3A). (Conti nued)

1.750

1.760

1.770

1.780

1.790

1.800

1.810

1.820

1.830

OUTPUT VOLTAGE (V)

2.02.53.03.54.04.55.05.5

INPUT VOLTAGE (V)

3A LOAD PWM 0A LOAD PWM

1.750

1.760

1.770

1.780

1.790

1.800

1.810

1.820

1.830

OUTPUT VOLTAGE (V)

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

INPUT VOLTAGE (V)

3A LOAD 0A LOAD

LX 2V/DIV

VOUT RIPPLE 20mV/DIV

IL 0.5A/DIV

LX 2V/DIV

VOUT RIPPLE 20mV/DIV

IL 0.5A/DIV

LX 2V/DIV

VOUT RIPPLE 20mV/DIV

IL 1A/DIV

LX 2V/DIV

VOUT RIPPLE 50mV/DIV

IL 1A/DIV

ISL8013

10 FN6309.1

December 27, 2007

FIGURE 21. MODE TRANSITION DCM TO CCM FIGURE 22. LOAD TRANSIENT (PWM)

FIGURE 23. LOAD TRANSIENT (PFM) FIGURE 24. SOFT-START WITH NO LOAD (PWM)

FIGURE 25. SOFT-START AT NO LOAD (PFM) FIGURE 26. SOFT-START WITH PRE-BIASED 1V

Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 2.5V to 5.5V, EN = VIN,

SYNCH = 0V, L = 1.5µH, C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 3A). (Conti nued)

LX 2V/DIV

VOUT RIPPLE 50mV/DIV

IL 1A/DIV

VOUT RIPPLE 50mV/DIV

IL 1A/DIV

LX 2V/DIV

VOUT RIPPLE 50mV/DIV

IL 1A/DIV

EN 5V/DIV

VOUT 0.5V/DIV

IL 1A/DIV

PG 5V/DIV

EN 5V/DIV

VOUT 0.5V/DIV

IL 1A/DIV

PG 5V/DIV

EN 5V/DIV

VOUT 0.5V/DIV

IL 5A/DIV

PG 5V/DIV

ISL8013

11 FN6309.1

December 27, 2007

FIGURE 27. SOFT-START AT FULL LOAD FIGURE 28. SOFT-DISCHARGE SHUTDOWN

FIGURE 29. STEADY STATE OPERATION AT NO LOAD WITH

FREQUENCY = 2MHz FIGURE 30. STEADY STATE OPERATION AT FULL LOAD

WITH FREQUENCY = 2MHz

FIGURE 31. STEADY STATE OPERATION AT NO LOAD WITH

FREQUENCY = 4MHz

FIGURE 32. STEADY STATE OPERATION AT FULL LOAD

(PWM) WITH FREQUENCY = 4MHz

Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 2.5V to 5.5V, EN = VIN,

SYNCH = 0V, L = 1.5µH, C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 3A). (Conti nued)

VOUT 0.5V/DIV

IL 1A/DIV

EN 5V/DIV

PG 5V/DIV

VOUT 0.5V/DIV

IL 1A/DIV

EN 5V/DIV

PG 5V/DIV

LX 2V/DIV

SYNCH 2V/DIV

VOUT RIPPLE 20mV/DIV

IL 1A/DIV

LX 2V/DIV

SYNCH 2V/DIV

VOUT RIPPLE 20mV/DIV

IL 1A/DIV

LX 2V/DIV

SYNCH 2V/DIV

VOUT RIPPLE 20mV/DIV

IL 1A/DIV

LX 2V/DIV

SYNCH 2V/DIV

VOUT RIPPLE 20mV/DIV

IL 1A/DIV

ISL8013

12 FN6309.1

December 27, 2007

Theory of Operation

The ISL8013 is a step-down switching regulator optimized for

battery-powered handheld applications. The regulator operates

at 1MHz fixed switching frequency under heavy load conditions

to allow smaller external inductors and capacitors to be used for

minimal printed-circuit board (PCB) area. At light load, the

regulator reduces the switching frequency, unless forced to the

fixed frequency , to minimize the switching loss and to maximize

the battery life. The quiescent current when the output is not

loaded is typically only 35µA. The supply current is typically

only 0.1µA when the regulator is shut down.

PWM Control Scheme

Pulling the SYNCH pin HI (>2.5V) forces the converter into

PWM mode, regardless of output current. The ISL8013

employs the current-mode pulse-width modulation (PWM)

control scheme for fast transient response and pulse-by-pulse

current limiting. Figure 2 shows the block diagram. The current

loop consists of the oscillator , the PWM comparator, current

sensing circuit and the slope compensation for the current loop

stability. The gain for the current sensing circuit is typically

250mV/A. The control reference for the current loops comes

from the error amplifier's (EAMP) output.

The PWM operation is initialized by the clock from the

oscillator. The P-Channel MOSFET is turned on at the

beginning of a PWM cycle and the cu rrent in the MOSFET

start s to ramp up. When the sum of the current ampli fier CSA

and the slope compensation (237 mV/µs) reaches the control

reference of the current loop, the PWM co mp arator C OMP

sends a signal to the PWM logic to turn off the P-MOSFET

and turn on the N-Chan nel MOSFET. The N-MOSFET stays

on until the end of the PWM cycle. Figure 36 shows the typical

operating waveforms during the PWM ope rati on. The dotted

lines illustrate th e sum of the slope compensati on ramp and

the current-sense amplifier’s CSA output.

The output voltage is regulated by controlling the VEAMP

voltage to the current loop. The bandgap circuit outputs a

0.8V reference voltage to the voltage loop. The feedback

signal comes from the VFB pin. The soft-start block only

affects the operation during the start-up and will be

discussed separately. The error amplifier is a

transconductance amplifier that converts the voltage error

FIGURE 33. OUTPUT SHORT CIRCUIT FIGURE 34. OUTPUT SHORT CIRCUIT RECOVERY

FIGURE 35. OUTPUT CURRENT LIMIT vs TEMPERATURE

Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 2.5V to 5.5V, EN = VIN,

SYNCH = 0V, L = 1.5µH, C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 3A). (Conti nued)

PHASE 2V/DIV

VOUT 0.5V/DIV

IL 2A/DIV

PG 5V/DIV

LX 2V/DIV

VOUT 1V/DIV

IL 2A/DIV

PG 5V/DIV

4.000

4.125

4.250

4.375

4.500

4.625

4.750

4.875

5.000

-50-250 255075100

TEMPERATURE (°C)

OUTPUT CURRENT (A)

OCP_3.3VIN

OCP_5VIN

ISL8013

13 FN6309.1

December 27, 2007

signal to a current output. The voltage loop is internally

compensated with the 27pF and 39 0kΩ RC network. The

maximum EAMP voltage output is precisely clamped to 1.6V.

SKIP Mode

Pulling the SYNCH pin LO (<0.4V) forces the converter into

PFM mode. The ISL8013 enters a pulse-skippi ng mode at

light load to minimize the switching loss by reducing the

switching frequency. Figure 37 illustrates the skip-mode

operation. A zero-cross sensing circuit shown in Figure 2

monitors the N-MOSFET current for zero crossing. When 8

consecutive cycles of the inductor current crossing zero are

detected, the regulator enters the skip mode. During the

eight detecting cycles, the current in the inductor is allowed

to become negative. The counter is reset to zero when the

current in any cycle does not cross zero.

Once the skip mode is entered, the pulse modulation starts

being controlled by the SKIP comparator shown in Figure 2.

Each pulse cycle is still synchronized by the PWM clock. The

P-MOSFET is turned on at the clock's rising edge and turned

off when the output is higher than 1.5% of the nominal

regulation or when its current reaches the peak Skip current

limit value. Then the inductor current is discharging to zero

Ampere and stays at zero. The internal clock is disabled.The

output voltage reduces gradually due to the load current

discharging the output capacitor. When the output voltage

drops to the nominal voltage, the P-MOSFET will be turned

on again at the rising edge of the internal clock as it repeats

the previous operations.

The regulator resumes normal PWM mode operation when

the output voltage drops 1.5% below the nominal voltage.

Synchronization Control

The frequency of operation can be synchronized up to 4MHz by

an external signal applied to the SYNCH pin. The falling edge

on the SYNCH triggers the rising edge of the LX pulse. Make

sure that the minimum on time of the LX node is greater than

140ns.

Overcurrent Protection

The overcurrent protection is realized by monitoring the CSA

output with the OCP comparator, as shown in Figure 2. The

current sensing circuit has a gain of 250mV/A, from th e

P-MOSFET current to the CSA output. When the CSA output

reaches 1.4V, which is equivalent to 4.8A for the switch

current, the OCP comp arator is tripped to turn of f the

P-MOSFET immediately. The overcurrent function protects

the switching converter from a shorted output by monitoring

the current flowing throu gh the upp er MOSFET.

Upon detection of overcurrent condition, the upper MOSFET

will be immediately turned off and will not be turned on again

until the next switching cycle. Upon detection of the initial

overcurrent condition, the overcurrent fault counter is set to

1. If, on the subsequent cycle, another overcurrent condition

is detected, the OC fault counter will be incremented. If there

are 17 sequential OC fault detections, the regulator will be

shut down under an overcurrent fault condition. An

overcurrent fault condition will result in the regulator

attempting to restart in a hiccup mode within the delay of four

soft-start periods. At the end of the fourth soft-start wait

period, the fa ul t co un ters are reset and soft-start is

attempted again. If the overcurrent condition goes away

during the delay of four soft-start periods, the output will

resume back into regulation point after hiccup mode expires.

Short-Circuit Protect ion

The short-circuit protection SCP comparator monitors the

VFB pin voltage for output short-circuit protection. When the

VFB is lower than 0.2V, the SCP comparator forces the

PWM oscillator frequency to drop to 1/3 of the normal

operation value. This comparator is effective during start-up

or an output short-circuit event.

FIGURE 36. PWM OPERATION WAVEFORMS

VEAMP

VCSA

DUTY

CYCLE

VOUT

FIGURE 37. SKIP MODE OPERATION WAVEFORMS

CLOCK

VOUT

NOMINAL +1.5%

NOMINAL

CURRENT LIMIT

LOAD CURRENT

8 CYCLES

ISL8013

14 FN6309.1

December 27, 2007

During power-up, the open-drain power good output holds low

for about 1ms after VOUT reaches the regulation voltage. The

PG output also serves as a 1ms delayed the Power Good

signal when the pull-up resistor R1 is installed.

UVLO

When the input voltage is below the undervoltage lock-out

(UVLO) threshold, the regulator is disabled.

Soft Start-Up

The soft-start-up reduces the inrush current during the start-

up. The soft-start block outputs a ramp reference to the input

of the error amplifier. This voltage ramp limits the inductor

current as well as the output voltage speed so that the output

voltage rises in a controlled fashion. When VFB is less than

0.2V at the beginning of the soft-start, the switching

frequency is reduced to 1/3 of the nominal value so that the

output can start up smoothly at light load condition. During

soft-st art, the IC operates in the SKIP mode to support

pre-biased output condition .

Enable

The enable (EN) input allows the user to control the turning

on or off the regulator for purposes such as power-up

sequencing. When the regulator is enabled, there is typically

a 600µs delay for waking up the bandgap reference and then

the soft-start-up begins.

Discharge Mode (Soft-Stop)

When a transition to shutdown mode occurs or the VIN

UVLO is set, the outputs discharge to GND through an

internal 100Ω switch.

Power MOSFETs

The power MOSFETs are optimized for best efficiency. The

ON-resistance for the P-MOSFET is typically 50mΩ and the

ON-resistance for the N-MOSFET is typically 50mΩ.

100% Duty Cycle

The ISL8013 features 100% duty cycle operation to

maximize the battery life. When the battery voltage drops to

a level that the ISL8013 can no longer maintain the

regulation at the output, the regulator completely turns on

the P-MOSFET. The maximum dropout voltage under the

100% duty-cycle operation is the product of the load current

and the ON-resistance of the P-MOSFET.

Thermal Shut-Down

The ISL8013 has built-in thermal protection. When the internal

temperature reaches +140°C, the regulator is completely shut

down. As the temperature drops to +115°C, the ISL8013

resumes operation by stepping through the soft-start.

Applications Information

Output Inductor and Capacitor Selection

To consider steady state and transient operations, ISL8013

typically uses a 1.5µH output inductor. The higher or lower

inductor value can be used to optimize the total converter

system performance. For example, for higher output voltage

3.3V application, in order to decrease the inductor current

ripple and output voltage ripple, the output inductor value

can be increased. It is recommended to set the ri pple

inductor current approximately 30% of the maximum output

current for optimized performance. The inductor ripple

current can be expressed as shown in Equation 1:

The inductor’s saturation current rating needs to be at least

larger than the peak current. The ISL8013 protects the

typical peak current 4.8A. The saturation current needs be

over 5.5A for maximum output current application.

ISL8013 uses internal compensation network and the output

capacitor value is dependent on the output voltage. The

ceramic capacitor is recommended to be X5R or X7R. The

recommended X5R or X7R minimum output capacitor

values are shown in Table 1.

In Table 1, the minimum output capacitor value is given for

the different output voltage to make sure that the whole

converter system is stable.

TABLE 1. OUTPUT CAPACITOR VALUE vs VOUT

VOUT COUT L

0.8V 2 x 22µF 1.0µH~2.2µH

1.2V 2 x 22µF 1.0µH~2.2µH

1.5V 2 x 22µF 1.5µH~3.3µH

1.8V 2 x 22µF 1.5µH~3.3µH

2.5V 2 x 22µF 1.5µH~3.3µH

3.3V 2 x 22µF 2.2µH~4.7µH

3.6V 2 x 22µF 2.2µH~4.7µH

ΔI

VO1VO

VIN

---------

–

⎝⎠

⎜⎟

⎛⎞

•

---------------------------------------

(EQ. 1)

ISL8013

15 FN6309.1

December 27, 2007

Output Voltage Selection

The output voltage of the regulator can be programmed via an

external resistor divider that is used to scale the output voltage

relative to the internal reference voltage and feed it back to the

inverting input of the error amplifier. Refer to Figure 1.

The output voltage programming resistor, R3, will depend on

the value chosen for the feedback resistor and the desired

output voltage of the regulator. The value for the feedback

resistor is typically between 10kΩ and 100kΩ, as shown in

Equation 2.

If the output voltage desired is 0.8V, then R3 is left

unpopulated and R2 is shorted. Ther e is a leakage current

from VIN to LX. It is recommended to preload the output with

10µA minimum. For better performance, add 47pF in parallel

with R2 (100kΩ).

Input Capacitor Selection

The main functions for the input capacitor are to provide

decoupling of the parasitic inductance and to provide filtering

function to prevent the switching current flowing back to the

battery rail. Two 22µF X5R or X7R ceramic capacitors are a

good starting point for the input capacitor selection.

R3R20.8V×

VOUT 0.8V–

----------------------------------=(EQ. 2)

ISL8013

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6309.1

December 27, 2007

ISL8013

Quad Flat No-Lead Plastic Package (QFN)

Micro Lead Frame Plastic Package (MLFP)

L16.4x4

16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

(COMPLIANT TO JEDEC MO-220-VGGC ISSUE C)

SYMBOL

MILLIMETERS

NOTESMIN NOMINAL MAX

A 0.80 0.90 1.00 -

A1 - - 0.05 -

A2 - - 1.00 9

A3 0.20 REF 9

b 0.23 0.28 0.35 5, 8

D 4.00 BSC -

D1 3.75 BSC 9

D2 1.95 2.10 2.25 7, 8

E 4.00 BSC -

E1 3.75 BSC 9

E2 1.95 2.10 2.25 7, 8

e 0.65 BSC -

k0.25 - - -

L 0.50 0.60 0.75 8

L1 - - 0.15 10

N162

Nd 4 3

Ne 4 3

P- -0.609

θ--129

Rev. 5 5/04

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land Pattern

Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when

Anvil singulation method is used and not present for saw

singulation.

10. Depending on the method of lead termination at the edge of the

package, a maximum 0.15mm pull back (L1) maybe present. L

minus L1 to be equal to or greater than 0.3mm.