Dual-Channel Digital Isolators, 5 kV
Data Sheet ADuM2200/ADuM2201
Rev. C
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FEATURES
High isolation voltage: 5000 V rms
Enhanced system-level ESD performance per IEC 61000-4-x
Low power operation
5 V operation
1.6 mA per channel maximum @ 0 Mbps to 2 Mbps
3.7 mA per channel maximum @ 10 Mbps
3 V operation
1.4 mA per channel maximum @ 0 Mbps to 2 Mbps
2.4 mA per channel maximum @ 10 Mbps
Bidirectional communication
3 V/5 V level translation
High temperature operation: 105°C
High data rate: dc to 10 Mbps (NRZ)
Precise timing characteristics
3 ns maximum pulse width distortion
3 ns maximum channel-to-channel matching
High common-mode transient immunity: >25 kV/μs
16-lead SOIC wide body package version (RW-16)
16-lead SOIC wide body enhanced creepage version (RI-16)
Safety and regulatory approvals (RI-16 package)
UL recognition: 5000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
IEC 60601-1: 250 V rms (reinforced)
IEC 60950-1: 400 V rms (reinforced)
VDE Certificate of Conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 846 V peak
APPLICATIONS
General-purpose, high voltage, multichannel isolation
Medical equipment
Power supplies
RS-232/RS-422/RS-485 transceiver isolation
GENERAL DESCRIPTION
The ADuM220x1 are 2-channel digital isolators based on Analog
Devices, Inc., iCoupler® technology. Combining high speed CMOS
and monolithic air core transformer technology, these isolation
components provide outstanding performance characteristics
that are superior to alternatives such as optocoupler devices.
By avoiding the use of LEDs and photodiodes, iCoupler devices
remove the design difficulties commonly associated with opto-
couplers. Typical optocoupler concerns regarding uncertain
current transfer ratios, nonlinear transfer functions, and temper-
ature and lifetime effects are eliminated with the simple iCoupler
FUNCTIONAL BLOCK DIAGRAMS
1
2
3
4
5
6
7
8
GND
1
NC
V
DD1
V
IA
V
IB
NC
GND
1
NC
GND
2
NC
V
DD2
V
OA
V
OB
NC
NC
GND
2
NC = NO CONNECT
ADuM2200
16
15
14
13
12
11
10
9
ENCODE
ENCODE
DECODE
DECODE
PIN 1
INDICATOR
07235-001
Figure 1. ADuM2200
1
2
3
4
5
6
7
8
GND
1
NC
V
DD1
V
OA
V
IB
NC
GND
1
NC
GND
2
NC
V
DD2
V
IA
V
OB
NC
NC
GND
2
NC = NO CONNECT
ADuM2201
16
15
14
13
12
11
10
9
DECODE
ENCODE
ENCODE
DECODE
PIN 1
INDICATOR
07235-002
Figure 2. ADuM2201
digital interfaces and stable performance characteristics. The
need for external drivers and other discrete components is elimi-
nated with these iCoupler products. Furthermore, iCoupler
devices run at one-tenth to one-sixth the power of optocouplers
at comparable signal data rates.
The ADuM220x isolators provide two independent isolation
channels in a variety of channel configurations and data rates
(see the Ordering Guide). The ADuM220x models operate with
the supply voltage of either side ranging from 3.0 V to 5.5 V,
providing compatibility with lower voltage systems as well as
enabling voltage translation functionality across the isolation
barrier. The ADuM220x isolators have a patented refresh feature
that ensures dc correctness in the absence of input logic transi-
tions and during power-up/power-down conditions.
Similar to the ADuM320x isolators, the ADuM220x isolators
contain various circuit and layout enhancements to provide
increased capability relative to system-level IEC 61000-4-x
testing (ESD, burst, and surge). The precise capability in these
tests for either the ADuM320x or ADuM220x products is strongly
determined by the design and layout of the user’s board or
module. For more information, see the AN-793 Application Note,
ESD/Latch-Up Considerations with iCoupler Isolation Products.
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents pending.
ADuM2200/ADuM2201 Data Sheet
Rev. C | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—5 V Operation................................ 3
Electrical Characteristics—3 V Operation................................ 5
Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V
Operation....................................................................................... 7
Package Characteristics ............................................................. 10
Regulatory Information............................................................. 10
Insulation and Safety-Related Specifications.......................... 10
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics ............................................................................ 11
Recommended Operating Conditions .................................... 11
Absolute Maximum Ratings ......................................................... 12
ESD Caution................................................................................ 12
Pin Configurations and Function Descriptions......................... 13
Typical Performance Characteristics ........................................... 15
Applications Information.............................................................. 16
PCB Layout ................................................................................. 16
Propagation Delay-Related Parameters................................... 16
DC Correctness and Magnetic Field Immunity..................... 16
Power Consumption .................................................................. 17
Insulation Lifetime..................................................................... 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 19
REVISION HISTORY
3/12—Rev. B to Rev. C
Created Hyperlink for Safety and Regulatory Approvals
Entry in Features Section................................................................. 1
Change to PCB Layout Section..................................................... 16
8/11—Rev. A to Rev. B
Added 16-Lead SOIC_IC Package ...................................Universal
Changes to Features Section............................................................ 1
Changes to Table 5 and Table 6..................................................... 10
Changes to Endnote 1, Table 8...................................................... 11
Updated Outline Dimensions....................................................... 19
Changes to Ordering Guide .......................................................... 19
7/08—Rev. 0 to Rev. A
Changes to Features Section and General Description
Section................................................................................................ 1
Changes to Table 5.......................................................................... 10
1/08—Revision 0: Initial Version
Data Sheet ADuM2200/ADuM2201
Rev. C | Page 3 of 20
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION1
4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current, per Channel, Quiescent IDDI (Q) 0.4 0.8 mA
Output Supply Current, per Channel, Quiescent IDDO (Q) 0.5 0.6 mA
ADuM2200, Total Supply Current, Two Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.3 1.7 mA DC to 1 MHz logic signal
frequency
VDD2 Supply Current IDD2 (Q) 1.0 1.6 mA DC to 1 MHz logic signal
frequency
10 Mbps (BR Grade Only)
VDD1 Supply Current IDD1 (10) 3.5 4.6 mA 5 MHz logic signal frequency
VDD2 Supply Current IDD2 (10) 1.7 2.8 mA 5 MHz logic signal frequency
ADuM2201, Total Supply Current, Two Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.1 1.5 mA DC to 1 MHz logic signal
frequency
VDD2 Supply Current IDD2 (Q) 1.3 1.8 mA DC to 1 MHz logic signal
frequency
10 Mbps (BR Grade Only)
VDD1 Supply Current IDD1 (10) 2.6 3.4 mA 5 MHz logic signal frequency
VDD2 Supply Current IDD2 (10) 3.1 4.0 mA 5 MHz logic signal frequency
For All Models
Input Currents IIA, IIB −10 +0.01 +10 μA 0 V ≤ VIA, VIB ≤ VDD1 or VDD2
Logic High Input Threshold VIH 0.7 (VDD1
or VDD2)
V
Logic Low Input Threshold VIL
0.3 (VDD1
or VDD2)
V
Logic High Output Voltages VOAH (VDD1 or
VDD2) −
0.1
5.0 V IOx = −20 μA, VIx = VIxH
V
OBH (VDD1 or
VDD2) −
0.5
4.8 V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages VOAL 0.0 0.1 V IOx = 20 μA, VIx = VIxL
V
OBL 0.04 0.1 V IOx = 400 μA, VIx = VIxL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM220xAR
Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t
PHL, tPLH 20 150 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 40 ns CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 t
PSK 100 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching7 t
PSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) tR/tF 10 ns CL = 15 pF, CMOS signal levels
ADuM2200/ADuM2201 Data Sheet
Rev. C | Page 4 of 20
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM220xBR
Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t
PHL, tPLH 20 50 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 3 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 t
PSK 15 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels7
tPSKCD 3 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing Directional Channels7
tPSKOD 15 ns CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels
For All Models
Common-Mode Transient Immunity
at Logic High Output8
|CMH| 25 35 kV/μs
VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity
at Logic Low Output8
|CML| 25 35 kV/μs
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate fr 1.2 Mbps
Input Dynamic Supply Current, per Channel9 I
DDI (D) 0.19 mA/Mbps
Output Dynamic Supply Current, per Channel9 I
DDO (D) 0.05 mA/Mbps
1 All voltages are relative to their respective ground.
2 The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See
Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11
for total IDD1 and IDD2 supply currents as a function of data rate for ADuM2200 and ADuM2201 channel configurations.
3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for
information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply
current for a given data rate.
Data Sheet ADuM2200/ADuM2201
Rev. C | Page 5 of 20
ELECTRICAL CHARACTERISTICS—3 V OPERATION1
3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V. All minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V.
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current, per Channel, Quiescent IDDI (Q) 0.3 0.5 mA
Output Supply Current, per Channel, Quiescent IDDO (Q) 0.3 0.5 mA
ADuM2200, Total Supply Current, Two Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 0.8 1.3 mA DC to 1 MHz logic signal
frequency
VDD2 Supply Current IDD2 (Q) 0.7 1.0 mA DC to 1 MHz logic signal
frequency
10 Mbps (BR Grade Only)
VDD1 Supply Current IDD1 (10) 2.0 3.2 mA 5 MHz logic signal frequency
VDD2 Supply Current IDD2 (10) 1.1 1.7 mA 5 MHz logic signal frequency
ADuM2201, Total Supply Current, Two Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 0.7 1.3 mA DC to 1 MHz logic signal
frequency
VDD2 Supply Current IDD2 (Q) 0.8 1.6 mA DC to 1 MHz logic signal
frequency
10 Mbps (BR Grade Only)
VDD1 Supply Current IDD1 (10) 1.5 2.1 mA 5 MHz logic signal frequency
VDD2 Supply Current IDD2 (10) 1.9 2.4 mA 5 MHz logic signal frequency
For All Models
Input Currents IIA, IIB −10 +0.01 +10 μA 0 V ≤ VIA, VIB ≤ VDD1 or VDD2
Logic High Input Threshold VIH 0.7 (VDD1
or VDD2)
V
Logic Low Input Threshold VIL 0.3 (VDD1
or VDD2)
V
Logic High Output Voltages VOAH (VDD1 or
VDD2) −
0.1
3.0 V IOx = −20 μA, VIx = VIxH
V
OBH (VDD1 or
VDD2) −
0.5
2.8 V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages VOAL 0.0 0.1 V IOx = 20 μA, VIx = VIxL
V
OBL 0.04 0.1 V IOx = 400 μA, VIx = VIxL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM220xAR
Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t
PHL, tPLH 20 150 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 40 ns CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 t
PSK 100 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching7 t
PSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) tR/tF 10 ns CL = 15 pF, CMOS signal levels
ADuM2200/ADuM2201 Data Sheet
Rev. C | Page 6 of 20
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM220xBR
Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t
PHL, tPLH 20 60 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH −tPHL|5 PWD 3 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 t
PSK 22 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels7
tPSKCD 3 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing Directional Channels7
tPSKOD 22 ns CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) tR/tF 3.0 ns CL = 15 pF, CMOS signal levels
For All Models
Common-Mode Transient Immunity
at Logic High Output8
|CMH| 25 35 kV/μs VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity
at Logic Low Output8
|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate fr 1.1 Mbps
Input Dynamic Supply Current, per Channel9 I
DDI (D) 0.10 mA/Mbps
Output Dynamic Supply Current, per
Channel9
IDDO (D) 0.03 mA/Mbps
1 All voltages are relative to their respective ground.
2 The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See
Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11
for total IDD1 and IDD2 supply currents as a function of data rate for ADuM2200 and ADuM2201 channel configurations.
3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for
information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply
current for a given data rate.
Data Sheet ADuM2200/ADuM2201
Rev. C | Page 7 of 20
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION1
5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VDD2 ≤ 3.6 V. 3 V/5 V operation: 3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All minimum/
maximum specifications apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at
TA = 25°C; VDD1 = 3.0 V, VDD2 = 5 V; or VDD1 = 5 V, VDD2 = 3.0 V.
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current, per Channel, Quiescent IDDI (Q)
5 V/3 V Operation 0.4 0.8 mA
3 V/5 V Operation 0.3 0.5 mA
Output Supply Current, per Channel, Quiescent IDDO (Q)
5 V/3 V Operation 0.3 0.5 mA
3 V/5 V Operation 0.5 0.6 mA
ADuM2200, Total Supply Current, Two Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q)
5 V/3 V Operation 1.3 1.7 mA DC to 1 MHz logic signal
frequency
3 V/5 V Operation 0.8 1.3 mA DC to 1 MHz logic signal
frequency
VDD2 Supply Current IDD2 (Q)
5 V/3 V Operation 0.7 1.0 mA DC to 1 MHz logic signal
frequency
3 V/5 V Operation 1.0 1.6 mA DC to 1 MHz logic signal
frequency
10 Mbps (BR Grade Only)
VDD1 Supply Current IDD1 (10)
5 V/3 V Operation 3.5 4.6 mA 5 MHz logic signal frequency
3 V/5 V Operation 2.0 3.2 mA 5 MHz logic signal frequency
VDD2 Supply Current IDD2 (10)
5 V/3 V Operation 1.1 1.7 mA 5 MHz logic signal frequency
3 V/5 V Operation 1.7 2.8 mA 5 MHz logic signal frequency
ADuM2201, Total Supply Current, Two Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q)
5 V/3 V Operation 1.1 1.5 mA DC to 1 MHz logic signal
frequency
3 V/5 V Operation 0.7 1.3 mA DC to 1 MHz logic signal
frequency
VDD2 Supply Current IDD2 (Q)
5 V/3 V Operation 0.8 1.6 mA DC to 1 MHz logic signal
frequency
3 V/5 V Operation 1.3 1.8 mA DC to 1 MHz logic signal
frequency
10 Mbps (BR Grade Only)
VDD1 Supply Current IDD1 (10)
5 V/3 V Operation 2.6 3.4 mA 5 MHz logic signal frequency
3 V/5 V Operation 1.5 2.1 mA 5 MHz logic signal frequency
VDD2 Supply Current IDD2 (10)
5 V/3 V Operation 1.9 2.4 mA 5 MHz logic signal frequency
3 V/5 V Operation 3.1 4.0 mA 5 MHz logic signal frequency
ADuM2200/ADuM2201 Data Sheet
Rev. C | Page 8 of 20
Parameter Symbol Min Typ Max Unit Test Conditions
For All Models
Input Currents IIA, IIB −10 +0.01 +10 μA 0 V ≤ VIA, VIB ≤ VDD1 or VDD2
Logic High Input Threshold VIH 0.7 (VDD1
or VDD2)
V
Logic Low Input Threshold VIL 0.3
(VDD1
or VDD2)
V
Logic High Output Voltages VOAH, VOBH (VDD1 or
VDD2) − 0.1
(VDD1 or
VDD2)
V IOx = −20 μA, VIx = VIxH
(VDD1 or
VDD2) − 0.5
(VDD1 or
VDD2) −
0.2
V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages VOAL, VOBL 0.0 0.1 V IOx = 20 μA, VIx = VIxL
0.04 0.1 V IOx = 400 μA, VIx = VIxL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM220xAR
Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t
PHL, tPLH 15 150 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 40 ns CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 t
PSK 50 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching7 t
PSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) tR/tF 10 ns CL = 15 pF, CMOS signal levels
ADuM220xBR
Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t
PHL, tPLH 15 55 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 3 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 t
PSK 22 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels7
tPSKCD 3 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing Directional Channels7
tPSKOD 22 ns CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) tR/tF
5 V/3 V Operation 3.0 ns CL = 15 pF, CMOS signal levels
3 V/5 V Operation 2.5 ns CL = 15 pF, CMOS signal levels
5 V/3 V Operation 3.0 ns CL = 15 pF, CMOS signal levels
3 V/5 V Operation 2.5 ns CL = 15 pF, CMOS signal levels
For All Models
Common-Mode Transient Immunity
at Logic High Output8
|CMH| 25 35 kV/μs VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity
at Logic Low Output8
|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate fr
5 V/3 V Operation 1.2 Mbps
3 V/5 V Operation 1.1 Mbps
Input Dynamic Supply Current,
per Channel9
IDDI (D)
5 V/3 V Operation 0.19 mA/Mbps
3 V/5 V Operation 0.10 mA/Mbps
Data Sheet ADuM2200/ADuM2201
Rev. C | Page 9 of 20
Parameter Symbol Min Typ Max Unit Test Conditions
Output Dynamic Supply Current,
per Channel9
IDDO (D)
5 V/3 V Operation 0.03 mA/Mbps
3 V/5 V Operation 0.05 mA/Mbps
1 All voltages are relative to their respective ground.
2 The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See
Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11
for total IDD1 and IDD2 supply currents as a function of data rate for ADuM2200 and ADuM2201 channel configurations.
3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for
information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply
current for a given data rate.
ADuM2200/ADuM2201 Data Sheet
Rev. C | Page 10 of 20
PACKAGE CHARACTERISTICS
Table 4.
Parameter Symbol Min Typ Max Unit Test Conditions
Resistance (Input-to-Output)1 R
I-O 1012 Ω
Capacitance (Input-to-Output)1 CI-O 2.2 pF f = 1 MHz
Input Capacitance2 C
I 4.0 pF
IC Junction-to-Case Thermal Resistance, Side 1 θJCI 33 °C/W
IC Junction-to-Case Thermal Resistance, Side 2 θJCO 28 °C/W
Thermocouple located at
center of package underside
1 Device considered a 2-terminal device: Pin 1 through Pin 8 are shorted together and Pin 9 through Pin 16 are shorted together.
2 Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM220x are approved by the organizations listed in Ta bl e 5. Refer to Table 10 and the Insulation Lifetime section for details
regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.
Table 5.
UL CSA VDE
Recognized under 1577 Component
Recognition Program1
Approved under CSA Component
Acceptance Notice #5A
Certified according to DIN V VDE V 0884-10 (VDE V
0884-10): 2006-122
Single Protection
5000 V rms Isolation Voltage
Basic insulation per CSA 60950-1-07 and IEC
60950-1, 600 V rms (848 V peak) maximum
working voltage
Reinforced insulation, 846 V peak
RW-16 package:
Reinforced insulation per CSA 60950-1-07
and IEC 60950-1, 380 V rms (537 V peak)
maximum working voltage; reinforced
insulation per IEC 60601-1 125 V rms
(176 V peak) maximum working voltage
RI-16 package:
Reinforced insulation per CSA 60950-1-07
and IEC 60950-1, 400 V rms (565 V peak)
maximum working voltage; reinforced
insulation per IEC 60601-1 250 V rms
(353 V peak) maximum working voltage
File E214100 File 205078 File 2471900-4880-0001
1 In accordance with UL1577, each ADuM220x is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 10 μA).
2 In accordance with DIN V VDE V 0884-10, each ADuM220x is proof tested by applying an insulation test voltage ≥1590 V peak for 1 sec (partial discharge detection
limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 6.
Parameter Symbol Value Unit Conditions
Rated Dielectric Insulation Voltage 5000 V rms 1-minute duration
Minimum External Air Gap L(I01) 8.0 min mm Distance measured from input terminals to output
terminals, shortest distance through air along the PCB
mounting plane, as an aid to PC board layout
Minimum External Tracking (Creepage) RW-16 Package L(I02) 7.7 min mm Measured from input terminals to output terminals,
shortest distance path along body
Minimum External Tracking (Creepage) RI-16 Package L(I02) 8.3 min mm Measured from input terminals to output terminals,
shortest distance path along body
Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
Data Sheet ADuM2200/ADuM2201
Rev. C | Page 11 of 20
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
means of protective circuits. Note that the asterisk (*) branded on packages denotes DIN V VDE V 0884-10 approval for 846 V peak
working voltage.
Table 7.
Description Conditions Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 300 V rms I to IV
For Rated Mains Voltage ≤ 450 V rms I to II
For Rated Mains Voltage ≤ 600 V rms I to II
Climatic Classification 40/105/21
Pollution Degree (DIN VDE 0110, Table 1) 2
Maximum Working Insulation Voltage VIORM 846 V peak
Input-to-Output Test Voltage, Method B1 VIORM × 1.875 = VPR, 100% production test, tm = 1 sec,
partial discharge < 5 pC
VPR 1590 V peak
Input-to-Output Test Voltage, Method A VPR
After Environmental Tests Subgroup 1 VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC 1375 V peak
After Input and/or Safety Test Subgroup 2
and Subgroup 3
VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC 1018 V peak
Highest Allowable Overvoltage Transient overvoltage, tTR = 10 seconds VTR 6000 V peak
Safety-Limiting Values Maximum value allowed in the event of a failure;
see Figure 3
Case Temperature TS 150 °C
Side 1 Current IS1 265 mA
Side 2 Current IS2 335 mA
Insulation Resistance at TS VIO = 500 V RS >109 Ω
350
300
200
100
00 50 100 150 200
07235-003
SAFETY-LIMITING CURRENT (mA)
CASE T E M P E RATURE (°C)
250
150
50
SIDE 1
SIDE 2
Figure 3. Thermal Derating Curve, Dependence of Safety-Limiting
Values with Case Temperature per DIN V VDE V 0884-10
RECOMMENDED OPERATING CONDITIONS
Table 8.
Parameter Symbol Min Max Unit
Operating Temperature TA −40 +105 °C
Supply Voltages1 V
DD1, VDD2 3.0 5.5 V
Input Signal Rise and Fall Times 1.0 ms
1 All voltages are relative to their respective ground.
ADuM2200/ADuM2201 Data Sheet
Rev. C | Page 12 of 20
ABSOLUTE MAXIMUM RATINGS
Table 9.
Parameter Rating
Storage Temperature (TST) −65°C to +150°C
Ambient Operating Temperature (TA) −40°C to +105°C
Supply Voltage (VDD1, VDD2)1 −0.5 V to +7.0 V
Input Voltage (VIA, VIB, VIC, VID, VE1, VE2)1, 2 −0.5 V to VDDI + 0.5 V
Output Voltage (VOA, VOB, VOC, VOD)1, 2 −0.5 V to VDDO + 0.5 V
Average Output Current per Pin3
Side 1 (IO1) −18 mA to +18 mA
Side 2 (IO2) −22 mA to +22 mA
Common-Mode Transients4 −100 kV/μs to +100 kV/μs
1 All voltages are relative to their respective ground.
2 VDDI and VDDO refer to the supply voltages on the input and output sides of a
given channel, respectively. See the section. PCB Layout
3 See for maximum rated current values for various temperatures. Figure 3
4 Refers to common-mode transients across the insulation barrier. Common-
mode transients exceeding the Absolute Maximum Rating can cause latch-
up or permanent damage.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Table 10. Maximum Continuous Working Voltage1
Parameter Max Unit Constraint
AC Voltage, Bipolar Waveform 565 V peak 50-year minimum lifetime
AC Voltage, Unipolar Waveform
Reinforced Insulation 846 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
DC Voltage
Reinforced Insulation 846 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
1 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
Table 11. ADuM2200 Truth Table (Positive Logic)
VIA Input VIB Input VDD1 State VDD2 State VOA Output VOB Output Notes
H H Powered Powered H H
L L Powered Powered L L
H L Powered Powered H L
L H Powered Powered L H
X X Unpowered Powered H H Outputs return to the input state within
1 μs of VDDI power restoration.
X X Powered Unpowered Indeterminate Indeterminate Outputs return to the input state within
1 μs of VDDO power restoration.
Table 12. ADuM2201 Truth Table (Positive Logic)
VIA Input VIB Input VDD1 State VDD2 State VOA Output VOB Output Notes
H H Powered Powered H H
L L Powered Powered L L
H L Powered Powered H L
L H Powered Powered L H
X X Unpowered Powered Indeterminate H Outputs return to the input state within
1 μs of VDDI power restoration.
X X Powered Unpowered H Indeterminate Outputs return to the input state within
1 μs of VDDO power restoration.
Data Sheet ADuM2200/ADuM2201
Rev. C | Page 13 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
GND
11
NC
2
V
DD1 3
V
IA 4
GND
2
16
NC
15
V
DD2
14
V
OA
13
V
IB 5
V
OB
12
NC
6
NC
11
GND
17
NC
10
NC
8
GND
2
9
NC = NO CONNECT
NOTES:
1. PIN 1 AND PIN 7 ARE INTERNALLY CO NNE CT ED, AND
CONNECTING BOTH TO G ND
1
IS RECOMM E NDE D.
2
. PIN 9 AND PIN 16 ARE INTERNALLY CONNE CTED, AND
CONNECTING BOTH TO G ND
2
IS RECOMM E NDE D.
ADuM2200
TOP VI EW
(Not to Scal e)
07235-004
Figure 4. ADuM2200 Pin Configuration
Table 13. ADuM2200 Pin Function Descriptions
Pin No. Mnemonic Description
1 GND1 Ground 1. Ground reference for Isolator Side 1.
2 NC No internal connection.
3 VDD1 Supply Voltage for Isolator Side 1, 3.0 V to 5.5 V.
4 VIA Logic Input A.
5 VIB Logic Input B.
6 NC No internal connection.
7 GND1 Ground 1. Ground reference for Isolator Side 1.
8 NC No internal connection.
9 GND2 Ground 2. Ground reference for Isolator Side 2.
10 NC No internal connection.
11 NC No internal connection.
12 VOB Logic Output B.
13 VOA Logic Output A.
14 VDD2 Supply Voltage for Isolator Side 2, 3.0 V to 5.5 V.
15 NC No internal connection.
16 GND2 Ground 2. Ground reference for Isolator Side 2.
ADuM2200/ADuM2201 Data Sheet
Rev. C | Page 14 of 20
GND
11
NC
2
V
DD1 3
V
OA 4
GND
2
16
NC
15
V
DD2
14
V
IA
13
V
IB 5
V
OB
12
NC
6
NC
11
GND
17
NC
10
NC
8
GND
2
9
NC = NO CONNECT
NOTES:
1. PIN 1 AND PIN 7 ARE INTERNALLY CO NNE CT ED, AND
CONNECTING BOTH TO G ND
1
IS RECOMM E NDE D.
2
. PIN 9 AND PIN 16 ARE INTERNALLY CONNE CTED, AND
CONNECTING BOTH TO G ND
2
IS RECOMM E NDE D.
ADuM2201
TOP VI EW
(Not to Scal e)
07235-005
Figure 5. ADuM2201 Pin Configuration
Table 14. ADuM2201 Pin Function Descriptions
Pin No. Mnemonic Description
1 GND1 Ground 1. Ground reference for Isolator Side 1.
2 NC No internal connection.
3 VDD1 Supply Voltage for Isolator Side 1, 3.0 V to 5.5 V.
4 VOA Logic Output A.
5 VIB Logic Input B.
6 NC No internal connection.
7 GND1 Ground 1. Ground reference for Isolator Side 1.
8 NC No internal connection.
9 GND2 Ground 2. Ground reference for Isolator Side 2.
10 NC No internal connection.
11 NC No internal connection.
12 VOB Logic Output B.
13 VIA Logic Input A.
14 VDD2 Supply Voltage for Isolator Side 2, 3.0 V to 5.5 V.
15 NC No internal connection.
16 GND2 Ground 2. Ground reference for Isolator Side 2.
Data Sheet ADuM2200/ADuM2201
Rev. C | Page 15 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
DATA RAT E ( M bp s)
CURRENT/ CHANNE L (mA)
0
0
6
2
8
10
10 20 30
4
5V
3V
07235-006
Figure 6. Typical Input Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation (No Output Load)
DATA RAT E ( M bp s)
CURRENT/ CHANNE L (mA)
0
0
3
2
1
4
10 20 30
5V
3V
07235-007
Figure 7. Typical Output Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation (No Output Load)
DATA RAT E ( M bp s)
0
010 20 30
CURRENT/CHANNEL ( mA)
3
2
1
4
5V
3V
07235-008
Figure 8. Typical Output Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation (15 pF Output Load)
DATA RATE (Mbps)
CURRENT ( mA)
0
0
15
10
5
20
10 20 30
5V
3V
07235-009
Figure 9. Typical ADuM2200 VDD1 Supply Current vs. Data Rate
for 5 V and 3 V Operation
DATA RAT E ( Mbps)
CURRENT (mA)
0
0
3
2
1
4
10 20 30
5V
3V
07235-010
Figure 10. Typical ADuM2200 VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
DATA RAT E ( Mbps)
CURRENT (mA)
0
0
6
2
8
10
10 20 30
5V
3V
4
07235-011
Figure 11. Typical ADuM2201 VDD1 or VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
ADuM2200/ADuM2201 Data Sheet
Rev. C | Page 16 of 20
APPLICATIONS INFORMATION
PCB LAYOUT
The ADuM220x digital isolator requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at the input and output supply pins (see
Figure 12). Bypass capacitors are most conveniently connected
between Pin 1 and Pin 3 for VDD1 and between Pin 14 and
Pin 16 for VDD2. The capacitor value should be between 0.01 μF
and 0.1 μF. The total lead length between both ends of the
capacitor and the input power supply pin should not exceed
20 mm. Bypassing between Pin 3 and Pin 7 and between Pin 9
and Pin 14 should be considered unless the ground pair on each
package side are connected close to the package.
GND
1
NC
V
DD1
V
IA
/V
OA
GND
2
NC
V
DD2
V
OA
/V
IA
V
IB
V
OB
NC NC
GND
1
NC
NC GND
2
07235-012
Figure 12. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, care
should be taken to ensure that board coupling across the
isolation barrier is minimized. Furthermore, the board layout
should be designed such that any coupling that does occur
equally affects all pins on a given component side. Failure to
ensure this could cause voltage differentials between pins
exceeding the device’s Absolute Maximum Ratings, thereby
leading to latch-up or permanent damage.
See the AN-1109 Application Note for board layout guidelines.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the length of
time it takes for a logic signal to propagate through a compo-
nent. The propagation delay to a logic low output can differ
from the propagation delay to logic high.
INPUT (
V
Ix
)
OUTPUT (V
Ox
)
t
PLH
t
PHL
50%
50%
07235-018
Figure 13. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the input signal’s timing is preserved.
Channel-to-channel matching refers to the maximum amount
the propagation delay differs among channels within a single
ADuM220x component.
Propagation delay skew refers to the maximum amount the
propagation delay differs among multiple ADuM220x
components operated under the same conditions.
DC CORRECTNESS AND MAGNETIC FIELD
IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent via the transformer to the
decoder. The decoder is bistable and is therefore either set or
reset by the pulses, indicating input logic transitions. In the
absence of logic transitions at the input for more than ~1 μs, a
periodic set of refresh pulses indicative of the correct input state
is sent to ensure dc correctness at the output. If the decoder
receives no internal pulses for more than approximately 5 μs,
the input side is assumed to be without power or nonfunctional;
in which case, the isolator output is forced to a default state (see
Tabl e 11 and Table 12) by the watchdog timer circuit.
The limitation on the ADuM220x magnetic field immunity is
set by the condition in which induced voltage in the transformer
receiving coil is large enough to either falsely set or reset the
decoder. The following analysis defines the conditions under
which this can occur. The 3 V operating condition of the
ADuM220x is examined because it represents the most suscep-
tible mode of operation.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V,
therefore establishing a 0.5 V margin in which induced voltages
can be tolerated. The voltage induced across the receiving coil is
given by
V = (−dβ/dt)Σπrn2; n = 1, 2,…, N
where:
β is the magnetic flux density (gauss).
N is the number of turns in the receiving coil.
rn is the radius of the nth turn in the receiving coil (cm).
Given the geometry of the receiving coil in the ADuM220x and
an imposed requirement that the induced voltage be at most
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated as shown in Figure 14.
MAGNE TIC FIE LD FRE QUENCY ( Hz )
100
MAXIMUM ALLOWABLE MAG NETIC FLUX
DENSITY (kgauss)
0.001 1M
10
0.01
1k 10k 10M
0.1
1
100M100k
07235-019
Figure 14. Maximum Allowable External Magnetic Flux Density
Data Sheet ADuM2200/ADuM2201
Rev. C | Page 17 of 20
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event were to occur during a transmitted
pulse (and was of the worst-case polarity), it would reduce the
received pulse from >1.0 V to 0.75 V—still well above the 0.5 V
sensing threshold of the decoder.
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances away from the
ADuM220x transformers. Figure 15 expresses these allowable
current magnitudes as a function of frequency for selected
distances. As can be seen, the ADuM220x is immune and can
be affected only by extremely large currents operated at high
frequency and very close to the component. For the 1 MHz
example noted previously, one would have to place a 0.5 kA current
5 mm away from the ADuM220x to affect operation of the
component.
MAGNETI C F IELD FRE QUENCY ( Hz )
MAXI MUM ALLO WABLE CURRENT (kA)
1000
100
10
1
0.1
0.011k 10k 100M100k 1M 10M
DISTANCE = 5mm
DISTANCE = 1m
DISTANCE = 100mm
07235-020
Figure 15. Maximum Allowable Current
for Various Current-to-ADuM220x Spacings
Note that at combinations of strong magnetic field and high
frequency, any loops formed by printed circuit board traces can
induce sufficiently large error voltages to trigger the thresholds
of succeeding circuitry. Care should be taken in the layout of
such traces to avoid this possibility.
POWER CONSUMPTION
The supply current at a given channel of the ADuM220x
isolator is a function of the supply voltage, the channel’s data
rate, and the channel’s output load.
For each input channel, the supply current is given by
IDDI = IDDI (Q) f ≤ 0.5fr
IDDI = IDDI (D) × (2f − fr) + IDDI (Q) f > 0.5fr
For each output channel, the supply current is given by
IDDO = IDDO (Q) f ≤ 0.5fr
IDDO = (IDDO (D) + (0.5 × 10−3) × CL × VDDO) × (2f − fr) + IDDO (Q)
f > 0.5fr
where:
IDDI (D), IDDO (D) are the input and output dynamic supply currents
per channel (mA/Mbps).
CL is the output load capacitance (pF).
VDDO is the output supply voltage (V).
f is the input logic signal frequency (MHz, half of the input data
rate, NRZ signaling).
fr is the input stage refresh rate (Mbps).
IDDI (Q), IDDO (Q) are the specified input and output quiescent
supply currents (mA).
To calculate the total IDD1 and IDD2, the supply currents for
each input and output channel corresponding to IDD1 and IDD2
are calculated and totaled. Figure 6 and Figure 7 provide per-
channel supply currents as a function of data rate for an
unloaded output condition. Figure 8 provides per-channel
supply current as a function of data rate for a 15 pF output
condition. Figure 9 through Figure 11 provide total IDD1 and IDD2
as a function of data rate for ADuM2200/ADuM2201 channel
configurations.
ADuM2200/ADuM2201 Data Sheet
Rev. C | Page 18 of 20
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation. In addition to
the testing performed by the regulatory agencies, Analog
Devices carries out an extensive set of evaluations to determine
the lifetime of the insulation structure within the ADuM220x.
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage. Accel-
eration factors for several operating conditions are determined.
These factors allow calculation of the time to failure at the actual
working voltage. The values shown in Table 10 summarize the
peak voltage for 50 years of service life for a bipolar ac operating
condition and the maximum CSA/VDE approved working volt-
ages. In many cases, the approved working voltage is higher than
50-year service life voltage. Operation at these high working
voltages can lead to shortened insulation life in some cases.
The insulation lifetime of the ADuM220x depends on the voltage
waveform type imposed across the isolation barrier. The iCoupler
insulation structure degrades at different rates, depending on
whether the waveform is bipolar ac, unipolar ac, or dc. Figure 16,
Figure 17, and Figure 18 illustrate these different isolation
voltage waveforms.
Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime under the ac bipolar condition
determines the Analog Devices recommended maximum
working voltage.
In the case of unipolar ac or dc voltage, the stress on the
insulation is significantly lower. This allows operation at higher
working voltages while still achieving a 50-year service life. The
working voltages listed in Table 10 can be applied while main-
taining the 50-year minimum lifetime, provided the voltage
conforms to either the unipolar ac or dc voltage cases. Any
cross-insulation voltage waveform that does not conform to
Figure 17 or Figure 18 should be treated as a bipolar ac
waveform and its peak voltage should be limited to the 50-year
lifetime voltage value listed in Table 10.
Note that the voltage presented in Figure 17 is shown as
sinusoidal for illustration purposes only. It is meant to represent
any voltage waveform varying between 0 V and some limiting
value. The limiting value can be positive or negative, but the
voltage cannot cross 0 V.
0V
RATED P E AK V OLTAGE
07235-021
Figure 16. Bipolar AC Waveform
0V
RATED P E AK V OLTAGE
07235-022
Figure 17. Unipolar AC Waveform
0V
RATED P E AK V OLTAGE
07235-023
Figure 18. DC Waveform
Data Sheet ADuM2200/ADuM2201
Rev. C | Page 19 of 20
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AA
10.50 (0.4134)
10.10 (0.3976)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75(0.0295)
0.25(0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
C
OPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
16 9
8
1
1.27 (0.0500)
BSC
03-27-2007-B
Figure 19. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-16)
Dimensions shown in millimeters and (inches)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AC
10-12-2010-A
13.00 (0.5118)
12.60 (0.4961)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75(0.0295)
0.25(0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
8°
0°
16 9
8
1
1.27
(0.0500)
BSC
SEATING
PLANE
Figure 20. 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]
Wide Body (RI-16-1)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1, 2
Number
of Inputs,
VDD1 Side
Number
of Inputs,
VDD2 Side
Maximum
Data Rate
(Mbps)
Maximum
Propagation
Delay, 5 V (ns)
Maximum
Pulse Width
Distortion (ns)
Temperature
Range Package Description
Package
Option
ADuM2200ARWZ 2 0 1 150 40 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM2200BRWZ 2 0 10 50 3 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM2200ARIZ 2 0 1 150 40 −40°C to +105°C 16-Lead SOIC_IC RI-16-1
ADuM2200BRIZ 2 0 10 50 3 −40°C to +105°C 16-Lead SOIC_IC RI-16-1
ADuM2201ARWZ 1 1 1 150 40 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM2201BRWZ 1 1 10 50 3 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM2201ARIZ 1 1 1 150 40 −40°C to +105°C 16-Lead SOIC_IC RI-16-1
ADuM2201BRIZ 1 1 10 50 3 −40°C to +105°C 16-Lead SOIC_IC RI-16-1
1 Z = RoHS Compliant Part.
2 Tape and reel is available. The addition of an -RL suffix designates a 13” (1,000 units) tape and reel option.
