DS26522DK
Dual T1/E1/J1 Transceive
r
Demo Kit
1 of 9 REV: 091806
www.maxim-ic.com
GENERAL DESCRIPTION
The DS26522DK is an easy-to-use demo kit for the
DS26522 T1/E1/J1 dual transceiver. The
DS26522DK is a stand-alone system. The board
comes complete with a transceiver, transformer,
termination resistors, configuration switches, network
connectors, microprocessor, and RS-232 connector.
The on-board processor and Dallas’ ChipView
software give point-and-click access to configuration
and status registers from a Windows®-based PC.
On-board LEDs indicate receive loss-of-signal and
interrupt status, as well as multiple clock and signal
routing configurations.
Windows is a registered trademark of Microsoft Corp.
DEMO KIT CONTENTS
DS26522DK PCB
CD_ROM Including:
ChipView Software
DS26522 Definition files
DS26522 Initialization files
DS26522DK Data Sheet
DS26522 Data Sheet
DS26522 Errata Sheet (if applicable)
FEATURES
 Demonstrates Key Functions of DS26522
T1/E1/J1 Dual Transceiver
 Includes Transceiver, Transformers, and
Termination Passives
 BNC Connections for 75Ω E1
 RJ48 Connector for 120Ω E1 and 100Ω T1
 On-Board Processor and ChipView Software
Provide Point-and-Click Access to the
DS26522 Register Set
 Accessible Address/Data Bus with Tri-State
Control to Allow Interface for External
Processor
 All Equipment-Side Framer Pins are Easily
Accessible for External Data Source/Sink
 LEDs for Loss-of-Signal and Interrupt Status
 Easy-to-Read Silkscreen Labels Identify the
Signals Associated with All Connectors,
Jumpers, and LEDs
ORDERING INFORMATION
PART DESCRIPTION
DS26522DK Demo kit for DS26522
DS26522DK
2 of 23
TABLE OF CONTENTS
1. BOARD FLOORPLAN........................................................................................................3
2. PCB ERRATA.....................................................................................................................3
3. BASIC OPERATION ...........................................................................................................4
3.1 HARDWARE CONFIGURATION...........................................................................................................4
3.1.1 General .................................................................................................................................................. 4
3.2 QUICK SETUP (REGISTER VIEW)......................................................................................................4
3.2.1 Miscellaneous ........................................................................................................................................ 4
4. ADDRESS MAP..................................................................................................................5
5. TEST POINTS AND CONNECTORS .................................................................................5
6. ADDITIONAL INFORMATION/RESOURCES....................................................................6
6.1 DS26522 INFORMATION..................................................................................................................6
6.2 DS26522DK INFORMATION.............................................................................................................6
6.3 TECHNICAL SUPPORT......................................................................................................................6
7. COMPONENT LIST............................................................................................................7
8. SCHEMATICS ....................................................................................................................9
LIST OF TABLES
Table 4-1. Address Map .............................................................................................................................................. 5
Table 5-1. Main Board PCB Configuration.................................................................................................................. 5
DS26522DK
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1. BOARD FLOORPLAN
1.2V FPGA
SUPPLY
BOARD POWER
5.0V DC JACK TEST POINTS:
DS26522
ADDRESS[12:0]
DATA[7:0]
INT, CS, RW, RD
TEST POINTS:
SPI_CPOL, SPI_CPHA, SPI_SWAP,
SPI_SEL, BTS, TXENABLE
FPGA
CONFIG
PR
O
M
5V
PROCESSOR
FLASH
SUPPLY
PORT 1
TRANSFORMER
BNCs, RJ45
INT LED
LATTICE
EC3
FPGA
DS26522
JTAG
DS26522
RS-232 DB9
CONNECTOR
2. PCB ERRATA
DS26522DK01A0
4/17/2006:
A 100pF capacitor has been added between processor reset and VCC. This was added to eliminate crosstalk
issues present in the OnCE programming pod.
FPGA
JTAG
RLOS LED
RLF LED
TEST POINTS:
TSER, RSER, TSSYNCIO, TSYNC, RSYNC,
REFCLKIO, MCLK, RSIG, TSIG
TEST POINTS:
BPCLK, MCLK,
RSYSCLK,
TSYSCLK, TCLK, RCLK
TEST POINTS:
RCHBLK_CLK,
RLF_LTC, AL_RSIGF,
RM_RFSYNC, TCHBLK
CLK
PORT 2
TRANSFORMER
BNCs, RJ45
MMC2107
PROCESSOR
PROCESSOR
SRAM OSCILLATOR
SELECTION
1.544MHz
,
2.048MHz
DS26522DK
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3. BASIC OPERATION
This design kit relies upon several supporting files, which are available for downloading on our website at
www.maxim-ic.com/DS26522DK QuickView page.
3.1 Hardware Configuration
• Supply 5.0V to the wall jack receptacle on the bottom of the PCB.
• Install the following jumpers (see Table 5-1):
o JP06: MCLK driven by 1.544MHz for T1. (Set E1 for 2.048MHz.)
o JP01, JP03: RSYSCLK driven by MCLK.
o JP02, JP04: TSYSCLK driven by MCLK.
o JP09, JP12: TCLK driven by MCLK.
o JP16 SPI_SEL to GND. JP17 BTS to VCC. JP18, JP19 TXENABLE to VCC.
• From the Programs menu, launch the host application named ChipView.exe. Run the Chi pView
application. If the default installation options were used, click the Start button on the Windows toolbar a nd
select Programs → ChipView → ChipView.
3.1.1 General
Upon power-up, the RLF and AL_LOS LEDs (red ) will be lit, but the INT LED (red) will not be lit. The board draws
approximately 200mA at power-up.
3.2 Quick Setup (Register View)
1) The PC loads ChipView, offering a choice among DE MO MODE, REGISTER VIEW, and TERMINAL
MODE. Select REGISTER VIEW.
2) The program will request a definition file. Navigate to the .def files in the T1 or E1 folder, then sele ct the file
named DS26522_GLB_T1_DEV1.def (T1 mode) or DS26522_GLB_E1_DEV1.def (E1 mode).
Note: Through the Links section, this will also load the LIU def file and framer def file.
3) Repeat Step 2 for DS26522_GLB_T1_DEV2.def (or DS26522_GLB_E1_DEV2.def).
4) The Register View Screen will appear, showing the register names, acronyms, and values for the
DS26522.
5) Predefined register settings for several functions are available as initialization files.
o .ini files are loaded by selecting the menu File→Reg Ini File→Load Ini File.
o Load the .ini file Load_T1_LBO0_0_133_impMatchOn_DEV1.ini (T1 mode) or
Load_E1_75_impMatchOn_DEV1.ini (E1 mode).
o Load the .ini file Load_T1_LBO0_0_133_impMatchOn_DEV2.ini (T1 mode) or
Load_E1_75_impMatchO n_DEV2.ini (E1 mode).
6) After loading the .ini file, the following may be observed:
o The DS26522 begins transmitting AIS with impedan ce match.
o The AL_LOS LEDs extinguishes upon external loopback.
3.2.1 Miscellaneous
The DS26522 uses three registe r definition files. All three files are loaded when the DS26522_GLOBAL*.def file is
loaded. Individual files are selected from the Def File Selection menu in ChipView.
DS26522DK
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4. ADDRESS MAP
The on-board microcontroller is configured to start the user address space at 0x81000000. All offsets given in
Table 4-1 are relative to the beginning of the user address space.
Table 4-1. Address Map
OFFSET DEVICE DESCRIPTION
0X0000 to
0X0087 FPGA Board identification and FPGA test registers
0X2000 to
0X3FFF DS26522 DS26522 framer, LIU, and BERT regi sters on CS1
0X4000 to
0X5FFF DS26522 DS26522 framer, LIU and BERT regi sters on CS2
5. TEST POINTS AND CONNECTORS
The DS26522DK has several connectors, test points, oscillators, and jumpers. Table 5-1 provides a description of
these signals, given in order of appearance on the PCB from left to right, then top to bottom (with the board held so
that the RS-232 connector is on the top edge).
Table 5-1. Main Board PCB Configuration
SILKSCREEN
REFERENCE FUNCTION DEFAULT
SETTING SCHEMATIC
PAGE DESCRIPTION
JB01
(PCB bottom side) Power supply 5.0V 3 System VDD. Always connected to power supply.
DS01 LED On (green) 3 Power OK LED.
J02 RS-232
Connector Connected to
host PC 6 Used for communication with host PC. Basic
setting is 57.6K baud, 8 bits, no stop bit, 1 parity
bit (57.6, 8, N, 1).
J01 OnCE BDM
Connector — 6
OnCE debug connector for MMC2107
processor.
SW01 System Reset — 4 System reset. Connects to all device reset pins.
J03 Flash VPP
Jumper Not Installed 6 Provides flash programming voltage (5V) to
processor.
J04 Lattice FPGA — 9 JTAG connector for Lattice EC3 FPGA.
DS04, DS06 LED — 11 DS26522 LEDs. Analog loss or receive
signaling freeze or framer LOS.
DS05, DS07 LED — 11 DS26522 LEDs. Receive loss of frame or loss of
transmit clock.
J05 DS26 522 Test
points — 10 DS26522 JTAG chains.
J06 DS26 522 Test
points — 14 DS26522 test points for RCHBLK, T CHBLK,
RMSYNC, REFCLKIO.
JP01, JP03 RSYSCLK
Selection Jumpered
Pins 1+2 14 RSYSCLK selection: MCLK (default), BPCLK.
JP02, JP04 TSYSCLK
Selection Jumpered
Pins 1+2 14 TSYSCLK selection: MCLK (default), BPCLK.
JP05 BPCLK MUX Jumpered
Pins 1 + 2 14 BPCLK mux, driven to pin 3 of JP01, JP02,
JP03, JP04.
J07 DS26 522 Test
points — 14 DS26522 test points for RSYNC, T SYNC, and
TSSYNCIO.
YB01, YB02
(PCB bottom side) Oscillators — 14 Oscillators for 2.048MHz and 1.544MHz.
J08, J09 Test points — 8 Test points for DS26522 address/data b us and
control lines.
DS26522DK
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SILKSCREEN
REFERENCE FUNCTION DEFAULT
SETTING SCHEMATIC
PAGE DESCRIPTION
J09.12 + J09.14 Bus Tri-state Not Jumpered 8 Install jumper to tri-state the FPGA pins that
connect to the DS26522.
JP06 MCLK Selection Jumpered
Pins 2+3 14 MCLK Selection: 1.544MHz, 2.048MHz
(default).
JP09, JP12 TCLK Selection Jumpered
Pins 1+2 14 TCLK Selection: MCLK (default), RCLK.
JP07, JP08 TSER Selection Not Jumpered 14 TSERx Selection: RSER2, RSER1.
JP14, JP11 TSIG Selection Not Jumpered 14 TSIGx Selection: RSIG2, RSIG1.
JP10 SPI_CPOL Bias Not Jumpered 10 SPI_CPOL Selection: pulldown, pullup.
JP13 SPI_CPHA Bias Not Jumpered 10 SPI_CPHA Selection: pulldo wn, pullup
JP15 SPI_SWAP Bias Not Jumpered 10 SPI_SWAP Selection: pulldown, pullup
JP16 SPI_SEL Bias
Jumpered
Pins 1+2 10 SPI_SEL Selection: pulldown (default), pullup.
JP17 BTS Bias
Jumpered
Pins 2+3 10 BTS Selection: pulldown, pullup (default).
JP18, JP19 TXENABLE Bias Jumpered
Pins 2+3 10 TXENABLE Selection: pulldown, pullup
(default).
J15 + J14 Network BNC
J11 Network RJ48
— 12 Port 2 BNC for 75Ω network connection and
RJ48 network connection.
J12 + J13 Network BNC
J10 Network RJ48
— 13 Port 1 BNC for 75Ω network connection and
RJ48 network connection.
6. ADDITIONAL INFORMATION/RESOURCES
6.1 DS26522 Information
For more information about the DS26522, refer to the DS26522 data sheet at www.maxim-ic.com/DS26522.
6.2 DS26522DK Information
For more information about the DS26522DK including software downloads, refer to the DS26522DK Quick View
page at www.maxim-ic.com/DS26522DK.
6.3 Technical Support
For additional technical support, e-mail your questions to telecom.support@dalsemi.com.
DS26522DK
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7. COMPONENT LIST
DESIGNATION QTY DESCRIPTION SUPPLIER PART
C01, CB08,
CB11-CB13,
CB16, CB18,
CB21, CB31,
CB34-CB36,
CB38-CB40
15 0.1µF ±10%, 16V ceramic capacitors (0603) Phycomp 06032R104K7B20D
C02 1
1µF ±10%, 16V ceramic capacitor (1206) Panasonic ECJ-3YB1C105K
C03, C04,
CB01, CB02 4 10F ±20%, 10V ceramic capacitors (1206) Panasonic ECJ-3YB1A106M
CB03, CB05 2 68µF ±20%, 16V tantalum capacitors (D case) Panasonic ECS-T1CD686R
CB04 1
470µF ±20%, 6.3V tantalum capacitor (D case) Digi-Key 399-3002-1-ND
CB06, CB09,
CB15, CB17,
CB19, CB25,
CB27, CB29,
CB32, CB41,
CB42
11 10µF ±20% 10V ceramic capacitors (1206) Panasonic ECJ-3YB1A106M
CB07, CB24,
CB26, CB28,
CB43, CB44 6 0.1µF ±20%, 16V X7R ceramic capacitors (0603) AVX 0603YC104MAT
CB10, CB14,
CB20, CB22,
CB23, CB30,
CB33, CB37
8 4.7µF, 6.3V multilayer ceramic capacitors (0603) Digi-Key ECJ-1VB0J475M
CB45, CB46 2 560pF ±5%, 50V ceramic capacitors (1206) Digi-Key 478-1489-2-ND
DB01 1 1A, 40V Schottky diode Internatioanl
Rectifier 10BQ040
DS01 1 Green LED (SMD) Panasonic LN1351C
DS02 1 Green LED (SMD) Panasonic LN1351C
DS03–DS07 5 Red LEDs (SMD) Panasonic LN1251C
GND_TP02,
GND_TP19–
GND_TP22,
GND_TP24
6 Standard ground clip Keystone
Electronics 4954
H01, H02, H04,
H07, h08, H09 6 Kit, 4-40 hardware, 0.50 nylon standoff and nylon
hex-nut — 4-40KIT4
J01 1 100-mil 2-7 position jumper Lab Stock —
J02 1 DB9 right-angle connector (long case) AMP 747459-1
J03 1 100-mil 2-position jumper Lab Stock —
J04, J05, J06 3 10-pin terminal strip headers (dual row, vertical) Samtec TSW-105-07-T-D
J07 1 14-pin header (dual row, vertical) Samtec HDR-TSW- 107-14-T-D
J08, J09 2 14-pin headers (dual row, vertical)
NON POPULATED Samtec NOPOP-HDR-TSW-
107-14-T-D
DS26522DK
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DESIGNATION QTY DESCRIPTION SUPPLIER PART
J10, J11 2 8-pin single-port connectors (RJ48) Molex 15-43-8588
J12–J15 4 5-pin right-angle BNC connect ors Trompetor UCBJR220
JB01 1
2.1mm/5.5mm closed frame power jack, high
current (right angle PCB, 24VDC at 5A)
Also requires 5V AC-DC adapter.
Input: 100–240VAC, 50–60Hz, 0.6A.
Output: DC 5V, 2.6A.
PN DMS050260-P5P-SZ. Model 3Z-161WP05
CUI Inc. PJ-002AH
JP01–JP09,
JP10–JP19 19 3 position jumpers (100 mils) Lab Stock —
R01, R02,
RB28, RB41,
RB42, RB43,
RB48–RB52
11 1.0kΩ ±5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ102V
R03–R09, R10,
RB09 9 0Ω ±5%,1/8W resistors (1206) Panasonic ERJ-8GEYJ0R00V
RB01–RB06,
RB11–RB17,
RB20, RB21,
RB23, RB30
17 10kΩ ±5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ103V
RB07 1
1.0MΩ ±5%, 1/16W resistor (0603) Panasonic ERJ-3GEYJ105V
RB08, RB24,
RB32–RB35 6 330Ω ±5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ331V
RB10, RB19,
RB25, RB26,
RB31, RB38,
RB39, RB40
8 10kΩ ±5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ103V
RB18 1
1.0kΩ ±5%, 1/16W resistor (0603) Panasonic ERJ-3GEYJ102V
RB22 1
330Ω ±5%, 1/16W resistor (0603) Panasonic ERJ-3GEYJ331V
RB27 1
0.0Ω ±5%, 1/16W resistor (0603) Panasonic ERJ-3GEY0R00V
RB29 1
10kΩ ±1%, 1/10W resistor (0805) Panasonic ERJ-6ENF1002V
RB36, RB37 2 30Ω ±5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ300V
RB44–RB47 4
61.9Ω ±1%, 1/10W resistors (0805) Panasonic ERJ-6ENF61R9V
RB53, RB54 2 51.1Ω ±1%, 1/10W resistors (0805) Panasonic ERJ-6ENF51R1V
RPB01–RPB07 7 30Ω ±5% 4-pack resistors (0402) Panasonic EXB-N8V300JX
SW01 1 4-pin single-pole switch Panasonic EVQPAE04M
TB01, TB02 2 16-pin SMT transformers Pulse
Engineering TX1099
TP01, TP02 2 1 plated hole test points
DO NOT STUFF Lab Stock —
U01, U04 2 Cypress SRAM Lab Stock —
U02 1 3V to 5V Regulating charge pump Maxim MAX1686HEUA
U03 1 Processor Freescale
Semiconductor MMC2107
DS26522DK
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Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.
DESIGNATION QTY DESCRIPTION SUPPLIER PART
U05 1
1.2V FPGA
(144-pin, 20mm x 20mm TQFP) Lattice LFEC3E-3T144C
U06 1
Dual T1/E1/J1 transceiver (144-pin, 12mm x
12mm CSBGA) Dallas
Semiconductor DS26522
UB01 1
Dual RS-232 transceivers with 3.3V/5V internal
capacitors Maxim MAX3233E
UB02 1
Linear regulator
(1.5W, 3.3V or adjustable, 1A, 16-pin TSSOP-EP) Maxim MAX1793EUE-33
UB03 1
Microprocessor voltage monit or
(2.93V reset, 4-pin SOT143) Maxim MAX811SEUS-T
UB04 1
2Mb High-speed serial flash m emory
(2.7V to 3.6V, 8-pin SO) Atmel AT25F2048N-
10SU-2.7
UB05 1
300mA LDO regulator with RESET
(1.20V output, 6-pin thin SOT23-6) Maxim MAX1963EZT120-T
UB06, UB07 2 High-speed buffers Fairchild NC7SZ86
XB01 1 8.0MHz low-profile crystal ECL EC1-8.000M
YB01 1 3.3V 1.544MHz crystal clock oscillator SaRonix NTH 039A3-1.5440
YB02 1 3.3V 2.048MHz crystal clock oscillator SaRonix NTH 039A3-2.0480
8. SCHEMATICS
The DS26522DK schemat i cs are featured in the following 14 pages.
MICROPROCESSOR HIERARCHY BLOCK
PAGES 04-09
DS26522 HIERARCHY BLOCK
PAGES 10-14
HIERARCHY BLOCK. THESE SIGNALS APPEAR AS PINS ON THE HIERARCHY BLOCK CONNECTOR
ONLY SIGNALS WITH IMPORT/OUTPORT CONNECTORS HAVE CONNECTION OUTSIDE THE
NOTES: EACH HIERARCHY BLOCK IS INDEPENDENT OF THE NEXT.
CONTENTS
PAGES 03-03: POWER SUPPLY
PAGES 04-09: MICROPROCESSOR AND INTERFACE
PAGES 10-14: DS26522 DEVICE, LINE BUILDOUT AND TESTPOINTS
PAGE 02: DECOUPLING / MOUNTING HOLES
PAGE 01: DS26522 DESIGN KIT TOP LEVEL HIERARCHY BLOCKS
HIERARCHY BLOCKS:
D_DUT<7..0>
WR_DUT
CS_X2
INT_2
CS_X1
RD_DUT
RESET_DUT
A_DUT<12..0>
I9
DS26522DK TOP LEVEL
04/17/2006
BLOCK
NAME:
_ds26522topdn_.
PARENT
BLOCK:
<CON_PARENT_NAME>
STEVE SCULLY
1/14(TOTAL)
1/2(BLOCK)
DS26522DK01A0
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
_DS26522DK01A0DUTDN_
CS_X2
INT_DUT
CS_X1
RD_DUT
WR_DUT
D_DUT<7..0>
RESET_DUT
A_DUT<12..0>
_motprocrescard_dn
SPI_MISO
SPI_MOSI
SPI_SCK
SPI_CS
RESET
CS_X1
CS_X2
INT2
INT3
INT5
D_DUT<7..0>
WR_DUT
RD_DUT
CS_X5
CS_X4
CS_X3
INT4
A_DUT_<12..0>
PAGES 03-03
POWER SUPPLY HIERARCHY BLOCK
0.1UF
2
0.1UF
CB12
1
CB35
1
GND_TP19
GND_TP02
H09
CB17
10UF
CB15
10UF
CB29
10UF
CB32
10UF
CB41
10UF
CB42
0.1UF 4.7UF
10UF
CB06
10UF
CB04
470UF
GND_TP22
GND_TP24
GND_TP20
H04 H07
H01
H02 H08
1
1
0.1UF
CB39
CB36
2
2
0.1UF
CB40
2
0.1UF
1
2
CB31
1
1
2
0.1UF
1
0.1UF
CB16
CB08
2
2
1
1
0.1UF
CB38
2
CB20
4.7UF
CB37
4.7UF
CB33
0.1UF
0.1UF
CB34
2
1
0.1UF
CB21
2
4.7UF
CB14
4.7UF
CB23
4.7UF
CB10CB18
2
1
1
0.1UF
C01
2
0.1UF
1
CB11
2
4.7UF
CB22
4.7UF
CB30
GND_TP21
2/14(TOTAL)
BLOCK
NAME:
_ds26522topdn_.
PARENT
BLOCK:
<CON_PARENT_NAME>
STEVE SCULLY
2/2(BLOCK)
04/17/2006
DS26522DK01A0
CR-2
:
@\_ZTOP_LIB\.\_DS26522TOPDN_\(SCH_1):PAGE2
2
1
1 11 111
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
4 4 4
POWER_SUPPLY
REGULATOR_INPUT REGULATOR_OUTPUT
RESET_OUT
4 44
V3_3
V3_3
V3_3
REVERSE BIAS PROTECTION
5V DC POWER SUPPLY
3.3V 1% REGULATOR
END OF POWER SUPPLY HIERARCHY BLOCK
BEGINNING OF POWER SUPPLY HIERARCHY BLOCK
10UF
10UF
GREEN
REGULATOR_OUTPUT
68UF
68UF
10UF
10UF
RESET_OUT
1 AMP
RESET_OUT
REGULATOR_INPUT
3.3V
REGULATOR_OUTPUT
10K
330
REGULATOR_INPUT
UB02
DB01
RB08
DS01
RB10
CB01
C03
CB02
C04
CB03
CB05
3A6<
3A4<> 3A6<>
3/14(TOTAL)
DS26522DK01A0
STEVE SCULLY
04/17/2006
1/1(BLOCK)
BLOCK
NAME:
power_supply_1amp_dn.
PARENT
BLOCK:
\_ds26522topdn_\
CR-3
:
@\_ZTOP_LIB\.\_DS26522TOPDN_\(SCH_1):PAGE2_I230@MODULES.POWER_SUPPLY_1AMP_DN(SCH_1):PAGE1
1
2
2
1
JB01
2
1
2
1
15
6
7
13
5
4
2
17
10
11
14
12
3
2
1
2
1
3D4>
3C8>
3D7<
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
MAX1793_U
IN2
OUT1
OUT3
SET
GND
GND
IN1
IN3
IN4
OUT2
SHDN
RST
OUT4
OUT
IN
OUT
BEGINNING OF PROCESSOR HIERARCHY BLOCK
PQB0
PQB2
PQB3
KIT_STATUS
INT2
1UF
17
TC2
TA
RCON
OE
VRH
TEA
RW
SCI1_IN
USER_LED1
SCI2_OUT
ICOC10
TEST
ICOC13
ICOC12
ICOC11
ICOC21
ICOC20
ICOC23
ICOC22
PQA4
PQA3
PQA0
PQA1
CS3
TC1
ONCE_TDI
2107_TDO
CSE1
EB3
PQB1
EB1
EB2
CSE0
CS2
CPUCLK_OUT
YCO
XTAL
INT4
RUN_KIT_USR
USER_LED2
INT3
SCI2_IN
SCI1_OUT
25
20
2.93V
22
13
12
11
10
8
9
7
6
5
3
21
4
1
0
.1UF
0.0
20
0
2
3
4
5
31
30
29
27
19
28
26
24
23
6
7
8
9
10
21
18
19
17
18
16
13
12
11
16
15
14
GND
PA<22..0>
2
1
22
15
14
VDDSYN
FLASH_VPP
PROC_RESET
1.0K
RESET
SPI_SCK
EB0
ONCE_DE_B
PROC_RESET_OUT
CS0
CS1
SPI_CS
PROC_RESET
SPI_MOSI
SPI_MISO
OSC_MCU
ONCE_TCLK
ONCE_TRST_B
ONCE_TMS
TIM_16H_8L
PD<31..0>
CB07
RB09
SW01
UB03
U03
U03
C02
R01
BLOCK NAME: _motprocrescard_dn. PARENT BLOCK: \_ds26522topdn_\
4/14(TOTAL)
STEVE SCULLY
04/17/2006
1/6(BLOCK)
DS26522DK01A0
PRINTED
Fri
Aug
04
13:58:16
2006
4
3
1
2
3
1
4
2
45
9
19
17
20
21
22
25
27
30
31
34
35
16
15
12
10
7
5
4
3
2
1
36
37
38
39
40
41
42
43
46
48
51
114
73
126
140
127
76
64
44
32
18
8
50
49
47
29
28
26
24
23
13
11
6
139
137
136
134
132
131
122
121
119
117
116
144
14
112
59
65
33
123
141
129
77
87
115
74
103
102
92
113
95
97
99
69
68
82
84
75
79
124
91
90
80
71
138
86
118
128
120
93
143
83
85
62
67
98
100
101
104
105
106
88
96
60
135
133
78
81
110
111
109
108
107
94
142
130
125
53
52
55
54
58
57
56
72
63
61
66
89
70
6A3<
1D7^ 8C5< 8C3< 8B6<> 7C4<>
5D6<
7D5<>5B7<>5B4<>
7D5<>
6B8>
6D3<>
6D3<>
7D4<>5B4<>
7D5<>
7C8<>
6C5<>
8C5< 8C3<
8C5< 8C3< 8B6<>
6B8<
6B1<>
6C3<>4B5<>
1C7^9B4<8C2>7C8<>
7D5<>5B7<>
6C2<>
7D5<>5B7<>5B3<>
7D5<>
4A4<6C3<>
6D5<>
6C3<>
6C2<>
6C1<>
7D65D7<5C7<5A6>5A2>
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
OUT
OUT
IN
OUT
MMC2107
CONTROL
RXD1
INT7*
TXD2
ICOC10
TEST
INT1*
ICOC13
ICOC12
ICOC11
ICOC21
ICOC20
ICOC23
ICOC22
EXTAL
TCLK
TRST*
SS*
PQB0
PQA4
PQA3
PQA0
PQA1
CS3*
TC1
TDI
TDO
CSE1
EB3*
INT6*
PQB1
PQB2
PQB3
EB0*
EB1*
EB2*
TC2
CSE0
CS1*
CS2*
DE*
SCK
RSTOUT*
CLKOUT
RESET*
CS0*
TMS
INT0*
YC0
MOSI
MISO
XTAL
INT3*
INT2*
INT5*
INT4
RXD2
TXD1
MMC2107
PORT
TA*
SHS*
OE*
VRH
VSTBY
TEA*
VDDH
VDDF
VDDA
VPP
VDD6
VDD7
VDD8
VDDSYN
VDD3
VDD5
RW
VRL
A8
D31
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A7
A6
A5
A4
A3
A2
A1
A0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSSSYN
VSSF
VSSA
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
VDD2
VDD1
VDD4
V3_3
MAX811_U
RESET*
VCC
GND
MR*
V3_3
XTAL W/ PLL
BOOT INTERNAL
D18 HAS A 10K LOAD TO GND
D18 HAS A 10.5K LOAD TO V3V
BOOT EXT
WHEN SET FOR
INTERN/EXTERN
BOOT
RESET CONFIGURATION
FULL DRIVE
MASTER MODE
INTERNAL
FLASH ENABLE
PA<17..1>
PD<18>
PD<19>
PD<28>
PD<22>
PD<23>
PD<21>
PD<16>
PD<17>
PD<26>
16
10K
10K
10K
10K
10K
10K
10K
17
10K
10K
20
19
24
21
25
26
27
28
29
30
31
10K
22
9
10
11
12
13
14
16
8
7
6
5
4
3
2
1
15
17
OE
EB0
CS0
CY62128V
PA<17..1>
CY62128V
OE
EB1
CS0
RCON
23
PD<23..16>
18
PD<31..24>
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
9
U04
RB15
1
1
2
U01
RB12
1
1
2
RB11
1
2
1
RB17
1
2
1
RB21
RB14
1
1
2
RB13
1
1
2
RB23
RB16
1
1
2
RB20
DS26522DK01A0
STEVE SCULLY
04/17/2006
2/6(BLOCK)
5/14(TOTAL)
BLOCK
NAME:
_motprocrescard_dn.
PARENT
BLOCK:
\_ds26522topdn_\
CR-5
:
@\_ZTOP_LIB\.\_DS26522TOPDN_\(SCH_1):PAGE1_I6@\_ZTOP_LIB\.\_MOTPROCRESCARD_DN\(SCH_1):PAGE2
21
20
19
18
17
15
14
13
27
26
23
25
4
28
3
31
2
32
16
24
29
1
12
11
10
9
8
7
6
5
30
22
21
20
19
18
17
15
14
13
27
26
23
25
4
28
3
31
2
32
16
24
29
1
12
11
10
9
8
7
6
5
30
22
2
1
2
1
2
1
7B8
5A5
4A1>
7D6 5A2> 4A2>
7D6
5A6>
4A2>
7D6 5A2> 4A2>
7D6
5A2> 4A2>
7D6 5A2> 4A2>
7D6 5A2> 4A2>
7D6 5A2> 4A2>
7D6 5A6> 4A2>
7B8
5A8
4A1>
7D5<>5B7<>4D3<>
7D4<>4D7<>
7D5<>5B7<>4B5<>
4D3<>
7D65D7<5C7<4A2>
7D65D7<5C7<4A2>
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
CY62128V
CE1*
CE2
A7
A6
A5
A4
A3
A2
A1
A0
N_C
WE*
OE*
GND
VCC
A16
A15
A14
A13
A12
A11
A10
A9
A8 IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
V3_3
CY62128V
CE1*
CE2
A7
A6
A5
A4
A3
A2
A1
A0
N_C
WE*
OE*
GND
VCC
A16
A15
A14
A13
A12
A11
A10
A9
A8 IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
V3_3
BUT DO NOT POPULATE
ALIGN KEY
PLACE PADS FOR CAP
HAS BEEN ADDED BETWEEN PROC_RESET AND VCC
NOTE: A 100PF CAPACITOR
THIS ADDITION IS NOT SHOWN IN THE SCHEMATIC
(SEE ERRATA SECTION OF DESIGN KIT USER MANUAL)
10K
1
RB06
1
2
CB13
CB09
U02
1
2
1
RB22
DS02
J03
2
1
1
RB18
XB01
1
2
1
RB07
RB01
1
2
1
RB05
J02
1
2
1
RB02
1
2
1
RB03
UB01
RB04
2
1
J01
FLASH_VPP
10UF
330
ONCE_TDI
2107_TDO
ONCE_TCLK
PROC_RESET
8.0MHZ
1.0M
10K
10K
10K
10K
10K
XTAL
PRT1_OUT
PRT1_IN
OSC_MCU
CON14P
ONCE_TMS
ONCE_DE_B
ONCE_TRST_B
SCI1_OUT
SCI1_IN
PRT1_OUT
1.0K
GREEN
KIT_STATUS
0.1UF
PRT1_IN
3/6(BLOCK)
04/17/2006
STEVE SCULLY
DS26522DK01A0
BLOCK
NAME:
_motprocrescard_dn.
PARENT
BLOCK:
\_ds26522topdn_\
6/14(TOTAL)
CR-6
:
@\_ZTOP_LIB\.\_DS26522TOPDN_\(SCH_1):PAGE1_I6@\_ZTOP_LIB\.\_MOTPROCRESCARD_DN\(SCH_1):PAGE3
13
9
7
5
11
3
1
10
12
8
6
4
14
2
2
1
20
1
8
4
5
6
7
9
10
11
12
13
14
15
16
17
18
19
3
2
9
5
4
2
1
3
6
7
8
2
1
1
2
2
1
1
2
3
2 8
6
4
5
1
7
4D3<
4D6<>
4D6<>
4A6<>
4B5<>4A4<
4A7<>
6B8>
6B8<
4A6<>
4A6<>
4B5<>
4A6<>
4B8<>
4B8<>
6A8<>
4A7<>
6A8<>
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
MAX1686_U
CXP
V3/5*
PGND
GND
CXN
OUT
SHDN
IN
V3_3
V3_3
V3_3
CONN_DB9P
H
G
F
C
A
B
D
E
J
V3_3
MAX3233E
INVALID*
T2IN
T2OUT
GND
V-
C2-
C2+
C1-
C1+
V+2
V+1
FORCEOFF*
VCC
T1OUT
R1OUT
FORCEON
T1IN
R1IN
R2OUT R2IN
V3_3
CON14P
MEM_SCK MUST BE AT PIN77 FOR TQFP144
TRISTATE_AD_BUS
7
4
3
97_IO
MEM_SO
USERFPGA2
0.0
INT5
330
INT_LED
ALE_DUT
WR_DUT
PD<31..16>
23
CS_X1
CS_X2
RESET
CS2
CS1
CS0
RW
OE
INT2
RD_DUT
0
1
2
3
4
5
6
7
D_DUT<7..0>
PA<16..0>
16
17
18
19
20
21
22
24
25
26
28
30
31
29
27
CPUCLK_OUT
0
1
2
5
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MEM_SCK
EB0
EB1
MEM_CS
MEM_SI
CS_X3
CS_X4
CS_X5
9
12
6
A_DUT_<12..0>
8
U05
RB24
DS03
RB27
BLOCK
NAME:
_motprocrescard_dn.
PARENT
BLOCK:
\_ds26522topdn_\
04/17/2006
STEVE SCULLY
DS26522DK01A0
4/6(BLOCK)
7/14(TOTAL)
CR-7
:
@\_ZTOP_LIB\.\_DS26522TOPDN_\(SCH_1):PAGE1_I6@\_ZTOP_LIB\.\_MOTPROCRESCARD_DN\(SCH_1):PAGE4
85
87
88
127
77
8
75
74
76
78
79
82
83
100
101
102
103
105
104
107
106
124
123
122
138
137
121
119
118
120
116
115
114
113
112
111
6
7
5
4
3
2
69
70
68
66
64
61
32
39
41
42
43
45
46
47
48
50
49
53
56
34
35
33
30
31
29
23
22
21
20
57
62
65
67
40
141
142
135
60
59
58
51
140
139
25
26
27
134
86
81
131
132
133
129
130
9
8B6<>
9C8>
8C5<8C3<
1C7^8B2>8A6<>
5D7< 5C7< 5A6> 5A2> 4A2>
1C7^ 8B2> 8A6<>
1C7^ 8B2> 8A6<>
1C7^
9B4< 8C2> 4A4<>
4C5<>
4B5<>
4D4<>
1D7^8C5<8C3<8B6<>4A7<>
1C7^8B2>8A6<>
1C7^
8A6
8B2<>
4B5<>
5B7<>4D7<>
5B4<>4D7<>
9B8<
9C8<
8B2> 8A6<>
8B2> 8A6<>
8B2>
1C7^ 8B7
8B2>
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
BANK 3
LFEC_T144_U
BANK 0
I/O PORT
BANK 6
BANK 4BANK 5
BANK 1
BANK 2
INPUT
PLL
PLL
INPUT
PLL
INPUT
BANK 7
INPUT
PLL
INPUT
PLL
PLL
INPUT
PL9B/PCLKC7_0
PT16B/VREF1_0
PT17A/PCLKT0_0
PT15A
PT15B
PT16A/VREF2_0
PR14A/RLM0_PLLT_FB_A
PR12A/DOUT/CSO*
PT14B
PL14A
PL13B
PL13A
PT12B
PT12A
PB17A/PCLKT5_0
PB19A/VREF1_4
PB19B/CS*
PB20A/VREF2_4
PT14A/TDQS14
PT10A
PT10B
PB10B
PB23A
PB22A/BDQS22
PB21A/D2/SPID5
PB18B/CS1*
PL11A/LLM0_PLLT_IN_A
PL11B/LLM0_PLLC_IN_A
PL12A/LLM0_PLLT_FB_A
PL12B/LLM0_PLLC_FB_A
PL14B
PL15B
PL15A/LDQS15
PL16B
PL18B/VREF2_6
PL18A/VREF1_6
PB18A/WRITE*
PB17B/PCLKC5_0
PB16A/VREF2_5
PB16B/VREF1_5
PB15B
PB15A
PB14B
PB14A/BDQS14
PB13B
PB11B
PB11A
PB10A
PL16A
PB20B/D0/SPID7
PB21B/D1/SPID6
PB22B/D3/SPID4
PB23B/D4/SPID3
PB25B/D6/SPID1
PB24B/D5/SPID2
PL2A/VREF2_7
PL2B/VREF1_7
PL7A
PL7B
PL8B
PL8A
PT25B
PT25A
PT23A
PT22B
PT22A/TDQS22
PT21B
PT20A
PT21A
PT20B
PT19B/VREF2_1
PT13B
PT13A
PT19A/VREF1_1
PT18B
PT18A
PR2B/VREF1_2
PR2A/VREF2_2
PR7B
PR7A
PR8A
PR8B
PR9A/PCLKT2_0
PR9B/PCLKC2_0
PR13A/RLM0_PLLT_IN_A
PR13B/RLM0_PLLC_IN_A
PR14B/RLM0_PLLC_FB_A
PR15A/RDQS15
PR16A
PR18A/VREF1_3
PR16B
PL9A/PCLKT7_0
PR15B
PT17B/PCLKC0_0
PR11A/D7/SPID0
PR11B/BUSY/SISPI
PR12B/DI/CSSPI*
THIS ALLOWS THE USER TO CONNECT A DIFFERENT PROCESSOR
JUMPER PINS 12+14 TO TRISTATE THE ADDRESS DATABUSS OF THE FPGA.
CS_X3
CS_X2
CS_X1
RD_DUT
WR_DUT
INT3
INT2
10K
8
7
6
5
4
A_DUT_<12..0>
CS_X4
CS_X5
CS_X1
CS_X2
CS_X3
10K
INT2
NOPOP
7
6
5
4
3
2
1
INT4
10K
10K
RESET
INT4
INT5
RD_DUT
WR_DUT
INT2
INT3
0
NOPOP
INT5
0
1
2
D_DUT<7..0>
3
12
A_DUT_<12..0>
CS_X4
D_DUT<7..0>
10K
INT3
TRISTATE_AD_BUS
RB40
RB38
RB19
RB31
J08
J09
RB39
1C7^8B77A6
8A6<>7A5<>
7A5<>
1C7^8A6<>7A7<>
1C7^8A6<>7A7<>
8A6<>7A4<>
1C7^9B4<7C8<>4A4<>
8C5< 4A7<>
8C5< 7B4<>
1C7^8A6<>7C4<>
1C7^8A6<>7C4<>
1D7^ 8C5< 8B6<> 7C4<> 4A7<>
8C5< 8B6<> 4A7<>
1C7^
8A6
7A6
BLOCK
NAME:
_motprocrescard_dn.
PARENT
BLOCK:
\_ds26522topdn_\
5/6(BLOCK)
DS26522DK01A0
STEVE SCULLY
04/17/2006
8/14(TOTAL)
CR-8
:
@\_ZTOP_LIB\.\_DS26522TOPDN_\(SCH_1):PAGE1_I6@\_ZTOP_LIB\.\_MOTPROCRESCARD_DN\(SCH_1):PAGE5
2
1
2
1
2
1
2
1
2
4
8
6
3
1
9
11
13
10
5
7
14
12
2
4
8
6
3
1
9
11
13
10
5
7
14
12
2
1
8B2>7A4<>
1C7^8B2>7A7<>
1C7^8B2>7A7<>
1C7^8B2>7C4<>
1C7^8B2>7C4<>
8C5<8C3<4A7<>
1D7^8C5<8C3<7C4<>4A7<>
1D7^ 8C3< 8B6<> 7C4<> 4A7<>
8C3< 4A7<>
8C3< 7B4<>
8B2>7A5<>
8C3< 8B6<> 4A7<>
7C3>
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
OUT
OUT
OUT
V3_3
OUT
OUT
2
3
7
13
8
5
9
11
6
4
10
12
14
1
CONN_14P
2
3
7
13
8
5
9
11
6
4
10
12
14
1
CONN_14P
OUT
OUT
IN
IN
IN
IN
IO
OUT
OUT
V3_3
END OF PROCESSOR HIERARCHY BLOCK
10K
97_IO
10K
10K
10UF
10UF
10UF
.1UF
.1UF
.1UF
2.7V
V1_2
L_TMS
L_TCK
V1_2
L_TCK
L_TMS
RESET
L_TDO
L_TDI
L_TDI
L_TDO
MEM_CS
MEM_SCK
MEM_SO
MEM_SI
I10
I24
I26
I28
I5
10K
MEM_SCK
I6
RB29
TP02
TP01
RB30
U05
RB26
RB25
CB27
CB25
CB19
CB28
CB24
CB26
J04
UB04
UB05
BLOCK
NAME:
_motprocrescard_dn.
PARENT
BLOCK:
\_ds26522topdn_\
DS26522DK01A0
STEVE SCULLY
04/17/2006
6/6(BLOCK)
9/14(TOTAL)
CR-9
:
@\_ZTOP_LIB\.\_DS26522TOPDN_\(SCH_1):PAGE1_I6@\_ZTOP_LIB\.\_MOTPROCRESCARD_DN\(SCH_1):PAGE6
36
1
52
28
63
12
11
128
117
109
72
80
37
144
15
96
98
97
14
24
44
13
92
17
91
89
90
94
136
93 95
143
110
125
108
38
71
73
18
16
99
19
54
126
10
84
55
1
9
5
7
3
4
2
6
10
8
1
6
2
8
7
3
4
5
1
5
6
42
3
11
9A6<
9C4<
9C4<
9C1<
9D6<>
9D6<>
1C7^ 8C2> 7C8<> 4A4<>
9D6<>
9D6<>
9C4<
9C4>
7B4<>
7B3< 9B1<>
7C4<>
7C4<>
9B8< 7B3<
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
MAX1963
SHDN*
GND
RST*
OUT
IC
IN
V3_3
AT25160A_U
SI
GND
WP*
HOLD*
VCC
SO
SCK
CS*
CONN_10P
7
1
5
GND
3
TCK
TMS
TDI
VCC
TDO
V3_3
V3_3
CONTROL
LFEC_T144_U
ALL LOW FOR
SPI3 MODE
NEEDS 10K,1% RESISTOR
PLACE CLOSE TO PIN
VCCIO4A
VCCIO3B
XRES
VCCAUX2
VCCAUX1
VCCJ
VCC3
TDI
TDO
VCCIO3A
VCCIO4B
VCCIO5A
VCCIO2
VCCIO1B
VCCIO1A
VCCIO0B
INIT*
PROGRAM*
VCCIO0A
CCLK
CFG1
CFG2
CFG0
TMS
VCC2
VCC1
VCCIO5B
VCCIO6A
TCK
DONE
GND10
GND9
GND8
GND7/GND0
GND6B/GND5
GND3B
GND3A/GND4
GND2/GND1
GND1
GND0
NC1
NC2
GND4
GND6A
GND5
VCCIO7
VCCIO6B
V3_3
ARE IN THE MICRO PROCESSOR BLOCK
TESTPOINTS FOR ADDR/DATA/CTRL
INT_LED AND TESTPOINTS FOR ADDR/DATA/CTRL
(LOW FOR PARALLEL PORT)
(LOW FOR NORMAL OPERATION)
(HIGH FOR MOTO MODE)
(LOW FOR NORMAL OPERATION)
BEGINNING OF DS26522DK HIERARCHY BLOCK
(HIGH FOR NORMAL OPERATION)
0
3
5
4
I235
I236
D5_SPI_SWAP
JTMS_DUT
JTDI_2_DUT
JTDO_2_DUT
JTRST_DUT
I231
1.0K
TXENABLE_1
BTS_DUT
I219
BGA
DS26522
RESET_DUT
A_DUT<12..0>
D4
D3
D6_SPI_CPHA
RESET_DUT
BTS_DUT
SPISEL_DUT
SCANEN_DUT
CS_X1
CS_X2
WR_DUT
JTCLK_DUT
RD_DUT
JTDI_1_DUT
JTDI_2_DUT
JTDO_1_DUT
JTMS_DUT
JTRST_DUT
MCLK_TAP7
INT_DUT
JTDO_2_DUT
0
1
2
3
4
5
6
8
12
I237
I238
7
NA
SCANEN_DUT
D7_SPI_CPOL
D6_SPI_CPHA
SPISEL_DUT
D5_SPI_SWAP
TXENABLE_2
1.0K
1.0K
1.0K
I527
1.0K
1.0K
1.0K
I525
I515
I521
1.0K
I520
1.0K
I535
I538
D_DUT<7..0>
INT_DUT
WR_DUT
RD_DUT
SCANMO_DUT
JTDO_1_DUT
1.0K
JTDI_1_DUT
JTCLK_DUT
JTCLK_DUT
2
1
SCANMO_DUT
A_DUT<12..0>
CS_X1
CS_X2
D7_SPI_CPOL
7
I234
6
D_DUT<7..0>
U06
J05
JP10
RB48
JP15
JP13
RB43
RB41
RB49
JP16
JP17
R02
RB42
JP18
JP19
RB51
RB52
RB50
RB28
1C6^10B8<
1C6^10C3
1D6^10C8>
1C6^10B8<
1C6^10B8<
1C6^10B4
1C6^10B8<
1C6^10B8<
DS26522DK01A0
1/5(BLOCK)
10/14(TOTAL)
STEVE SCULLY
04/17/2006
BLOCK
NAME:
_ds26522dk01a0dutdn_.
PARENT
BLOCK:
\_ds26522topdn_\
J2
J1
H2
G1
F2
F1
M8
G5
F5
K11
K10
C3
C2
C5
C4
C1
B7
E9
H9
A3
C7
A7
D10
D9
B3
B10
A10
F3
G9
F4
E4
E3
F10
F9
E10
D8
E8
K4
M9
L6
M5
M7
L7
L5
H3
M6
J3
M4
C6
L4
D6
D7
E5
K3
H10
J10
J9
G10
G3
J4
H4
G4
C12
C11
B6
A6
C10
D12
D11
C8
C9
D1
D3
D2
D4
D5
K9
H5
H1
G2
E2
E1
L3
M2
M1
L2
L1
K2
K1
M3
1
9
5
7
3
4
2
6
10
8
1
3
2
1
3
2
1
3
2
1
3
2
1
3
2
1
3
2
1
3
2
10C2<
10C8<
10C8<
10C8>
10C8<
11C7<
10B8<
1C6^ 10D7<
10C2<
1C6^ 10D7<
10B2<
10B2<
10A2<
1C6^ 10D7<
1C6^ 10D7<
1C6^ 10D7<
10A7< 10A7<>
1C6^ 10D7<
10A7<>
10A8<>
10A7<>
10A7<>
10A8<>
14D5>
1D6^ 10D7<
10A8<>
10B8<
10C4<>
10C4<>
10B8<
10C4<>
11A7<
10B8<
10C8>
10C8<
10C8<10A7<
10C8<10A7<>
10B2<
10B2<
1C6^10D7<>
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
IN
V3_3
IN
IN
IN
IN
IN
IN
IO
V3_3
CONN_10P
7
1
5
GND
3
TCK
TMS
TDI
VCC
TDO
V3_3
DS26522
D0
D7
D6
D5
D4
D3
D2
D1
A12
A8
A4
A3
ACVDD1_1
ACVDD2_2
ARVDD1_1
ARVDD1_2
ARVDD1_4
ARVDD1_3
ARVDD1_5
ARVDD2_1
ARVDD2_2
ARVDD2_3
ARVDD2_4
ARVDD2_5
ATVDD1_1
ATVDD1_2
ATVDD2_1
ATVDD2_2
DVDD1_1
DVDD1_2
DVDD1_3
DVDD1_4
DVDD2_1
DVDD2_2
DVDD2_3
DVDD2_4
RESETB
BTS
SPI_SEL
SCAN_EN
CSB1
SCAN_MODE
CSB2
WRB_RWB
JTCLK
RDB_DBS
JTDI1
JTDI2
JTDO1
JTMS
JTRST
MCLK
INT
DVSS2_5
DVSS2_4
DVSS2_3
DVSS2_2
DVSS2_1
DVSS1_4
DVSS1_2
DVSS1_3
DVSS2_6
DVSS1_1
ATVSS2_2
ATVSS2_1
ATVSS1_1
ARVSS2_5
ARVSS2_4
ARVSS2_3
ARVSS2_2
ATVSS1_2
DVSS2_7
DVSS2_8
ARVSS2_1
ARVSS1_5
ARVSS1_4
ARVSS1_1
ARVSS1_2
ARVSS1_3
ACVSS2_2
ACVSS2_1
ACVSS1_2
ACVSS1_1
JTDO2
A7
A6
A5
A2
A1
A0
NA
DS26522
BGA
BGA
DS26522
NA
RTIP_1
RRING_1
TRING_1
TTIP_1
RTIP_2
RRING_2
TRING_2
TTIP_2
RSIG_1
BPCLK_1
RCLK_1
RCHBLK_CLK_1
RSYNC_1
RM_RFSYNC_1
REFCLKIO_1
RSYSCLK_1
RSER_1
TCHBLK_CLK_1
TXENABLE_1
TSSYNCIO_1
TCLK_1
TSYSCLK_1
TSIG_1
TSYNC_1
TSER_1
AL_RSIGF_FLOS_1
RLF_LTC_1
RCLK_2
RCHBLK_CLK_2
RM_RFSYNC_2
RSYNC_2
REFCLKIO_2
RSIG_2
RSYSCLK_2
BPCLK_2
RSER_2
TXENABLE_2
TCHBLK_CLK_2
TCLK_2
TSSYNCIO_2
TSYNC_2
TSYSCLK_2
TSIG_2
TSER_2
RLF_LTC_2
I1
I2
330
330
330
330
AL_RSIGF_FLOS_1
RLF_LTC_1
AL_RSIGF_FLOS_2
RLF_LTC_2
I7
I8
I13
I14
AL_RSIGF_FLOS_2
U06
U06
RB32
RB33
DS04
DS05
RB34
RB35
DS06
DS07
DS26522DK01A0
STEVE SCULLY
04/17/2006
2/5(BLOCK)
11/14(TOTAL)
BLOCK
NAME:
_ds26522dk01a0dutdn_.
PARENT
BLOCK:
\_ds26522topdn_\
CR-11
:
@\_ZTOP_LIB\.\_DS26522TOPDN_\(SCH_1):PAGE1_I9@\_ZTOP_LIB\.\_DS26522DK01A0DUTDN_\(SCH_1):PAGE2
H6
K6
A1
L8
J6
K7
G6
K8
J8
K5
F7
E6
G7
G8
H8
H7
J7
F8
A5
B5
A4
B4
B1
A2
B2
F6
J5
1
2
1
2
L9
M11
L12
K12
L10
L11
J11
M10
H12
E7
G12
G11
F12
F11
H11
E11
E12
B12
A12
B11
A11
A8
B8
A9
B9
J12
M12
1
2
1
2
12B7<
12B7<
12B7<
12C7<
13B7<
13B7<
13B7<
13C7<
14C6<
14A2<>
14B8<
14B3<
14A6<>
14B3<
14B2<>
14A5<>
14D3<
14B3<
10A2<
14A8<>
14B6<>
14A5<>
14C4<>
14A8<>
14D1<>
11C3<>
11B3<>
14A8<
14C3<
14C3<
14A6<>
14B2<>
14B6<
14A5<>
14A2<>
14D3<
10A2<
14C3<
14A6<>
14A8<>
14A8<>
14B5<>
14B4<>
14D1<> 11B3<>
11D5>
11D5>
11B5>
11B5>
11B3<>
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
DS26522
RLF_LTC2
AL_RSIGF_FLOS2
RTIP2B
RTIP2A
RRING2A
RRING2B
TRING2B
TRING2A
TTIP2A
TTIP2B
TSER2
TSIG2
TSYSCLK2
TSYNC2
TSSYNCIO2
TCLK2
TCHBLK_CLK2
TXENABLE2
RSER2
BPCLK2
RSYSCLK2
RSIG2
REFCLKIO2
RSYNC2
RM_RFSYNC2
RCHBLK_CLK2
RCLK2
DS26522
RLF_LTC1
AL_RSIG_FLOS1
RTIP1B
RTIP1A
RRING1B
TRING1B
TRING1A
TTIP1A
TTIP1B
TSER1
TSYNC1
TSIG1
TSYSCLK1
TCLK1
TSSYNCIO1
TXENABLE1
TCHBLK_CLK1
RSER1
RSYSCLK1
REFCLKIO1
RM_RFSYNC1
RSYNC1
RCHBLK_CLK1
RCLK1
RRING1A
BPCLK1
RSIG1
_1
51.1
0.0
0.0
0.0
0.0
61.9
61.9
560PF
.1UF
TTIP_1
TRING_1
RTIP_1
RRING_1
J12
J10
TB01
J13
TB01
RB54
RB45
RB44
CB44
CB46
R09
R10
R08
R07
04/17/2006
STEVE SCULLY
DS26522DK01A0
BLOCK
NAME:
_ds26522dk01a0dutdn_.
PARENT
BLOCK:
\_ds26522topdn_\
12/14(TOTAL)
3/5(BLOCK)
CR-12
:
@\_ZTOP_LIB\.\_DS26522TOPDN_\(SCH_1):PAGE1_I9@\_ZTOP_LIB\.\_DS26522DK01A0DUTDN_\(SCH_1):PAGE3
1
2
2
1
2
1
1
2
1
4
7
2
3
6
8
5
8
7
6
5
9
11
10
1
2
4
3
2
1
14
16
15
2
1
11C5>
11C5>
11D5<
11C5<
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
1:1
1:0.8
CONN_BNC_5PIN
1:1
1:0.8
CONN_RJ48
E
H
F
C
B
G
D
A
CONN_BNC_5PIN
_1
I6
I4
I3
I2
51.1
0.0
0.0
0.0
0.0
61.9
61.9
560PF
.1UF
TTIP_2
TRING_2
RTIP_2
RRING_2
I5
J15
J11
TB02
TB02
J14
RB53
R03
R04
R06
R05
RB47
RB46
CB45
CB43
04/17/2006
STEVE SCULLY
DS26522DK01A0
11/34(TOTAL)
2/4(BLOCK)
BLOCK
NAME:
_ds26522dk01a0dutdn_.
PARENT
BLOCK:
\_ds26522topdn_\
CR-13
:
@\_ZTOP_LIB\.\_DS26522TOPDN_\(SCH_1):PAGE1_I9@\_ZTOP_LIB\.\_DS26522DK01A0DUTDN_\(SCH_1):PAGE4
2
1
2
1
1
2
1
2
1
4
7
2
3
6
8
5
8
7
6
5
9
11
10
4
3
2
1
14
16
15
1
2
2
1
11A5>
11A5>
11B5<
11A5<
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
CONN_BNC_5PIN
1:1
1:0.8
1:1
1:0.8
CONN_RJ48
E
H
F
C
B
G
D
A
CONN_BNC_5PIN
END OF DS26522DK HIERARCHY BLOCK
TO DUT (NO TERMINATION RESISTORS)
PLACE SYNC AND SYNCIO PINS CLOSE
RSYNC_2
TSIG_1
MCLK_TAP8
RM_RFSYNC_1
RCHBLK_CLK_1
TCHBLK_CLK_1
RM_RFSYNC_2
RCHBLK_CLK_2
TCHBLK_CLK_2
30
30
RSIG_1
MCLK_TAP2
T1_OSC
E1_OSC
30
1.544MHZ_3.3V
2.048MHZ_3.3V
TSER_2
TSER_1
RSER_2
30
TSYSCLK_2
MCLK_TAP4
BPCLK_1
TSYSCLK_1
BPCLK_2
30
30
MCLK_TAP1
RCLK_1
RCLK_2
30
TCLK_1
TSYNC_2
TSYNC_1
TSYNC_1
TSSYNCIO_2
TSYNC_2
TSSYNCIO_1
TSIG_2
30
MCLK_TAP5
TCLK_2
MCLK_TAP3
MCLK_TAP6
RSYSCLK_2
RSYSCLK_1
RSYNC_1
REFCLKIO_2
REFCLKIO_1
MCLK_TAP8
MCLK_TAP5
MCLK_TAP6
MCLK_TAP8
MCLK_TAP7
30
MCLK_TAP1
MCLK_TAP2
MCLK_TAP3
MCLK_TAP4
BUFFER
BUFFER
RSIG_2
RSER_1
JP08
YB02
YB01
JP07
JP06
RPB01
J06
RPB02
RPB06
RPB04
RPB07
UB06
RPB05
UB07
RB37
RB36
RPB03
JP14
JP11
JP09
JP12
JP05
JP02
JP01
JP04
JP03
J07
BLOCK
NAME:
_ds26522dk01a0dutdn_.
PARENT
BLOCK:
\_ds26522topdn_\
14/14(TOTAL)
5/5(BLOCK)
STEVE SCULLY
04/17/2006
DS26522DK01A0
1
3
2
1
3
2
1
3
2
1
3
2
1
3
2
1
3
2
1
3
2
2
4
8
6
3
1
9
11
13
10
5
7
14
12
1
8
4 5
1
8
4 5
1
3
2
1
3
2
3
1
2
5
6
7
8
4
6 5
4
9
7
3
10
8
1
2
3
1
2
5
6
7
8
4
1
3
2
3
1
2
5
6
7
8
4
3
1
2
5
6
7
8
4
3
1
2
5
6
7
8
4
4
1
3
1
2
5
6
7
8
44
1
3
1
2
5
6
7
8
4
1
3
2
1
3
2
11A7<>
11D7<
14D5>
14B1<>
11C7>
11B7>
11D7>
11A7>
11A7>
11A7>
11C7>
14C5>
11B7<
11D7<
11A7>
11B7<
14D5>
11C7>
11D7<
11A7>
14C5>
11C7>
11A7>
11D7<
14A8<> 11B7>
14A8<> 11D7<>
14A8<> 11D7<>
11B7<>
14A8<> 11B7>
11D7<>
11B7<
14D5>
11A7<
14D5>
14D5>
11A7>
11C7<
11C7<>
11A7<>
11C7<> 14D5>
14B1<>
14A4<>
14A4<>
14B1<>
10C8<
14B7<>
14A7<>
14A4<>
14A4<>
11A7>
11C7>
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
NC7SZ86_U
NC7SZ86_U
6
10
8
4
1
2
3
5
7
9
CONN_10P
VCC
1
OSC
GND OUT
V3_3
VCC
1
OSC
GND OUT
V3_3
2
3
7
13
8
5
9
11
6
4
10
12
14
1
CONN_14P
Mouser Electronics
Authorized Distributor
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Maxim Integrated:
DS26522DK